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> Try a 3 button Logitech serial mouse. I have one right here, and it doesn't work. Viewlogic requires an exact hardware equivalent of the PC MOUSE. Up to a few years ago, most mice had a Microsoft/PC-Mouse switch on the bottom. I use one of them now, a no-name Taiwanese job which won't last forever. Peter.Article: 4226
In article <324A817A.2C6D@nmp.nokia.com>
teppo.hemia@nmp.nokia.com "Teppo Hemia" writes:
"Hi all,
"
"Does anyone know a good partition tool for multiple
"FPGAs? It should not be too automatic letting possible
"to do the partition partly manually also.
"
"It can be fully manual, if it is interactive for
"resulting the partition changes.
"
"Any suggestion most welcome.
"
The partitioner from MINC-IST is worth looking at. You can constrain
it via a number of means such as manual partition definition.
The product is timing-driven, and supports Xilinx, Actel and Altera
FLEX. MINC also have a PLD partitioner that supports AMD MACH
devices.
Try salesinfo@minc.com or support@ist.fr
Cheers
David
Article: 4227Sorry, I don't have specifics about Syanrio/Xilinx example but here some other background info... I am currently in the process of using Synario with VHDL. Synario is fairly easy to use. The tools appears to generate valid reduced equations. However, the jury is still out on how well it will map things. I coded and then mapped a small state machine (16 states) 6 inputs - 6 outputs) to the Flex device. Top speed reported by the Altera layout tool was 35 Mhz reg to reg. That however was using their fastest device. Other devices reported about 15-18 Mhz. TonyDArticle: 4228
VirginiaTechVirginiaTechVirginiaTechVirginiaTechVirginiaTechVirginiaTech
VT
VT RESEARCH ASSISTANT PROFESSOR
VT * Position Announcement *
VT
VirginiaTechVirginiaTechVirginiaTechVirginiaTechVirginiaTechVirginiaTech
* * * * *
The Bradley Department of Electrical and Computer Engineering at Virginia
Polytechnic Institute and State University (Virginia Tech) invites
applications for a Research Assistant Professor (a renewable 12 month,
non-tenure track appointment) in the computer engineering area. Expertise
is sought in the areas of configurable computing (FPGA-based computing),
VLSI,
computer architecture, and hardware-software co-design. The requirements
for
the position are the following: a Ph.D. in Electrical Engineering,
Computer
Engineering, or closely related field; a record of scholarly research and
professional development in computer engineering; and a demonstrated
strong
commitment towards teaching in the area of computer engineering and
micro-electronics. The candidate will be responsible for conducting
original
research and leading graduate students in the areas mentioned above as
part
of the Virginia Tech Information Systems Center (VISC). The position will
be renewable on a yearly basis. Qualified applicants should submit their
resume and names of three references to Dr. P. M. Athanas, Resource
Director,
Virginia Tech Information Systems Center, 340 Whittemore Hall, Blacksburg,
Virginia 24061-0111. Applications will be reviewed beginning
October 21, 1996, and will continue until a suitable candidate is
selected.
Virginia Tech is Virginia's land grant university offering degrees through
the Ph.D. The Department offers ABET-accredited Bachelor of Science in
Computer Engineering and Bachelor of Science in Electrical Engineering
degrees, the Master of Science in Electrical Engineering degree, including
a computer engineering option, and the Ph.D. degree in Electrical
Engineering.
Article: 4229Does anyone know where there is a web site or newsgroup where I can post positions I have for pSOS skilled professionals? The misc.jobs.... newsgroups are just too generic (and flooded). I am trying to reach a more specific crowd. We have a client that needs someone and will pay well and I'm tired of receiving resumes from everyone BUT pSOS skilled individuals. I do not mean to offend or break any group charters. If I have, please forgive me. Thank you for your time and consideration. --- Lloyd Songne Volt Services Group Please view our searchable employment web site at http://www.volt-tech.comArticle: 4230
>The above app requires a "Mouse Systems PC Mouse". It calls it >directly, on com1 or com2, so any driver emulation does not work. >Has anyone ever found a way to use a normal "Microsoft" serial or bus >mouse with this program? It wasn't only Mouse Systems mice which worked -- most Genius or Logitech mice also work OK -- in 3 button mode. -- Gavin Melville, gavin@cypher.co.nzArticle: 4231
Peter wrote: > > > Try a 3 button Logitech serial mouse. > > I have one right here, and it doesn't work. Viewlogic requires an > exact hardware equivalent of the PC MOUSE. > That's funny, I've been using a logitech mouseman serial mouse with my viewlogic for years without a hitch. Did you install the mouse drivers correctly?Article: 4232
The Logitech mice run fine with the old DOS VL 4.1, you just have to know the secret incantation, and here it is!!! This is a batch file that lives in my workview directory ( i:\WV510 ), where the rest of the executeables live. Note that my mouse is on COM2, so I still have to have run VL's setup, and set the port to COM2. VL does not use the driver, but you need it to have been loaded, to send the mode info to the mouse to make it work. Note that having done this, you need another batch file to change modes to run XDE. Integration at its best! My mouse is a Logitech MouseMan, and the driver is version 7.00 WV.BAT REM fixed for my Logitech Mouseman V7.0 on 9/8/96 rem workview needs 5B or PC rem XDE needs MI or MP c:\mouse7\mouse 5b WORKVIEW c:\mouse7\mouse mp And it works. All the best, Philip. In article <325494e6.11024106@news.alt.net> scanner@dial.pipex.com (Peter) writes: > >> Try a 3 button Logitech serial mouse. > >I have one right here, and it doesn't work. Viewlogic requires an >exact hardware equivalent of the PC MOUSE. > >Up to a few years ago, most mice had a Microsoft/PC-Mouse switch on >the bottom. I use one of them now, a no-name Taiwanese job which won't >last forever. > >Peter.Article: 4233
Hello, I have tried to ask Xilinx tech support (UK) but they have changed their system, and all one now gets is an answering machine which gives out telephone numbers, followed by a queue for calls, followed by another answering machine!!! So much for support on $5000-$10000 software... You can tell this is Europe. Anyway, I am doing a rather long Viewsim (Viewlogic v4.1) script, and wonder if there is any "macro" capability. The docs I have don't mention this. For example, I have the following commands h d0 l wr- sim 1us h wr- sim 1us This sequence is used all over the place, and I wonder if one can give them a name, and then invoke them using that name only. Peter. (address mis-spelt to stop automated junk mail)Article: 4234
On Thu, 03 Oct 1996 09:52:24 GMT, scannner@dial.pipex.com (mis-spelt!) wrote: >Anyway, I am doing a rather long Viewsim (Viewlogic v4.1) script, and >wonder if there is any "macro" capability. The docs I have don't >mention this. > >For example, I have the following commands > >h d0 >l wr- >sim 1us >h wr- >sim 1us > >This sequence is used all over the place, and I wonder if one can give >them a name, and then invoke them using that name only. > Peter, Just put that series of commands in a file named something dot cmd and then just issue the filename from within your top level cmd file whenever you want to execute the commands. e.g. place the above commands in write.cmd then create top.cmd as: l reset cycle 5 h reset write .. etc. -- AlanArticle: 4235
mis-spelt! (scannner@dial.pipex.com) wrote: : Hello, : Anyway, I am doing a rather long Viewsim (Viewlogic v4.1) script, and : wonder if there is any "macro" capability. The docs I have don't : mention this. : For example, I have the following commands : h d0 : l wr- : sim 1us : h wr- : sim 1us Put this sequence in a separate command file (i.e wr_macro.cmd) and call it from your main command file.Article: 4236
CALL FOR PAPERS AND PARTICIPATION
1997 IEEE INTERNATIONAL WORKSHOP
ON MEMORY TECHNOLOGY, DESIGN AND TESTING
August 11-12, 1997
Submission deadline: January 15, 1997
Send submissions to:
TECHNICAL PROGRAM CHAIR
Thomas Wik
LSI Logic, MS E-194
1501 McCarthy Blvd
Milpitas CA 95035, USA
408/954--4471; trw@lsil.com
Address general inquiries to:
GENERAL CHAIR
Fabrizio Lombardi
Computer Science MS 3112
Texas A&M University
College Station TX 77843, USA
409/845--5464; fax 847--8578
lombardi@cs.tamu.edu
The 1997 IEEE International Workshop on Memory Technology, Design and
Testing will be held at the Hilton Hotel and Towers, 300 Almaden Blvd,
San Jose, California, USA (408/287--2100), on August 11-12, 1997.
The workshop will include all aspects of memory design, process
technologies and testability related topics. Memory circuit designs,
cell structures, fabrication processes, design architectures as
related to testing, verification and test methods for SRAM, DRAM,
Flash and Non-Volatile memories, EPROM, eEPROM, embedded memories,
logic-enhanced and FIFO memories, 3-D memories and content addressable
memories. Some representative topics are:
- Memory fault modeling and test generation
- Built-in test and testable designs for memories
- Concurrent checking and memory fault diagnosis
- Quality and reliability issues
- Space applications and radiation hardening issues
- Memory failure and yield analysis
- High-speed, innovative designs
- Fault isolation, reconfiguration and repair
- Multiported, multibuffered memories
- Logic-enhanced and programmable memories
- Application-specific and embedded memories
- Multimegabit SRAMs and DRAMs
- CMOS, BiCMOS and bipolar designs for high yield and reliability
Authors please submit five (5) copies of an extended abstract of about
1000 words of original work on any aspect of memory technology, design
and testing to the Technical Program Chair. Submissions should
include full names and affiliations of authors, contact information
and should indicate the intended presenter.
Submissions are due January 15, 1997. Authors will be notified of
acceptance on March 31, 1997. Final papers will be due May 15, 1997.
Presentations will be 30 minutes, inclusive of discussion.
Sponsored by:
IEEE Computer Society
Technical Committee on Test Technology
Technical Committee on VLSI
In cooperation with:
IEEE Solid-State Circuit Council/Society
PUBLICITY CHAIR
Fred "Jackie" Meyer
Computer Science MS 3112
Texas A&M University
College Station TX 77843, USA
409/845--1014; fmeyer@cs.tamu.edu
FINANCE CHAIR
Duncan "Hank" Walker
Computer Science MS 3112
Texas A&M University
College Station TX 77843, USA
409/862--4387; fax 847--8578
walker@cs.tamu.edu
STEERING COMMITTEE
Rochit Rajsuman, Chair
LSI Logic, MS E-171
1501 McCarthy Blvd
Milpitas CA 95035, USA
408/433--8789; rajsuman@lsil.com
PROGRAM COMMITTEE
Bruce Cockburn
University of Alberta
Edmonton AB, Canada
Bernard Courtois
INPG/TIMA
Grenoble, France
Bob Evans
MosAid
San Jose CA, USA
S. Griep
Siemens AG
Munchen, Germany
David Lepejian
HPL
Milpitas CA, USA
Yashwant Malaiya
Colorado State University, USA
Ritu Shrivastava
Alliance Semiconductor
San Jose CA, USA
Article: 4237I am taking (another) look at VHDL for FPGA design. I am a complete novice at VHDL but have been doing FPGA design for years. I would be looking for a solution which runs under HP-UX on the HP 700-series. The target will probably be Xilinx 5k and 4k series. Our past attempts at synthesising Xilinx (3000) LCAs from VHDL apparently failed because it took too much manual intervention to get a decent end result. Have the tools improved significantly? Which vendors should I contact? With VHDL entry, is it still possible to make use of the static-timing driven routing facilities of the Xilinx PPR router? Has anyone tried mixing ABEL-HDL with VHDL? What would be the issues here? Any information will be gratefully received! Nick ============================================================================ Nick Gent Queensferry Telecom Operation Email: nickg@hpsqf.sqf.hp.com Hewlett-Packard Telephone: +44 131 331 7644 South Queensferry EH30 9TG Fax: +44 131 331 7488 Scotland ============================================================================Article: 4238
I am soliciting opinions on QuickLogic development tools, QuickLogic customer service and/or the company as a whole. I am not an Engineer, so please be gentle. please reply to: fitz@innova.wa.comArticle: 4239
Thanks all. Viewsim is a rather basic simulator. I wish it had some basic macros, like rept 256 l rd- sim 1us h rd- sim 1us endm Instead one has to use the "wfm" command, which makes the creation of *multiple* complex repetitive waveforms horrendously hard. Or maybe all this stuff is in there after all... What about loops generally? Peter.Article: 4240
>This is a batch file that lives in my workview directory ( i:\WV510 ), where >the rest of the executeables live. Note that my mouse is on COM2, so I still >have to have run VL's setup, and set the port to COM2. Philip, Presumably, therefore, a *bus* mouse can never work. But at least serial Logitechs are available. Peter.Article: 4241
mis-spelt! <scannner@dial.pipex.com> wrote in article <32538b02.20981@news.alt.net>... > Hello, > > I have tried to ask Xilinx tech support (UK) but they have changed > For example, I have the following commands > > h d0 > l wr- > sim 1us > h wr- > sim 1us > > > Peter. > > (address mis-spelt to stop automated junk mail) Peter, Open a dos file called 'xxx.cmd'. Put the commands in the file. In the simulator just type 'xxx' and the commands will run. Personally, I find the Viewlogic simulator very useable and predictable. Stan Hodge Grimes Aerospace srhodge@foryou.netArticle: 4242
Boy, am I con*fused*. I have two programmed Altera EPLDs which are the same raw part but show different checksums when read in from the device. Part A CS = 8DD2 Part B CS = 8DD5 The programmer is a Data I/O Unisite. Device is EP1810-25 Device code used to read is 10. There is only one master part also a EP1810-25. There is only one JED source file which was used to create the master. Thes two devices function identically yet there must be some difference between them Possibilities: 1 - I can imagine is that the internal utilization of cells may be different between the two devices . Possibly because of programming method. 2 - Some other bits in the parts that do not contribute to the functionality of the part are programmed differently. Possibly a checksum field? Security bits? Status register? 3 - I still don't understand the difference between Turbo and NonTurbo. (confidence fading) 4 - I am loosing my marbles and should retire to greener pastures. Clue: The EP1810-25T (turbo) parts I have programmed all have 8DD2 as their checksum when read as device type 14. Altera and Data I/O lead me to believe that the parts are identical functionally. They do both function in circuit. But I have not verified with logic analyzer that the parts are staying out of the power down state. I am not technically satisfied. And the persons that program these on the production floor are confused too. Has anyone else come across this problem? If so, please explain it to me. --fred fgiorg@atl.comArticle: 4243
In article <3255f5e3.849744@news.alt.net> scannner@dial.pipex.com (mis-spelt!) writes: > >>This is a batch file that lives in my workview directory ( i:\WV510 ), where >>the rest of the executeables live. Note that my mouse is on COM2, so I still >>have to have run VL's setup, and set the port to COM2. > >Philip, > >Presumably, therefore, a *bus* mouse can never work. But at least >serial Logitechs are available. > >Peter. I suspect that you are right. I have never heard of a bus mouse working with VL 4.1 PhilipArticle: 4244
Peter, looks like you need to study the manuals more closely :-) , then again, the indexes and examples in the VL manuals are borderline useless, so finding this stuff isn't easy. (l rd- ; sim 1us ; h rd- ; sim 1us)*256 You might also want to go look at the pattern and check commands. The clock command can also be helpfull in complex simulations. The other thing I do often is use the break command together with the pattern command to apply data on bus state transitions, and with the check command to implement automatic regression. all the best, Philip In article <3254f51e.652454@news.alt.net> scannner@dial.pipex.com (mis-spelt!) writes: > >Thanks all. Viewsim is a rather basic simulator. I wish it had some >basic macros, like > >rept 256 > l rd- > sim 1us > h rd- > sim 1us >endm > >Instead one has to use the "wfm" command, which makes the creation of >*multiple* complex repetitive waveforms horrendously hard. Or maybe >all this stuff is in there after all... What about loops generally? > >Peter.Article: 4245
hi.
I want best synthesis tool for fpga/cpld.
please, sned me mail.
Thank yon.
Article: 4246
hi.
I want best synthesis tool for fpga/cpld.
please, sned me mail.
Thank you.
Article: 4247Hello, In article <530kg5$1sp@hpwin055.uksr.hp.com> nickg@hpqt0220.sqf.hp.com (Nick Gent) writes: > Our past attempts at synthesising Xilinx (3000) LCAs from VHDL apparently > failed because it took too much manual intervention to get a decent end > result. Have the tools improved significantly? I'm currently using VHDL for synthesizing, target is the XC3020. I'm using ViewLogic's Viewsynthesis (which is said to be better for ASICs) and Xilinx' XACT. I'd been used to VHDL before I started with the project that was to be synthesized - mistake! I personally recommend a lack (!) of knowledge about VHDL, as synthesistools are placing many restrictions on your VHDL-coding style. Had to come down from a fairly high level to connecting gates in VHDL, actually. > Which vendors should I contact? Viewlogic's ProSynthesis seems to be suited for FPGAs - at least the ViewSynth manual says so. In the manuals from Xilinx I found the name "Synopsis" most often. Hidden clue? bye, PatrickArticle: 4248
Hi! does anybody know of reconfigurable hardware for arithmetic operations? For example, reconfigurable hardware for division and square root. Tanks, Pasquale Corsonello email:pascor@ccusc1.unical.itArticle: 4249
Fred, A couple of suggestions: Use the programmer's Compare function to find out exactly which bits are different. This may give you a clue. Check the date codes of the two devices. If they are from different batches the likelihood of a device/batch related problem is increased. This can be confirmed by programming more devices from the different batches. Finally, the best way to ensure a good device is not to rely on checksums or fuse verification, but to apply a full set of test vectors with a high degree of coverage. There are software products on the market that will measure vector fault coverage, and generate new vectors if required. The programmer will automatically apply vectors appended to the JEDEC file. Being programmed is the most stressful event in the life of the device, and only by applying vector test after this event can you reach the highest quality levels. In article <1996Oct3.224708.8548@atl.com> fgiorg@atl.com "Fred Giorgi" writes: "Boy, am I con*fused*. " I have two programmed Altera EPLDs which are the same raw part "but show different checksums when read in from the device. "Part A CS = 8DD2 "Part B CS = 8DD5 "The programmer is a Data I/O Unisite. "Device is EP1810-25 "Device code used to read is 10. "There is only one master part also a EP1810-25. "There is only one JED source file which was used to create the "master. " "Thes two devices function identically yet there must be some "difference between them "Possibilities: "1 - I can imagine is that the internal utilization of cells may "be different between the two devices . Possibly because of "programming method. "2 - Some other bits in the parts that do not contribute to the "functionality of the part are programmed differently. Possibly a "checksum field? Security bits? Status register? "3 - I still don't understand the difference between Turbo and "NonTurbo. (confidence fading) "4 - I am loosing my marbles and should retire to greener pastures. " "Clue: "The EP1810-25T (turbo) parts I have programmed all have 8DD2 as "their checksum when read as device type 14. " "Altera and Data I/O lead me to believe that the parts are "identical functionally. They do both function in circuit. But I "have not verified with logic analyzer that the parts are staying "out of the power down state. "I am not technically satisfied. And the persons that program "these on the production floor are confused too. Has anyone else "come across this problem? If so, please explain it to me. " "--fred "fgiorg@atl.com " -- David Pashley
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Threads starting:
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