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Are you running a special driver for the Xilinx dongle? This alone normally totally stops the s/w running under NT. Funnily enough I find that XACT runs much *faster* under FWG3.11 than under DOS, probably due to excessive disk cache flushing. Peter. >Hi All, > >Following the instructions offered up by Xilinx, I've gotten the command >line portion of XACT (5.2.1) running under WinNT 3.51. However it runs >about 30 times slower than under pure DOS 6.22. Has anyone else >encountered this problem? Better yet, has anyone else encountered a >solution?! > >Thanks, >ScottArticle: 4476
Peter wrote: > Are you running a special driver for the Xilinx dongle? This alone > normally totally stops the s/w running under NT. Yes, I'm running the NT version of the Rainport driver. The software runs my design to completion, it just takes 26 minutes to place and route a test design containing 6 CLBs. And as you might imagine my real design is somewhat more complex. > Funnily enough I find that XACT runs much *faster* under FWG3.11 than > under DOS, probably due to excessive disk cache flushing. I didn't notice much difference between DOS6.22 and Win3.1 but both are faster than Win95 and lots faster than WinNT. ScottArticle: 4477
Hi, Any 16 bit DOS app is going to run much slower under NT. To run 16 bit programs in NT, NT uses a lot of software layers to maintain the integrety of the OS. Even EDIT runs real real slow... The next release of the Xilinx tools will be made to run under NT. This current release does run, at least all the DOS tools do. I don't know if the number I get is 30 times slower, it may be 2-4 times slower. You may want to pick up the Windows NT 4.0 WS Resource Kit and follow the tips on speeding up NT. It has a whole chapter on optimizing NT. Good Luck! Austin Franklin darkroom@ix.netcom.comArticle: 4478
In article <55clpn$dod@news2.Belgium.EU.net>, Vincent.Himpe@ping.be (Vincent Himpe) wrote: > hi > > I have a small problem. > > I have a fairy simple circuit : a 24 bit counter with parallel load I forgot to explain the acid test for a TRULY UNIVERSA UNRESTRICTED circuit of the kind you described: Reset the 24-bit counter to 000000, then load FFFFFF on one clock edge, then use the next clock edge to increment to 000000, and the following clock edge to increment to 000001. In this case, the carry logic must be built up and then be built down, each in one single clock period. All sneaky tricks will fail this high-speed test, only a straightforward carry implementation will succeed. But ithat takes a 24-input AND/XOR gate to drive the MSB input, and that is tough to implement when you have only 16 ns minus the clock-to-out of all flip-flops, minus the input set-up time of the MSB. I'll look into an EPLD implementation using the XC7300 family. Peter Alfke, Xilinx ApplicationsArticle: 4479
=============================================================================
Call for Papers
1997 International Symposium on Physical Design
April 14-16, 1997
Napa Valley, California
Sponsored by the ACM SIGDA in cooperation with
IEEE Circuits and Systems Society
The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems. All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium. Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop. Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:
1. Management of design data and constraints
2. Interactions with behavior-level synthesis flows
3. Interactions with logic-level (re-)synthesis flows
4. Analysis and management of power dissipation
5. Techniques for high-performance design
6. Floorplanning and building-block assembly
7. Estimation and point-tool modeling
8. Partitioning, placement and routing
9. Special structures for clock, power, or test
10. Compaction and layout verification
11. Performance analysis and physical verification
12. Physical design for manufacturability and yield
13. Mixed-signal and system-level issues.
IMPORTANT DATES: Submission deadline: December 20, 1996
Acceptance notification: February 1, 1997
Camera-ready (6 page limit) due: March 1, 1997
SUBMISSION OF PAPERS:
Authors should submit full-length, original, unpublished papers
(maximum 20 pages double spaced) along with an abstract of at most
200 words and contact author information (name, street/mailing address,
telephone/fax, e-mail).
Electronic submission via uuencoded e-mail is encouraged (single
postscript file, formatted for 8 1/2" x 11" paper, compressed with
Unix "compress" or "gzip''). Email to:
ispd97@ece.nwu.edu
Alternatively, send ten (10) copies of the paper to:
Prof. Majid Sarrafzadeh
Technical Program Chair, ISPD-97
Dept. of ECE, Northwestern University
2145 Sheridan Road, Evanston, IL 60208 USA
Tel 847-491-7378 / Fax 847-467-4144
SYMPOSIUM INFORMATION:
To obtain information regarding the Symposium or to be added to the
Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu.
Information can also be found on the ISPD-97 web page:
http://www.cs.virginia.edu/~ispd97/
SYMPOSIUM ORGANIZATION:
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee: J. Cohoon (Virginia), S. Dasgupta (Sematech),
S. M. Kang (Illinois), B. Preas (Xerox PARC)
Program Chair: M. Sarrafzadeh (Northwestern)
Keynote Address: T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address: R. Camposano (Synopsys)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
W. W.-M. Dai (UC Santa Cruz)
J. Frankle (Xilinx)
D. D. Hill (Synopsys)
M. A. B. Jackson (Motorola)
J. A. G. Jess (Eindhoven)
Y.-L. Lin (Tsing Hua)
C. L. Liu (Illinois)
M. Marek-Sadowska (UC Santa Barbara)
M. Sarrafzadeh (Northwestern)
C. Sechen (Washington)
K. Takamizawa (NEC)
M. Wiesel (Intel)
D. F. Wong (Texas-Austin)
E. Yoffa (IBM)
=============================================================================
Article: 4480Hi, Can anyone suggest references for a beginner who wants to learn about FPGAs? I'm an Elec Eng undergrad. Please email me --- I will summarise should there be interest. Many thanks, Bert --------------------------------------------------------------------------- Bert Thompson aet@cs.mu.oz.au ---------------------------------------------------------------------------Article: 4481
Hi, I'm looking for info on any FPGA's currently available where the internal architecture and programming information is known (ie. where I can write to programming registers myself instead of having to use manufacturers own tools). Does anyone know of such an FPGA (from what I've found in the data books so far, they talk only about the tools supplied by vendors to produce the programming code). Reply by e-mail to craigs@elec.gla.ac.uk would be preferred. Best regards Craig SlorachArticle: 4482
Hi ORCA friends, Has anybody encountered problems with two consecutive configurations of the ATT2C26.? In our case it seems like, after a successful first time configuration, that the device's I/Os are activated somewhere in the middle of a second one. We made a testcircuit consisting of the TSALL component only, and this time we were able to reconfigure the device repeatedly. BTW, the device is programmed in the serial slave mode from an on-board uP using the *.rbt option. Does anbode have a hint? Best regards Aage FarstadArticle: 4483
Lucent ORCA chips can probably do the job without too much fancy logic. From their timing specs I get a cycle time for a 24-bit loadable counter of about 15ns for the 2C00a-4 speed chips. The -3 chips would give an 18ns cycle. This is probably the limiting circuit. The comparator and reset logic can be easily pipelined.Article: 4484
The Altera apps note will be different to the Xilinx one because Xilinx 4000 parts have DISTRIBUTED RAM which is much more suitable for generating look-up table based multipliers. Also, because the RAM is DISTRIBUTED, it's right where you need it to be (i.e. right where you want your multiplier) and hence it will be faster. I seriously suggest waiting for the Xilinx Apps note before making a decision as using DISTRIBUTED RAM and partial products (hence smaller look-up tables) makes for faster, more compact multipliers. -- Simon 106072.1620@Compuserve.com These opinions are entirely my own and, in keeping with the true nature of opinions, are not always valid or rational.Article: 4485
In article <55k839$ljd@mulga.cs.mu.OZ.AU>, aet@murlibobo.cs.mu.OZ.AU (Bert THOMPSON) writes: CHi, C CCan anyone suggest references for a beginner who wants to learn Cabout FPGAs? I'm an Elec Eng undergrad. C CPlease email me --- I will summarise should there be interest. C CMany thanks, CBert C--------------------------------------------------------------------------- CBert Thompson aet@cs.mu.oz.au C---------------------------------------------------------------------------Article: 4486
Hello,
I work at a research center, and currently use PIC uP's.
What I want to do expand our knowledge in FPGA or FPAA...
...This topic seems to be a "meat market" between
manufacturers and I would simply like some "real world"
information. ie: What kind of setup can I get for $5,000.
What have you made your FPxx do? What can it do?-impress me
Beau Schwabe
bschwabe@ionet.net
Article: 4487Scott Kroeger <Scott.Kroeger@mail.mei.com> writes: > Hi All, > > Following the instructions offered up by Xilinx, I've gotten the command > line portion of XACT (5.2.1) running under WinNT 3.51. However it runs > about 30 times slower than under pure DOS 6.22. Has anyone else > encountered this problem? Better yet, has anyone else encountered a > solution?! > > Thanks, > Scott I have used the XACT 5.2X software on Windows NT 4.0. The Place and Routing of the device was fast compared to Win 95. Wir2Xnf was very fast on NT 4.0 Beta (5 to 10 times faster that on WIN 95) On the final release of NT 4.0, Wir2Xnf was very slow. It does a lot of disk swopping. It sounds as if the hard drive is going to crash. I would also like know to what the reason for the change in Wir2Xnf behaviour is. Hope this helps PietArticle: 4488
Hi! I need a RS-232 interface for XILINX FPGAS. Who can help me ? I need a ready and tested UART-DESIGN for quick implementation. -- --- Mit freundlichen Gruessen Jens Weigle, Dept. T62 ======================================================================= ESW, Extel Systems Wedel Gesellschaft fuer Ausruestung mbH | Phone : (+49) 4103 60-3664 Industriestr. 23-33 | FAX : (+49) 4103 60-4513 D-22880 Wedel | e-mail: weigle@tc-wedel.de =======================================================================Article: 4489
Dear Netters: Does anyone know some good pointers on very recent FPGA boards ? (commercial products) I need around 100,000 available gates for my designs (several FPGA chips on the same board). regards, Kimiko -- º¬ËÜ´îÈþ»ÒArticle: 4490
Piet du Toit wrote: > > Scott Kroeger <Scott.Kroeger@mail.mei.com> writes: > Hi All, > > > > Following the instructions offered up by Xilinx, I've gotten the command > > line portion of XACT (5.2.1) running under WinNT 3.51. However it runs > > about 30 times slower than under pure DOS 6.22. Has anyone else > > encountered this problem? Better yet, has anyone else encountered a > > solution?! > > > > Thanks, > > Scott > > I have used the XACT 5.2X software on Windows NT 4.0. > The Place and Routing of the device was fast compared to Win 95. > > Wir2Xnf was very fast on NT 4.0 Beta (5 to 10 times faster that on WIN 95) > On the final release of NT 4.0, Wir2Xnf was very slow. It does a lot of > disk swopping. It sounds as if the hard drive is going to crash. I would > also like know to what the reason for the change in Wir2Xnf behaviour is. Piet, Edit _DEFAULT.PIF in your WINNT(40?) directory. If you haven't allocated enough XMS memory the MS-DOS command prompt the tools will swap excessively. Under NT3.51 the most you can allocate is 16Megs, which is insufficient for large designs. The factory default is 1Meg, which slowed things so much that PPR took all night just to open my input file! To let NT automatically allocate as much XMS memory as needed, replace the default 1024KB with -1. Win95 appears nearly as fast as DOS6.22 to me. Regards, ScottArticle: 4491
Craig Slorach (craigs@elec.gla.ac.uk) wrote: : Hi, : I'm looking for info on any FPGA's currently available where the internal : architecture and programming information is known (ie. where I can write to : programming registers myself instead of having to use manufacturers own : tools). : Does anyone know of such an FPGA (from what I've found in the data books so : far, they talk only about the tools supplied by vendors to produce the : programming code). : Reply by e-mail to craigs@elec.gla.ac.uk would be preferred. : Best regards : Craig Slorach I think that you are currently out of luck here. As far as I'm aware all FPGA manufacturers still seem to treat this info as a dark secret. This probably stems from the early days of FPGAs where the market was so small that the vendors thought the only way to make any money was to charge the earth for highly vendor specific tools. The prices of the tools have dropped sharply but they still haven't opened up their architecures completely to allow 3rd party tool sets. _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 4492
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Article: 4493Here is the reason why there are no UART designs in the libraries: UARTs were invented more than 20 years ago by semiconductor manufacturers like Intel and NSC and Motorola and Zilog, who wanted to sell one standard device to many customers with different requirements ( word length, number of stop bits, parity, etc ). So they made all these parameters programmable, the Zilog SIO then threw in a FIFO and so on. Implementing the functionality in an FPGA for any one useris trivial, but implementing all these programming registers is very inefficient, and is inherently unnecessary in an FPGA. So, we should not have one UART in our library, but dozens, one for each programming option. Otherwise our users would laugh about the inefficiency of the FPGA implementation. Using four CLBs for an 8-bit control register that gets set once and for all, is not an efficient use of an FPGA. Peter Alfke, Xilinx ApplicationsArticle: 4494
Peter Alfke wrote: > > Here is the reason why there are no UART designs in the libraries: > UARTs were invented more than 20 years ago by semiconductor > manufacturers like Intel and NSC and Motorola and Zilog, who wanted to > sell one standard device to many customers with different requirements ( > word length, number of stop bits, parity, etc ). So they made all these > parameters programmable, the Zilog SIO then threw in a FIFO and so on. > > Implementing the functionality in an FPGA for any one useris trivial, > but implementing all these programming registers is very inefficient, > and is inherently unnecessary in an FPGA. So, we should not have one > UART in our library, but dozens, one for each programming option. > Otherwise our users would laugh about the inefficiency of the FPGA > implementation. Using four CLBs for an 8-bit control register that gets > set once and for all, is not an efficient use of an FPGA. > > Peter Alfke, Xilinx Applications Even so, it seems silly to build and debug yet another 8 bit, no parity, 1 stop bit UART. Such things are not trivial and I would really rather buy one than build one. It seems to me that this is the case for virtually every high level function I would like to implement. This problem goes right to the heart of why we are still reinventing the wheel. Well actually an 8 bit loadable wheel with a 4 deep FIFO for reads ... and it's really tight for area, but it only need to run at 1 MHz. (by the way I need it in an obsolete version of viewlogic). What I really need is not 2^gazillion different UART macros, but a UART generator. Same with multipliers, adders etc. Of course, if you built one, it probably wouldn't give me exactly what I need so why bother. On the other hand, I could then blame the macro generator for generating what I asked for and not what I wanted. - Brad TaylorArticle: 4495
Hello: Is anybody using the Actel Designer tools with Windows NT v4.0 Thanks, Jeff Marden jmarden@world.std.comArticle: 4496
Austin Franklin wrote: > You say you're using synthesis? Did you try doing the design in > schematics? exactly my thought! i'm using mentor's autologic II to target VHDL to a xilinx 4025e. earlier this summer, i was dissapointed to discover that counter inference is not that easy to attain. this means that autologic will normally not build a xilinx counter for you using any special architectural primitives or even macros. at best, al2 will use an xblox inc/dec rpm as part of the counter. i'd be surprised if any synth tool can infer something like a cc16ce straight away from your code. fortunately, many synth tools will let you do a target component instantiation in your hdl code. but that's like using a schematic. :) -- _______________________________________________________________________ Lance Gin "off the keyboard Delco Systems - GM Hughes Electronics over the bridge, OFC: 805.961.7567 FAX: 805.961.7739 through the gateway, C43LYG@dso.hac.com nothing but NET!" _______________________________________________________________________Article: 4497
Vincent Himpe (Vincent.Himpe@ping.be) wrote: : hi : I have a small problem. : I have a fairy simple circuit : a 24 bit counter with parallel load : The counter is hooked to a comparator which can either reset the counter , or : make it load a new value. I'd agree with what others have been saying: try using a prescaler. The other possibility is to use CPLD devices. They don't have anywhere near as much logic in them but for small fast designs, they are ideal. I've been using Lattice ispLSI 2064 devices for about a year now. They delay from flip-flop to flip-flop within the device can be as low a 5ns. Hope this helps, Erik ====================================================== Erik de Castro Lopo erikd@zip.com.au ======================================================Article: 4498
Hello,
We are using Allegro to make several complicated PCBs for
our designs. We use extensively Xilinx FPGAs and other chips but up
to now we take care our chips not to exceed ~ 100 pins. Actually when
the package comes in any PGA we can handle it easily with our layout
software and our lab's facilities. But when it comes to greater chip
packages we do not have the necessary experience.
Are there any pointers to info about the handling of these
monster chips? How about the PCB manufacturers, do they normally support
them? How does the package choice affect the total cost of the PCB?
It is true that at least for the Xilinx FPGAs the PGA packages tend to
be a lot more expensive than the respective PLCCs. I would expect this
to be especially true with the more complicated packages.
Also are there any converter sockets available that would
convert a xxx (xxx = a difficult to handle) package to PGA?
Please mail cc: strataki@ics.forth.gr
Thank you in advance,
Manolis Stratakis.
_______________________________________________________________
Manolis Stratakis, E-mail: strataki@ics.forth.gr
Digital Design Engineer, Tel: +30-81-391669
VLSI Design & Computer Architecture Lab, Fax: +30-81-391609
Institute of Computer Science (ICS),
Foundation for Research and Technology - Hellas (FORTH),
P.O.Box 1385, S.T.E.P.-C, Heraklio, Crete, GR 71-110 GREECE.
_______ Home Page: http://www.ics.forth.gr/~strataki __________
Article: 4499>Yes, I'm running the NT version of the Rainport driver. OK. > The software >runs my design to completion, it just takes 26 minutes to place and >route a test design containing 6 CLBs. And as you might imagine my real >design is somewhat more complex. Curious. I assume that, as in most XACT runs, 90+% of the time is being spent in PPR. This program does not use the disk, or indeed the API. It is purely a CPU-intensive process. So I would check the DOS box priority, or whatever governs how much CPU time that app gets under NT. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.
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