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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Feb 1996
2743: 96/02/01: Mike Diack: WTB : Xilinx development system
2747: 96/02/01: Sha Ryu Kim Hofmans: help ! pci-interface
2770: 96/02/05: Trevor Hall: Re: help ! pci-interface
2751: 96/02/01: <sbaker@best.com>: FPGAs challenging the industry
2752: 96/02/02: alain arnaud: Synplify from SYNPLICITY
2754: 96/02/02: Darron May: Re: Synplify from SYNPLICITY
2761: 96/02/03: mccask: Re: Synplify from SYNPLICITY
2759: 96/02/02: Keith Blei: Converting Altera .FIT file to Orcad SDT Symbol File
2762: 96/02/03: STUART CLUBB: Re: AT&T Orca vs Xilinx
2766: 96/02/04: Erik Jessen: Re: AT&T Orca vs Xilinx
2767: 96/02/04: Scott Kroeger: Re: AT&T Orca vs Xilinx
2771: 96/02/05: Don Husby: Re: AT&T Orca vs Xilinx
2768: 96/02/05: Lance Gin: Xilinx FPGA's with Mentor Tools?
2777: 96/02/06: Jeff Cunningham: Re: Xilinx FPGA's with Mentor Tools?
2785: 96/02/07: Les Hughes: Re: Xilinx FPGA's with Mentor Tools?
2830: 96/02/13: Lance Gin: Re: Xilinx FPGA's with Mentor Tools?
2878: 96/02/22: Zeev Yelin: Re: Xilinx FPGA's with Mentor Tools?
2900: 96/02/27: Lance Gin: Re: Xilinx FPGA's with Mentor Tools?
2818: 96/02/12: John Murray: Re: Xilinx FPGA's with Mentor Tools?
2820: 96/02/12: Christopher VanBeek: Re: Xilinx FPGA's with Mentor Tools?
2835: 96/02/14: Lance Gin: Re: Xilinx FPGA's with Mentor Tools?
2837: 96/02/15: Robert Barker: Re: Xilinx FPGA's with Mentor Tools?
2869: 96/02/21: Lance Gin: Re: Xilinx FPGA's with Mentor Tools?
2902: 96/02/27: Les Hughes: Re: Xilinx FPGA's with Mentor Tools?
2772: 96/02/05: Dr. Jason Cong: FPGA'96 Final Program -- It's next week!
2773: 96/02/05: Gerrit Telkamp: PIC16C71 CORE for XC4000 ?
2787: 96/02/07: Dorian Nawrath: Re: PIC16C71 CORE for XC4000 ?
2825: 96/02/13: Les Hughes: Re: PIC16C71 CORE for XC4000 ?
2809: 96/02/11: Eric Ryherd: Re: PIC16C71 CORE for XC4000 ?
2774: 96/02/05: Phil Sailer: Re: help ! pci-interface
2776: 96/02/06: STUART CLUBB: Re: AT&T Orca vs Xilinx
2778: 96/02/06: Jeffrey M. Arnold: FCCM'96 Registration
2779: 96/02/06: Steve Casselman: Test Bounce of comp-arch-fpga@super.org
2781: 96/02/06: Robert J. Brown: Need embeddable on-chip CPU written in Verilog
2782: 96/02/07: Iwan Pekertia: Postgraduate Research Opportunity
2783: 96/02/07: Greg Stenzoski: VLSI DESIGN AND TEST Short Course at Ga Tech
2784: 96/02/07: Mike Diack: FPGA entry for <$1000?
2813: 96/02/12: Tad B Artis: Re: FPGA entry for <$1000?
2821: 96/02/12: David Van den Bout: Re: FPGA entry for <$1000?
2786: 96/02/07: Miranda Baten: FPGA density
2799: 96/02/09: Jan Gray: Re: FPGA density
2827: 96/02/13: Eric Ryherd: Re: FPGA density
2788: 96/02/08: Takashi Hidai: Help ! Xilinx FPGA -> ASIC conversion
2857: 96/02/18: Steve Knapp (Xilinx, Inc.): Re: Help ! Xilinx FPGA -> ASIC conversion
2789: 96/02/08: Hima Bindu Yalamati: High Speed FPGA's and EPLD's
2790: 96/02/08: Hima Bindu Yalamati: Info wanted on high speed(3-5ns) FPGA's
2858: 96/02/18: Steve Knapp (Xilinx, Inc.): Re: Info wanted on high speed(3-5ns) FPGA's
2791: 96/02/09: B. Mitchell Loebel: The PARALLEL Processing Conection - What Is It?
2792: 96/02/09: B. Mitchell Loebel: The PARALLEL Processing Connection - February Meeting Notice
2793: 96/02/09: Steve Casselman: New Reconfigurable Computing Threads.
2803: 96/02/09: Richard Vireday: Re: New Reconfigurable Computing Threads.
2840: 96/02/15: Philip Freidin: Re: New Reconfigurable Computing Threads.
2849: 96/02/16: Jan Gray: Re: New Reconfigurable Computing Threads. -- Java machines
2845: 96/02/16: Achim Gratz: Re: New Reconfigurable Computing Threads.
2855: 96/02/17: Bill Mangione-Smith: Re: New Reconfigurable Computing Threads.
2861: 96/02/19: Achim Gratz: Re: New Reconfigurable Computing Threads.
2794: 96/02/09: Peter Wurbs: Help: Xilinx behavior if Power down
2804: 96/02/09: Scott Kroeger: Re: Help: Xilinx behavior if Power down
2819: 96/02/12: Peter Alfke: Re: Help: Xilinx behavior if Power down
2831: 96/02/14: *: Re: Help: Xilinx behavior if Power down
2795: 96/02/09: Steve Casselman: Performance Benchmarks
2800: 96/02/09: Jan Gray: Re: Performance Benchmarks: Emulating FPGAs Using General Purpose Processors
2801: 96/02/09: Jan Gray: Repost: Performance Benchmarks: Emulating FPGAs Using General Purpose Processors
2796: 96/02/09: Paulo Oliveira: 8274 Inside FPGA?
2810: 96/02/11: Eric Ryherd: Re: 8274 Inside FPGA?
2811: 96/02/12: Applications Division: Re: 8274 Inside FPGA?
2797: 96/02/09: <opworld@worldnet.fr>: Looking for OPAL, PALASM, PLAN
2798: 96/02/09: David Pashley: Re: Looking for OPAL, PALASM, PLAN
2824: 96/02/13: Mike Diack: Re: Looking for OPAL, PALASM, PLAN
2802: 96/02/09: Andy Gulliver: Re: Looking for OPAL, PALASM, PLAN
2805: 96/02/10: HIKIMA Toshio: Xilinx is NOT specified MINIMUM delay -- is it right??
2807: 96/02/10: Scott Kroeger: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2817: 96/02/12: Tony Clark: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2829: 96/02/13: Ray Andraka: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2833: 96/02/14: Peter Wurbs: Re: Xilinx is NOT specified MINIMUM delay -
2843: 96/02/15: Bill Clark: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2822: 96/02/12: Andy Gulliver: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2808: 96/02/10: Neal Becker: Altera Simulation
2816: 96/02/12: Tony Clark: Re: Altera Simulation
2848: 96/02/16: Dean Fitzgerald: Re: Altera Simulation
2871: 96/02/21: Gnuge: Re: Altera Simulation
2814: 96/02/12: Stephan Dubach: uC HDL models
2815: 96/02/12: Barry B. Brey: Re: Help wanted: Addressing PCI memory-mapped device above 16mB
2823: 96/02/13: Balakrishnan Iyer: SIGDA UNIVERSITY BOOTH AT DAC-96, CALL FOR DESIGN DEMOS
2826: 96/02/13: Ian Page: ARM-based ASICs
2834: 96/02/14: Bill Mangione-Smith: Re: ARM-based ASICs
2828: 96/02/13: Mike Diack: FPGA software for <$1000
2832: 96/02/14: SnowBin: Crosspoint Solutions FPGA
2836: 96/02/14: Joe Troxel: re-routing with locked pinout
2838: 96/02/15: Andreas Hofmann: Re: re-routing with locked pinout
2841: 96/02/15: Greg Peek: Re: re-routing with locked pinout
2839: 96/02/15: Christopher G. Holmes: Abel mode for Emacs?
2842: 96/02/15: Alberto Broggi: CFP: Hawaii Intl Conf: ENGINEERING COMPLEX COMPUTER SYSTEMS Track
2844: 96/02/16: Tad B Artis: Re: Xilinx is NOT specified MINIMUM delay -
2852: 96/02/16: Peter Alfke: Re: Xilinx is NOT specified MINIMUM delay -
2853: 96/02/17: Hal Murray: Re: Xilinx is NOT specified MINIMUM delay -
2863: 96/02/19: Peter Alfke: Re: Xilinx is NOT specified MINIMUM delay -
2870: 96/02/21: Tom Keaveny: Re: Xilinx is NOT specified MINIMUM delay -
2874: 96/02/21: Peter Alfke: Re: Xilinx is NOT specified MINIMUM delay -
2883: 96/02/23: Mike Budwey: Re: Xilinx is NOT specified MINIMUM delay -
2907: 96/02/27: Peter Alfke: Re: Xilinx is NOT specified MINIMUM delay -
2912: 96/02/28: Mike Budwey: Re: Xilinx is NOT specified MINIMUM delay -
2917: 96/02/28: Brad Taylor: Re: Xilinx is NOT specified MINIMUM delay -
2946: 96/03/04: Peter Alfke: Re: Xilinx is NOT specified MINIMUM delay -
2897: 96/02/26: Hal Murray: Re: Xilinx is NOT specified MINIMUM delay -
2909: 96/02/28: Tom Keaveny: Re: Xilinx is NOT specified MINIMUM delay -
2913: 96/02/28: Mike Budwey: Re: Xilinx is NOT specified MINIMUM delay -
2859: 96/02/18: Brad Taylor: Use of tracking delays instead of min delays.
2846: 96/02/16: Miranda Baten: ASIC& full-cust versus FPGA-future 5 jears
2847: 96/02/16: <gomez66@eucmax.sim.ucm.es>: BDD Help
2850: 96/02/16: John Schewel: CALL FOR PAPERS
2851: 96/02/16: Steve Casselman: JAVA and beer
2854: 96/02/17: Tim Eccles: Re: JAVA and beer
2862: 96/02/19: Don Husby: Re: JAVA and beer
2856: 96/02/17: Rick Farmer: Lowest power FPGA or PLD
2860: 96/02/17: Scott Kroeger: Re: Lowest power FPGA or PLD
2866: 96/02/20: Peter Alfke: Re: Lowest power FPGA or PLD
2864: 96/02/19: Fred Fierling: Verilog vs. VHDL comparison
2865: 96/02/20: Rick Cox: Re: Verilog vs. VHDL comparison
2891: 96/02/25: Alex Koegel: Re: Verilog vs. VHDL comparison
2894: 96/02/25: Fred Fierling: Re: Verilog vs. VHDL comparison
2867: 96/02/20: Edward Leventhal: Xilinx 8100 Series
2893: 96/02/25: Eric Ryherd: Re: Xilinx 8100 Series
2895: 96/02/26: Steve Knapp (Xilinx, Inc.): Re: Xilinx 8100 Series
2868: 96/02/20: Nalini Ratha: FPGA usage distribution
2872: 96/02/21: Mark Stephens: Giga Operations ... Comments from customers?
2873: 96/02/21: Steve Casselman: Java and reconfigurable computing
2881: 96/02/23: Bill Mangione-Smith: Re: Java and reconfigurable computing
2875: 96/02/21: Andre' DeHon: Floating Point and Reconfigurable Architectures
2880: 96/02/22: Brad Taylor: Re: Floating Point and Reconfigurable Architectures
2887: 96/02/23: Loucas Louca: Re: Floating Point and Reconfigurable Architectures
2908: 96/02/27: Ray Andraka: Re: Floating Point and Reconfigurable Architectures
2882: 96/02/23: Andreas Doering: Re: Floating Point and Reconfigurable Architectures
2884: 96/02/23: G. Herrmannsfeldt: Re: Floating Point and Reconfigurable Architectures
2876: 96/02/22: Steve Casselman: Re: Floating Point and Reconfigurable Architectures
2877: 96/02/22: Mike Butts: Re: Floating Point and Reconfigurable Architectures
2886: 96/02/23: Loucas Louca: Re: Floating Point and Reconfigurable Architectures
2889: 96/02/24: John Lazzaro: Re: Floating Point and Reconfigurable Architectures
2879: 96/02/22: Lance Gin: Re[2]: Xilinx FPGA's with Mentor Tools?
2885: 96/02/24: David Emrich: PCI models synthesized to FPGAs?
2892: 96/02/25: Eric Ryherd: Re: PCI models synthesized to FPGAs?
2915: 96/02/28: <news@logici.com>: Re: PCI models synthesized to FPGAs?
2888: 96/02/24: William A. Gordon: Xilinx 7336 EPLD
2890: 96/02/24: Andre' DeHon: Floating Point on FPGAs -- Numbers are great...
2896: 96/02/26: Peter Fenn: Programming ATMEL config. PROMs ?
2903: 96/02/27: Ingo Cyliax: Re: Programming ATMEL config. PROMs ?
2898: 96/02/26: Marcin Piaskowski: FPGA and testing
2899: 96/02/26: Steve Casselman: Languages for reconfigurable computing.
2904: 96/02/27: Herman Schmit: Re: Languages for reconfigurable computing.
2905: 96/02/27: Brad Hutchings: Re: Languages for reconfigurable computing.
2926: 96/03/01: Dave Galloway: Re: Languages for reconfigurable computing.
2928: 96/03/01: Brad Hutchings: Re: Languages for reconfigurable computing.
2906: 96/02/27: EPV: Re: Languages for reconfigurable computing.
2963: 96/03/06: "Michael Jones": Re: Languages for reconfigurable computing.
2919: 96/02/29: Richard Lazarus: Re: Languages for reconfigurable computing.
2921: 96/02/29: Erik Jessen: Re: Languages for reconfigurable computing.
2942: 96/03/04: Richard Lazarus: Re: Languages for reconfigurable computing.
2956: 96/03/05: Erik Jessen: Re: Languages for reconfigurable computing.
2957: 96/03/05: Erik Jessen: Re: Languages for reconfigurable computing.
2943: 96/03/04: Bill Mangione-Smith: Re: Languages for reconfigurable computing.
2901: 96/02/27: ** Atmel FPGA Apps. :-): Atmel Serial Configuration E2PROMs
2924: 96/03/01: Udi Finkelstein: Re: Atmel Serial Configuration E2PROMs
2910: 96/02/28: Linda Dawson: ANNOUNCE: VHDL Tips and Models on NEW Web Site
2911: 96/02/28: Andreas Koch: Viewlogic WIR or XNF from/to SLIF or BLIF?
2914: 96/02/28: Steve Casselman: High Level Languages
2927: 96/03/01: Brad Hutchings: Re: High Level Languages
2937: 96/03/03: Erik Jessen: Re: High Level Languages
2929: 96/03/01: Brad Hutchings: Re: High Level Languages
2916: 96/02/28: Jenny Pencis: Zycad GF100K FPGA's
2918: 96/02/29: Grad. Lee Dae-Hee: How to multiple-download with Xilinx 4005 ?
2920: 96/02/29: Pete Becker: JEDEC Specification?
2933: 96/03/01: Andy Gulliver: Re: JEDEC Specification?
2988: 96/03/09: Erich Wagner: Re: JEDEC Specification?
2922: 96/02/29: Steve Casselman: Re: Comp.Arch.FPGA
2930: 96/03/01: Peter Alfke: Re: Comp.Arch.FPGA
2935: 96/03/02: John Lazzaro: Re: Comp.Arch.FPGA
2936: 96/03/03: Jeffrey Arnold: Re: Comp.Arch.FPGA
2951: 96/03/05: Stefan Ludwig: Re: Comp.Arch.FPGA
2959: 96/03/05: David Pashley: Re: Comp.Arch.FPGA
2945: 96/03/04: Paul Franklin: Re: Comp.Arch.FPGA
2953: 96/03/05: Bill Mangione-Smith: Re: Comp.Arch.FPGA
3115: 96/04/04: Stephen Bell: Re: Comp.Arch.FPGA
2923: 96/02/29: Don Husby: ORCA and 3.3V logic
2931: 96/03/01: Peter Alfke: Re: ORCA and 3.3V logic
2934: 96/03/01: Don Husby: Re: ORCA and 3.3V logic
2938: 96/03/03: Erik Jessen: Re: ORCA and 3.3V logic
2947: 96/03/05: Peter Alfke: Re: ORCA and 3.3V logic
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