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DavidS8021 wrote: > > I agree with with the assesment of John Cooley. I was a DoD Engineer who > was laid off when "peace broke out." My former company would rather hire > new grads and train them rather than allow their present employees to get > training. <major snip> While I sympathize to some extent with your plight, I have a hard time agreeing with your demands that somebody else should do something for you. There are many excellent and relatively inexpensive texts that will teach you much more than just the "buzz words" you think you need to know. There are inexpensive (under $100) VHDL/Verilog compilers that you can use to teach yourself what you want to learn. There is a wealth of information available absolutely free here on the Web and from a variety of trade publications. While it may seem an unfair generalization, I feel you have only yourself to blame for the fact that your skills are not up to date. The harsh reality of engineering dictates that you constantly keep up your skills or fall by the wayside. Nobody is responsible for your skills but you. Crack the books, and good luck!Article: 2776
Scott Kroeger wrote SK>What about NeoCAD/Xilinx software and Xilinx hardware? Yes indeed, but where do you get NeoCAD supported now? I suppose you wait until Xilinx re-release it. SK>> I have confusing reports as to how many NeoCAD people are working for SK>> ATT; Don't know - I'll try to find out. SK>Also important: how many NeoCAD people are working for Xilinx? Answers on a postcard..... In reply to using FPGA's as a process driver rather than DRAM: Maybe, but AT&T don't make DRAM (do they?), and had the 0.5 micron ORCA 2C series shipping in 1994, with the 40K gate 2C40 in 0.5 micron shipping since February 1995. By using FPGA's as process drivers, AT&T can produce a high performance product, drive costs down, and get to market faster. They also have the advantage that they have their own fab plants. The 0.35 micron 2CxxA series is set to ship in Q2/96. Some competitor products are now on 0.5, but 0.35 gives a crude 50% reduction in chip surface area (another phrase for cost?), plus a rough 30% speed increase. Looks like a reasonable reason for 'making your own'. > As far as who to use for a new person: I'd also take a look at > Altera; engineers I knew who used them seemed to be happy with the > software & support. SK>Agreed. As with Xilinx, you also have a wide range of architectures to SK>look at. SK>EPROM, Flash, SRAM etc. Does AT&T have anything besides SRAM based SK>products? AT&T only has SRAM based products at the moment. I wouldn't suggest AT&T, Xilinx, or any other vendor as a one-stop shop for programmable logic. Just as with processors and other technology, everybody has their place, and some products are 'better' than others dependent on the design in mind. The argument should not be "who's better?" as a blanket statement, but "who best fits my design criteria?". ORCA beats Xilinx in some things, just as Xilinx beat ORCA in others. Be an engineer, evaluate all solutions and chose the one that is right for you and your company. Best Regards Stuart Clubb These are my own musings. I do not speak for my company or AT&T. ========================================= Stuart Clubb, Field Applications Engineer Eurodis Bytech Limited Direct Line: (+44) 1256 602578 Facsimile : (+44) 1256 707162 E-mail : STUART_CLUBB@bytech.win-uk.net ========================================= --- * PowerAccess 1.06 Apathy Error: Don't bother striking any key.Article: 2777
In article <4f3l48$c6o@hacgate2.hac.com> Lance Gin <c43lyg@dso.hac.com> writes: > Is anyone out there designing Xilinx FPGA's using Mentor? I have been for many years. >I'd like to hear your comments on how the Mentor XACT kit is working > out for you. It generally works great, pretty solid and rhobust. > like to hear how your other MGC tools are working out (Autologic, QuickVHDL, I used Autologic about 2.5 years ago targeting xilinxes and it was absolute worthless junk. We ended up ditching it half way through the project and going back to schematics. Since then they have come out with Autologic II, maybe that is better (it couldn't be worse). QuickVHDL is the repackaged Model Technology simulator - I haven't tried it, but have heard only good things about it. If you want to target xilinxes with synthesis, I would look into the Exemplar tool (which is now owned by Mentor, isn't it?), or maybe the Synplicity tool. Both of these are supposed to be good with FPGAs. Above all, if you want to go the synthesis route with FPGAs, plan to spend some real time and effort doing an in-house evaluation on a real design before you buy. > Are you getting the support you need (from Mentor and/or Xilinx)? They both have pretty good phone support. Either they answer your question when you call or will call you back within a couple of hours usually. > ... -JeffArticle: 2778
Attached is the registration information for FCCM'96. For more
information see the FCCM'96 web page at:
http://www.super.org:8000/FPGA/fccm96.html
-Jeffrey M. Arnold
02/6/96
REGISTRATION AND HOTEL INFORMATION
IEEE Symposium on FPGAs for Custom Computing Machines, April 17-19, 1996
Marriott at Napa Valley, Napa, California
3425 Solano, Napa, California 94558
707-253-7433, 707-258-1320 (fax)
Accommodation arrangements should be made directly with the hotel. The
special FCCM'96 rate is $89/night, single or double occupancy. Hotel
rates are subject to applicable state and local taxes, currently
$12/night.
PLEASE TYPE OR PRINT
Name ___________________________________________________________
Address ___________________________________________________________
___________________________________________________________
___________________________________________________________
Email ___________________________________________________________
Phone ____________________________ Fax ________________________
Active IEEE Member Number (Y/N)? ___ Member No: _________________
Registration Fee (see table below): $_____________________________
Credit Card Payers:
Card Holder's Name _____________________________________________
Card Type(MC, Visa) _________________ Exp Date__________________
Card Number _____________________________________________
Signature _____________________________________________
(Credit card payment cannot be made by email--a signature is required)
Student registrants:
I certify that I am a registered student at _______________________
(signed) __________________________________________________________
University address:________________________________________________
The registration fee schedule is as follows. The deadline for
preregistration is March 22, 1996. Regular (nonstudent)
registration includes a copy of the proceedings and lunch on
Wednesday and Thursday, April 17 and 18.
Preregistration Onsite Registration
IEEE Members 220 270
Non-Members 300 360
Students 90 110
All rates are U. S. dollars. Checks must be drawn on a U.S. bank
and should be made payable to IEEE FCCM Symposium. Checks and
registration forms should be mailed to IEEE FCCM Symposium,
c/o Ken Pocek, Intel, Mailstop RN6-18, 2200 Mission College Blvd.,
Santa Clara, CA 95052 (USA).
Article: 2779Please excuse the noise. This is a test of the comp-arch-fpga@super.org reflector. Steve CasselmanArticle: 2780
In article <4eupv8$q91@ixnews3.ix.netcom.com>, Frank Guerino <guerino1@ix.netcom.com> wrote: >Exactly. Buzzwords only fool the people that don't know any better... The latest variation is to propose a project, put every single feature with the right buzzwords into it, and put that on your resume as your current project, with no indication of its state of completion, or indeed even whether it has started or not. That'll get you past all the screeners. It also provides a good laugh for some of us who do the real technical screening. -- Michael M.Y. Hui (speaking privately) myhui@thlayli.newport-beach.ca.usArticle: 2781
I am looking for a CPU, preferably written in Verilog, that is suitable to use as a timing and control sequencer component in a complex ASIC. It should operate with a minimun of a 56 MHz clock, and preferably be a 32-bit architecture. We have already looked at ARM and MIPS standard cells from silicon foundries, but these CPU standard cells have aparently only been used in foundry originated designs so far, and the documentation details are not sufficient for us to proceed with our design. Besides, with these CPUs, we are locked into a single vendor for the chip, and that may not be desirable. If you have, or know of, any such CPU design, please contact me via email or fax. Thank you. -- ----------- "... And the men went up and viewed Ai." [Jos 7:2] ----------- Robert Jay Brown III rj@eli.wariat.org http://eli.wariat.org 1 847 705-0370 Elijah Laboratories Inc; 759 Independence Drive; Suite 5; Palatine IL 60074 ----- M o d e l i n g t h e M e t h o d s o f t h e M i n d ------Article: 2782
Post-Graduate Research Opportunity A Centre of Excellence specialising in the advanced visualisation of computer graphics is to be established in France during the second half of 1996. This centre will be strongly linked to Universities in Europe, Australia, and New Zealand. Graduate students wishing to carry out post-graduate studies in this international environment are invited to apply for research positions - a number of which are currently available. Selected students will be able to spend part or all of their post-graduate study period within the Centre of Excellence. Initially, only students with strong interests in one or more of the following areas of research will be considered: - Electronics (Analogue/Digital) - Software Design and Development - Experimental Physics - Visualisation (Display Systems) - Graphic Art - Computer Hardware Also applications of 3-Dimensional Visualisation to areas such as: - Chemical Structure and Dynamics - Air Traffic Control and Defence - Automation and Control - Medical Imaging - Virtual Prototyping (CAD) - Mathematics Students must have high academic standards, be self motivated and be able to work within a team. For selected students travel expenses will be provided from the country of origin together with a subsistence allowance whilst working within the framework of the centre. Interested parties should forward a detailed Curriculum Vitae together with a letter of application before 15 March 1996 (English prefered) to Dr. B. G. Blundell and Dr. A. J. Schwarz. Department of Electrical and Electronic Engineering, University of Canterbury, Private Bag, Christchurch, New Zealand. Fax: (64-3)3642-761 pekertia@cad.canterbury.ac.nzArticle: 2783
PRESS RELEASE
For Immediate Release
February 6, 1996
UPCOMING SHORT COURSE
^^^^^^^^^^^^^^^^^^^^^
VLSI DESIGN AND TEST
Georgia Institute of Technology
March 18-22, 1996
The Georgia Institute of Technology (Atlanta, GA) is offering a continuing
education short course in the area of very large-scale integrated (VLSI)
circuit design. The lectures focus on the custom and semicustom design,
verification, testing, and packaging of digital and mixed-signal integrated
circuits. A design-intensive laboratory experience provides participants
with hands-on experience designing and verifying a complete mixed-signal
VLSI chip.
For more information:
World-Wide Web: http://www.ee.gatech.edu/academic/conted/VLSI/
Registration or brochure: conted@gatech.edu OR 404-894-2547
AND ALSO http://www.conted.gatech.edu
Course content/requirements: steve.deweerth@ece.gatech.edu
Article: 2784Can anyone suggest any software vendor supplying entry level FPGA tools for less than $US1k ?. I know of the Xilinx $995 package, but it requires additional schematic entry ($$$$$) software. What's out there that wint reqiure me to mortgage the cat ?. SRAM based preferred. MArticle: 2785
Hi,
We teach digital systems using the Mentor / Xilinx s/ware. This consists
of a basic schematic capture - simulation - bit file production -
download to a test rig using xchecker, exercise followed by
similar tasks using VHDL - QuickSim - Autologic - XACT - XChecker
As for QuickVHDL and A/logic II, this was only released for our
OS last month so I haven't installed it yet.
We have a direct support agreement with MGC and I have found
there help excellent. Our Xilinx support is through an academic
scheme and is not as good.
Just for the record, we're using the A3F release and XACT 5.1.1 on
Sun Solaris 2.5. Generally, once bashed into shape by my mate vi ;-)
the system works well.
Hope this helps,
Les.
--
Les Hughes - Applications Group
Computing Services | Phone: +44 (0)181 331 8390 / 8566
University of Greenwich |
Woolwich, London SE18 6PF | E-Mail: L.J.Hughes@greenwich.ac.uk
Article: 2786Dear Sir if today a best FPGA have some 100 k gater density and some 50 % duty,is it possibly to make from one FPGA chip R3000/r3010 or R3081 MP ? I would very pleased for some info .Please post me.Article: 2787
Gerrit Telkamp (telkamp@eis.cs.tu-bs.de) wrote: : Hello, : where can I get a PIC16C71-core (schematic or VHDL) for a XILINX XC4000 design ? : Thank you for every comment, : Gerrit. I'm interested too, DorianArticle: 2788
I am having a problem to translate my FPGA design to an ASIC. Basically, I am giving the original XNF files created from the WIR netlist by wir2xnf command. Then the ASIC vendor was having a difficulty to translate to their format since I am using a lot of Xilinx XBLOX libraries. According to a suggestion I've got from Xilinx guy, I changed to give a different xnf file created from LCA file by lca2xnf. Then, the ASIC vendor found another problems. The problems are timing violation and unproper optimization. I would like to hear the absolute solution for these chaos. Can anyone give me a great suggenstion ?? Thanks, TakashiArticle: 2789
I wanted to find out if anyone has experience working with high speed FPGA's, EPLD's and CPLD's. I am targeting at the tune of 3ns to 5ns. I have looked at parts from Lattice and QuickLogic. Also I would appreciate it if you could share some of your design experiences. Please cc me on all replies. My mailing address is Hima_Yalamati@ccm.sc.intel.com Thanks, Hima.Article: 2790
I wanted to get information on high speed FPGA's, EPLD's and CPLD's. I am targeting 3ns to 5ns. I have been looking at parts from Lattice and QuickLogic. Any input from design experience will be greately appreciated. Can you also cc me on all reply's. My email address is Hima_Yalamati@ccm.sc.intel.com Thanks, Hima.Article: 2791
The PARALLEL Processing Connection is an entrepreneurial association; we mean to assist our members in spawning very successful new businesses involving parallel processing. Our meetings take place on the second Monday of each month at 7:30 PM at Sun Microsystems at 901 South San Antonio Road in Palo Alto, California. Southbound travelers exit 101 at San Antonio ; northbound attendees also exit at San Antonio and take the overpass to the other side of 101. There is an $10 visitor fee for non- members and members ($50 per year) are admitted free. Our phone number is (408) 732-9869 for a recorded message about upcoming meetings; recordings are available for those who can't attend - please inquire. Since the PPC was formed in late 1989 many people have sampled it, found it to be very valuable, and even understand what we're up to. Nonetheless, certain questions persist. Now, in our seventh year of operation, perhaps we can and should clarify some of the issues. For example: Q. What is PPC's raison d'etre? A. The PARALLEL Processing Connection is an entrepreneurial organization intent on facilitating the emergence of new businesses. PPC does not become an active member of any such new entities, ie: is not itself a profit center. Q. The issue of 'why' is perhaps the most perplexing. After all, a $50 annual membership fee is essentially free and how can anything be free in 1996? What's the payoff? For whom? A. That's actually the easiest question of all. Those of us who are active members hope to be a part of new companies that get spun off; the payoff is for all of us -- this is an easy win-win! Since nothing else exists to facilitate hands-on entrepreneurship, we decided to put it together ourselves. Q. How can PPC assist its members? A. PPC is a large technically credible organization. We have close to 100 paid members and a large group of less regular visitors; we mail to approximately 400 engineers and scientists (primarily in Silicon Valley). Major companies need to maintain visibility in the community and connection with it; that makes us an important conduit. PPC's strategy is to trade on that value by collaborating with important companies for the benefit of its members. Thus, as an organization, we have been able to obtain donated hardware, software, and training and we've put together a small development lab for hands-on use of members at our Sunnyvale office. Further, we've been able to negotiate discounts on seminars and hardware/software purchases by members. Most important, alliances such as we described give us an inside opportunity to JOINT VENTURE SITUATIONS. Q. As an attendee, what should I do to enhance my opportunities? A. Participate, participate, participate. Many important industry principals and capital people are in our audience looking for the 'movers'! For further information contact: -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing ConnectionArticle: 2792
February 12th - Dynamically Run-Time Reconfigurable FPGA's At our upcoming meeting Dr. John Gray, Director of Development at Xilinx Development Corporation in Scotland will tell us about an exciting new run time reconfigurable device that his team developed. Their 6200 family of FPGA's supports partial reconfiguration in run time! And quickly - in the order of 100's of microseconds for 15K to 25K gates. Thus, one portion of the device may be undergoing reconfiguration at the same time that the remainder of the device is operating as a co-processor in conjunction with the main CPU. Clock speeds of 25 MHz now and 40-50 MHz within a year. Although PPC's members have been interested in run time reconfigurable hardware for some time now, the inability of software engineers to map their experience into the hardware domain has been a stumbling block; Dr. Gray is well equipped to help our people get through that paradigm shift and his presentation will certainly deal with the issue. There is a significant business opportunity available for PPC members to collaboratively build and market a library of high performance algorithms using this hardware; find out more at our February 12th meeting. The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 San Antonio Road in Palo Alto. This is just off the southbound San Antonio exit of 101. Northbound travelers also exit at San Antonio and take the overpass to the other side of 101. A discussion of member projects currently underway and other issues of interest to entrepreneurs follows immediately thereafter at 9PM. Please be prompt; as usual, we expect a large attendance; don't be left out or left standing. There is a $10 fee for non-members and members will be admitted free. Yearly membership fee is $50. -- B. Mitchell Loebel parallel@netcom.com Director - Strategic Alliances and Partnering 408 732-9869 PARALLEL Processing Connection Xref: netcom.com comp.arch.fpga:2940Article: 2793
The threads on comp.arch.fpga have been anything but threads on reconfigurable computing. I know that many researchers are working in this area but we rarely hear from them. I am loath to talk about my own research since it may result in patents and don't want to get scooped on papers and such. However I would like to start some new threads so we can at least read something other than "where do I get pals." The first and most important thread should be: What kinds of threads should we all talk about? Others might be: What architectures are most appropriate for reconfigurable computing. DeHon etal. thinks it might be a cross between SIMD and FPGAs. What kinds of board architectures are appropriate? Systolic Arrays ala Splash Mesh type like PAM or something else? Do interconnect chips like Aptix and I-Cube belong in the mix or do they just get in the way? Is floating point important or because current FPGAs don't have floating point structures do we just through up our hands and keep to integer math? Will VHDL or Verilog be the programming language for reconfigurable computing or are some of the current C like compliers (tmcc, nlc) really the new wave? Is there any way to trade designs help each other out? What will it take to get reconfigurable computing off the ground? There are many other interesting subjects that we could talk about. Why don't we do it? Steve Casselman Virtual Computer Corp.Article: 2794
Hi Xilinx-Freaks,
I use an output of a XC3195A as a Chip-Select for a SRAM.
The CS-Signal has a pullup to a battery-buffered voltage to
maintain RAM data if the power is down. The FPGA is supplied
by the unbuffered power supply.
It is the normal behavior of the IOB, that it is high impedance
if the power voltage is below a certain level.
But I could measure that the CS-signal is pulled to Low by the
FPGA if the power voltage is near 0.8V. For less than 0.8 V it is
o.k. again.
But the precondition for the pullup to Vbatt is, that the FPGA output
is high impedance over the full range of power supply.
| Vbatt (1.8V if power down)
|
|
|
-
| |
| |
|_|
|---------------| | |------|
| | | CS | |
| FPGA |-------------------| RAM |
| | | |
|---------------| |------|
| |
| |
VCC Vbatt
Is this behavior a property of Xilinx-FPGA's ?
Or is it the problem, that I pull the output to Vbatt while VCC is low ?
Can I avoid this problem ?
Thanks in advance for your help .
Bye,
Peter.
---------------------------------------------------------
Peter Wurbs (MAZ Hamburg GmbH, Dep. Broadband Communication)
Phone: ++40-76629 1771
Fax: ++40-76629 199
e-Mail: pwu@maz-hh.de
---------------------------------------------------------
Article: 2795Another thread that would be good is just for some benchmark data on what people are doing now. For example if someone is doing neural nets you might post: I did a 12 neuron neural net that did 12 Billion connections/sec in 3000 gates and a ALPHA 330MegHz can do them @ 300 Million connections/sec. (no I did not do this it is just an example of the detail of the proposed post) I not even sure what type of reconfigurable computing (except for conferance papers) people are doing out there. Steve Casselman Virtual ComputerArticle: 2796
Hello ! I'm developing a system in which I need a HDLC/LAPD controller to add to my Intel 386 EX processor. Is there a chance to put the controller inside a FPGA? Do you know a family of FPGAs whith such libraries? Thank you in advance, Paulo Oliveira.Article: 2797
Hi, I'm looking for a copy of these software for PLD. I start to use PLD and I appreciate all advices. Thanks Have a nice opworld@worldnet.fr DayArticle: 2798
In article <4ffjrj$olj@aldebaran.sct.fr> opworld@worldnet.fr writes: "Hi, " "I'm looking for a copy of these software for PLD. " "I start to use PLD and I appreciate all advices. " "Thanks Since AMD stopped developing their own software, PALASM has been superceded by MACH-XL3, which is a very good tool, being based on MINC's PLDesigner-XL. I'm not sure how much AMD charge for MACH-XL3, but I imagine it would be good value for a beginner. David PashleyArticle: 2799
In <baten.13.3118E326@hermes1.econ.uni-hamburg.de> baten@hermes1.econ.uni-hamburg.de (Miranda Baten) writes: > >Dear Sir > >if today a best FPGA have some 100 k gater density >and some 50 % duty,is it possibly to make from >one FPGA chip R3000/r3010 or R3081 MP ? > >I would very pleased for some info .Please >post me. R3000: sure. R3081: probably not. (Recall the former had no cache and no FPU whereas the latter has 8K+8K Icache/Dcache, FPU, etc.) It is possible to build a minimal 32-register 32-bit pipelined RISC with a very MIPS-like instruction set in as little as half of a "10,000 gate" XC4010E and run it with a <30 ns instruction clock. "Minimal" meaning no caches, no TLB or memory management, no FP, no barrel shifter, no multiply or divide hardware, 4-stage pipeline (IF/RF/EX/WB, data MEM accesses stall the pipeline), 2- instead of 1- cycle branch delay latencies, wait on all load/store memory accesses, and no write buffers. "Minimal" does still allow for such "necessities" as memory data operand alignment logic to perform byte/halfword/word load/store, and result forwarding. At 30 ns per instruction, you don't really need an Icache or Dcache, although I have a 512 byte (32-entry by 16 byte-line direct-mapped) Icache design which consumes approximately 11 columns of 16 rows of CLBs (e.g. about the other "5000 gates" of a XC4010E). 16 KB of on-chip cache would not fit in the forthcoming XC40125XE nor in the Altera Flex10K family (which can have up to ~3 KB of SRAM in EABs). One could do a very nice on-chip external cache controller with on-chip tags, though. A 16- or 32-entry TLB can be emulated "slowly" by searching through entries in a 16x32 or 32x32 entry SRAM. By adding more "banks" of RAMs and virtual page number comparators and by probing entries more cleverly you can speed this up to taking only a few clocks per lookup on a PTE lookup "miss". A simple 17-cycle 32x32->64 unsigned multiplier is only ~2000 "gates". Anyone care to comment on FP implementations? Jan Gray Redmond, WA
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