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Compare FPGA features and resources
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Threads Starting Jun 2002
43761: 02/06/01: Spam Hater: WTB: Insight SpartanXL Demo board
43762: 02/06/01: Roger King: CMOS camera
43771: 02/06/01: Jay: Re: CMOS camera
43857: 02/06/04: Ryan Henderson: Re: CMOS camera
43767: 02/06/01: Chris Zimman: NIOS GNUPro tool chain + SDK for Linux
43821: 02/06/04: Janusz Raniszewski: Re: NIOS GNUPro tool chain + SDK for Linux
43843: 02/06/04: jerry1111: Re: NIOS GNUPro tool chain + SDK for Linux
43768: 02/06/01: jetmarc: Clock double trigger problem
43770: 02/06/02: Sir Charles W. Shults III: Re: Clock double trigger problem
43782: 02/06/02: jetmarc: Re: Clock double trigger problem
43773: 02/06/02: Falk Brunner: Re: Clock double trigger problem
43779: 02/06/03: Jim Granville: Re: Clock double trigger problem
43812: 02/06/03: Jay: Re: Clock double trigger problem
43769: 02/06/02: Kyle Davis: Looking for FPGA board with USB interface
43772: 02/06/02: Johann Glaser: Re: Looking for FPGA board with USB interface
43787: 02/06/03: Kyle Davis: Re: Looking for FPGA board with USB interface
44014: 02/06/10: Manfred Kraus: Re: Looking for FPGA board with USB interface
43788: 02/06/03: Felix Bertram: Re: Looking for FPGA board with USB interface
43809: 02/06/03: Jay: Re: Looking for FPGA board with USB interface
43828: 02/06/04: Kyle Davis: Re: Looking for FPGA board with USB interface
43837: 02/06/04: Laurent Gauch: Re: Looking for FPGA board with USB interface
43856: 02/06/04: Kyle Davis: Re: Looking for FPGA board with USB interface
44772: 02/06/30: Blake Henry: Re: Looking for FPGA board with USB interface
43781: 02/06/02: harkirat: Interfacing B5 spartan FPGA with a Motorola 68HC11
43805: 02/06/03: Falk Brunner: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
43819: 02/06/03: harkirat: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
43860: 02/06/04: Falk Brunner: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
43941: 02/06/06: harkirat: Re: Interfacing B5 spartan FPGA with a Motorola 68HC11
43784: 02/06/02: Rajat Karol: Engineering Samples for free?
43785: 02/06/03: John Williams: Pipelining
43786: 02/06/03: John Williams: Re: Pipelining
43798: 02/06/03: Brian Philofsky: Re: Pipelining
43818: 02/06/04: John Williams: Re: Pipelining
43789: 02/06/03: sweir: Re: Pipelining
43800: 02/06/03: Jacky Renaux: Re: Pipelining
43806: 02/06/03: Falk Brunner: Re: Pipelining
43808: 02/06/03: Benjamin Todd: Re: Pipelining
43810: 02/06/03: Jay: Re: Pipelining
43790: 02/06/03: Thomas Buerner: FPGA Download via FTP
43793: 02/06/03: Chy Talles: Instantiating Coregen Dual-port RAM in Verilog
43794: 02/06/03: Ralf: Lattice Synario Service Pack
43795: 02/06/03: Michael Boehnel: FPGA destruction possible?
43796: 02/06/03: Prager Roman: Re: FPGA destruction possible?
43804: 02/06/03: Falk Brunner: Re: FPGA destruction possible?
43811: 02/06/03: Nicholas Weaver: Re: FPGA destruction possible?
43824: 02/06/04: John Eaton: Re: FPGA destruction possible?
43859: 02/06/04: Falk Brunner: Re: FPGA destruction possible?
43863: 02/06/04: Rick Filipkiewicz: Re: FPGA destruction possible?
43892: 02/06/05: John Eaton: Re: FPGA destruction possible?
43900: 02/06/05: Rick Filipkiewicz: Re: FPGA destruction possible?
43912: 02/06/06: Hal Murray: Re: FPGA destruction possible?
43844: 02/06/04: Michael Boehnel: Re: FPGA destruction possible?
43847: 02/06/04: Ray Andraka: Re: FPGA destruction possible?
43846: 02/06/04: Ray Andraka: Re: FPGA destruction possible?
43853: 02/06/04: Austin Lesea: FPGA destruction vs power management
43870: 02/06/04: Ray Andraka: Re: FPGA destruction vs power management
43921: 02/06/06: Cemal Coemert (TIP): Re: FPGA destruction vs power management
43927: 02/06/06: Austin Lesea: Re: FPGA destruction vs power management
43928: 02/06/06: Ray Andraka: Re: FPGA destruction vs power management
43854: 02/06/04: Michael Boehnel: Re: FPGA destruction possible?
43869: 02/06/04: Ray Andraka: Re: FPGA destruction possible?
43896: 02/06/05: Steve Casselman: Re: FPGA destruction possible?
43799: 02/06/03: Eyal Shachrai: divide by 5
43802: 02/06/03: Christopher Saunter: Re: divide by 5
43940: 02/06/06: Cyrille de Brébisson: Re: divide by 5
43803: 02/06/03: Kevin Neilson: Re: divide by 5
43807: 02/06/03: Austin Lesea: Re: divide by 5
43822: 02/06/03: John: Re: divide by 5
43823: 02/06/04: Kevin Neilson: Re: divide by 5
43825: 02/06/04: Jim Granville: Re: divide by 5
43832: 02/06/03: John_H: Re: divide by 5
43839: 02/06/04: Rick Filipkiewicz: Re: divide by 5
43855: 02/06/04: John_H: Re: divide by 5
43864: 02/06/04: John: Re: divide by 5
43883: 02/06/05: Rick Filipkiewicz: Re: divide by 5
44000: 02/06/08: Kolja Sulimma: Re: divide by 5
43816: 02/06/03: John_H: Re: divide by 5
43820: 02/06/03: James Horn: Re: divide by 5
43831: 02/06/04: Steve Casselman: Re: divide by 5
43845: 02/06/04: Ray Andraka: Re: divide by 5
43826: 02/06/04: cfk: chipscope
43835: 02/06/04: Matt: Re: chipscope
43838: 02/06/04: Rick Filipkiewicz: Re: chipscope
43904: 02/06/05: Jay: Re: chipscope
43827: 02/06/04: John Williams: FPGAs used to crack Xbox security
43829: 02/06/04: Nicholas Weaver: Re: FPGAs used to crack Xbox security
43833: 02/06/04: Matt: Re: FPGAs used to crack Xbox security
43834: 02/06/04: Matt: Re: FPGAs used to crack Xbox security
43830: 02/06/04: Kelvin XCJ: Sigma-delta DACs.
43836: 02/06/04: F. Modderkolk: Problem with spartan2 vhdl code
43968: 02/06/07: Manfred Kraus: Re: Problem with spartan2 vhdl code
44038: 02/06/10: Benjamin Todd: Re: Problem with spartan2 vhdl code
43842: 02/06/04: Nimrod Mesika: VirtexE DLL Output clock phase
43848: 02/06/04: H.L: Re: VirtexE DLL Output clock phase
43849: 02/06/04: Ray Andraka: Re: VirtexE DLL Output clock phase
43862: 02/06/04: Falk Brunner: Re: VirtexE DLL Output clock phase
43865: 02/06/04: John_H: Re: VirtexE DLL Output clock phase
43868: 02/06/04: Ray Andraka: Re: VirtexE DLL Output clock phase
43885: 02/06/05: Nimrod Mesika: Re: VirtexE DLL Output clock phase
43866: 02/06/04: Cyrille de Brébisson: Hard macro in FPGA, or how to cut a big project in smaller ones
43867: 02/06/04: Ray Andraka: Re: Hard macro in FPGA, or how to cut a big project in smaller ones
43874: 02/06/05: Roger King: burning a design
43898: 02/06/05: Falk Brunner: Re: burning a design
43906: 02/06/05: jetmarc: Re: burning a design
43920: 02/06/06: David DOMINGUEZ: Re: burning a design
44075: 02/06/11: Steve Casselman: Re: burning a design
44078: 02/06/11: Peter Alfke: Re: burning a design
44102: 02/06/11: Jay: Re: burning a design
43875: 02/06/05: John Williams: OFFSET timing contraints
43884: 02/06/05: <hamish@cloud.net.au>: Re: OFFSET timing contraints
43891: 02/06/05: John_H: Re: OFFSET timing contraints
43894: 02/06/05: newman: Re: OFFSET timing contraints
43979: 02/06/07: rickman: Re: OFFSET timing contraints
43981: 02/06/07: John_H: Re: OFFSET timing contraints
44003: 02/06/09: rickman: Re: OFFSET timing contraints
44004: 02/06/09: John_H: Re: OFFSET timing contraints
44009: 02/06/09: Phil Hays: Re: OFFSET timing contraints
43876: 02/06/04: kuldeep: synthesis issue
43881: 02/06/05: Alan Fitch: Re: synthesis issue
43901: 02/06/05: Jay: Re: synthesis issue
43879: 02/06/05: Jerre: Resetting problem on my Xi 4000 due to very slow reset
43882: 02/06/05: Ken Mac: Interpreting coregen footprint output in terms of slices
43886: 02/06/05: Ray Andraka: Re: Interpreting coregen footprint output in terms of slices
43887: 02/06/05: Ken Mac: Re: Interpreting coregen footprint output in terms of slices
43903: 02/06/05: Ray Andraka: Re: Interpreting coregen footprint output in terms of slices
43888: 02/06/05: Eyal Shachrai: virtex 2 : IOBUF tristate plarity
43889: 02/06/05: Austin Lesea: Re: virtex 2 : IOBUF tristate plarity
43895: 02/06/05: Eyal Shachrai: virtex 2 : init values
43897: 02/06/05: John_H: Re: virtex 2 : init values
43905: 02/06/05: Boris and Cristi Sheikman: How to find a big, EEPROM based CPLD in a PGA package?
43935: 02/06/06: Mikhail Matusov: Re: How to find a big, EEPROM based CPLD in a PGA package?
43907: 02/06/06: cfk: IOSTANDARD
43931: 02/06/06: Falk Brunner: Re: IOSTANDARD
43959: 02/06/07: <hamish@cloud.net.au>: Re: IOSTANDARD
43971: 02/06/07: cfk: Re: IOSTANDARD
43908: 02/06/05: Wang Xiao-yun: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
44016: 02/06/10: Prager Roman: Re: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
44032: 02/06/10: Steve Casselman: Re: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
43909: 02/06/06: William Lenihan: xc3042
43913: 02/06/06: Kevin Neilson: Re: xc3042
43916: 02/06/06: F.M. Fontaine: Re: xc3042
43960: 02/06/07: <hamish@cloud.net.au>: Re: xc3042
43963: 02/06/07: Rick: Re: xc3042
43917: 02/06/06: Ray Andraka: Re: xc3042
43934: 02/06/06: Jay: Re: xc3042
43936: 02/06/06: Kevin Neilson: Re: xc3042
43947: 02/06/07: Philip Freidin: Re: xc3042
43948: 02/06/07: Ray Andraka: Re: xc3042
43911: 02/06/06: Damir Danijel Zagar: Xilinx JTAG verification failed
43932: 02/06/06: Falk Brunner: Re: Xilinx JTAG verification failed
43933: 02/06/06: Nick Suttora: Re: Xilinx JTAG verification failed
43980: 02/06/07: Mikhail Matusov: Re: Xilinx JTAG verification failed
44206: 02/06/13: Jon Elson: Re: Xilinx JTAG verification failed
43914: 02/06/06: olivier JEAN: How design a 10 bits counter by using an XILINX FPGA
43930: 02/06/06: Falk Brunner: Re: How design a 10 bits counter by using an XILINX FPGA
43919: 02/06/06: javid: Xilinx ise software?
43925: 02/06/06: Mikhail Matusov: Re: Xilinx ise software?
43946: 02/06/07: Utku Ozcan: Re: Xilinx ise software?
43964: 02/06/07: Mikhail Matusov: Re: Xilinx ise software?
43977: 02/06/07: rickman: Re: Xilinx ise software?
43991: 02/06/08: Ray Andraka: Re: Xilinx ise software?
43922: 02/06/06: Russell: New verilog
43923: 02/06/06: Laurent Gauch: PowerPC Architecture
43924: 02/06/06: Allan Herriman: Re: PowerPC Architecture
43926: 02/06/06: Laurent Gauch: Re: PowerPC Architecture
43955: 02/06/07: Vladislav Vasilenko: Re: PowerPC Architecture
43942: 02/06/06: Rick: Xilinx guided PAR problem
43961: 02/06/07: <hamish@cloud.net.au>: Re: Xilinx guided PAR problem
43962: 02/06/07: Rick: Re: Xilinx guided PAR problem
43943: 02/06/06: Prashant: Quartus v/s Leonardo
43945: 02/06/06: Kevin Brace: Re: Quartus v/s Leonardo
43952: 02/06/07: Paul Baxter: Re: Quartus v/s Leonardo
44514: 02/06/22: Endric Schubert: Re: Quartus v/s Leonardo
44606: 02/06/24: Prashant: Re: Quartus v/s Leonardo
44648: 02/06/25: Fabio G.: Re: Quartus v/s Leonardo
43949: 02/06/07: Steve Meyer: Scientific puzzle of formal circuit verification at next week's DAC
43951: 02/06/07: Kelly Hall: Re: Scientific puzzle of formal circuit verification at next week's DAC
44005: 02/06/09: Steve Meyer: Re: Scientific puzzle of formal circuit verification at next week's DAC
43954: 02/06/07: Noddy: Quick newbie question...
43958: 02/06/07: Torbjörn Stabo: Re: Quick newbie question...
43996: 02/06/08: Hal Murray: Re: Quick newbie question...
43956: 02/06/07: Iain Waugh: Help - Xilinx SRL16 primitive gives 'X's in simulation
43967: 02/06/07: John_H: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
43970: 02/06/07: Ray Andraka: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
44002: 02/06/09: Iain Waugh: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
43957: 02/06/07: Guido Pohl: Re: FPGA destruction vs power management
43965: 02/06/07: Austin Lesea: Thresholds
43966: 02/06/07: Dan Kuechle: VirtexE LVDS problem / question
43972: 02/06/07: Anton Erasmus: Doing Trig Functions in FPGA, EPLD
43974: 02/06/07: Ray Andraka: Re: Doing Trig Functions in FPGA, EPLD
43983: 02/06/07: Kevin Neilson: Re: Doing Trig Functions in FPGA, EPLD
43990: 02/06/08: Ray Andraka: Re: Doing Trig Functions in FPGA, EPLD
43973: 02/06/07: cfk: opencore PCI bridge versus LogiCORE
43993: 02/06/08: Spam Hater: Re: opencore PCI bridge versus LogiCORE
43976: 02/06/07: rickman: Xilinx ISE BaseX... What is it?
43994: 02/06/07: newman: Re: Xilinx ISE BaseX... What is it?
43998: 02/06/08: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44270: 02/06/15: Troy Schultz: Re: Xilinx ISE BaseX... What is it?
44282: 02/06/16: Spam Hater: Re: Xilinx ISE BaseX... What is it?
44285: 02/06/16: Troy Schultz: Re: Xilinx ISE BaseX... What is it?
44290: 02/06/16: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44289: 02/06/16: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44304: 02/06/17: <hamish@cloud.net.au>: Re: Xilinx ISE BaseX... What is it?
44307: 02/06/17: Rick Filipkiewicz: Re: Xilinx ISE BaseX... What is it?
44315: 02/06/17: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44367: 02/06/18: rickman: Re: Xilinx ISE BaseX... What is it?
44375: 02/06/18: Keith R. Williams: Re: Xilinx ISE BaseX... What is it?
44380: 02/06/18: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44291: 02/06/16: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44438: 02/06/20: Spam Hater: Re: Xilinx ISE BaseX... What is it?
44440: 02/06/20: Kevin Brace: Re: Xilinx ISE BaseX... What is it?
44516: 02/06/22: Spam Hater: Re: Xilinx ISE BaseX... What is it?
43978: 02/06/07: Kent Krumvieda: Help!!! Stack SW versus Applications SW
43999: 02/06/07: nickel: F3.1i:Timing warning
44001: 02/06/08: Nesrine: RC 1000 board and Handel-c
44006: 02/06/09: <=?ISO-8859-1?Q?Antonio_Mart=EDnez_=C1lvarez?=>: Do you know a e-mail list where I can make questions about Handel-C
44011: 02/06/10: Jim Granville: Re: Do you know a e-mail list where I can make questions about Handel-C?
44012: 02/06/10: Phil Hays: Re: Do you know a e-mail list where I can make questions about Handel-C?
44007: 02/06/09: Berend Ozceri: Inserting flops to help timing (in Virtex-II)
44008: 02/06/09: John_H: Re: Inserting flops to help timing (in Virtex-II)
44987: 02/07/08: Lee Khoon: Re: Inserting flops to help timing (in Virtex-II)
44013: 02/06/10: Noddy: Cascaded PROMS
44017: 02/06/10: Rick Filipkiewicz: Re: Cascaded PROMS
44018: 02/06/10: Noddy: Re: Cascaded PROMS
44021: 02/06/10: Marc Randolph: Re: Cascaded PROMS
44015: 02/06/10: Laurent Gauch: synplicity/synopsys users: synthesis for A7 TRISCEND
44019: 02/06/10: Noddy: Power supply caps on PCB
44022: 02/06/10: Arash Salarian: Re: Power supply caps on PCB
44031: 02/06/10: John_H: Re: Power supply caps on PCB
44132: 02/06/12: rickman: Re: Power supply caps on PCB
44140: 02/06/12: John_H: Re: Power supply caps on PCB
44192: 02/06/13: rickman: Re: Power supply caps on PCB
44197: 02/06/13: John_H: Re: Power supply caps on PCB
44204: 02/06/14: Jim Granville: Re: Power supply caps on PCB
44209: 02/06/13: John_H: Re: Power supply caps on PCB
44213: 02/06/14: Jim Granville: Re: Power supply caps on PCB
44224: 02/06/14: Martin Thompson: Re: Power supply caps on PCB
44241: 02/06/14: rickman: Re: Power supply caps on PCB
44245: 02/06/14: John_H: Re: Power supply caps on PCB
44295: 02/06/17: rickman: Re: Power supply caps on PCB
44299: 02/06/17: Allan Herriman: Re: Power supply caps on PCB
44436: 02/06/20: cfk: Re: Power supply caps on PCB
44305: 02/06/17: John_H: Re: Power supply caps on PCB
44306: 02/06/17: Falk Brunner: Re: Power supply caps on PCB
44311: 02/06/17: Rick Filipkiewicz: Re: Power supply caps on PCB
44312: 02/06/17: Falk Brunner: Re: Power supply caps on PCB
44478: 02/06/20: John Larkin: Re: Power supply caps on PCB
44020: 02/06/10: Ken Mac: where did my MHz go!
44024: 02/06/10: Rick Filipkiewicz: Re: where did my MHz go!
44026: 02/06/10: Ken Mac: Re: where did my MHz go!
44027: 02/06/10: Ray Andraka: Re: where did my MHz go!
44028: 02/06/10: Ken Mac: Re: where did my MHz go!
44047: 02/06/11: XU QIJUN: Re: where did my MHz go!
44041: 02/06/10: Davis Moore: Re: where did my MHz go!
44077: 02/06/11: Jay: Re: where did my MHz go!
44116: 02/06/12: Ken Mac: Re: where did my MHz go!
44137: 02/06/12: Jay: Re: where did my MHz go!
44117: 02/06/12: Ken Mac: Re: where did my MHz go!
44023: 02/06/10: Piotr: OFFSET constraint for internal clock
44080: 02/06/11: Jay: Re: OFFSET constraint for internal clock
44088: 02/06/11: Utku Ozcan: Re: OFFSET constraint for internal clock
44131: 02/06/12: rickman: Re: OFFSET constraint for internal clock
44025: 02/06/10: Jerry Francis: Virtex 2 Pro Board
44029: 02/06/10: Austin Lesea: Re: Virtex 2 Pro Board
44030: 02/06/10: Goteb: Information about FPGA
44035: 02/06/10: Kate: Re: Information about FPGA
44046: 02/06/10: Al Williams: Re: Information about FPGA
44048: 02/06/11: Felix Bertram: Re: Information about FPGA
44033: 02/06/10: Rick Filipkiewicz: synthesis query: Xilinx + Synplify
44037: 02/06/10: John_H: Re: synthesis query: Xilinx + Synplify
44042: 02/06/10: Rick Filipkiewicz: Re: synthesis query: Xilinx + Synplify
44043: 02/06/10: John_H: Re: synthesis query: Xilinx + Synplify
44051: 02/06/11: Rick Filipkiewicz: Re: synthesis query: Xilinx + Synplify
44050: 02/06/11: Rick Filipkiewicz: Re: synthesis query: Xilinx + Synplify
44065: 02/06/11: John_H: Re: synthesis query: Xilinx + Synplify
44076: 02/06/11: John_H: Re: synthesis query: Xilinx + Synplify
44082: 02/06/11: Rick Filipkiewicz: Re: synthesis query: Xilinx + Synplify
44086: 02/06/11: John_H: Re: synthesis query: Xilinx + Synplify
44110: 02/06/12: Ray Andraka: Re: synthesis query: Xilinx + Synplify
44139: 02/06/12: John_H: Re: synthesis query: Xilinx + Synplify
44155: 02/06/12: Ray Andraka: Re: synthesis query: Xilinx + Synplify
44147: 02/06/12: Rick Filipkiewicz: Re: synthesis query: Xilinx + Synplify
44034: 02/06/10: SierraTech (NOSPAM): ALTERA EPC16 Configuration in MAX+PLUS II V10.1
44036: 02/06/10: Thijs: programming xc3030 using atmel's ATDH2225 programmer cable
44040: 02/06/10: Ray Andraka: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44049: 02/06/11: Thijs: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44058: 02/06/11: Ray Andraka: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44118: 02/06/12: Thijs: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44067: 02/06/11: newman: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44138: 02/06/12: Werner Dreher: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44039: 02/06/10: Jim Raynor: Spartan II E -- BUFGDLL
44044: 02/06/10: Jim Raynor: BUFGDLL again
44045: 02/06/10: Ray Andraka: Re: BUFGDLL again
44052: 02/06/11: Paul: IBIS to Spice Translation (part1)
44094: 02/06/11: Austin Lesea: Re: IBIS to Spice Translation (part1)
44105: 02/06/11: Paul: Re: IBIS to Spice Translation (part1)
44106: 02/06/11: Paul: Re: IBIS to Spice Translation (part1)
44128: 02/06/12: Austin Lesea: Re: IBIS to Spice Translation (part1)
44053: 02/06/11: Benjamin Todd: Problems initialising an FPGA - SPARTAN II
44064: 02/06/11: Damir Danijel Zagar: Re: Problems initialising an FPGA - SPARTAN II
44066: 02/06/11: Benjamin Todd: Re: Problems initialising an FPGA - SPARTAN II
44083: 02/06/11: Lorenzo Lutti: Re: Problems initialising an FPGA - SPARTAN II
44085: 02/06/11: John_H: Re: Problems initialising an FPGA - SPARTAN II
44091: 02/06/11: Peter Alfke: Re: Problems initialising an FPGA - SPARTAN II
44124: 02/06/12: Lorenzo Lutti: Re: Problems initialising an FPGA - SPARTAN II
44054: 02/06/11: Paul: IBIS to Spice Translation (part2)
44055: 02/06/11: Paul: IBIS to Spice Translation (part2)
44056: 02/06/11: Ken Mac: surely this is mad? (clock rate issues)
44057: 02/06/11: Kevin Neilson: Re: surely this is mad? (clock rate issues)
44059: 02/06/11: Rick Filipkiewicz: Re: surely this is mad? (clock rate issues)
44062: 02/06/11: Ken Mac: Re: surely this is mad? (clock rate issues)
44070: 02/06/11: John_H: Re: surely this is mad? (clock rate issues)
44060: 02/06/11: Jerre: How to implement synchronous reset on an FPGA
44061: 02/06/11: Iwo Mergler: Busses & permutations
44069: 02/06/11: John_H: Re: Busses & permutations
44186: 02/06/13: Iwo Mergler: Re: Busses & permutations
44191: 02/06/13: John_H: Re: Busses & permutations
44103: 02/06/11: Jay: Re: Busses & permutations
44187: 02/06/13: Iwo Mergler: Re: Busses & permutations
44063: 02/06/11: Roger King: 20,000 gates?
44068: 02/06/11: John_H: Re: 20,000 gates?
44072: 02/06/11: Roger King: Re: 20,000 gates?
44073: 02/06/11: John_H: Re: 20,000 gates?
44071: 02/06/11: Falk Brunner: Re: 20,000 gates?
44097: 02/06/11: Roger King: Re: 20,000 gates?
44099: 02/06/11: Peter Alfke: Re: 20,000 gates?
44100: 02/06/11: Roger King: Re: 20,000 gates?
44134: 02/06/12: Falk Brunner: Re: 20,000 gates?
44198: 02/06/13: Nicholas Weaver: Re: 20,000 gates?
44207: 02/06/14: Tony Burch: Re: 20,000 gates?
44219: 02/06/14: <samg@codenet.net>: Re: 20,000 gates?
44220: 02/06/14: Peter Alfke: Re: 20,000 gates?
44226: 02/06/14: Rick Filipkiewicz: Re: 20,000 gates?
44109: 02/06/12: Ray Andraka: Re: 20,000 gates?
44146: 02/06/12: Tyler Reed: Re: 20,000 gates?
44150: 02/06/12: Peter Alfke: Re: 20,000 gates?
44163: 02/06/13: Ray Andraka: Re: 20,000 gates?
44074: 02/06/11: Mauricio Lange: Asynchronous Perhiperal Mode
44079: 02/06/11: Peter Alfke: Re: Asynchronous Perhiperal Mode
44126: 02/06/12: Mauricio Lange: Re: Asynchronous Perhiperal Mode
44081: 02/06/11: Pat Ford: fpga and ultra highspeed counters
44084: 02/06/11: Peter Alfke: Re: fpga and ultra highspeed counters
44092: 02/06/12: Jim Granville: Re: fpga and ultra highspeed counters
44098: 02/06/11: Peter Alfke: Re: fpga and ultra highspeed counters
44185: 02/06/13: Paul Butler: Re: fpga and ultra highspeed counters
44278: 02/06/16: Peter Alfke: Re: fpga and ultra highspeed counters
44095: 02/06/11: John_H: Re: fpga and ultra highspeed counters
44201: 02/06/13: Jay: Re: fpga and ultra highspeed counters
44233: 02/06/14: Pat Ford: Re: fpga and ultra highspeed counters
44288: 02/06/16: Kolja Sulimma: Re: fpga and ultra highspeed counters
44480: 02/06/20: Jay: Re: fpga and ultra highspeed counters
44504: 02/06/21: Pat Ford: Re: fpga and ultra highspeed counters
44524: 02/06/22: Kolja Sulimma: Re: fpga and ultra highspeed counters
44087: 02/06/11: Jerry Francis: Visual SourceSafe and VHDL files
44115: 02/06/12: Muzaffer Kal: Re: Visual SourceSafe and VHDL files
44089: 02/06/11: Paul: IBIS to Spice Translation (part2)
44090: 02/06/11: Jim Raynor: Multi Pass PAR
44188: 02/06/13: Benjamin Todd: Re: Multi Pass PAR
44093: 02/06/11: Rick Filipkiewicz: MAP problem with RLOC'ed macros
44108: 02/06/12: Ray Andraka: Re: MAP problem with RLOC'ed macros
44121: 02/06/12: Rick Filipkiewicz: Re: MAP problem with RLOC'ed macros
44144: 02/06/12: Rick Filipkiewicz: Re: MAP problem with RLOC'ed macros
44149: 02/06/12: John_H: Re: MAP problem with RLOC'ed macros
44151: 02/06/12: John_H: Re: MAP problem with RLOC'ed macros
44168: 02/06/12: Brian Davis: Re: MAP problem with RLOC'ed macros
44169: 02/06/13: Ray Andraka: Re: MAP problem with RLOC'ed macros
44190: 02/06/13: John_H: Re: MAP problem with RLOC'ed macros
44202: 02/06/13: Ray Andraka: Re: MAP problem with RLOC'ed macros
44212: 02/06/14: Rick Filipkiewicz: Re: MAP problem with RLOC'ed macros
44216: 02/06/14: John_H: Re: MAP problem with RLOC'ed macros
44218: 02/06/14: Ray Andraka: Re: MAP problem with RLOC'ed macros
44217: 02/06/14: Ray Andraka: Re: MAP problem with RLOC'ed macros
44227: 02/06/14: Rick Filipkiewicz: Re: MAP problem with RLOC'ed macros
44235: 02/06/14: <hamish@cloud.net.au>: Re: MAP problem with RLOC'ed macros
44250: 02/06/14: Rick Filipkiewicz: Re: MAP problem with RLOC'ed macros
44247: 02/06/14: cfk: Re: MAP problem with RLOC'ed macros
44249: 02/06/14: Rick Filipkiewicz: Re: MAP problem with RLOC'ed macros
44236: 02/06/14: jakab tanko: Re: MAP problem with RLOC'ed macros
44239: 02/06/14: John_H: Re: MAP problem with RLOC'ed macros
44240: 02/06/14: Ray Andraka: Re: MAP problem with RLOC'ed macros
44243: 02/06/14: Nicholas Weaver: Re: MAP problem with RLOC'ed macros
44189: 02/06/13: John_H: Re: MAP problem with RLOC'ed macros
44096: 02/06/11: Huy Nguyen: LVPECL open-emitter interface to Virtex-II
44142: 02/06/12: Tom Burgess: Re: LVPECL open-emitter interface to Virtex-II
44251: 02/06/14: Huy Nguyen: Re: LVPECL open-emitter interface to Virtex-II
44101: 02/06/11: Erik Brunvand: Synopsys, Spartan2, and Viewsim...
44104: 02/06/11: Patrick Robin: virtual ground in Xilinx XC9572 CPLD?
44125: 02/06/12: Al Williams: Re: virtual ground in Xilinx XC9572 CPLD?
44127: 02/06/12: Patrick Robin: Re: virtual ground in Xilinx XC9572 CPLD?
44136: 02/06/12: Rick Filipkiewicz: Re: virtual ground in Xilinx XC9572 CPLD?
44141: 02/06/12: Jay: Re: virtual ground in Xilinx XC9572 CPLD?
44107: 02/06/11: Paul: IBIS to Spice translation (part2)
44111: 02/06/11: Peter Brenner: Searching for high performance PLD
44112: 02/06/12: Jim Granville: Re: Searching for high performance PLD
44157: 02/06/12: Peter Brenner: Re: Searching for high performance PLD
44162: 02/06/13: Jim Granville: Re: Searching for high performance PLD
44158: 02/06/12: Peter Brenner: Re: Searching for high performance PLD
44199: 02/06/13: Falk Brunner: Re: Searching for high performance PLD
44113: 02/06/11: jaideep: Digital FM demodulator in FPGA
44114: 02/06/12: Noddy: Re: Digital FM demodulator in FPGA
44119: 02/06/12: jaideep: Digital FM demodulator in FPGA-continue
44120: 02/06/12: Allan Herriman: Re: Digital FM demodulator in FPGA-continue
44122: 02/06/12: Bevan Weiss: Re: Digital FM demodulator in FPGA-continue
44129: 02/06/12: John_H: Re: Digital FM demodulator in FPGA-continue
44130: 02/06/12: Austin Lesea: Re: Digital FM demodulator in FPGA-continue
44143: 02/06/12: Kevin Neilson: Re: Digital FM demodulator in FPGA-continue
44161: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44160: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44172: 02/06/13: Noddy: Re: Digital FM demodulator in FPGA-continue
44179: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44145: 02/06/13: Bevan Weiss: Re: Digital FM demodulator in FPGA-continue
44148: 02/06/12: John_H: Re: Digital FM demodulator in FPGA-continue
44123: 02/06/12: Ulf Samuelsson: Re: Digital FM demodulator in FPGA-continue
44167: 02/06/12: jaideep: Re: Digital FM demodulator in FPGA-continue
44159: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44171: 02/06/13: Bevan Weiss: Re: Digital FM demodulator in FPGA-continue
44180: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44174: 02/06/13: Noddy: Re: Digital FM demodulator in FPGA-continue
44181: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44175: 02/06/13: XU QIJUN: Re: Digital FM demodulator in FPGA-continue
44182: 02/06/13: Ray Andraka: Re: Digital FM demodulator in FPGA-continue
44133: 02/06/12: Lasse Langwadt Christensen: constrains for external memory
44196: 02/06/13: Jay: Re: constrains for external memory
44135: 02/06/12: Petter Gustad: MicroBlaze uClinux port?
44320: 02/06/17: Jesse Kempa: Re: MicroBlaze uClinux port?
44333: 02/06/18: Petter Gustad: Re: MicroBlaze uClinux port?
44153: 02/06/13: John Williams: clock gating by any other name...
44165: 02/06/13: Peter Alfke: Re: clock gating by any other name...
44166: 02/06/13: John Williams: Re: clock gating by any other name...
44195: 02/06/13: Jay: Re: clock gating by any other name...
44260: 02/06/14: John: Re: clock gating by any other name...
44154: 02/06/12: hristo: ISE4.2i patch is it the same for F4.2i
44156: 02/06/12: capnx01: Re: How to estimate the cost of writing EMBEDDED software ?
44170: 02/06/13: John Lee: About Programming CPLD using Xilinx Programming Cable IV
44376: 02/06/18: Brendan Bridgford: Re: About Programming CPLD using Xilinx Programming Cable IV
44173: 02/06/13: Michael J.: Altera APEX reconfigurates endlessly
44200: 02/06/13: Ben Twijnstra: Re: Altera APEX reconfigurates endlessly
44203: 02/06/13: Mike: Re: Altera APEX reconfigurates endlessly
44223: 02/06/14: Michael J.: Re: Altera APEX reconfigurates endlessly
44176: 02/06/13: David de Andrés Martínez: Virtex Readback
44254: 02/06/14: Steve Casselman: Re: Virtex Readback
44177: 02/06/13: David R Brooks: Xilinx primitives & ModelSim
44178: 02/06/13: Allan Herriman: Re: Xilinx primitives & ModelSim
44183: 02/06/13: Ray Andraka: Re: Xilinx primitives & ModelSim
44221: 02/06/14: David R Brooks: Re: Xilinx primitives & ModelSim
44231: 02/06/14: Ray Andraka: Re: Xilinx primitives & ModelSim
44272: 02/06/16: David R Brooks: Re: Xilinx primitives & ModelSim
44237: 02/06/14: Michael Rhotert: Re: Xilinx primitives & ModelSim
44184: 02/06/13: Clark Pope: Multiple constraints, same net?
44262: 02/06/15: Victor Hannak: Re: Multiple constraints, same net?
44993: 02/07/09: seabedj163.com: Re: Multiple constraints, same net?
44995: 02/07/09: Stephan Neuhold: Re: Multiple constraints, same net?
44193: 02/06/13: Hristo Stevic: compatibility between F3.1 and F4.1
44208: 02/06/14: John Williams: Re: compatibility between F3.1 and F4.1
44194: 02/06/13: Jee Chi: what's difference between .edf and .edn
44205: 02/06/14: Holger Kleinegraeber: must signals to ram come from a register?
44210: 02/06/13: Peter Alfke: Re: must signals to ram come from a register?
44211: 02/06/13: Nicholas Weaver: Re: must signals to ram come from a register?
44269: 02/06/15: Holger Kleinegraeber: Re: must signals to ram come from a register?
44214: 02/06/13: Ananth: new to fpga.
44215: 02/06/14: Peter Alfke: Re: new to fpga.
44323: 02/06/17: Al Williams: Re: new to fpga.
44222: 02/06/13: Arena.Yang: I am a novice at FPGA.Please take care of me.THX!
44225: 02/06/14: Kevin Brace: Can someone who is not a student use Xilinx Foundation 2.1i Student
44232: 02/06/14: Leon Heller: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student Edition?
44244: 02/06/14: Winnie Hsu: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student
44279: 02/06/15: Kevin Brace: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student
44228: 02/06/14: tony: 6505 ip core
44229: 02/06/14: Andreas Wassatsch: ISE 4.2i and Synopsys Design Compiler
44230: 02/06/14: Andreas Wassatsch: Re: ISE 4.2i and Synopsys Design Compiler
44234: 02/06/14: Minlin Fan: BGA package
44238: 02/06/14: John_H: Re: BGA package
44242: 02/06/14: Minlin Fan: Xilinx JTAG embedded programming
44246: 02/06/14: cfk: GCK input routing
44261: 02/06/15: Victor Hannak: Re: GCK input routing
44248: 02/06/14: Domagoj: DCT in fpga ?
44252: 02/06/14: Pouya Razavi: TTL library in Xilinx?
44255: 02/06/14: Ray Andraka: Re: TTL library in Xilinx?
44256: 02/06/14: Ray Andraka: Re: TTL library in Xilinx?
44266: 02/06/15: Leon Heller: Re: TTL library in Xilinx?
44267: 02/06/15: Peter Alfke: Re: TTL library in Xilinx?
44268: 02/06/15: Leon Heller: Re: TTL library in Xilinx?
44271: 02/06/15: Hal Murray: Re: TTL library in Xilinx?
44280: 02/06/16: Rick Filipkiewicz: Re: TTL library in Xilinx?
44253: 02/06/14: Derrick Cheng: Xilinx newest version?
44257: 02/06/14: Ray Andraka: Re: Xilinx newest version?
44263: 02/06/15: Victor Hannak: Dividing constants in Synplicity
44265: 02/06/15: VhdlCohen: Re: Dividing constants in Synplicity
44264: 02/06/15: yhl: Lattice download cable schematic?
44273: 02/06/15: Jim Stewart: Stupid WebPack question
44274: 02/06/15: cfk: Re: Stupid WebPack question
44275: 02/06/15: Jim Stewart: Re: Stupid WebPack question
44277: 02/06/15: Jim Stewart: Re: Stupid WebPack question
44281: 02/06/16: David R Brooks: Re: Stupid WebPack question
44276: 02/06/15: Pat Ford: Strathnuey kit from Nallatech
44283: 02/06/16: Sukandar Kartadinata: Problems programming a XCR3128XL with Webpack4.2
44284: 02/06/16: Roger King: Which is greater?
44287: 02/06/16: Falk Brunner: Re: Which is greater?
44292: 02/06/16: Peter Alfke: Re: Which is greater?
44286: 02/06/16: Wolfgang Pieper: core generator / where is it?
44293: 02/06/16: newman: Re: core generator / where is it?
44294: 02/06/16: mac teh knife: new computer
44345: 02/06/18: Pete: Re: new computer
44390: 02/06/19: Mark: Re: new computer
44418: 02/06/19: rickman: Re: new computer
44420: 02/06/19: Nicholas Weaver: Re: new computer
44526: 02/06/22: rickman: Re: new computer
44529: 02/06/22: Neil Franklin: Re: new computer
44543: 02/06/23: rickman: Re: new computer
44550: 02/06/23: Nicholas Weaver: Re: new computer
44553: 02/06/23: rickman: Re: new computer
44557: 02/06/23: Neil Franklin: Re: new computer
44567: 02/06/24: rickman: Re: new computer
44586: 02/06/24: Nicholas Weaver: Re: new computer
44609: 02/06/24: Neil Franklin: Re: new computer
44565: 02/06/24: Nicholas Weaver: Re: new computer
44566: 02/06/24: rickman: Re: new computer
44442: 02/06/20: Mark: Re: new computer
44296: 02/06/17: Naohiko Shimizu: [ANN] Free SFL to Verilog converter (with 6502/z80 core)
44351: 02/06/18: <nshimizu_no_spam@bosei.cc.u-tokai.ac.jp>: Re: [ANN] Free SFL to Verilog converter (with 6502/z80 core)
44297: 02/06/17: H.L: Many thanks to everyone!!
44298: 02/06/17: Ken Mac: Xilinx System Generator FIR vs Core Generator FIR
44303: 02/06/17: Ray Andraka: Re: Xilinx System Generator FIR vs Core Generator FIR
44300: 02/06/17: Peter Buschhorn: impacts batch mode....
44346: 02/06/18: newman: Re: impacts batch mode....
44392: 02/06/19: Peter Buschhorn: Re: impacts batch mode....
44301: 02/06/17: <=?ISO-8859-1?Q?Antonio_Mart=EDnez_=C1lvarez?=>: Does anyone have experience with HandelC and Celoxica's RC1000 with
44485: 02/06/21: Ash: Re: Does anyone have experience with HandelC and Celoxica's RC1000 with VirtexE
44302: 02/06/17: Manfred Kraus: Which Synthesis tool for XILINX
44314: 02/06/17: Ray Andraka: Re: Which Synthesis tool for XILINX
44317: 02/06/17: John_H: Re: Which Synthesis tool for XILINX
44319: 02/06/17: John_H: Re: Which Synthesis tool for XILINX
44336: 02/06/18: Ray Andraka: Re: Which Synthesis tool for XILINX
44358: 02/06/18: John_H: Re: Which Synthesis tool for XILINX
44362: 02/06/18: Ray Andraka: Re: Which Synthesis tool for XILINX
44316: 02/06/17: Kevin Brace: Re: Which Synthesis tool for XILINX
44338: 02/06/18: Manfred Kraus: Re: Which Synthesis tool for XILINX
44381: 02/06/18: Kevin Brace: Re: Which Synthesis tool for XILINX
44327: 02/06/17: mac teh knife: Re: Which Synthesis tool for XILINX
44339: 02/06/18: Manfred Kraus: Re: Which Synthesis tool for XILINX
44308: 02/06/17: doug: lfsr and implementation and alpha
44349: 02/06/18: newman: Re: lfsr and implementation and alpha
44359: 02/06/18: doug: Re: lfsr and implementation and alpha
44309: 02/06/17: FEMI: Pls Recommend a Development Board
44330: 02/06/18: Tony Burch: Re: Pls Recommend a Development Board
44332: 02/06/18: Felix Bertram: Re: Pls Recommend a Development Board
44347: 02/06/18: Manfred Kraus: Re: Pls Recommend a Development Board - Have you checked out the CESYS boards ?
44310: 02/06/17: FEMI: Advice on xilinx development board(kit)
44313: 02/06/17: Jim Stewart: Another stupid WebPack question
44364: 02/06/18: Falk Brunner: Re: Another stupid WebPack question
44318: 02/06/17: David Rogoff: Internal oscillator in CPLD?
44321: 02/06/17: John_H: Re: Internal oscillator in CPLD?
44322: 02/06/18: James Kennedy: Re: Internal oscillator in CPLD?
44324: 02/06/18: Jim Granville: Re: Internal oscillator in CPLD?
44326: 02/06/18: Peter Alfke: Re: Internal oscillator in CPLD?
44329: 02/06/17: John_H: Re: Internal oscillator in CPLD?
44379: 02/06/18: Leon Heller: Re: Internal oscillator in CPLD?
44325: 02/06/17: Farhad Abdolian: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44388: 02/06/19: Spam Hater: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44426: 02/06/19: Steve Casselman: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44434: 02/06/19: Farhad Abdolian: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44461: 02/06/20: jakab tanko: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44479: 02/06/20: Jay: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44513: 02/06/21: Jeff Mock: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44517: 02/06/22: Spam Hater: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44391: 02/06/19: Kevin Brace: Re: 12 years experience in Digital HW/ FPGA design, looking for job in
44538: 02/06/22: Magnus Homann: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
44328: 02/06/17: Nagaraj: what's the use of BlockRAM
44352: 02/06/18: newman: Re: what's the use of BlockRAM
44356: 02/06/18: Peter Alfke: Re: what's the use of BlockRAM
44387: 02/06/18: Nagaraj: Re: what's the use of BlockRAM
44403: 02/06/19: rickman: Re: what's the use of BlockRAM
44437: 02/06/19: Nagaraj: Re: what's the use of BlockRAM
44454: 02/06/20: rickman: Re: what's the use of BlockRAM
44473: 02/06/21: Ray Andraka: Re: what's the use of BlockRAM
44411: 02/06/19: Peter Alfke: Re: what's the use of BlockRAM
44360: 02/06/18: Domagoj: Re: what's the use of BlockRAM
44365: 02/06/18: Falk Brunner: Re: what's the use of BlockRAM
44370: 02/06/18: Rick Filipkiewicz: Re: what's the use of BlockRAM
44368: 02/06/18: Kolja Sulimma: Re: what's the use of BlockRAM
44331: 02/06/17: <ted_jmt@zapta.com>: Seeking CPLD/FPGA recomendation
44337: 02/06/18: Jim Granville: Re: Seeking CPLD/FPGA recomendation
44348: 02/06/18: <ted_jmt@zapta.com>: Re: Seeking CPLD/FPGA recomendation
44354: 02/06/18: Austin Lesea: Re: Seeking CPLD/FPGA recomendation
44355: 02/06/18: <ted_jmt@zapta.com>: Re: Seeking CPLD/FPGA recomendation
44357: 02/06/18: Austin Lesea: Re: Seeking CPLD/FPGA recomendation
44576: 02/06/24: Santiago de Pablo: Re: Seeking CPLD/FPGA recomendation
44369: 02/06/18: Kolja Sulimma: Re: Seeking CPLD/FPGA recomendation
44378: 02/06/19: Jim Granville: Re: Seeking CPLD/FPGA recomendation
44334: 02/06/18: digari: hierarchy in Altera FPGAs
44472: 02/06/21: Ray Andraka: Re: hierarchy in Altera FPGAs
44335: 02/06/18: Jerre: How to deal with a slowly rising reset signal?
44340: 02/06/18: Jonathan Bromley: Re: How to deal with a slowly rising reset signal?
44341: 02/06/18: hull: Initial of virtex II block ram
44343: 02/06/18: Benjamin Todd: Re: Initial of virtex II block ram
44344: 02/06/18: Benjamin Todd: Re: Initial of virtex II block ram
44374: 02/06/18: Rick Filipkiewicz: Re: Initial of virtex II block ram
44563: 02/06/24: Philip Freidin: Re: Initial of virtex II block ram
44342: 02/06/18: =?iso-8859-1?Q?St=E9phane?= Guyetant: 5V tolerance
44353: 02/06/18: Austin Lesea: Re: 5V tolerance
44361: 02/06/18: =?iso-8859-1?Q?St=E9phane?= Guyetant: Re: 5V tolerance
44377: 02/06/18: Austin Lesea: Re: 5V tolerance
44452: 02/06/20: Austin Franklin: Re: 5V tolerance
44458: 02/06/20: Ray Andraka: Re: 5V tolerance
44464: 02/06/20: Theron Hicks: Re: 5V tolerance
44471: 02/06/21: Ray Andraka: Re: 5V tolerance
44506: 02/06/21: Theron Hicks: Re: 5V tolerance
44676: 02/06/26: rickman: Re: 5V tolerance
44677: 02/06/26: Ray Andraka: Re: 5V tolerance
44679: 02/06/27: Jim Granville: Re: 5V tolerance
44686: 02/06/27: rickman: Re: 5V tolerance
44701: 02/06/27: Peter Alfke: Re: 5V tolerance
44707: 02/06/27: rickman: Re: 5V tolerance
44726: 02/06/28: Muzaffer Kal: Re: 5V tolerance
44756: 02/06/29: Kolja Sulimma: Re: 5V tolerance
44762: 02/06/29: rickman: Re: 5V tolerance
44769: 02/06/30: Peter Alfke: Re: 5V tolerance
44775: 02/06/30: rickman: Re: 5V tolerance
44779: 02/07/01: Jim Granville: Re: Timed Licenses and version control ( was 5V tolerance )
44739: 02/06/28: Lorenzo Lutti: Re: 5V tolerance
44382: 02/06/18: Davis Moore: Re: 5V tolerance
44404: 02/06/19: rickman: Re: 5V tolerance
44384: 02/06/19: Ray Andraka: Re: 5V tolerance
44395: 02/06/19: Rick Filipkiewicz: Re: 5V tolerance
44402: 02/06/19: Ray Andraka: Re: 5V tolerance
44445: 02/06/20: Bevan Weiss: Re: 5V tolerance
44463: 02/06/20: Dan Kuechle: Re: 5V tolerance
44468: 02/06/20: Rick Filipkiewicz: Re: 5V tolerance
44469: 02/06/20: Austin Lesea: Re: 5V tolerance
44470: 02/06/20: emanuel stiebler: Re: 5V tolerance
44350: 02/06/18: Wolfgang Pieper: ram initialization
44363: 02/06/18: FEMI: Pls Recommend a Xilinx development Board
44371: 02/06/18: Anna Acevedo: Re: Pls Recommend a Xilinx development Board
44372: 02/06/18: Cyrille de Brébisson: Re: Pls Recommend a Xilinx development Board
44401: 02/06/19: Manfred Kraus: Re: Pls Recommend a Xilinx development Board
44439: 02/06/20: Felix Bertram: Re: Pls Recommend a Xilinx development Board
44366: 02/06/18: Josan Moreno: XC6200 Synopsys synthesis libraries
44373: 02/06/18: Cyrille de Brébisson: beginer's question: what does tran means in verilog
44393: 02/06/19: Muzaffer Kal: Re: beginer's question: what does tran means in verilog
44396: 02/06/19: Rick Filipkiewicz: Re: beginer's question: what does tran means in verilog
44397: 02/06/19: Jonathan Bromley: Re: beginer's question: what does tran means in verilog
44383: 02/06/18: Hristo Stevic: systolic Vs pipelined
44386: 02/06/19: glen herrmannsfeldt: Re: systolic Vs pipelined
44405: 02/06/19: Hristo Stevic: Re: systolic Vs pipelined
44523: 02/06/22: Sushant: Re: systolic Vs pipelined
44389: 02/06/19: Kevin Neilson: The Placer is Crazy
44394: 02/06/19: Abhishek Ghate: Info required on SPI3
44398: 02/06/19: Felix Bertram: Re: ISE Webpack Basics
44399: 02/06/19: Thomas: ISE Webpack Basics
44400: 02/06/19: Holger Kleinegraeber: Re: ISE Webpack Basics
44417: 02/06/19: Patrick: Re: ISE Webpack Basics
44451: 02/06/20: <ted_jmt@zapta.com>: Re: ISE Webpack Basics
44505: 02/06/21: Al Williams: Re: ISE Webpack Basics
44406: 02/06/19: Anthony Ellis: Xilinx/Simprims & Modelsim
44450: 02/06/20: Benjamin Todd: Re: Xilinx/Simprims & Modelsim
44407: 02/06/19: Leon Heller: Xilinx Webpack Fatal Error (0031)
44408: 02/06/19: DAVID WRIGHT: ATMEL CPLD
44416: 02/06/19: rickman: Re: ATMEL CPLD
44427: 02/06/19: Troy Schultz: Re: ATMEL CPLD
44428: 02/06/20: Jim Granville: Re: ATMEL CPLD
44429: 02/06/19: DAVID WRIGHT: Re: ATMEL CPLD
44430: 02/06/19: Uwe Bonnes: Re: ATMEL CPLD
44432: 02/06/19: Troy Schultz: Re: ATMEL CPLD
44409: 02/06/19: harsha: uart code using vhdl
44412: 02/06/19: Falk Brunner: Re: uart code using vhdl
44415: 02/06/19: Nicholas Weaver: Re: uart code using vhdl
44424: 02/06/19: Falk Brunner: Re: uart code using vhdl
44431: 02/06/19: Uwe Bonnes: Re: uart code using vhdl
44410: 02/06/19: Marcel: Xilinx .bit file via jtag ?
44414: 02/06/19: Falk Brunner: Re: Xilinx .bit file via jtag ?
44421: 02/06/19: Marcel: Re: Xilinx .bit file via jtag ?
44423: 02/06/19: Falk Brunner: Re: Xilinx .bit file via jtag ?
44425: 02/06/19: Steve Casselman: Re: Xilinx .bit file via jtag ?
44413: 02/06/19: guy: probs with...
44422: 02/06/19: Jacky Renaux: barrel shifter
44446: 02/06/20: Ray Andraka: Re: barrel shifter
44465: 02/06/20: Jacky Renaux: Re: barrel shifter
44433: 02/06/19: Dan Kuechle: Xilinx Bel - how do I find the Bel nane?
44455: 02/06/20: Falk Brunner: Re: Xilinx Bel - how do I find the Bel nane?
44435: 02/06/20: Jim: Help!I can't use the programmer of Max-plus II on windows XP.
44498: 02/06/21: Marcin E. Hamerla: Re: Help!I can't use the programmer of Max-plus II on windows XP.
44585: 02/06/24: jerry1111: Re: Help!I can't use the programmer of Max-plus II on windows XP.
44619: 02/06/25: Jim: Re: Help!I can't use the programmer of Max-plus II on windows XP.
44441: 02/06/20: Anthony Ellis: How to get Unisims netlist?
44456: 02/06/20: newman: Re: How to get Unisims netlist?
44459: 02/06/20: Ray Andraka: Re: How to get Unisims netlist?
44481: 02/06/21: Anthony Ellis: Re: How to get Unisims netlist?
44474: 02/06/20: newman: Re: How to get Unisims netlist?
44495: 02/06/21: Rick Filipkiewicz: Re: How to get Unisims netlist?
44443: 02/06/20: Ryan: Multiple Nios CPU's on Altera PLD?
44444: 02/06/20: Vincent JADOT: Re: Multiple Nios CPU's on Altera PLD?
44482: 02/06/21: Ryan: Re: Multiple Nios CPU's on Altera PLD?
44486: 02/06/21: Vincent JADOT: Re: Multiple Nios CPU's on Altera PLD?
44507: 02/06/21: Alan Calac: Re: Multiple Nios CPU's on Altera PLD?
44491: 02/06/21: Wolfgang Loewer: Re: Multiple Nios CPU's on Altera PLD?
44571: 02/06/24: Ryan: Re: Multiple Nios CPU's on Altera PLD?
44447: 02/06/20: Dmitri Katchalov: WebPack - How to view synthesis results?
44448: 02/06/20: Stephan Neuhold: Re: WebPack - How to view synthesis results?
44453: 02/06/20: rickman: Re: WebPack - How to view synthesis results?
44449: 02/06/20: Russell: Re: WebPack - How to view synthesis results?
44457: 02/06/20: Falk Brunner: How to generate a valid EDIF netlist?
44460: 02/06/20: John_H: Re: How to generate a valid EDIF netlist?
44462: 02/06/20: Falk Brunner: Re: How to generate a valid EDIF netlist?
44466: 02/06/20: Falk Brunner: Re: How to generate a valid EDIF netlist?
44467: 02/06/20: Kevin Brace: Re: How to generate a valid EDIF netlist?
44501: 02/06/21: Falk Brunner: Re: How to generate a valid EDIF netlist?
44512: 02/06/21: Steven Elzinga: Re: How to generate a valid EDIF netlist?
44653: 02/06/25: Duane Clark: Re: How to generate a valid EDIF netlist?
44655: 02/06/25: Kevin Brace: Re: How to generate a valid EDIF netlist?
44521: 02/06/22: Kevin Brace: Re: How to generate a valid EDIF netlist?
44475: 02/06/21: XU QIJUN: Multiply by 8 with DLL in Spaertan-II.
44477: 02/06/21: XU QIJUN: Re: Multiply by 8 with DLL in Spaertan-II.
44500: 02/06/21: Falk Brunner: Re: Multiply by 8 with DLL in Spaertan-II.
44509: 02/06/21: Yury: Re: Multiply by 8 with DLL in Spaertan-II.
44617: 02/06/25: XU QIJUN: Re: Multiply by 8 with DLL in Spaertan-II.
44622: 02/06/25: Ray Andraka: Re: Multiply by 8 with DLL in Spaertan-II.
44657: 02/06/26: XU QIJUN: Re: Multiply by 8 with DLL in Spaertan-II.
44658: 02/06/26: Ray Andraka: Re: Multiply by 8 with DLL in Spaertan-II.
44670: 02/06/26: XU QIJUN: Re: Multiply by 8 with DLL in Spaertan-II.
44476: 02/06/21: PDemos: design cycle metrics
44483: 02/06/20: Muthu: Xilinx's 4.1i's Lastest webpack
44496: 02/06/21: Rick Filipkiewicz: Re: Xilinx's 4.1i's Lastest webpack
44522: 02/06/22: Johann Glaser: Re: Xilinx's 4.1i's Lastest webpack
44510: 02/06/21: Leon Heller: Re: Xilinx's 4.1i's Lastest webpack
44525: 02/06/22: rickman: Re: Xilinx's 4.1i's Lastest webpack
44527: 02/06/22: Uwe Bonnes: Re: Xilinx's 4.1i's Lastest webpack
44540: 02/06/23: rickman: Re: Xilinx's 4.1i's Lastest webpack
44530: 02/06/22: Leon Heller: Re: Xilinx's 4.1i's Lastest webpack
44541: 02/06/23: rickman: Re: Xilinx's 4.1i's Lastest webpack
44531: 02/06/22: Rick Filipkiewicz: Re: Xilinx's 4.1i's Lastest webpack
44532: 02/06/22: Peter Alfke: Re: Xilinx's 4.1i's Lastest webpack
44535: 02/06/22: Rick Filipkiewicz: Re: Xilinx's 4.1i's Lastest webpack
44539: 02/06/23: Russell: Re: Xilinx's 4.1i's Lastest webpack
44542: 02/06/23: rickman: Re: Xilinx's 4.1i's Lastest webpack
44611: 02/06/24: Kevin Brace: Re: Xilinx's 4.1i's Lastest webpack
44544: 02/06/23: Rick Filipkiewicz: Re: Xilinx's 4.1i's Lastest webpack
44614: 02/06/24: rickman: Re: Xilinx's 4.1i's Lastest webpack
44615: 02/06/24: Kevin Brace: Re: Xilinx's 4.1i's Lastest webpack
44764: 02/06/29: rickman: Re: Xilinx's 4.1i's Lastest webpack
44768: 02/06/29: Kevin Brace: Re: Xilinx's 4.1i's Lastest webpack
44545: 02/06/23: Jim Granville: Re: Xilinx's 4.1i's Lastest webpack
44547: 02/06/23: Terry Newton: Re: Xilinx's 4.1i's Lastest webpack
44546: 02/06/23: Rick Filipkiewicz: Re: Xilinx's 4.1i's Lastest webpack
44814: 02/07/02: Peter Alfke: Re: Xilinx's 4.1i's Lastest webpack
44837: 02/07/02: Kevin Brace: Re: Xilinx's 4.1i's Lastest webpack
44853: 02/07/02: Keith R. Williams: Re: Xilinx's 4.1i's Lastest webpack
44855: 02/07/03: rickman: Re: Xilinx's 4.1i's Lastest webpack
44858: 02/07/03: Kevin Brace: Re: Xilinx's 4.1i's Lastest webpack
44558: 02/06/23: Falk Brunner: Re: Xilinx's 4.1i's Lastest webpack
44568: 02/06/24: rickman: Re: Xilinx's 4.1i's Lastest webpack
44484: 02/06/20: Muthu: Retiming option in synplify pro
44489: 02/06/21: Ken McElvain: Re: Retiming option in synplify pro
44487: 02/06/21: Ulises Hernandez: StrongARM - 110 Model request
44488: 02/06/21: Cyrille de Brébisson: Re: xilinx, jtag vs. serial parallel mode
44490: 02/06/21: David: Self upgrading Data I/O programmers?
44492: 02/06/21: Laurent Gauch: Re: xilinx, jtag vs. serial parallel mode
44493: 02/06/21: Steven Derrien: Xpower accuracy
44494: 02/06/21: steve synakowski: Coolrunner Orcad, Pads ChipScale packages?
44497: 02/06/21: cfk: adding timing constraints
44502: 02/06/21: Falk Brunner: Re: adding timing constraints
44758: 02/06/30: Kang Liat Chuan: Re: adding timing constraints
44499: 02/06/21: Johnny Fu: Logic Minimization in Max+Plus II compiler
44503: 02/06/21: Allan Herriman: Re: Logic Minimization in Max+Plus II compiler
44519: 02/06/21: Jay: Re: Logic Minimization in Max+Plus II compiler
44520: 02/06/22: Jim Granville: Re: Logic Minimization in Max+Plus II compiler
44508: 02/06/21: Nesrine: Baugh-Wooley multiplier using Handel-C
44511: 02/06/21: Johnny Fu: Logic Minimization in Max+Plus II
44528: 02/06/22: Cyra.Nargolwalla: Re: Logic Minimization in Max+Plus II
44515: 02/06/22: Endric Schubert: Bad Virtex2 devices - any similar experiences
44533: 02/06/22: Phil Hays: Re: Bad Virtex2 devices - any similar experiences
44552: 02/06/23: cfk: Re: Bad Virtex2 devices - any similar experiences
44639: 02/06/25: <hamish@cloud.net.au>: Re: Bad Virtex2 devices - any similar experiences
44534: 02/06/22: Jay: Re: Bad Virtex2 devices - any similar experiences
44536: 02/06/22: Marc Randolph: Re: Bad Virtex2 devices - any similar experiences
44537: 02/06/22: Allan Herriman: Re: Bad Virtex2 devices - any similar experiences
44590: 02/06/24: Steve Casselman: Re: Bad Virtex2 devices - any similar experiences
44599: 02/06/24: Austin Lesea: Parts are almost never bad ....
44518: 02/06/22: David R Brooks: Initialising BlockSelectRAM
44548: 02/06/23: Marcel: Xilinx webpack if - else if statement ??
44551: 02/06/23: Duane Clark: Re: Xilinx webpack if - else if statement ??
44569: 02/06/24: rickman: Re: Xilinx webpack if - else if statement ??
44587: 02/06/24: Marcel: Re: Xilinx webpack if - else if statement ??
44549: 02/06/23: Ghys: Clock enable & Synplify 7.1
44554: 02/06/23: Ken McElvain: Re: Clock enable & Synplify 7.1
44556: 02/06/23: Ghys: Re: Clock enable & Synplify 7.1
44559: 02/06/23: newman: Re: Clock enable & Synplify 7.1
44561: 02/06/23: Ken McElvain: Re: Clock enable & Synplify 7.1
44635: 02/06/25: Ghys: Re: Clock enable & Synplify 7.1
44560: 02/06/23: Ken McElvain: Re: Clock enable & Synplify 7.1
44562: 02/06/23: newman: Re: Clock enable & Synplify 7.1
44581: 02/06/24: Marc Randolph: Re: Clock enable & Synplify 7.1
44596: 02/06/24: Ray Andraka: Re: Clock enable & Synplify 7.1
44646: 02/06/25: Marc Randolph: Re: Clock enable & Synplify 7.1
44650: 02/06/26: Ray Andraka: Re: Clock enable & Synplify 7.1
44685: 02/06/26: newman: Re: Clock enable & Synplify 7.1
44695: 02/06/27: Marc Randolph: Re: Clock enable & Synplify 7.1
44719: 02/06/27: newman: Re: Clock enable & Synplify 7.1
44597: 02/06/24: newman: Re: Clock enable & Synplify 7.1
44607: 02/06/24: newman: Re: Clock enable & Synplify 7.1
44555: 02/06/23: cfk: CLK/2
44564: 02/06/23: John_H: Re: CLK/2
44570: 02/06/23: Sushant: Re: CLK/2
44604: 02/06/24: Ray Andraka: Re: CLK/2
44992: 02/07/09: xueqing: Re: CLK/2
44572: 02/06/24: Thomas: Agilent ADS generated Code
44573: 02/06/24: Vincent JADOT: Microblaze uart communication pb!!
44605: 02/06/24: Matthew P. Ouellette: Re: Microblaze uart communication pb!!
44631: 02/06/25: Vincent JADOT: Re: Microblaze uart communication pb!!
44574: 02/06/24: Riccardo Rubini: [Newbie] Help with 20L8 PAL
44575: 02/06/24: Jim Granville: Re: [Newbie] Help with 20L8 PAL
44579: 02/06/24: Rick Filipkiewicz: Re: [Newbie] Help with 20L8 PAL
44582: 02/06/24: Mikeandmax: Re: [Newbie] Help with 20L8 PAL
44577: 02/06/24: Jerzy Gbur: CIC filter
44593: 02/06/24: Paul Butler: Re: CIC filter
44594: 02/06/24: Ray Andraka: Re: CIC filter
44616: 02/06/24: Tom Seim: Re: CIC filter
44578: 02/06/24: Thomas Buerner: book recommenation
44583: 02/06/24: Christian Plessl: Re: book recommenation
44580: 02/06/24: Markus Wolfgart: Old Synario SW, how to adapt for MACH211 and MACH4-64/32 programming?
44584: 02/06/24: Ken Mac: Will this clock divider be good on hardware?
44601: 02/06/24: Falk Brunner: Re: Will this clock divider be good on hardware?
44610: 02/06/24: Ken Mac: Re: Will this clock divider be good on hardware?
44641: 02/06/25: Falk Brunner: Re: Will this clock divider be good on hardware?
44664: 02/06/26: Ken Mac: Re: Will this clock divider be good on hardware?
44608: 02/06/24: newman: Re: Will this clock divider be good on hardware?
44612: 02/06/24: newman: Re: Will this clock divider be good on hardware?
44626: 02/06/24: Jay: Re: Will this clock divider be good on hardware?
44632: 02/06/25: Ken Mac: Re: Will this clock divider be good on hardware?
44588: 02/06/24: Philippe Robert: Driving memory with an FPGA
44589: 02/06/24: Daniel Tschurr: latch in Altera APEX20KE causes oscillations
44591: 02/06/24: spyng: skew control between different signals ?
44600: 02/06/24: Falk Brunner: Re: skew control between different signals ?
44602: 02/06/24: Bryan: Re: skew control between different signals ?
44625: 02/06/24: Jay: Re: skew control between different signals ?
44652: 02/06/26: Ray Andraka: Re: skew control between different signals ?
44672: 02/06/26: spyng: Re: skew control between different signals ?
44674: 02/06/26: Falk Brunner: Re: skew control between different signals ?
44704: 02/06/27: spyng: Re: skew control between different signals ?
44592: 02/06/24: Eyal Shachrai: virtex2 : ALT_VRP / ALT_VRN
44595: 02/06/24: John_H: Re: virtex2 : ALT_VRP / ALT_VRN
44598: 02/06/24: rshaley: For Sale NEW fact packed Xilinx, Atmel, AMD, etc. over 500K pcs.
44603: 02/06/24: rickman: Xilinx tools under WinXP
44620: 02/06/25: Kevin Neilson: Re: Xilinx tools under WinXP
44636: 02/06/25: Rick Filipkiewicz: Re: Xilinx tools under WinXP
44804: 02/07/01: Simon Gornall: Re: Xilinx tools under WinXP
44645: 02/06/25: Petter Gustad: Re: Xilinx tools under WinXP
44660: 02/06/26: Rick Filipkiewicz: Re: Xilinx tools under WinXP
44668: 02/06/26: Petter Gustad: Re: Xilinx tools under WinXP
44698: 02/06/27: Kevin Neilson: Re: Xilinx tools under WinXP
44643: 02/06/25: ae: Re: Xilinx tools under WinXP
44699: 02/06/27: Kevin Neilson: Re: Xilinx tools under WinXP
44709: 02/06/27: Rick Filipkiewicz: Re: Xilinx tools under WinXP
44713: 02/06/27: Duane Clark: Re: Xilinx tools under WinXP
44613: 02/06/24: Katherine Compton: FPGA 2003 Conference
44618: 02/06/24: ssy: too hot fpga device
44623: 02/06/25: Peter Alfke: Re: too hot fpga device
44627: 02/06/24: Jim Stewart: Re: too hot fpga device
44629: 02/06/25: sunny: Re: too hot fpga device
44651: 02/06/26: Ray Andraka: Re: too hot fpga device
44642: 02/06/25: ae: Re: too hot fpga device
44654: 02/06/25: ssy: Re: too hot fpga device
44656: 02/06/26: Peter Alfke: Re: too hot fpga device
44659: 02/06/25: Jay: Re: too hot fpga device
44706: 02/06/27: Ben Twijnstra: Re: too hot fpga device
44621: 02/06/24: Helen: Help with Lattice ispLSIv2192VE
44624: 02/06/24: Nagaraj: FPGA to ASIC migration
44628: 02/06/25: Ansgar Bambynek: Re: FPGA to ASIC migration
44630: 02/06/25: Thomas: Programming examples for Spartan II
44633: 02/06/25: Vincent JADOT: Re: Programming examples for Spartan II
44634: 02/06/25: Cemal Coemert (TIP): Re: fast adders using HDL in Xilinx fpga
44637: 02/06/25: suchitra: cpld fpga programming
44638: 02/06/25: Rick Filipkiewicz: Re: Xilinx cpld under Windows?
44640: 02/06/25: Petter Gustad: Re: Xilinx cpld under Windows?
44644: 02/06/25: ae: Virtex w/PowerPC cores
44647: 02/06/25: Yury: Library declaration in Verilog?
44663: 02/06/26: Rick Filipkiewicz: Re: Library declaration in Verilog?
44682: 02/06/26: Yury: Re: Library declaration in Verilog?
44649: 02/06/25: Andrew Bridger: Foundation ISE 4.2i SP3 release notes
44711: 02/06/27: Francois Choquette: Re: Foundation ISE 4.2i SP3 release notes
44661: 02/06/26: Charles Wagner: amplify and xilinx : map error 679
44738: 02/06/28: Steven Elzinga: Re: amplify and xilinx : map error 679
44967: 02/07/08: Wayne: Re: amplify and xilinx : map error 679
44662: 02/06/26: Andrew Bridger: Applying voltage to FPGA I/O while FPGA is not powered
44700: 02/06/27: Manfred Kraus: Re: Applying voltage to FPGA I/O while FPGA is not powered
44665: 02/06/26: Philippe Robert: IBIS simulator
44673: 02/06/26: Austin Lesea: Re: IBIS simulator
44666: 02/06/26: Young-Su Kwon: Virtex-E Readback.
44669: 02/06/26: Christian Plessl: Re: Virtex-E Readback.
44667: 02/06/26: Ken Mac: why not pipeline by default?
44671: 02/06/26: Ray Andraka: Re: why not pipeline by default?
44678: 02/06/26: Richard Iachetta: Re: why not pipeline by default?
44710: 02/06/27: Rick Filipkiewicz: Re: why not pipeline by default?
44680: 02/06/26: John_H: Re: why not pipeline by default?
44681: 02/06/27: John Williams: Re: why not pipeline by default?
44684: 02/06/27: Nicholas Weaver: Re: why not pipeline by default?
44675: 02/06/26: FEMI: XESS / Digilent / Trenz Board Experience ? Help.
44717: 02/06/28: Tony Burch: Re: XESS / Digilent / Trenz Board Experience ? Help.
44777: 02/06/30: anon: Re: XESS / Digilent / Trenz Board Experience ? Help.
44683: 02/06/26: Francois Choquette: Multiple XC_PROPS attributes
44730: 02/06/28: Francois Choquette: Re: Multiple XC_PROPS attributes
44687: 02/06/26: Jay: Re: fast adders using HDL in Xilinx fpga
44703: 02/06/27: Ray Andraka: Re: fast adders using HDL in Xilinx fpga
44688: 02/06/27: Norris Leong: FPT - Final Call for Papers
44689: 02/06/27: Ryan: Loops in Quartus II
44692: 02/06/27: Paul Baxter: Re: Loops in Quartus II
44690: 02/06/27: Minlin Fan: blank CPLD
44691: 02/06/27: Uwe Bonnes: Re: blank CPLD
44731: 02/06/28: M. Randelzhofer: Re: blank CPLD
44737: 02/06/28: Jim Raynor: Re: blank CPLD
44750: 02/06/29: M. Randelzhofer: Re: blank CPLD
44789: 02/07/01: Rick Filipkiewicz: Re: blank CPLD
44795: 02/07/01: M. Randelzhofer: Re: blank CPLD
44693: 02/06/27: a.j.: 32KHz oscilator in CPLD
44702: 02/06/27: Leon Heller: Re: 32KHz oscilator in CPLD
44705: 02/06/28: Jim Granville: Re: 32KHz oscilator in CPLD
44783: 02/07/01: Tuomo Auer: Re: 32KHz oscilator in CPLD
44868: 02/07/03: a.j.: Re: 32KHz oscilator in CPLD
44694: 02/06/27: Jonas Thor: Limited sving IO - LVPECL?
44696: 02/06/27: Roland Manders: clock skew in quartus, not in maxplus
44697: 02/06/27: Wolfgang Loewer: Re: clock skew in quartus, not in maxplus
44720: 02/06/27: newman: Re: clock skew in quartus, not in maxplus
44761: 02/06/29: Jay: Re: clock skew in quartus, not in maxplus
44708: 02/06/27: John Daae: Generate loop and RLOC
44714: 02/06/27: Ray Andraka: Re: Generate loop and RLOC
44715: 02/06/27: Goran Bilski: Re: Generate loop and RLOC
44718: 02/06/28: Ray Andraka: Re: Generate loop and RLOC
44712: 02/06/27: Peter Alfke: Re: VIRTEX II DCM Question
44716: 02/06/27: Kevin Neilson: The Placer is Crazy II
44721: 02/06/27: Dan: Who near London UK can burn a Xilinx SPROM ?
44722: 02/06/28: Peter Alfke: Re: Who near London UK can burn a Xilinx SPROM ?
44723: 02/06/27: Jeff Mock: Re: VIRTEX II DCM Question
44724: 02/06/27: John Larkin: Silly questions about configuring Spartan 2's
44732: 02/06/28: Falk Brunner: Re: Silly questions about configuring Spartan 2's
44736: 02/06/28: rickman: Re: Silly questions about configuring Spartan 2's
44746: 02/06/28: Falk Brunner: Re: Silly questions about configuring Spartan 2's
44725: 02/06/27: Jay: Re: VIRTEX II DCM Question
44727: 02/06/28: Peter Alfke: Re: VIRTEX II DCM Question
44733: 02/06/28: Peter Alfke: Re: VIRTEX II DCM Question
44749: 02/06/28: Jeff Mock: Re: VIRTEX II DCM Question
44757: 02/06/29: Jay: Re: VIRTEX II DCM Question
44807: 02/07/01: Peter Alfke: Re: VIRTEX II DCM Question
44728: 02/06/28: Dirk Sütterlin @ newsgroups: variable decimation filter with rational sampling factors
44729: 02/06/28: Ray Andraka: Re: variable decimation filter with rational sampling factors
44734: 02/06/28: David Langmann: Problem: Designing for older FPGAs
44735: 02/06/28: Falk Brunner: Re: Problem: Designing for older FPGAs
44742: 02/06/28: Peter Alfke: Re: Problem: Designing for older FPGAs
44740: 02/06/28: Lorenzo Lutti: State machine and syncronous inputs
44744: 02/06/28: Peter Alfke: Re: State machine and syncronous inputs
44748: 02/06/29: Jim Granville: Re: State machine and syncronous inputs
44745: 02/06/28: Falk Brunner: Re: State machine and syncronous inputs
44755: 02/06/29: Lorenzo Lutti: Re: State machine and syncronous inputs
44741: 02/06/28: Lorenzo Lutti: Foundation and ISE
44743: 02/06/28: Martin Sauer: Programming a Xilinx CPDL with a Microcontroller
44754: 02/06/29: Falk Brunner: Re: Programming a Xilinx CPDL with a Microcontroller
44760: 02/06/29: Jay: Re: Programming a Xilinx CPDL with a Microcontroller
44767: 02/06/29: Kasper Pedersen: Re: Programming a Xilinx CPDL with a Microcontroller
44747: 02/06/28: Joerg Schneide: XC9572 VCCIO change
44753: 02/06/29: Peter Alfke: Re: XC9572 VCCIO change
44751: 02/06/28: Sandeep Unni: Altera equivalent for GAL 16V8
44752: 02/06/29: Jim Granville: Re: Altera equivalent for GAL 16V8
44759: 02/06/29: Jay: Re: Altera equivalent for GAL 16V8
44766: 02/06/29: Sandeep Unni: Re: Altera equivalent for GAL 16V8
45053: 02/07/11: Spam Hater: Re: Altera equivalent for GAL 16V8
44763: 02/06/29: Eyal Shachrai: virtex2 : 180 deg. phase clocks
44765: 02/06/29: Falk Brunner: Re: virtex2 : 180 deg. phase clocks
44770: 02/06/30: Peter Alfke: Re: virtex2 : 180 deg. phase clocks
44773: 02/06/30: Philip Freidin: Re: virtex2 : 180 deg. phase clocks
44771: 02/06/30: Kevin Brace: How can I preserve FFs in LeonardoSpectrum?
44780: 02/07/01: Nicolas Matringe: Re: How can I preserve FFs in LeonardoSpectrum?
44781: 02/07/01: Laurent Gauch: Re: How can I preserve FFs in LeonardoSpectrum?
44898: 02/07/04: Kevin Brace: Re: How can I preserve FFs in LeonardoSpectrum?
44787: 02/07/01: Kevin Brace: Re: How can I preserve FFs in LeonardoSpectrum?
44816: 02/07/02: jb: Re: How can I preserve FFs in LeonardoSpectrum?
44818: 02/07/02: Roberta Crescentini: Re: How can I preserve FFs in LeonardoSpectrum?
44897: 02/07/04: Kevin Brace: Re: How can I preserve FFs in LeonardoSpectrum?
45630: 02/07/30: Daryl: Who can compare the synthesis tools for me ?
45648: 02/07/30: Mike Treseler: Re: Who can compare the synthesis tools for me ?
45666: 02/07/31: Ian Smith: Re: Who can compare the synthesis tools for me ?
45690: 02/08/01: Jay: Re: Who can compare the synthesis tools for me ?
44986: 02/07/08: Kevin Brace: Re: How can I preserve FFs in LeonardoSpectrum?
44994: 02/07/09: Ray Andraka: Re: How can I preserve FFs in LeonardoSpectrum?
44774: 02/06/30: Steven Derrien: Xpower accuracy (is there anybody from Xilinx out there ?)
44790: 02/07/01: Matthias Neuroth: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44794: 02/07/01: John Blaine: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44797: 02/07/01: Peter Alfke: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44799: 02/07/01: Austin Lesea: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44805: 02/07/01: Dennis McCrohan: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44815: 02/07/02: Rick Filipkiewicz: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44918: 02/07/05: Dennis McCrohan: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44920: 02/07/05: Rick Filipkiewicz: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44921: 02/07/06: Jim Granville: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44778: 02/06/30: anon: Xilinx Virtex2-Pro: availability?
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