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Messages from 44375

Article: 44375
Subject: Re: Xilinx ISE BaseX... What is it?
From: Keith R. Williams <krw@btv.ibm.com>
Date: Tue, 18 Jun 2002 16:13:42 -0400
Links: << >>  << T >>  << A >>
In article <3D0F8D5C.FC044FFC@yahoo.com>, spamgoeshere4@yahoo.com 
says...
> Kevin Brace wrote:
> > 
> > hamish@cloud.net.au wrote:
> > >
> > >
> > > What does "bubble up" mean?
> > >
> > 
> >         Rick already explained it correctly, but the term "bubbling up
> > tri-state buffers" means when the design hierarchy is kept, moving
> > tri-state buffers to the top of the hierarchy, and converting them to
> > OBUFT or IOBUF IO pads.
> > LeonardoSpectrum's manual uses this term, and that's where I picked it
> > up.
> > 
> > > Do you mean push-through? If so you must be the only person on this
> > > newsgroup who thinks that's a desirable feature.
> > 
> > 
> >         Nope, Synplicity's CTO is the guy who thinks tri-state
> > push-through is a desirable feature.
> > 
> > Kevin Brace (In general, don't respond to me directly, and respond
> > within the newsgroup.)
> 
> Ok, bubble up is now clear, but what the heck is "CTO"?

Chief Technical Officer? (Ken McElvain) 

----
  Keith

Article: 44376
Subject: Re: About Programming CPLD using Xilinx Programming Cable IV
From: Brendan Bridgford <brendanb@xilinx.com>
Date: Tue, 18 Jun 2002 13:41:27 -0700
Links: << >>  << T >>  << A >>

--------------65317FF9095A21B27AA79D13
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

John,

There's probably a problem with one of the JTAG pin connections.  This error
message is caused by:
- Cable powering problem
- Device powering problem
- JTAG pin connection problem.

The good news is that you're using a package that you should provide you with
access to the pins.  I would start by hooking an oscilloscope up to the TDI,
TDO, TMS, and TCK pins on the device, using the Debug Chain feature in iMPACT
(File -> debug chain) to toggle them (alternatively, you could use IDCODE
looping to drive the three input signals).  Look to make sure that the signals
are actually switching and that there isn't excessive ringing or noise.

My suggestion is that you actually put your probes on the pins of the device -
not on the breakout board.   There could be a problem with the socket adapter or
the breakout board, so you should start by determining what the device is
actually seeing, and move outward from there.

Last, you should be aware that iMPACT does not support all 9500 devices (see
Xilinx Answer Record 12737 for more information about this).  Note that all
9500XL and 9500XV devices are supported, though.  This limitation would not
cause the problems that you are seeing, however - iMPACT will be able to at
least detect the devices in any JTAG chain, regardless of the number or type of
devices.

Brendan Bridgford
Xilinx Applications


John Lee wrote:

> Hi all,
>
> I am a newbie to digital computing, and for my project I had to program a
> CPLD XC9536 or XC9572.
>
> Resource I have:
> Xilinx Webpack 4.2 (newest frok xilinx.com)
> Xilinx Programming Cable IV
> a break out board for PLCC44
> a self-made 5 V regulator (I measured the output of my voltage supply, it's
> 4.98 V)
>
> I kept getting errors like
> "
> ERROR:iMPACT:634 - Boundary-scan chain test failed at bit position '1' .
>     A problem may exist in the hardware configuration.
>     Check that the cable, scan chain, and power connections are intact,
>     that the specified scan chain configuration matches the actual hardware,
> and
>     that the power supply is adequate and delivering the correct voltage."
> =>
>
> I have connected the JTAG pins, applied 4.98 V to VCCINT(21,41) and
> VCCIO(32),  and connect GND (10,23,31) to GND
>
> and still I get this error, my status LED on my Paragram cable IV is shown
> GREEN
>
> really need help...
>
> John



Article: 44377
Subject: Re: 5V tolerance
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 18 Jun 2002 14:02:07 -0700
Links: << >>  << T >>  << A >>
Rick,

I would still do the IBIS simualtion to see if the 5V is really there.

Also, Virtex is 5V tolerant without any resistor at all (ie 5V PCI interface IO
standard).  It is only in Virtex E and later parts where the resistor is going to
be (possibly) required.

Austin

rickman wrote:

> ATA is correct.  In fact I have been told that IDE is not really the
> correct name anymore and it sould ONLY be called ATA.
>
> I can't say I have seen a source for IBIS description files for the ATA
> bus.  It uses 5 volt TTL logic levels so I would not feel safe without
> the series resistors.  But the series resistors are only usable on
> inputs or slow IOs.  If you are running at the full 66 MHz of the most
> recent ATA bus spec, you may run into trouble with rise/fall time when
> driving from the FPGA.
>
> I recommend that you use a 5 volt tolerant interface device or FPGA.
> The resistor trick is very limited in range of applications.
>
> Stéphane Guyetant wrote:
> >
> > I meant ADA/IDE spec: the spartan will interface with a hard drive.
> > I'm not familiar with IBIS models, but I bet I can find it easily for
> > HDDs...
> >
> > Austin Lesea wrote:
> >
> > > Stéphane,
> > >
> > > I do not know what an ATA bus is, so I can not answer.  As long as the IO
> > > drivers do not pull up to greater than Vcco + 0.5V with current more than
> > > 10 mA, no resistor is required.  A quick IBIS simulation of the ATA
> > > output into a capacitive load would show if this is true.  Do you have
> > > the IBIS models for the ATA bus driver?  Is there a website for them?
> > >
> > > The resistor is required if one is able to source current at greater than
> > > Vcco + 0.5V to the Virtex input diode clamp.
> > >
> > > Austin
> > >
> > > Stéphane Guyetant wrote:
> > >
> > > > Hi all,
> > > >
> > > > after reading virtex "5V tolerant I/Os"
> > > > (see http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf  )
> > > > and Spartan II functional description, I would say that I can use a
> > > > Spartan-II
> > > > (PQ208 package) with all VccO=3.3V in LVTTL mode directly on a 5V ATA
> > > > bus
> > > > with no need of resistor or buffering. Right?
> > > >
> > > > Any comment/suggestion appreciated!
> > > > Thx,
> > > > Stephane
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 44378
Subject: Re: Seeking CPLD/FPGA recomendation
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 19 Jun 2002 09:02:55 +1200
Links: << >>  << T >>  << A >>
ted_jmt@zapta.com wrote:
> 
> >>
> >> 2. Must work on 5V (or higher)
> >
> >Interesting request - How much higher - and for what loads ?
> 
> 10V will be optimal. Current requirements are very very low (250uA is
> more than enough)

Is this driving LCD displays ?

You need to define the IO more precisely, it maybe a CPLD is not the
right choice at all.

> >
> >150 i/o is a lot in one package - what is this driving ?
> >( are all the loads in one place ? )
> >
> >Is the IO by Serial or parallel BUS, 8 or 16 bits wide ?
> >
> >Better may be 32 io in 44 pin packages, and use 5 packages spread on the
> >board(s).
> >CPLDs come in 32/64/128/.. macrocells, the better ones can pack a shift
> >and latch
> >into one macrocell. Prices are appx $1/32MC
> 
> Is the price per IO pin goes up with larger CPLD's (e.g. >100 pins) or
> is it cheaper to have one big CPLD ? We can go both ways depending on
> which option is cheaper.

When I last checked, the prices were surprisingly 'linear', at appx
$1/32MCells
so there was little pressure either way. The PCB layout and mechanics
can
have more impact.

If it is a relay drive / LED drive, or wire type load, more modular 
IO can be a good idea.

If it is driving a single LCD display, then a single CPLD makes more
sense,
but CPLD's cannot cover all LCD driver space.
 
> >>
> >> 5. Can be easily converted to a mask based equivalent chip (a full
> >> ASIC is not possible at this stage, maybe for second generation).
> >>
> >> 6. Cost of the masked version is very critical (and having a
> >> reasonable conversion/tooling cost is also very nice to have).
> >
> >So too are the volumes :) - what is the budget per I/O pin ?
> 
> 1c per I/O in large quantities will be OK.

 I've been told 1c/pin is appx the package-flow cost, so you will not
get close to that.

 If you need 150 x 5V -> 10V post pin buffers, you will balloon further.

-jg

Article: 44379
Subject: Re: Internal oscillator in CPLD?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Tue, 18 Jun 2002 22:09:39 +0000 (UTC)
Links: << >>  << T >>  << A >>



"Peter Alfke" <palfke@earthlink.net> wrote in message
news:3D0EB699.78E095E0@earthlink.net...
> John, just follow the instructions: resistor to A and to C, capacitor to
B.
> Peter

I just tried it, and it works fine with a couple of 1K5 resistors and a 100n
cap. I used an Altera Flex 10K10. Sorry about that, Peter, but my Xilinx
Parallel Cable III doesn't seem to be working, otherwise I'd have tried a
Xilinx device.

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.com
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com




Article: 44380
Subject: Re: Xilinx ISE BaseX... What is it?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Tue, 18 Jun 2002 17:29:59 -0500
Links: << >>  << T >>  << A >>


"Keith R. Williams" wrote:
> 
> > Ok, bubble up is now clear, but what the heck is "CTO"?
> 
> Chief Technical Officer? (Ken McElvain)

         Yes, that is what I meant.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 44381
Subject: Re: Which Synthesis tool for XILINX
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Tue, 18 Jun 2002 17:47:24 -0500
Links: << >>  << T >>  << A >>


Manfred Kraus wrote:
> 
> >         Regarding the QoR (Quality of Results) of XST, when your friend
> > compiled your design with LeonardoSpectrum, did that person optimized
> > the design for area or speed?
> 
> No, we only adjusted the syntax of the attributes.
> 


        I have some experience dealing with LeonardoSpectrum-Altera
Level 1, and I believe the default option is to synthesize for area, not
speed.
Your friend might want to change that option to speed, to see how
LeonardoSpectrum will do.
Another thing to consider is, does your design meet whatever timing
requirements with either tools?
Often time, when you optimize your design for area, it is likely not to
meet timing requirements compared to optimizing it for speed.




> Today I got the offer from Altium:
> 
> Leonardo Level 3 -- NodeLocked  US$ 21.875
> Leonardo Level 3 -- Floating US$ 32.815
> Leonardo Level 3 Single Vendor -- Nodelocked US$ 13.690
> Leonardo Level 3 Single Vendor -- Floating US$ 20.625
> Optional  Schematic Viewer Leonardo Insight  Nodelocked -- US$ 5.625
> Optional  Schematic Viewer Leonardo Insight  Floating -- US$ 8440
> 
> If it was about 8k to 10k, I would buy it immediately.
> 

        Does Altium resell Mentor Graphics software?
Anyhow, I read a press release by Mentor Graphics that the list price
for LeonardoSpectrum Level 2 is $8,000.
I am totally sure about the current pricing for Synplify, but I read a
press release a while ago that said it was $9,000.



> Maybe Ray  is right and XST will get better with future ServicePacks ?
> 

        I won't count on that.
I recently used an XST from WebPACK ISE 3.3WP8.0 (XST Ver. D.27), and
the QoR of it was pretty much same as an XST from ISE WebPACK 4.2WP2.0
(XST Ver. E.35).
That probably means that other than bug fixes and support of VHDL
syntax, XIlinx hasn't made much improvement to XST.
Plus, the tri-state buffer "bubble up" issue and valid FFs disappearing
when blackboxes are used and the design hierarchy is flattened bug have
been there as far back as XST of WebPACK ISE 3.3WP8.0, which means that
perhaps Xilinx isn't too interested in fixing problems.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 44382
Subject: Re: 5V tolerance
From: Davis Moore <davism@xilinx.com>
Date: Tue, 18 Jun 2002 17:02:30 -0600
Links: << >>  << T >>  << A >>
rickman wrote:

> ATA is correct.  In fact I have been told that IDE is not really the
> correct name anymore and it sould ONLY be called ATA.
>

Historically IDE and ATA meant the same thing.
Perhaps the industry is moving towards a preference.

A brief history on ATA/IDE interface:
http://www.ata-atapi.com/hist.htm


--
Davis Moore
Software Engineer -- PLP Implementation Tools
Xilinx, Inc. davism@NO_SPAMxilinx.com




Article: 44383
Subject: systolic Vs pipelined
From: "Hristo Stevic" <hristostev@yahoo.com>
Date: Tue, 18 Jun 2002 23:35:36 +0000 (UTC)
Links: << >>  << T >>  << A >>
hello,
I am bit confused about this point. sorry i know it is so basic, but..
what is the difference between a systolic architecture and a pipelined
one?
thanks


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 44384
Subject: Re: 5V tolerance
From: Ray Andraka <ray@andraka.com>
Date: Wed, 19 Jun 2002 00:55:26 GMT
Links: << >>  << T >>  << A >>
The ATA standard only specifies (5v) TTL level signals.  AFAIK, it is up to the
manufacturer to choose whatever logic family he wants for the disk side of
theinterface provided he fits within the specification.  SInce you normally will
not know what device the manufacturer is using (and if you allow use with any
drive), you must accept any signal level that conforms to the spec.  Likewise, I
sincerely doubt you will be able to get IBIS models for the drive, and even if
you could they would only be for a specific drive.  The data bits on the bus are
bidirectional, so you will have considerable trouble trying to get the resistor
trick to work reliably.  I highly recommend using one of the 5v tolerant devices
to interface to the disk, otherwise, you are going to need to use a level
translator to interface it.  For Xilinx families that means either the original
Virtex or SpartanII (not E) for new designs.

rickman wrote:

> ATA is correct.  In fact I have been told that IDE is not really the
> correct name anymore and it sould ONLY be called ATA.
>
> I can't say I have seen a source for IBIS description files for the ATA
> bus.  It uses 5 volt TTL logic levels so I would not feel safe without
> the series resistors.  But the series resistors are only usable on
> inputs or slow IOs.  If you are running at the full 66 MHz of the most
> recent ATA bus spec, you may run into trouble with rise/fall time when
> driving from the FPGA.
>
> I recommend that you use a 5 volt tolerant interface device or FPGA.
> The resistor trick is very limited in range of applications.
>
> Stéphane Guyetant wrote:
> >
> > I meant ADA/IDE spec: the spartan will interface with a hard drive.
> > I'm not familiar with IBIS models, but I bet I can find it easily for
> > HDDs...
> >
> > Austin Lesea wrote:
> >
> > > Stéphane,
> > >
> > > I do not know what an ATA bus is, so I can not answer.  As long as the IO
> > > drivers do not pull up to greater than Vcco + 0.5V with current more than
> > > 10 mA, no resistor is required.  A quick IBIS simulation of the ATA
> > > output into a capacitive load would show if this is true.  Do you have
> > > the IBIS models for the ATA bus driver?  Is there a website for them?
> > >
> > > The resistor is required if one is able to source current at greater than
> > > Vcco + 0.5V to the Virtex input diode clamp.
> > >
> > > Austin
> > >
> > > Stéphane Guyetant wrote:
> > >
> > > > Hi all,
> > > >
> > > > after reading virtex "5V tolerant I/Os"
> > > > (see http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf  )
> > > > and Spartan II functional description, I would say that I can use a
> > > > Spartan-II
> > > > (PQ208 package) with all VccO=3.3V in LVTTL mode directly on a 5V ATA
> > > > bus
> > > > with no need of resistor or buffering. Right?
> > > >
> > > > Any comment/suggestion appreciated!
> > > > Thx,
> > > > Stephane
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44385
(removed)


Article: 44386
Subject: Re: systolic Vs pipelined
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 19 Jun 2002 04:01:31 GMT
Links: << >>  << T >>  << A >>
"Hristo Stevic" <hristostev@yahoo.com> writes:

>hello,
>I am bit confused about this point. sorry i know it is so basic, but..
>what is the difference between a systolic architecture and a pipelined
>one?


A systolic array is an array of similar processors operating on
data passed from the previous processor, kept itself, and sometimes
passed from the subsequent processor.  Usually they are special purpose,
and contain a fairly large number of processors.

Pipelined architecture is used to implement parts of a more
general processor, such as the multiplier or divider of a
processor.  Usually the pipeline is relatively short, as this
specifies the latency.

If this is homework, please reference the newsgroup.

-- glen

Article: 44387
Subject: Re: what's the use of BlockRAM
From: nagaraj@accord-soft.com (Nagaraj)
Date: 18 Jun 2002 21:21:13 -0700
Links: << >>  << T >>  << A >>
Its good that I learnt some more features of BlockRAM (I am new to
this). Thanx Peter.
   Still I have some questions. Suppose the data output of one of the
dual ports
which I am using as read port is directly connected to the data bus of
the system. Then, FPGA should put data onto the databus only when the
system master selects the FPGA device AND gives the read clock. But as
I see in the dual port BlockRAM module, whenever there is a clock,
data is read and put onto the port unconditionally (may create clashes
on system databus). Eventhough controlling the "read address latching"
is possible, controlling the "read operation" is not possible.
   Is the above argument correct? If so, Could you please tell me what
to do in such cases (reading conditionally)?


Peter Alfke <palfke@earthlink.net> wrote in message news:<3D0F5456.26153CA8@earthlink.net>...
> This is a fundamental misunderstanding.

Article: 44388
Subject: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
From: spam_hater_7@email.com (Spam Hater)
Date: Wed, 19 Jun 2002 06:06:33 GMT
Links: << >>  << T >>  << A >>

Notice to potential employers:

You will be displacing a US citizen who is qualified, and willing to
work for that salary.

Make sure that you put a statement to that effect on the H1-B transfer
application.

Nothing personal Farhad.  I have a family to feed.



On 17 Jun 2002 21:18:46 -0700, farhad@everdream.com (Farhad Abdolian)
wrote:

>Hi,
>I am currntly on H1-B visa, and since my current employer has decided
>to close our office, I am looking for a new job, and a company to take
>over my H1-B visa while my green card application goes through (my
>wife is American).
>


Article: 44389
Subject: The Placer is Crazy
From: "Kevin Neilson" <kevin-neilson@removethistextattbi.com>
Date: Wed, 19 Jun 2002 06:10:45 GMT
Links: << >>  << T >>  << A >>
My design has a big FIR, comprised of blockRAMs and pipelined adders, most
of which I had to hand-place with a Perl script to meet timing.  There are
64 adders, each with two 18-bit inputs and a registered 19-bit result.  My
script placed the output registers of each of the 19 flops for all the
adders.  As is to be expected, the Xilinx (4.2 sp3) placer put the requisite
LUTs and carry chains in a row, lined up next to the output registers.  The
exception was that in each  of the 64 adders, the LUT that adds the two most
significant bits was placed haphazardly, not in line with the rest.  Some
were fairly close, while some were as far away as they could be and still
remain on the die.  These paths all failed timing, of course.  I finally had
to modify my Perl script to place these LUTs in the correct position next to
the output register.  Since these are named by the synthesizer I don't like
doing this because the names can change after synthesis.  I shouldn't have
to do it anyway.  Has anybody else seen this?  (Virtex II)

-Kevin



Article: 44390
Subject: Re: new computer
From: Mark <mark@pac.net>
Date: Wed, 19 Jun 2002 06:42:19 GMT
Links: << >>  << T >>  << A >>
Hello,

From a single recent very unofficial PC performance comparison ....

Target: Virtex II XC2V6000
Xilinx: ngdbuild, map, par, trce using Design Manager. 4.1i, sp3

PC A: 650 MHz Pentium III, 1GB PC100
Execution time: ~1 hr: 30 min (+/- 5 min)

PC B: 2.4 GHz Pentium IV, 2 GB PC2100
Execution time: 40 min

Caveate:  This is only one comparison of a single run on each computer.
Most of the time (A: 1hr, 11 min  B: 35 min) was spent in par, where the CPU
utilization was 100%, according to NT 4.0, sp6 task manager.  par execution
time ratio: 71/35 ~= 2.03.  Memory speed ratio: 266/100 ~= 2.66.  CPU speed
ratio: 2400/650 ~= 3.69.  Although CPU utilization was 100%, the execution time
ratio seems to imply that memory bandwidth was the limiting factor.  But, the
CPU was not <100%, so it's unclear why the execution time was not shorter.
(IOW, I don't know what else the CPU was doing.)  Screen saver, virus scanner,
email, etc. were off.

I've heard several times that FPGA tools are CPU intensive, but I think that
machine specification should consider factors in addition to CPU speed, e.g.,
memory bandwidth, size of memory (to hold database), and M/B/chipset.  We also
considered a dual-CPU M/B.  Unfortunately, no tools, that we have, can take
advantage of multiprocessor PCs.  A multiprocessor PC, in our case, would allow
us to do synthesis/simulation, while the Xilinx tools are running.  (I've tried
to script the flow, but cannot since we're using ChipScope.)

I believe that Xilinx on Linux needs Wine (from Xilinx installation notes),
which I "heard" elsewhere ends up being slightly slower than native code.  For
front-end tools, we use the Mentor tools, which I believe have been ported to
Linux, but, I haven't tried any, yet....  (I've been hoping ISD Mag will do
another "annual" comparison.)  Microsoft and Linux seem close as fas as speed,
but, Linux seems to be ahead wrt stability.

I haven't used Altera since the Flex 10K and MaxPlusII, so I don't have any
experience with the latest Altera FPGAs.  I also have no experience with the
Xeon CPUs.

Hope this helps,
Mark

mac teh knife wrote:

> We have started development using the new fpgas. We are evaluating the
> virtex 2 and stratix devices.
> What I'm finding out is my 2 year old machine ain't got what it takes to
> crunch the files that can fill up
> these multi million gate chips. I was wondering if anybody would care to
> share with us the machine (PC)
> they are using. Also has anybody evaluated linux vs window performance as
> far as fpga applications are concerned.
>
> I'm looking at a P4 2.4ghz / 2 gig ram and 533 mhz front bus. I'm also
> looking at a Xeon 2.4 g with 400 mhz
> front bus. Does anybody know if there is a performance difference between
> these two type of processors?
>
> Mac the knife is of course not my real name, I'm just so tired of spam that
> posting to use net generates.
>
> thanks
> Jerry


Article: 44391
Subject: Re: 12 years experience in Digital HW/ FPGA design, looking for job in
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Wed, 19 Jun 2002 01:45:02 -0500
Links: << >>  << T >>  << A >>


Farhad Abdolian wrote:
> 
> Hi,
> I am currntly on H1-B visa, and since my current employer has decided
> to close our office, I am looking for a new job, and a company to take
> over my H1-B visa while my green card application goes through (my
> wife is American).
> 


        If your wife is an American, won't you automatically be able to
stay in this country legally, and work without an H1-B visa?


Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 44392
Subject: Re: impacts batch mode....
From: Peter Buschhorn <peter.buschhorn@fernuni-hagen.de>
Date: 19 Jun 2002 07:20:11 GMT
Links: << >>  << T >>  << A >>
Hello "Newman"

the problem was simply a wrong XILINX Environment variable.
I found this by looking into the WebPACK_setup.bat
file.

Almost at the same instant of time I received a mail from
Brendan, whom I would like to say thanks at this point.
Your hint was exactly what I was looking for.

Many thanks for the kind replies

Happy fpga-ing

Peter


> Peter,
>   I check the following link, and it say impact is supported by
>   webpack 
> 
> http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1085522837/UserTemp
> late/1 
> 
> When I type impact -batch on my ise4.2i SP3 system, i get a ">" prompt
> back. 
> 
> It sounds like you have a setup issue.
> 
> Newman
> 


Article: 44393
Subject: Re: beginer's question: what does tran means in verilog
From: Muzaffer Kal <kal@dspia.com>
Date: Wed, 19 Jun 2002 07:21:44 GMT
Links: << >>  << T >>  << A >>
On Tue, 18 Jun 2002 13:58:32 -0600, "Cyrille de Brébisson"
<cyrille_de-brebisson@hp.com> wrote:

>Hello,
>
>
>
>this is I am sure a silly question, but what does tran means in verilog
>code?

Tran declares a tranmission gate in Verilog which is a bidirectional
buffer. Tran doesn't (can't) delay the data going through it and the
main application seems to be converting Z state to X state.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 44394
Subject: Info required on SPI3
From: ghate_abhi@yahoo.com (Abhishek Ghate)
Date: 19 Jun 2002 00:29:18 -0700
Links: << >>  << T >>  << A >>
Hi,

Where can i get more information on SPI-3?
I want to know whether 32 bit interface is shared in case of 8 bit operation 
by 4 PHY devices or only device is supported in case of 8/32 interface.

Thanx in Advance .
Shripad

Article: 44395
Subject: Re: 5V tolerance
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 19 Jun 2002 08:46:00 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> The ATA standard only specifies (5v) TTL level signals.  AFAIK, it is up to the
> manufacturer to choose whatever logic family he wants for the disk side of
> theinterface provided he fits within the specification.  SInce you normally will
> not know what device the manufacturer is using (and if you allow use with any
> drive), you must accept any signal level that conforms to the spec.  Likewise, I
> sincerely doubt you will be able to get IBIS models for the drive, and even if
> you could they would only be for a specific drive.  The data bits on the bus are
> bidirectional, so you will have considerable trouble trying to get the resistor
> trick to work reliably.  I highly recommend using one of the 5v tolerant devices
> to interface to the disk, otherwise, you are going to need to use a level
> translator to interface it.  For Xilinx families that means either the original
> Virtex or SpartanII (not E) for new designs.
>

I think that for IDE drives supporting UDMA100 (ATA mode 5) the IO supply and
signalling are supposed to be 3.3V and there are some heavy requirements on the
cable & connector for modes > 2. Any IBIS modelling might have to take the ribbon
cable into account if the disk is not being directly mounted on the PCB with a
right-angled socket.


Article: 44396
Subject: Re: beginer's question: what does tran means in verilog
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 19 Jun 2002 08:49:01 +0100
Links: << >>  << T >>  << A >>


Muzaffer Kal wrote:

> On Tue, 18 Jun 2002 13:58:32 -0600, "Cyrille de Brébisson"
> <cyrille_de-brebisson@hp.com> wrote:
>
> >Hello,
> >
> >
> >
> >this is I am sure a silly question, but what does tran means in verilog
> >code?
>
> Tran declares a tranmission gate in Verilog which is a bidirectional
> buffer. Tran doesn't (can't) delay the data going through it and the
> main application seems to be converting Z state to X state.
>
> Muzaffer Kal
>
> http://www.dspia.com
> ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Its also useful in testbenches as the only way I know of "renaming" a bi-dir signal.


Article: 44397
Subject: Re: beginer's question: what does tran means in verilog
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Wed, 19 Jun 2002 09:07:39 +0100
Links: << >>  << T >>  << A >>
In article <aeo3da$pas$1@web1.cup.hp.com>, Cyrille de Brébisson
<cyrille_de-brebisson@hp.com> writes
>Hello,
>
>
>
>this is I am sure a silly question, but what does tran means in verilog
>code?

Not silly, but probably better posted on comp.lang.verilog

I guess you already know about Verilog "primitives" - they are
a kind of predefined module.  All the usual gates (and, or, xor...)
are available.  Primitives are different from modules in three 
important ways:

1) you do not need to supply an instance name, so this is OK:

  // an instance of the 'and' primitive with an instance name
  and U1 (out1, in1a, in1b);
  // an instance of the 'and' primitive with no instance name
  and (out2, in2a, in2b);

2) the parameter override syntax is used not to control parameters,
   but to specify a propagation delay for the primitive instance

3) the number of ports is variable for some primitives:  for 
   example, this is a 4-input AND gate:

   and My_4_input_gate (out3, in3a, in3b, in3c, in3d);

There is a family of primitives representing bidirectional
pass switches or transmission gates:

tran(A,B)       is a link between A and B
tranif1(A,B,E)  is a transmission gate between A and B,
                enabled by a high level on E

tranif0 is the same as tranif1 but has active-low enable.

There is also a family of unidirectional switch elements intended
to model MOS transistors used in transmission-gate logic: 
nmos, pmos, cmos.

Using the tran elements gives the simulator some extra work, and
makes it more difficult to do mixed VHDL/Verilog simulation.
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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Article: 44398
Subject: Re: ISE Webpack Basics
From: "Felix Bertram" <f.bertram@trenz-electronic.de>
Date: Wed, 19 Jun 2002 11:40:05 +0200
Links: << >>  << T >>  << A >>
Thomas,

we offer a set of tutorials, explaining FPGA technology in general, and
basic steps with WebPACK ISE. Check the following URLs:
http://www.trenz-electronic.de/down/tc-XC2S-SoC-1.pdf
http://www.trenz-electronic.de/down/tc-XC2S-SoC-2.pdf

In addition to the tutorials, there are a few application notes with
documentation and project files. Check our download page:
http://www.trenz-electronic.de/down/downen.htm#FDOWN3


Hope this helps,
best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic GmbH
Brendel 20
D - 32257 Buende
Tel.: +49 (0) 5223 4939755
Fax.: +49 (0) 5223 48945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de




Article: 44399
Subject: ISE Webpack Basics
From: Thomas <ThoLei@gmx.net>
Date: Wed, 19 Jun 2002 02:12:07 -0800
Links: << >>  << T >>  << A >>
Hi @ all! 

I am a complete Newbie to FPGA´s, but now i must work with them. I have a Spartan II Demo Board (Insight) with XC2S100 FPGA and want to use ISE Webpack for programming it. I have searched for documentations, tutorials but have not found yet any good results. Does anyone have suggestions where to find good eplainations using ISE Webpack??? 

Thank you, Thomas 

PS: Could you please answer as well via Email?



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