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Authors (B)
b:
10064: 98/04/24: http://www.ebnonline.com
B:
65902: 04/02/09: MAC FIR V3.0 POLYPAHSE DECIMATION
B Olney:
6392: 97/05/21: Aust. SMT PCB Design Course
$B%F%l%SElD.3t<02q<R(J:
12797: 98/10/30: $B$40FFb(J
B. Joshua Rosen:
17318: 99/07/20: Re: Solaris vs. NT, use Linux
17485: 99/07/30: Xilinx FPGA Editor works under wine
17538: 99/08/07: Re: comparison with xxxx
17623: 99/08/15: Re: Best synthesis tools for virtex?
17624: 99/08/15: Re: VHDL/Verilog? - Can of Worms
17821: 99/09/07: Re: synthesis comparion between Synplify and FPGA express
18785: 99/11/15: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18881: 99/11/19: Re: Virtex: Getting flip-flops into the pads
19107: 99/11/29: Re: HDL editor?
19232: 99/12/07: Re: AM2901 bit slice processor
20172: 00/01/29: Re: Xilinx programming from a Linux PC
20186: 00/01/30: Announcement: Xilinx on Linux HowTo
20227: 00/02/01: Re: Count 1's algorithm...
20263: 00/02/02: Re: Announcement: Xilinx on Linux HowTo
23031: 00/06/09: Re: XILINX RAM Useless
23032: 00/06/09: Re: XILINX RAM Useless
23098: 00/06/14: Re: DLL in virtex fpga
23204: 00/06/17: Request for experiences with Linux CAE tools
23239: 00/06/18: XilinxOnLinux Howto update
23322: 00/06/22: Re: dual processor PC for PPR - are they worth the extra cost?
23377: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23402: 00/06/23: Re: a lot of basic questions - where's the FAQ?
23581: 00/07/01: Re: Maximum Speed on obtainable on FPGAs?
23614: 00/07/02: Re: How can I search this newsgroup archive?
23924: 00/07/15: Re: Silicon Valley Housing Nightmare?
24392: 00/08/06: Re: Help!! Virtex system gate count.
24444: 00/08/08: Re: Memory specification
24477: 00/08/10: Xilinx of Linux Howto Updated
24694: 00/08/16: Re: Permanently programming FPGAs
25231: 00/08/31: Re: Latches
25257: 00/09/02: Re: Xilinx block Ram Verilog model
25328: 00/09/06: Re: About XNF, EDIF and UCF
25402: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25415: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25416: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25424: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25438: 00/09/11: Re: Nanoseconds and seasons
25439: 00/09/11: Re: Nanoseconds and seasons
25441: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25666: 00/09/16: Re: Reassurance on Xilinx Sought
28331: 01/01/07: Xilinx of Linux Howto Updated
28344: 01/01/08: Re: Alliance for Linux
28345: 01/01/08: Hdlmaker updated
31591: 01/05/30: Xilinx on Linux Howto Updated
33523: 01/07/29: Re: Xilinx/Altera "behavioral" verilog
33534: 01/07/29: Re: finite defect statistics
33546: 01/07/30: Re: finite defect statistics
33547: 01/07/30: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33580: 01/07/30: Re: finite defect statistics
33593: 01/07/31: Re: finite defect statistics
33617: 01/07/31: Re: finite defect statistics
33637: 01/08/01: Re: finite defect statistics
33641: 01/08/01: Re: finite defect statistics
39909: 02/02/21: Re: Linux tools
40532: 02/03/08: Re: exceeding 2GB limits in xilinx
40544: 02/03/09: Re: exceeding 2GB limits in xilinx
41632: 02/04/03: Re: powerpc in virtex2pro
43060: 02/05/11: Re: Transistor Counts for Xilinx FPGAs
49726: 02/11/19: HDLmaker
51349: 03/01/11: Has anyone used the SerDes on the VirtexIIP?
51504: 03/01/14: Re: Open FPGA please!
51788: 03/01/21: Re: VHDL or Verilog?
51823: 03/01/22: Re: VHDL or Verilog?
51843: 03/01/23: Re: VHDL or Verilog?
52179: 03/02/03: Re: Clock Feedback for DDR-SDRAM (XApp200)
53179: 03/03/05: Re: Mac Os X for FPGA design
53433: 03/03/13: Re: AMD Temp Specs
53544: 03/03/15: Re: blockram optimized away
53587: 03/03/17: Re: Help understanding 7408 and gate chip
53604: 03/03/17: Re: Help understanding 7408 and gate chip
53708: 03/03/20: Re: Help understanding 7408 and gate chip
54014: 03/03/31: Re: $4000 FPGAs
54259: 03/04/06: Re: Should I bother with Xilinx Foundation 1.5 vs 2.1?
54432: 03/04/10: Re: Webpack 5.2 and Win98se
54438: 03/04/10: Re: Webpack 5.2 and Win98se
54886: 03/04/21: Re: Webpack 5.2 Install problems?
54933: 03/04/22: Re: Webpack 5.2 Install problems?
55032: 03/04/24: New version of HDLmaker available
55056: 03/04/25: Xilinx of Linux HOWTO has been updated
55092: 03/04/25: Re: ise4.2i and wine
55100: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
55105: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
55831: 03/05/20: Re: a (PC) workstation for FPGA development
56297: 03/06/02: HDLmaker update available
56320: 03/06/03: Re: HDLmaker update available
56696: 03/06/11: Re: HDLmaker update available
56872: 03/06/17: Re: XCV 6000 data sheets
57081: 03/06/23: Re: Equivalent Gate Count ??
57115: 03/06/23: Re: Xilinx ISE Webpack on Linux?
57116: 03/06/23: Re: MIPS instruction set?
57351: 03/06/27: Re: defparam LUT_4
57762: 03/07/06: Re: Xilinx ISE drops support for more parts
57764: 03/07/06: Re: Xilinx ISE drops support for more parts
57765: 03/07/06: Re: Xilinx ISE drops support for more parts
57766: 03/07/06: Re: Xilinx ISE drops support for more parts
57845: 03/07/08: Re: Xilinx ISE drops support for more parts
57865: 03/07/08: Re: Xilinx ISE drops support for more parts
58004: 03/07/11: Re: Xilinx ISE drops support for more parts
58834: 03/08/02: Re: 5 volt tolerant Xilinx parts
58836: 03/08/02: Re: 5 volt tolerant Xilinx parts
58930: 03/08/04: Re: 5 volt tolerant Xilinx parts
59215: 03/08/12: Re: Upgrading OS or WebPack
61235: 03/09/30: New version of HDLmaker available
62175: 03/10/21: Re: 74 logic to CPLD. how easy for a Newbie?
62946: 03/11/11: Re: Reverse engineering an EDIF file?
63505: 03/11/24: Re: Xilinx legacy situation
63807: 03/12/04: Re: Ideal Development Machine Specifications
64114: 03/12/16: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
64126: 03/12/17: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
64589: 04/01/08: Re: Synthesis in VHDL vs. Verilog
64607: 04/01/08: New HDLmaker release available
64641: 04/01/09: Re: Synthesis in VHDL vs. Verilog
65052: 04/01/19: Re: QUES: Where can I find Xilinx M1 tools
65422: 04/01/28: Re: ISE6.1 : using virtex 800
65442: 04/01/29: Re: Is FPGA fully static?
65444: 04/01/29: Re: FPGA basics
65621: 04/02/03: Re: Is it possible that a Virtex II device performs below its spec?
65793: 04/02/06: Re: Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?
65844: 04/02/07: Re: A small clock synchronization challenge with Virtex E
65869: 04/02/09: Re: Virtex-3 PRO
66520: 04/02/20: Re: multiple clocking in FPGA
66529: 04/02/21: Re: Spartan 3 - avaliable in small quantities?
66533: 04/02/21: Re: Random logic verilog gate netlist generator
66553: 04/02/22: Re: Spartan 3 - avaliable in small quantities?
67118: 04/03/05: Re: Testing a Verilog design after synthesis in Xilinx ISE
67157: 04/03/07: Re: licence for Xilinx 2.1i
67334: 04/03/10: Re: licence for Xilinx 2.1i
67819: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67901: 04/03/22: Re: cpu and linux on a fpga (new to FPGAs)
68234: 04/03/30: Re: speed vs. temperature
68235: 04/03/30: New release of HDLmaker available
68271: 04/03/31: Re: Athlon FX vs Pentium 4 benchmarks for xilinx's par
68349: 04/04/01: Re: Xilinx License Question
68636: 04/04/11: Re: Help need writing Single Port Block Ram in verilog
68977: 04/04/23: Re: Best Xilinx toolchains for under $2,000 ?
69047: 04/04/26: Re: ASIC RTL and FPGA RTL
72299: 04/08/13: Re: Infiniband via RocketIOs (RocketIO, Rocket IO) on Virtex 2 (Virtex2, Virtex II, Virtex-II)
72469: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72497: 04/08/20: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72505: 04/08/21: Re: XST synthesis
72510: 04/08/21: Re: XST synthesis
72555: 04/08/24: Re: Xilinx in Linux
72624: 04/08/26: Re: Xilinx Command Prompt
72677: 04/08/28: Re: 16-depth FIFO and 64-depth FIFO use the same Ram
73706: 04/09/28: Re: XST Tool - Want a verilog simulation netlist
73735: 04/09/28: Re: Xilinx Constraints
73437: 04/09/21: Re: ISE and BaseX for Linux?
73515: 04/09/22: Can Map and Par still handle the XC4000e family?
73558: 04/09/23: New HDLmaker release, Virtex4 support added
74814: 04/10/19: Re: Virtex-4 Slower than V2Pro?
75709: 04/11/12: Re: Obsolete processors resurected in FPGAs
75946: 04/11/19: Re: RocketIO success?
76894: 04/12/15: Re: Xilinx speed grading
76914: 04/12/15: Re: Xilinx ISE 6.3.03i service pack size
76947: 04/12/16: Re: Xilinx speed grading
76953: 04/12/16: New HDLmaker release
77611: 05/01/12: Re: Starting with xilinix and Linux
77615: 05/01/12: Re: Starting with xilinix and Linux
77616: 05/01/12: Re: Starting with xilinix and Linux
77651: 05/01/13: Re: Starting with xilinix and Linux
78461: 05/02/01: Re: Evaluating EDIF netlist
80040: 05/02/28: FPGA tool benchmarks on Linux systems
80109: 05/03/01: Re: FPGA tool benchmarks on Linux systems
80241: 05/03/02: Re: FPGA tool benchmarks on Linux systems
80571: 05/03/08: Re: ISE Foundation/BaseX 7.1i evaluation for Linux
80630: 05/03/09: Re: ISE Foundation/BaseX 7.1i evaluation for Linux
80640: 05/03/09: Re: ISE Foundation/BaseX 7.1i evaluation for Linux
81162: 05/03/18: Re: Altera free web FPGA software license question
81427: 05/03/23: ISE 7.1 on Fedora Core 3
81433: 05/03/23: Re: ISE 7.1 on Fedora Core 3
82084: 05/04/06: Re: Stupid question
82752: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82754: 05/04/17: Re: Xilinx tools from the commandline
83224: 05/04/26: Re: A PC for make synthesis
83270: 05/04/26: Re: A PC for make synthesis
84225: 05/05/15: Re: FPGA design under Mac OS X ?
84316: 05/05/17: Re: FPGA design under Mac OS X ?
84385: 05/05/18: Re: FPGA design under Mac OS X ?
84504: 05/05/19: Re: Simulation of rocket IO in virtex 2 pro
84571: 05/05/21: Re: ISE and Linux
85041: 05/06/03: Re: ISE under Linux: 32 vs 64 bits
85597: 05/06/11: Re: Synplify vs XST...
85603: 05/06/11: Re: computer upgrade time.
85675: 05/06/13: Re: Synplify vs XST...
85798: 05/06/16: Re: Synplify vs XST...
86800: 05/07/06: Re: fastest FPGA speed grade?
87133: 05/07/16: Can't run Xilinx 7.1SP3 on FC3
87139: 05/07/16: Re: Can't run Xilinx 7.1SP3 on FC3
89351: 05/09/13: Re: CPU benchmark for Xilinx PAR
89354: 05/09/13: Re: ISE 7.1i & Linux / reg code question
89404: 05/09/14: Re: CPU benchmark for Xilinx PAR
89714: 05/09/23: Re: Synchronizer Flip Flop / Metastability
89824: 05/09/27: Re: Synchronizer Flip Flop / Metastability
115588: 07/02/14: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115601: 07/02/14: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115602: 07/02/14: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
116046: 07/02/28: Altera Byte Blaster Cable on Linux
116843: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
117461: 07/04/01: Re: ISE on Fedora?
117988: 07/04/15: Running Xilinx 9.1 GUIs on FC6
118020: 07/04/16: Re: Running Xilinx 9.1 GUIs on FC6
118194: 07/04/19: Re: Printing problem with Ise 9.1.03i
122570: 07/07/31: Re: DDR Simulation Model
B. Mitchell Loebel:
418: 94/11/12: The PARALLEL Processing Connection - November '94 meeting notice
419: 94/11/12: The PARALLEL Processing Connection - What Is It?
2570: 96/01/04: The PARALLEL Processing Connection - January Meeting Notice
2571: 96/01/04: The PARALLEL Processing Connection - What Is It?
2791: 96/02/09: The PARALLEL Processing Conection - What Is It?
2792: 96/02/09: The PARALLEL Processing Connection - February Meeting Notice
3293: 96/05/10: The PARALLEL Processing Connection - May 13th Meeting Notice
3294: 96/05/10: The PARALLEL Processing Connection - What Is It?
3904: 96/08/16: The PARALLEL Processing Connection - What Is It?
3903: 96/08/16: The PARALLEL Processing Connection - August '96 meeting notice
4058: 96/09/06: The PARALLEL Processing Connection - What Is It?
4059: 96/09/06: The PARALLEL Processing Connection - September 9th Meeting Notice
4060: 96/09/06: PARALLEL Processing Connection - September 9th Meeting Notice
B. Mitchell Loebel, Executive Director:
7381: 97/09/04: September 8th Meeting - The PARALLEL Processing Connection
7382: 97/09/04: The PARALLEL Processing Connection - What Is It?
<b.popoola@ntlworld.com>:
56511: 03/06/07: Re: Orcad 2 Quartus
B.Thierry:
17520: 99/08/05: [FRANCE] we need "help" with programming a FPGA
b1052:
3144: 96/04/12: ACTEL design with Synopsys
b2508:
158314: 15/10/20: Sum of 8 numbers in FPGA
158330: 15/10/22: DC Blocker
158333: 15/10/22: Re: DC Blocker
158337: 15/10/22: Re: DC Blocker
158347: 15/10/23: Re: DC Blocker
158348: 15/10/23: Re: DC Blocker
B?rge Strand:
78195: 05/01/26: Spartan III place fails
B__ S_______:
45448: 02/07/24: Re: How's the FPGA design job market near you??
45450: 02/07/24: Re: Translate the design from FPGA to Custom IC
<b_kapoor@yahoo.com>:
80990: 05/03/15: EDPS 2005 Early Registration Ends March 16, 2005
<b_rich2@my-dejanews.com>:
11744: 98/09/07: Altera 10K20 Register File Implementation??
11749: 98/09/07: Re: Altera 10K20 Register File Implementation??
ba@jb.man.ac.uk:
105671: 06/07/28: 4VSX35 LOC placements?
105674: 06/07/28: Re: 4VSX35 LOC placements?
<babock@yahoo.com>:
80600: 05/03/08: NIOS SRAM Problem with Stratix
baboonspanker@fastmail.fm:
105487: 06/07/24: Soft processor performance
bachimanchi@gmail.com:
98992: 06/03/18: question regarding maximum frequency on virte-e-2000
99060: 06/03/19: memories for virtex-4 and Spartan-3E
99069: 06/03/19: is conv_integer(unsigned(value)) synthesizable
99218: 06/03/21: BRAM for virtex-4
99277: 06/03/22: error from synopsys design compiler
99278: 06/03/22: regarding synopsys design anlyzer
101002: 06/04/24: regarding memories using megafunction wizard(altera)
115302: 07/02/06: regarding the usage of embedded ethernet MAC on Virtex4
115423: 07/02/09: regarding the usage of tri mode EMAC on virtex 4
<bachimanchi@gmail.com>:
92650: 05/12/02: problem with timing simulation
92652: 05/12/02: problem with timing simulation (clear explanation of problem)
92670: 05/12/03: how to build 32X32 LUT ROM
backhus:
80686: 05/03/10: Re: ethernet core on a xc3s200
81011: 05/03/16: Re: RS232 VHDL-core
82940: 05/04/20: Re: Strange FPGA problem
83516: 05/05/02: Re: Case statement illusions ?
83521: 05/05/02: Re: dynamic size of ports
86226: 05/06/23: Re: DC Offset removal in FPGA
87817: 05/08/02: Re: Conversion of Schematic to Verilog/VHDL
87818: 05/08/02: Re: Asynchronous Priority comparator
88096: 05/08/09: Re: START /STOP sync pattern
88175: 05/08/11: Re: Rapid prototyping in FPGA
88183: 05/08/11: Re: rom
89905: 05/09/30: Re: There is a way to instantiate 'N' VHDL components using a repetitive
89906: 05/09/30: Re: Preloading SDRAM?
90475: 05/10/14: Re: Storing a file onto FPGA
90565: 05/10/17: Re: Storing a file onto FPGA
90623: 05/10/18: Re: Data2Mem usage - help required
90624: 05/10/18: Re: Storing a file onto FPGA (the last word)
90694: 05/10/19: Re: Data2Mem usage - help required
90960: 05/10/26: Re: newbie question
91009: 05/10/27: Re: Optimizing a State Machine
91136: 05/10/31: Re: How to reduse the logic.
91455: 05/11/07: Re: Adder synthesis
91628: 05/11/10: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91718: 05/11/11: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91852: 05/11/15: Re: Help needed to design recursive digital circuit
92078: 05/11/22: Re: synthesis
92145: 05/11/23: Re: Newbie: Problems with clocks
92150: 05/11/23: Re: Question on 2048 point FFT( Basic)
92165: 05/11/23: Re: We need to program several thousands Xilinx flashes XCF025...
92336: 05/11/28: Re: subtractor
92349: 05/11/28: Re: subtractor
92458: 05/11/30: Re: subtractor
92534: 05/12/01: Re: Any fpga tutorials online?
92914: 05/12/09: ISE = Intelligent Synthesis Expectable :-)
93012: 05/12/12: Re: ISE = Intelligent Synthesis Expectable :-)
93051: 05/12/13: Re: ISE = Intelligent Synthesis Expectable :-)
93058: 05/12/13: Re: ISE = Intelligent Synthesis Expectable :-)
93112: 05/12/14: Re: ISE WebPack 8.1i
93225: 05/12/16: Re: Inverter Chain Synthesis Problem
93967: 06/01/04: Re: Coding style
94245: 06/01/09: Re: Help! FIR Filter - MATLAB fdatool - VHDL
94485: 06/01/12: Re: How to create a delay BUF?
94726: 06/01/17: Re: How to drive 4 output ports with one combinational signal
96527: 06/02/06: Re: Microblaze question
96892: 06/02/13: Re: digital logic library by 74xxxx part number?
96954: 06/02/14: Re: Entity with Multiple Architectures
97574: 06/02/24: Re: configuring Hardware
97575: 06/02/24: Re: Kalman filters
98443: 06/03/10: Re: FPGA imple. of aes
98642: 06/03/14: Re: Why does Xilinx hate version control?
98711: 06/03/15: Re: FPGA imple. of aes
99765: 06/03/29: Re: how to immitate clock behavior----Please guide
99767: 06/03/29: Re: Question about: Logic Levels in Critical Path
99924: 06/03/31: Re: design compiler optimization
99927: 06/03/31: Re: Xilinx Schematic Entry
100875: 06/04/20: Re: Is there anything fundamentally wrong with this code?
102061: 06/05/10: Re: Xilinx ISE 8.1 Makefile
103843: 06/06/13: FSM state minimization with ISE?
103883: 06/06/14: Re: FSM state minimization with ISE?
103885: 06/06/14: Re: FSM state minimization with ISE?
103888: 06/06/14: Re: null waveform element and webpack
103924: 06/06/15: Re: FSM state minimization with ISE?
103969: 06/06/16: Re: FSM state minimization with ISE? Apology:Tommys solution was
103972: 06/06/16: Re: FSM state minimization with ISE?
103974: 06/06/16: Re: How process statement works in vhdl
104104: 06/06/19: Re: FSM state minimization with ISE?
104143: 06/06/20: Re: using Impulse-C free edition for VHDL only FPGA designs.
104153: 06/06/20: FSM State Minimization on FPGAs
104192: 06/06/21: Re: FSM State Minimization on FPGAs
104194: 06/06/21: Locks for the peasants :-)
104254: 06/06/22: Re: FSM State Minimization on FPGAs
104256: 06/06/22: Re: Locks for the peasants :-)
104577: 06/06/30: Re: How to evaluate the space efficiency of a historic design.
105072: 06/07/13: Re: Binary Counter Core
105508: 06/07/25: Re: Connecting two buses in Xilinx ISE
105809: 06/08/01: Re: Quick way to change Xilinx BRAM init values
105814: 06/08/01: Re: FPGA : BUG in ISE- View RTL Schematics ?
106600: 06/08/16: Re: Alternative for Mentor''s HDL Designer
107053: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107056: 06/08/24: Re: esoteric hardware?
107168: 06/08/25: Re: Style of coding complex logic (particularly state machines)
110185: 06/10/12: Re: Functional Languages in Hardware
110186: 06/10/12: Re: Finite State Machine
111445: 06/11/03: Re: regardign signal assinment statement............................
111626: 06/11/07: Re: How to simulate netlist with gated clock?
111627: 06/11/07: Re: Should I use an external synthesis tool?
111683: 06/11/08: Re: How to simulate netlist with gated clock?
111684: 06/11/08: Re: confused result in Logic Analyser, being crazy...
111906: 06/11/13: Re: Question about adder structure
112030: 06/11/15: Re: Programming model on FPGA
112775: 06/11/29: Re: ModelSim Xilinx edition new bug?
112922: 06/12/01: Re: How to save a changed *.wlf file with ModelSim
114337: 07/01/12: Re: VHDL Model of a stepper motor
114341: 07/01/12: Medwedjew - who was that guy?
114566: 07/01/19: Re: "Gate" = ???
114642: 07/01/22: Re: how to use register to save data
114649: 07/01/22: what happened to modular design in ISE9
114691: 07/01/23: Re: how to use register to save data
114692: 07/01/23: Re: what happened to modular design in ISE9
114910: 07/01/26: Re: ModelSim Leaf Instances
115350: 07/02/08: Re: Parallelism in HDL
115457: 07/02/12: Re: ModelSim - Do Files
115466: 07/02/12: Re: substracting a whole array of values at once
115523: 07/02/13: Re: substracting a whole array of values at once
115524: 07/02/13: Re: Picobalze in the FPGA
115579: 07/02/14: Re: Picobalze in the FPGA
115580: 07/02/14: Re: substracting a whole array of values at once
115589: 07/02/14: Re: substracting a whole array of values at once
115590: 07/02/14: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115623: 07/02/15: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115975: 07/02/27: Re: Picobalze in the FPGA
118128: 07/04/18: Re: ModelSim Waveform naming question
119900: 07/05/29: Re: Looking for experiences with SUZAKU SZ010/SZ030
121116: 07/06/26: Re: Confused about FPGA devices recommended by Xilinx for my FFT
121783: 07/07/13: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
123006: 07/08/14: Re: edk+uclinux ??? <about make dep>
123090: 07/08/16: Re: about mb-gcc error???
124347: 07/09/19: Re: Looking for fast AES cores with low latency
124379: 07/09/20: Re: Looking for fast AES cores with low latency
124725: 07/10/02: Re: Error in simple code, plz help
124993: 07/10/15: Re: FIFO depth
124994: 07/10/15: Re: R: Newbie,the simplest way to program an FPGA at home?
125051: 07/10/16: Re: FPGA quiz: what can be wrong
125057: 07/10/16: Re: FIFO depth
125163: 07/10/17: Re: FPGA quiz: what can be wrong
127748: 08/01/07: Re: What does this do ?
128360: 08/01/23: Re: Ballistic chronograph using a Spartan 3E starter board
128970: 08/02/12: Re: how to implement this...
129024: 08/02/13: Re: '1' or '0' when I/O pin is pulled up
129026: 08/02/13: Re: how to implement this...
129087: 08/02/14: Re: State machine outputs and tri-state
129822: 08/03/06: Re: how to optimize a design for speed
131493: 08/04/23: Re: the order in which some switches are turned on
131725: 08/04/30: Re: how to optimize this comparator for better synthesis result?
132166: 08/05/16: Re: Length between blocks in FPGA
132167: 08/05/16: Re: What could be the problem?
132300: 08/05/21: Re: 2-bit Pseudo Random Number Generator
132501: 08/05/29: Re: HDL - simulation vs synthesis
132535: 08/05/30: Re: Xilinx Clock Doubler
132536: 08/05/30: Re: asic gate count
132609: 08/06/03: Re: asic gate count
132628: 08/06/04: Re: Counter implementation with ise problem
132667: 08/06/05: Re: Counter implementation with ise problem
133065: 08/06/17: Re: WARP
133067: 08/06/17: Re: Cheating the FPGA clock speed
133367: 08/06/26: Re: FPGA area use by module?
133370: 08/06/26: Re: Signal forwarding between FPGAs
133376: 08/06/26: Re: Xilinx register inits
133385: 08/06/26: Re: Xilinx register inits
133402: 08/06/27: Re: Xilinx register inits
134498: 08/08/14: Re: Hardware in Loop
135794: 08/10/16: Re: Simulation
136614: 08/11/26: Re: Deserializing Camerlink on Spartan XC3s400
136719: 08/12/03: Re: Hold Time Requirement
136981: 08/12/17: Re: Microblaze without external ram
137640: 09/01/26: Re: picoblaze q's
137888: 09/02/02: Re: Cameralink Big Help Needed
137890: 09/02/02: Re: Heavily pipelined design
141801: 09/07/09: Re: How to implementa an FSM in block ram
142555: 09/08/16: Re: BCD in FPGA
142592: 09/08/19: Re: BCD in FPGA
143325: 09/10/02: Re: Antti-Brain one year anniversary
143369: 09/10/06: Re: Ideas for a pulse programmer needed
143855: 09/10/29: Re: Simple state machine output question
143933: 09/11/03: Re: initialization issues on Spartan-3E after startup
144362: 09/11/30: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
145131: 10/01/28: Re: Xilinx DCM: Is CLKIN_PERIOD really required
145737: 10/02/21: Re: how to read bmp file in vhdl
146569: 10/03/22: Re: Writing Hex values to file in VHDL?
147070: 10/04/12: Re: How to find latches in Xilinx ISE 10.1
147291: 10/04/21: Re: Virtex 7?
147637: 10/05/10: Re: Expecting sequential output, but RTL shows concurrent
147649: 10/05/11: Re: Expecting sequential output, but RTL shows concurrent
147673: 10/05/13: Re: Expecting sequential output, but RTL shows concurrent
147912: 10/06/01: Re: Graphical User Interface project on Spartan-3 FPGA
147913: 10/06/01: Re: Graphical User Interface project on Spartan-3 FPGA
148042: 10/06/16: Re: How to detect a sync and start of a frame in an optimal way
148301: 10/07/06: Re: Q: Standard Programming Idiom
148316: 10/07/06: Re: FPGA Video processing board (HDMI).. who makes one?
148966: 10/09/16: Re: FPGA speech recongintion system
149266: 10/10/12: Re: store data into fpga
149463: 10/10/26: Re: Simulating Xilinx FIFOs
149556: 10/11/05: Re: SVGA Controller on FPGA
149943: 10/12/02: Re: SPI master controller with no embedded microprocessor
150139: 10/12/16: Re: FPGA modules/cards with peripheral functions
150256: 11/01/05: Re: Dual port Ram
150423: 11/01/20: Re: Prime number testing on FPGA
150437: 11/01/20: Re: Prime number testing on FPGA
150502: 11/01/24: Re: Prime number testing on FPGA
150537: 11/01/25: Re: how to read an image from the PC and store it in FPGA ROM
150617: 11/01/27: Re: Simple clock question
150666: 11/02/01: Re: Xilinx Acquires AutoESL
150820: 11/02/15: Re: why an FSM is not a counter?!
150905: 11/02/20: Re: timing issues at high speed
151386: 11/03/31: Re: Ideal FPGA Development Kit
151387: 11/03/31: Re: Spartan 3e FPGA and data from matlab workspace.
151470: 11/04/11: Re: Source of Dynamic Power Consumption in FPGAs
151622: 11/04/26: Re: VHDL design and System Verilog testbench
152588: 11/09/15: Re: clock enable for fixed interval
152623: 11/09/18: Re: clock enable for fixed interval
152624: 11/09/18: Re: How to digitize the VGA output using FPGA?
152647: 11/09/21: Re: Xilinx Spartan-3 Starter Kit and Webpack 13.2
152653: 11/09/23: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
152667: 11/09/25: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
152707: 11/10/04: Re: Testbench
152708: 11/10/05: Re: macro
152821: 11/10/25: Re: ADC by using counter method on FPGA using VHDL language
152822: 11/10/25: Re: FPGA functional flow..please help!
153112: 11/12/04: Re: Is it possible to save the FPGA state periodically?
153165: 11/12/21: Re: Equivalence between "XtremeDSP48 slice" and "slices of
153617: 12/04/05: Re: Mandelbrot set on Spartan3
Backman:
79771: 05/02/24: FSL : only reads 16 times
backspace:
153790: 12/05/22: ITU656 to Mpeg4 with Fpga?
bad synchrounous assignment:
101104: 06/04/25: 116 warnings... successive approximation register using both phases of clock by spliting them
badari:
96582: 06/02/06: clock problem --I new to this field so if question is silly don't mind
96585: 06/02/06: nios II stratix II handling interrrupts from uController
96594: 06/02/07: Re: nios II stratix II handling interrrupts from uController
Baddest Sinus:
98567: 06/03/13: What does a "1RW/1R Partial Write RAM Verilog HDL Model." usually. mean?
badduck:
82683: 05/04/15: hdl designer cvs in remote repository
badgrant:
91970: 05/11/18: hi everyone, tell me something about Cyclone II.
Baiju Jacob:
2: 94/07/27: FPGA based processors ?
baik jong sung <4224>:
1289: 95/05/29: Any company for conversion FPGA to ASIC?
1290: 95/05/29: Any company for conversion FPGA to ASIC?
Baitule Shreenivas Narayanrao:
15110: 99/03/07: I Need Help !!!!
bajaj:
104288: 06/06/22: Aurora 4 byte interface
<baker.ea@gmail.com>:
105227: 06/07/18: NAND flash hangs
105266: 06/07/19: Re: NAND flash hangs
bakito:
61152: 03/09/29: development-tools under linux for altera excalibur
Bakul Shah:
152606: 11/09/17: Re: The Manifest Destiny of Computer Architectures
152607: 11/09/17: Re: The Manifest Destiny of Computer Architectures
152619: 11/09/18: Re: The Manifest Destiny of Computer Architectures
152625: 11/09/18: Re: The Manifest Destiny of Computer Architectures
155370: 13/06/24: Re: New soft processor core paper publisher?
155375: 13/06/24: Re: New soft processor core paper publisher?
155399: 13/06/25: Re: New soft processor core paper publisher?
155401: 13/06/25: Re: New soft processor core paper publisher?
155415: 13/06/25: Re: New soft processor core paper publisher?
155441: 13/06/28: Re: New soft processor core paper publisher?
155444: 13/06/28: Re: New soft processor core paper publisher?
<bakul.vinchhi@gmail.com>:
99922: 06/03/30: Error : iMPACT 1208 : -'1' Boundary-Scan chain test failed at bit position 1
bala iyer:
40536: 02/03/08: Re: Mutual Clock Synchronization
Bala_k:
77779: 05/01/17: Forward-Annotating constraints to Quartus
77832: 05/01/18: Re: Input clock of PLL
77870: 05/01/19: Re: Forward-Annotating constraints to Quartus
78382: 05/01/31: Re: Master Serial Programming
78383: 05/01/31: Re: changing directory location
78514: 05/02/02: Re: Constraint on a asynchronous signal
<balajee.premraj@gmail.com>:
91757: 05/11/11: Re: Looking for tutorials for bootloader writing on xilinx SOC ??
Balaji Krishnapuram:
29709: 01/03/05: Re: ROM-based FSM implementation
Balaji Rangaswamy:
20846: 00/02/23: PWM implementation in Flex 10K.
20845: 00/02/23: test
balaji286@gmail.com:
91960: 05/11/17: aliases
<4balaji@gmail.com>:
116571: 07/03/13: faq
balajigec:
152253: 11/07/28: image storing into BRAM
152405: 11/08/19: Re: image storing into BRAM
Balakrishnan:
38356: 02/01/11: FPGA : Configurtion
balakrishnan:
35624: 01/10/12: Re: Linking components in VHDL
38360: 02/01/11: FPGA configuration
38407: 02/01/14: SPARTAN-XL CONFIGURTAION
Balakrishnan Iyer:
2823: 96/02/13: SIGDA UNIVERSITY BOOTH AT DAC-96, CALL FOR DESIGN DEMOS
BALAS009:
127432: 07/12/24: FPGA Project Support
Balogh Viktor:
93037: 05/12/12: Re: FPGA in industrial environment
baltam67:
148871: 10/09/05: Re: Want to get into FPGA
BAM:
41446: 02/03/28: I need an advice regarding a switch to a Digital Design Career
<bamboutcha9999@hotmail.com>:
131720: 08/04/29: Re: how can i recover my unencrypted bitstream starting from
131727: 08/04/30: what's the difference between .rba & .rbb files ?
131886: 08/05/06: BRAM initialization / bitstream configuration
131896: 08/05/06: Re: BRAM initialization / bitstream configuration
132158: 08/05/16: distributed RAM / BRAM
132241: 08/05/19: Re: frame format virtex 5
134710: 08/08/27: Virtex 5 bitstream encryption
134713: 08/08/27: Re: Virtex 5 bitstream encryption
134728: 08/08/28: Re: Virtex 5 bitstream encryption
136523: 08/11/20: How could i play my SVF file correctly ?
138104: 09/02/06: Problem within virtex5 LX prototype platform / BPI .
bams:
52174: 03/02/03: xilinx tools: How to convert Schematic design to VHDL code
52190: 03/02/03: Re: xilinx tools: How to convert Schematic design to VHDL code
52212: 03/02/04: component instantiation in Xilinx
52824: 03/02/23: interfacing keyboard to a xilinix fpga board
52860: 03/02/24: help me figure out this problem?
52911: 03/02/25: do xilinx has this option ?
54577: 03/04/14: synthesis of a VHDL module in Xilinx
54618: 03/04/14: writing a an entire audio file and reading it from a RAM?
Ban:
87909: 05/08/03: Re: System Engineering in the R/D World
Banana:
36142: 01/10/30: Clock attribute problem
36272: 01/11/04: Synplyfy to Xilinx pipe
36273: 01/11/04: Re: Clock attribute problem
36276: 01/11/05: Aldec question
36286: 01/11/05: count and divide Idea needed
36348: 01/11/07: Encoder timin question
36390: 01/11/07: Re: count and divide Idea needed
36391: 01/11/07: Implementation of filter with three set of coeffs
36392: 01/11/07: Can I enhance this Counter 4 and Counter 6 ???
36451: 01/11/08: Re: Implementation of filter with three set of coeffs
36543: 01/11/11: State of the art for my counters/dividers x3 , x4 , x6
37401: 01/12/09: Michelangelo's Counter
37441: 01/12/10: Re: Michelangelo's Counter
37482: 01/12/11: Re: Michelangelo's Counter
banesh:
71014: 04/07/05: Compensated clock in Stratix
<baneshwar_s@my-deja.com>:
22851: 00/05/27: implementation of mplrs using wallace,counters
23088: 00/06/14: delay variation
23554: 00/06/30: delta in timing report
Banetele news:
93383: 05/12/21: Re: Incremental Compilation in Quartus 5.1?
bankoo:
154337: 12/10/04: FPGA-Board for Ethernet
BANSAL DHAN RAJ:
74657: 04/10/15: What is role of place & route tools in synthesis in vhdl.& HOW THE AREA & time constrain are specifiesd in XIlinx or modelsim software?
74661: 04/10/15: How can FPGAs be used for high speed data acquisition????
Baoliang Wang:
47178: 02/09/19: porblem about mapping spartenII design using schematic
Bar Nash:
135555: 08/10/08: Those FPGA boards
135556: 08/10/08: Input to FPGA boards
baranwal:
97306: 06/02/20: JHDL Application
barbara feledziak:
42937: 02/05/07: Found a new interpreted language
barcode:
31652: 01/06/01: Re: Re: Help on Xilinx 6200
Bard_64:
29588: 01/02/27: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
29605: 01/02/28: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
Baris Aksoy:
16559: 99/05/28: Re: C to VHDL translator?
<barme2i@gmail.com>:
140007: 09/04/23: How to put area routing constraints in a xilinx flow
140012: 09/04/23: Re: How to put area routing constraints in a xilinx flow
140065: 09/04/27: Re: How to put area routing constraints in a xilinx flow
140606: 09/05/20: Port assignment question
BarNash:
142394: 09/08/09: EVERAGE ?
barnhart:
99270: 06/03/22: JTAG programing specs for XC18V01 PROM
99294: 06/03/22: Re: JTAG programing specs for XC18V01 PROM
Baron Samedi:
140021: 09/04/23: Seeking open-source operating system abstraction
Barron Barnett:
72051: 04/08/06: Microblaze opb_emc
Barry:
122850: 07/08/08: Re: New Xilinx forum.
122891: 07/08/09: Re: Reset and DCM
124175: 07/09/13: Virtex5 PLL for DDR2 interface
126372: 07/11/20: Xilinx Virtex 5 ISERDES vs ISERDES_NODELAY: which is better for DDR?
126488: 07/11/24: Re: DCM with instable clock
126815: 07/12/03: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?
126823: 07/12/03: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
126824: 07/12/03: Re: Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same
127968: 08/01/11: Re: Resource utilization broken down by hierarchy?
132117: 08/05/14: Re: xilinx beginner modelsim question
132542: 08/05/30: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on PLL
132548: 08/05/30: Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on
132566: 08/05/31: Re: Can I make ISE 9.2 ngdbuild stop generating new PERIOD specs on
133114: 08/06/18: Re: Basic Questions about MIG (Memory Interface Generator)
133204: 08/06/20: Re: Basic Questions about MIG (Memory Interface Generator)
135088: 08/09/15: Re: Problem with Virtex-4 IBIS model
135306: 08/09/25: Re: Xilinx Mode Select Pins
135478: 08/10/03: Re: Virtex-5 DDR2 DCI termination
135774: 08/10/15: Re: DDR2 timing questions
136862: 08/12/09: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
137383: 09/01/13: Re: Counter: natural VS std_logic_vector
138668: 09/03/03: Re: Virtex6 Virtex4 FPGA compatibility
140213: 09/05/04: Re: High-speed signals crossing a split-ground
141787: 09/07/08: Re: web alternatives to USENET comp.arch.fpga
143466: 09/10/12: Re: Xilinx post-routing signal names
Barry A. Brown:
18602: 99/11/02: Re: schematics ==> www
Barry Arneson:
41593: 02/04/02: Re: Clock termination affecting JTAG interface
Barry B. Brey:
2815: 96/02/12: Re: Help wanted: Addressing PCI memory-mapped device above 16mB
Barry Brown:
1489: 95/06/28: Re: Lattice Semiconductor WWW ??
1749: 95/08/24: Re: Quicklogic/Cypress/Warp3
7542: 97/09/19: Re: FPGA/CPLD Overview
10015: 98/04/22: Re: Problem with Minc Fitter - MACH
11366: 98/08/06: Re: PCI Core In FPGA
11511: 98/08/20: Re: Data I/O Chiplab and NT
15404: 99/03/22: Re: quicklogic w/ pci interface
24460: 00/08/09: Re: Crossing Clock Domains.
42633: 02/04/29: Power-up reset of Xilinx Spartan-II
46161: 02/08/20: How to include Xilinx library for both ModelSim and Synplify?
46200: 02/08/21: Re: How to include Xilinx library for both ModelSim and Synplify?
48068: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
48440: 02/10/17: Re: multiple clocks
48497: 02/10/18: Re: Testbenches
51421: 03/01/13: Re: from ABEL/PLDs to VHDL&VeriLog/FPGAs
51463: 03/01/14: Re: Simulate Virtex Primitive using ModelSim
52761: 03/02/20: Modelsim warnings about Spartan2 Block RAM read/write
53844: 03/03/25: Re: CLKDLL synthesized with synplify pro
58284: 03/07/18: Re: Synplify syn_direct_enable doesn't work for me.
58343: 03/07/21: Re: synplify pro
58355: 03/07/21: asynchronous FIFO
58359: 03/07/21: Re: asynchronous FIFO
61719: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
62221: 03/10/22: Re: Block Ram clocks
63254: 03/11/18: Re: xilinx platform flash question
63255: 03/11/18: Xilinx DCM LOCKED signal valid after input clock returns?
64807: 04/01/14: Virtex II - LVDS_33_DCI?
66018: 04/02/11: Re: attribute +generate statement
66127: 04/02/12: Xilinx FPGA Editor - can one see the switch box detail?
66384: 04/02/18: Re: regarding synchronization
68375: 04/04/02: Re: signal names in modelsim
70828: 04/06/29: Re: simprim X_FF component
80795: 05/03/11: Synplify Pro 8.0 - declaring clocks with DCM
97826: 06/02/28: Re: Coregen ISE 6.1
98332: 06/03/08: Re: DCM question
107080: 06/08/24: Re: DCM vs. PLL
116736: 07/03/16: Re: init of FPGA's Block-RAMs.
120260: 07/06/04: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
Barry Chu:
14499: 99/02/01: Need Help! clock multiplier!
Barry Friedman:
95743: 06/01/25: Re: Spartan-3 Starter Board
Barry Gershenfeld:
17133: 99/07/01: Re: newbie -- What's the best way to get started?
Barry Rising:
6588: 97/06/04: RIPP10 Board: Correct EMAIL Address
Barry Schneider:
25872: 00/09/24: Looking for Long Island Verilog or VHDL designers
25907: 00/09/26: Looking for ASIC,FPGA Designers
26195: 00/10/08: Long Island Verilog and VHDL people wanted!!
26288: 00/10/10: Re: Long Island Verilog and VHDL people wanted!!
26584: 00/10/21: Looking for ASIC,FPGA Designers
26746: 00/10/27: Long Island Verilog and VHDL people wanted!!
26779: 00/10/29: Re: Long Island Verilog and VHDL people wanted!!
26817: 00/10/31: Re: Long Island Verilog and VHDL people wanted!!
26819: 00/10/31: Re: Long Island Verilog and VHDL people wanted!!
27368: 00/11/20: Long Island Verilog and VHDL people wanted!!
27435: 00/11/22: Re: Long Island Verilog and VHDL people wanted!!
27838: 00/12/12: Verilog and VHDL people wanted!!
Barry T. Paterson:
6515: 97/05/30: Re: What is M1?
<barrytedstone@my-deja.com>:
25484: 00/09/12: IEC1131-3 PLC Programming Standard
25485: 00/09/12: IEC1131-3 PLC Programming Standard
Bart:
62046: 03/10/17: program a Lattice MACH211
93226: 05/12/15: Interfacing externally clocked data to an FPGA (Spartan 3)
93256: 05/12/16: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
bart:
83581: 05/05/03: Multiply Accumulate FPGA/DSP
83628: 05/05/04: Re: Multiply Accumulate FPGA/DSP
101548: 06/05/02: Re: bizzare unexplained random errors w/ Lattice 4256V CPLD
101690: 06/05/04: Re: New To FPGA, Program question
102009: 06/05/09: Re: FPGA-based hardware accelerator for PC
102100: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102101: 06/05/10: Re: 87C52 & 87C51 core
102182: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102485: 06/05/16: Re: getting good deals on small qty?
102767: 06/05/19: ispLEVER Starter 6.0 FPGA Design Software Available
103833: 06/06/12: Re: How to get lowest price for a ModelSim license?
103864: 06/06/13: ANNC: VHDL Coding for FPGA Webcast
104001: 06/06/16: Re: Time for a new "Largest FPGA with free tool support"?
104504: 06/06/28: ANNC: x8 PCI Express w/ FPGA Webcast
105294: 06/07/19: Re: Which PCI core for Cyclone II board?
105789: 06/07/31: Lattice Blogs
105791: 06/07/31: Re: Lattice Blogs
106113: 06/08/07: Re: Who is your favourite FPGA guru?
106172: 06/08/08: Re: Newbie question
106252: 06/08/09: Re: Who is your favourite FPGA guru?
106514: 06/08/14: Re: Lattice Blogs
106715: 06/08/17: Re: Why is Spartan-3 more expensive than Cyclone?
106719: 06/08/17: Re: Why is Spartan-3 more expensive than Cyclone?
108663: 06/09/14: ANNC: Verilog Coding for FPGA Webcast
108876: 06/09/18: Re: Lattice ECP2/M
108884: 06/09/18: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109072: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109664: 06/10/02: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
110492: 06/10/16: Re: FPGA comparision
110549: 06/10/17: ANNC: Open Source, Free 32-bit soft processor webcast
110618: 06/10/18: Re: ANNC: Open Source, Free 32-bit soft processor webcast
110619: 06/10/18: Re: ANNC: Open Source, Free 32-bit soft processor webcast
110869: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
110998: 06/10/26: Re: Survey on Quartus SOPC/Nios-II
111007: 06/10/26: Re: Xilinx Virtex4 Outputs for Camera Link
111040: 06/10/27: Re: Survey on Quartus SOPC/Nios-II
111245: 06/10/31: Re: FPGA's for Ethernet?
117289: 07/03/27: ANNC: Tips for FPGA Timing Closure Webcast
120527: 07/06/08: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120626: 07/06/12: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120644: 07/06/12: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
123398: 07/08/27: ANNC: FPGA Noise Fundamentals Webcast
131917: 08/05/07: ANNC: FPGA Design Software Webcast
Bart De Zwaef:
59163: 03/08/11: inconsistent DCM delay from TRCE report ?
71739: 04/07/29: XST vhdl adder with carry out : broken carry chain
71779: 04/07/30: Re: XST vhdl adder with carry out : broken carry chain
Bart Fox:
129455: 08/02/25: Re: Software Defined Radio on Xilinx Virtex 4
152239: 11/07/26: Re: Issues with Soft-Cores
152368: 11/08/12: Re: Xilinx Coregen, command not found java error
153054: 11/11/24: Re: Xilinx chipscope via Virtualbox
154333: 12/10/02: Re: Just gloating
154588: 12/11/30: Re: VHDL expert puzzle
154926: 13/02/16: Re: arm cortex M0 ds and legacy spartan 3E 3A 3ADSP starter kits
155161: 13/05/14: Re: Any experience of Equivalence Checking tools?
155803: 13/09/15: Re: FPGA temperature measurement
160518: 18/03/13: Re: How to handle a data packet while calculating CRC.
160524: 18/03/16: Re: How to handle a data packet while calculating CRC.
161385: 19/06/15: Re: bare-metal ZYNQ
bart plackle:
8796: 98/01/27: VHDL book
Bart van Deenen:
122873: 07/08/09: spartan3 picoblaze how to make .bmm file work
122874: 07/08/09: mem file
122885: 07/08/09: Re: spartan3 picoblaze how to make .bmm file work
122887: 07/08/09: got it!
123378: 07/08/26: [xilinx ise simulation] how to keep all settings between runs
123387: 07/08/27: Re: how to keep all settings between runs
<bart.deboeck@gmail.com>:
122172: 07/07/22: FPGA for HPC
<bart.hommels@gmail.com>:
128033: 08/01/14: Re: setup ETHERNET UDP link suing spartan-3E starter kit
Bartek:
149037: 10/09/23: Virtex5 MGT signals as standard diff ports
Barth?l?my von Haller:
62774: 03/11/07: xhwif for admxrc2 board (alpha data)
63753: 03/12/03: Problem using JBits 2.8 with (esl) RC1000-PP
Barton Quayle:
664: 95/01/31: Re: XC4000 boundary scan configuring. How??
<bartzenbeggar@gmail.com>:
111123: 06/10/29: Stratix to PC communication
<barukula.ramesh@gmail.com>:
116392: 07/03/08: CAN vhdl code document
Bas Arts:
47812: 02/10/04: Re: Low power design
47884: 02/10/07: Re: Low power design
Bas Evers:
2221: 95/11/04: US-NY-Syracuse Engineering positions
Bas Laarhoven:
125088: 07/10/16: Re: FPGA quiz: what can be wrong
128639: 08/02/01: Re: Why use small resistor for Vcco voltage regulator
136392: 08/11/14: Re: Why memory for this Nios II is still not enough
Bas Ruiter:
53466: 03/03/14: Re: AMD Temp Specs
basaro:
16269: 99/05/13: Can use pullup in XC9500XL?
BasePointer:
46277: 02/08/23: Help for Schematic Components
46287: 02/08/24: Re: Help for Schematic Components
46295: 02/08/24: Re: Help for Schematic Components
46298: 02/08/25: Can I directly connect XTAL to SpartanXL ?
46323: 02/08/26: Re: Can I directly connect XTAL to SpartanXL ?
46368: 02/08/27: Re: Can I directly connect XTAL to SpartanXL ?
46766: 02/09/07: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
bashir2000:
151718: 11/05/09: fpga
Baskaran Kasimani:
2268: 95/11/15: Re: AT&T vs. Xilinx
2269: 95/11/15: Re: AT&T vs. Xilinx
2368: 95/11/24: Re: Xilinx Viewlogic simulation
2414: 95/12/02: Re: Xilinx XACT Windows Version
2415: 95/12/02: Re: Xilinx XACT Windows Version
basri:
Bassam Al-Kharashi:
3814: 96/08/06: Pricing information - ACTEL
3815: 96/08/06: ACTEL Security Fuse
3813: 96/08/06: ACTEL Prices
Bassam Tabbara:
11974: 98/09/22: Re: Synthesis warning
14526: 99/02/03: Re: Espresso logic tool
Bassem:
27754: 00/12/06: FPGA starter kit
27911: 00/12/14: Re: FPGA starter kit
bassos:
75185: 04/10/28: spartan-3 development board
75918: 04/11/19: nucleus
89375: 05/09/13: edk service pack download
42Bastian Schick:
74738: 04/10/18: Re: ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74787: 04/10/19: Re: ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
135410: 08/10/01: Re: $99 XMOS Dev kit
Basuki Endah Priyanto:
52645: 03/02/18: Xilinx Filter
52735: 03/02/20: Synthesis Tools
52925: 03/02/26: Xilinx Back-annotation Problem
52960: 03/02/27: Extend PCI slot to outside PC
52973: 03/02/27: Re:Extend PCI slot to outside PC
53048: 03/03/02: Design Manager in ISE 5.x
53053: 03/03/02: FIR Filter from Xilinx
53063: 03/03/03: Re: FIR Filter from Xilinx
53415: 03/03/13: Re: VHDL & FPGA Design tools
54919: 03/04/22: Virtex2 and Logic Analyzer
54950: 03/04/23: Re: Virtex2 and Logic Analyzer
55649: 03/05/15: Re: Xilinx Coregen FFT64
56537: 03/06/09: Re: Xilinx FFT Core Problems
56582: 03/06/10: Re: Where can i buy virtex II ?
56710: 03/06/12: Re: A way to copy Modelsim waveforms into word documents
56788: 03/06/16: Xilinx Mapping Problem
56843: 03/06/17: None
56982: 03/06/20: Xilinx --> WARNING:DesignRules:372
57074: 03/06/23: Equivalent Gate Count ??
58456: 03/07/24: Active Probe
59330: 03/08/15: Free VHDL Simulator
62647: 03/11/04: Re: Searching for 802.11a/g implementations
63918: 03/12/09: Too many signals [Xilinx Foundation 4.1i]
63989: 03/12/11: Re: Too many signals [Xilinx Foundation 4.1i]
64966: 04/01/17: Block RAM
69649: 04/05/17: Xilinx Foundation [*.SCH -> *.VHD]
69650: 04/05/17: Re: FPGA vs Microprocessor: newbie question
69853: 04/05/22: FPGA Board with Flash Memory
#BASUKI ENDAH PRIYANTO#:
35767: 01/10/17: Xilinx 64 Point FFT Core Problem
36014: 01/10/26: Re: Recommend a book
36065: 01/10/28: Virtex 2 or E Evaluation Board
36546: 01/11/12: Clock Divider or Multiplier ???
36622: 01/11/14: Clock Skew
36702: 01/11/17: Xilinx and Multirate clock ??
37063: 01/11/30: Duty Cycle & Xilinx DLL
37252: 01/12/05: Multiple Drivers & illegal connection
37337: 01/12/07: RE: IP Updates and Modelsim
38558: 02/01/17: Re: Core Generator
38570: 02/01/18: RE: Signal processing using FPGAs
Bathala:
125786: 07/11/05: linking error using mb-g++
126273: 07/11/18: mb-g++ linker script problem 8.2i
127211: 07/12/14: using fstream to access File on Compact Flash Card
129029: 08/02/13: mb-g++ compilation error with EDK 8.2.02i
131217: 08/04/15: Inconsistent File Reading/writing in binary format using MicroBlaze
<batman2054@my-dejanews.com>:
15599: 99/04/02: How to implement Matched Filter in FPGA?
15615: 99/04/03: Re: How to implement Matched Filter in FPGA?
15625: 99/04/04: Re: How to implement Matched Filter in FPGA?
15626: 99/04/04: Re: How to implement Matched Filter in FPGA?
BaTT:
99693: 06/03/28: Re: Xilinx Coregen
baum:
156056: 13/11/15: Cyclone V hard memory controller
Baxter:
87507: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87508: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87843: 05/08/02: Porting Actel code
87867: 05/08/02: Re: Porting Actel code
87897: 05/08/03: Re: Porting Actel code
Baykov Vladimir:
964: 95/04/05: new group
bayowolf:
16612: 99/05/30: Re: YOURE NOT GOING TO BELIEVE THIS! 7449
16625: 99/05/31: Re: LOOK WHAT SOMEBODY PUT ON THEIR WEBSITE! 278
Bazaillion:
56863: 03/06/17: FPGA GPU (Spartan IIe 300K)
56864: 03/06/17: Re: FPGA GPU (Spartan IIe 300K)
56915: 03/06/18: Re: FPGA GPU (Spartan IIe 300K)
<bazaillion@yahoo.com>:
36247: 01/11/03: How dense are FPGA/CPLD's
<bazarnik@hotmail.com>:
105019: 06/07/12: Re: ISE8.1 on OpenSUSE 64bit => ISE8.2 works
107394: 06/08/27: Re: Arbiter design problem?
107477: 06/08/29: Re: Arbiter design problem?
<bazogec@hotmail.com>:
87582: 05/07/26: chipscope on opb bus
87768: 05/08/01: problem with Xilinx OPB to OPB bridge
bbdjsk:
45323: 02/07/19: Re: How's the FPGA design job market near you??
<bbenson@gmail.com>:
118839: 07/05/04: Re: Use of "blocks" in Quartus design
118841: 07/05/04: Have you used an Altera altufm_i2c canned megafunction successfully?
bbgangan:
128556: 08/01/30: Regarding Hyperterminal
BBKierst:
8652: 98/01/16: Digital Signal Processing Help
8697: 98/01/20: FPGA / Data Array help in Denver Colorado
<bblase@sdsu.edu>:
3802: 96/08/04: (no subject)
bbreynolds:
146005: 10/03/03: Re: using an FPGA to emulate a vintage computer
bbrown:
49502: 02/11/13: creating a fabric in an FPGA
BCD:
85001: 05/06/02: Re: some mistakes with EDK7.1i
<bcuzeau@gmail.com>:
131421: 08/04/21: Re: Problem writing quadrature decoder
BDipert:
5556: 97/02/24: Antifuse Comparisons?
7387: 97/09/05: FPGA-to-ASIC Conversion Advice Appreciated
<bdjmcw@sssdfdf.org>:
16628: 99/06/01: THOUGHT YOU MIGHT LIKE THIS... 7902
BDoherty:
49085: 02/10/31: Spartan-IIE Constraint Question
bdurr:
147832: 10/05/26: crc16 with 16 bit inputs
<be.geek@gmail.com>:
103435: 06/06/01: Building custom ASIC solutions
103440: 06/06/01: Re: Building custom ASIC solutions
103441: 06/06/01: Re: Building custom ASIC solutions
103466: 06/06/02: Adding a USB interface to Linksys WRT54G wifi router
<beagle197@hotmail.com>:
80538: 05/03/07: EDK service packs?
81732: 05/03/30: How to map FPGA pin outputs and use User Constraints File (UCF) ?
104901: 06/07/08: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
104903: 06/07/08: Re: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
113247: 06/12/08: How to develop custom opb devices for Microblaze?
113356: 06/12/11: Re: How to develop custom opb devices for Microblaze?
Beantown:
133113: 08/06/18: Mapping the DCM clock output onto a global buffer
133128: 08/06/18: Re: Mapping the DCM clock output onto a global buffer
133173: 08/06/19: Re: Mapping the DCM clock output onto a global buffer
133175: 08/06/19: Re: Mapping the DCM clock output onto a global buffer
<bear5@my-deja.com>:
22960: 00/06/06: [JOB] Engineering Director for FPGA/ASIC Design Company
Beau Schwabe:
4486: 96/11/05: Fastest way to get started??
31017: 01/05/09: Re: analog and digital?
<beau@lab-tools.co.uk>:
153753: 12/05/13: Re: Interfacing a circuit in an FPGA to a PC
beav:
38714: 02/01/22: Virtex-II Programming Highs and Lows
Bedrich:
68207: 04/03/30: Re: CLB usage: Xilinx XCS20 and Foundation 3.1
68208: 04/03/30: Re: Schematic Edition Tool : Suggestions
Bedrich Pola:
29725: 01/03/06: Re: SRAM fpga cell
beeraka@gmail.com:
80405: 05/03/04: Re: How to readback a BRAM
80406: 05/03/04: Regarding Linux on ML 310
80676: 05/03/09: Re: PLB IPIF + Master + DMA
80678: 05/03/09: ML310 + Linux (elf file ) + bit file
80740: 05/03/10: Re: ML310 + Linux (elf file ) + bit file
81127: 05/03/17: Re: ISE 7.1 WebPack + EDK 6.3
81336: 05/03/21: Need help regarding DMA ..
81846: 05/04/01: Re: IPIF user logic vs. Component insertion
81847: 05/04/01: OPB Master
82107: 05/04/06: Re: EDK-Creating new peripheral
82236: 05/04/08: Re: ML310 xirtex II pro development board: HOW TO WRITE onto the DDR DIMM?
83173: 05/04/25: Re: ml310: linux boot faillure
84400: 05/05/18: Re: Linux on Xilinx ml310
85686: 05/06/13: Re: xilinx ml310 : to run applications on 2 nd ppc
86518: 05/06/29: Re: Linux 2.6 on the Xilinx ML310 board
87674: 05/07/27: How to import a netlist in VHDL
89286: 05/09/10: Re: creating a custom opb bus master
90980: 05/10/26: Re: Anyone have experience with Linux in V2Pro?
91327: 05/11/03: Re: ChipScope on ML401 kit
91387: 05/11/04: Re: use ppc405 on virtex-II pro
91589: 05/11/09: Re: pci ml310 board
92127: 05/11/22: Aurora over Rocket IO and EDk
92290: 05/11/25: Re: simulating code loading in memory and jumping to memory
92291: 05/11/25: Re: simulating code loading in memory and jumping to memory
94426: 06/01/11: Re: application running on the top of Linux on virtex-ii pro
96996: 06/02/14: Re: Rocketio, modelsim xe
97448: 06/02/22: Re: Cannot use ML310 DDR
98513: 06/03/11: Re: synthesis time with XST
99800: 06/03/29: Re: Linux on ml403
103201: 06/05/28: Re: Peripheral connected to multiple OPB buses
113483: 06/12/14: Re: Maplib Error 661.
121480: 07/07/05: Re: Rocketio connection Virtex2pro-Virtex4
123109: 07/08/16: Re: about mb-gcc error???
124704: 07/10/01: Re: Error in simple code, plz help
124854: 07/10/08: Re: JTAG interconnect testing, prototypes
124946: 07/10/11: Re: FPGA tools under VMware or Parallels on a Mac?
124947: 07/10/11: Re: Xiinx ERROR:PhysDesignRules:10
126117: 07/11/14: Re: synopsys translate_off
126169: 07/11/15: Re: synopsys translate_off
129158: 08/02/15: Re: Virtex5 DCM lower limit
132661: 08/06/04: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
132744: 08/06/05: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
133483: 08/07/01: Re: lwip for FPGA
136281: 08/11/09: Re: Data transfer between CPU and FPGA over PCI bus
<beerbaron@my-deja.com>:
24798: 00/08/18: Fully contrained designs...
24929: 00/08/22: Re: Fully constrained designs...
Beeson Wong:
59004: 03/08/06: Questions in Altera FPGA MegaCore Compact-PCI Configuration Space under Windows NT
beginner:
156120: 13/11/29: Verilog! How to work with modules?
Behrang:
37789: 01/12/20: Array Divider
beky4kr@gmail.com:
131975: 08/05/09: AHB and APB master VHDL generator
131976: 08/05/09: SDIO CRC7 + VCD waves
132021: 08/05/10: Conversion from VERILOG READMEMB to INTEL HEX
132024: 08/05/10: USB full speed final project proposal
132384: 08/05/24: CRC7 Input bits in Command and Response
133913: 08/07/18: Re: The littlest CPU
134260: 08/08/01: Re: Is there a totally command-line driven way to use Xilinx Webpack?
134477: 08/08/12: Re: SDIO open source code
135458: 08/10/02: WEBPACK for linux
135718: 08/10/13: Re: Looking for a soft core 32 bit processor in VHDL
136547: 08/11/21: Re: Student FPGAs
136795: 08/12/05: Re: Equivalent ASIC Gate Estimate
<belanger002@wcsub.ctstateu.edu>:
292: 94/10/13: Re: PALASM versions?
378: 94/11/02: Re: about ALTERA
680: 95/02/05: Re: Question on 22v10 fitting in Warp2
699: 95/02/09: Re: Low cost Boundary Scan?
700: 95/02/09: Re: Low cost Boundary Scan?
<belchel01@gmail.com>:
155890: 13/10/11: Re: MicroBlaze MCS Error.
bellatoise:
145197: 10/02/01: Single Port Rom created by Core Generator configurable by generic values!!!!
145204: 10/02/01: Re: Single Port Rom created by Core Generator configurable by generic values!!!!
Ben:
18317: 99/10/14: compiling vhdl code(help please)
22161: 00/04/28: A Question on Virtex Configuration
22164: 00/04/28: Re: A Question on Virtex Configuration
22174: 00/04/28: Re: A Question on Virtex Configuration
22764: 00/05/23: A Question on XILINX Configuration PROM
23579: 00/07/01: Powering XCV300
31079: 01/05/11: [Q]CardBus PC Card with PCI device
31594: 01/05/31: [Q]setup-time violation
31667: 01/06/02: Re: [Q]setup-time violation
31672: 01/06/02: pci pads
32361: 01/06/25: [Q]ATPG - using bidir as scan in
35458: 01/10/05: Video processing
35657: 01/10/12: Re: Reassemble a BGA560 device
35808: 01/10/18: Firewire chipset
35820: 01/10/18: Re: Firewire chipset
35826: 01/10/19: Re: Firewire chipset
110519: 06/10/17: Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
110534: 06/10/17: Re: Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
110571: 06/10/18: Re: Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
125223: 07/10/18: What to consider for source synchronous clocking?
141804: 09/07/10: Re: About configuring FPGAs
141837: 09/07/11: Re: About configuring FPGAs
142173: 09/07/28: Daisychaining fpga with SPI flash?
142177: 09/07/28: Re: Daisychaining fpga with SPI flash?
142178: 09/07/28: Re: Daisychaining fpga with SPI flash?
142180: 09/07/28: Re: Daisychaining fpga with SPI flash?
ben:
3831: 96/08/07: Xilinx clock doubler?
Ben Bradley:
64388: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64398: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
85902: 05/06/17: Re: Idea exploration 1.1 - Inertia based angular sensor.
87412: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
132217: 08/05/18: Re: ANNC: FPGA Design Software Webcast
Ben Chaffin:
5056: 97/01/17: Advice request
5057: 97/01/17: advice request
ben cohen:
44899: 02/07/04: Lessons Learned -- Need your inputs
45353: 02/07/19: spiral / waterfall /watersluice : Which are your methods?
45365: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
45442: 02/07/23: Re: spiral / waterfall /watersluice : Which are your methods?
45898: 02/08/09: RMM 3rd Edition // Comments and recommendation
48665: 02/10/22: New brochure: KAP books on SOC and Design Reuse
49073: 02/10/31: Coding HDL for Reviewability // Link to paper + 2003 MAPLD Conf
51094: 02/12/31: Re: what is bus keeper / bus gate.
55081: 03/04/25: Re: need help converting Verilog to VHDL
55775: 03/05/19: New book on PSL/SUGAR with Verilog and VHDL
56469: 03/06/05: Assertion-based verification
57023: 03/06/20: Re: Bidirectional bus (tristate issue) // with ABV comments
Ben D:
136887: 08/12/10: mapping to custom architecture
136906: 08/12/11: Re: mapping to custom architecture
Ben Franchuk:
20560: 00/02/14: Re: Public Domain Micro Processor Project
20651: 00/02/16: Re: Choosing the correct size FPGA
21226: 00/03/11: Re: Extremely fault tolerant strategies
21436: 00/03/22: No- FPGA openness
21446: 00/03/22: Re: FPGA openness
21456: 00/03/22: Re: No- FPGA openness
21485: 00/03/23: Re: FPGA openness
21496: 00/03/23: FPGA - CPU's
21511: 00/03/23: Re: FPGA openness
21541: 00/03/24: Gate logic
21546: 00/03/24: Re: FPGA openness
21620: 00/03/26: FPGA open source
21640: 00/03/27: Re: FPGA & single point failure
21658: 00/03/27: Re: FPGA & single point failure
24470: 00/08/10: Re: 17 clocks in a Virtex
24309: 00/08/03: Re: Who needs all those printed ac parameters?
24445: 00/08/09: Re: Who needs all those printed ac parameters?
24446: 00/08/09: Re: Advantages and desadvantages of a reconfigurable processor
24501: 00/08/11: Re: Interview Questions
24507: 00/08/11: Yes but I want graphics.
24566: 00/08/14: Re: this is a reply test
24703: 00/08/17: Re: Permanently programming FPGAs
24751: 00/08/17: Re: Permanently programming FPGAs
24811: 00/08/19: Re: Further FPGA metastability questions
24831: 00/08/20: Re: Further FPGA metastability questions
24835: 00/08/20: Arg! 8051 - 6502 and friends
24848: 00/08/20: Re: Arg! 8051 - 6502 and friends
24865: 00/08/21: Re: Arg! 8051 - 6502 and friends
24921: 00/08/22: Re: Fully constrained designs...
24946: 00/08/23: Re: Some notes on metastability
25059: 00/08/25: Re: largest fpga in the industry
25068: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other
25207: 00/08/30: Re: Latches
25215: 00/08/31: Re: Balls!
25393: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25561: 00/09/14: Re: Guide to useing Atmel FPGA (at40k)
25562: 00/09/14: Re: hardware compatibility and patent infringement
25571: 00/09/14: Re: Simon , decoupling caps
25573: 00/09/14: Re: MAX PLUS 2
25581: 00/09/14: Re: Adders in FPGA?
25999: 00/09/29: Look MOM ... No Hardware
26002: 00/09/30: Re: Xilinx Student Edition 2.1i first impressions
27300: 00/11/17: Re: Can FPGA perform float point calculation?
27314: 00/11/17: Re: In the news
27343: 00/11/18: Re: What is the fundamental limitation factor for FPGA clock rate
27513: 00/11/27: Re: Gates in a typical small MPU
28032: 00/12/19: Re: FPGA and Board for Microprocessor Design?
28105: 00/12/21: Re: Help with encoder/decoder
28159: 00/12/23: evolving bitstreams
28813: 01/01/24: Re: Encryption is supported in new Virtex II but.....
28898: 01/01/28: Re: Xilinx fast carry counter question
31349: 01/05/20: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31350: 01/05/20: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31354: 01/05/20: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31544: 01/05/29: Re: Exact URL for ordering Webpack ISE CDROM?
31546: 01/05/29: Re: Exact URL for ordering Webpack ISE CDROM?
31808: 01/06/06: Re: one state machine
31820: 01/06/06: Re: Help in FIFO design
31821: 01/06/06: Re: Help in FIFO design
31831: 01/06/06: Re: Help in FIFO design
31945: 01/06/08: Re: Pin locking in Maxplus2
31947: 01/06/08: Re: one state machine
32560: 01/06/29: Re: Newbee and FAQ
33122: 01/07/17: Re: Newbie Question
32686: 01/07/04: Glitch hunting.
32814: 01/07/09: Re: What chip!?
32912: 01/07/11: Re: FPGA-based board vs bigger FPGA
32975: 01/07/13: Re: Design entry
33020: 01/07/15: Re: Design entry
33073: 01/07/17: Re: processor core
33125: 01/07/17: Re: Working Design - Anyone
33193: 01/07/18: Re: Working Design - Anyone
33308: 01/07/23: Re: Flex 10K10 prototyping system
33485: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33763: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
33781: 01/08/04: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
33885: 01/08/07: Re: Reconfigurable Computational Accelerator
34166: 01/08/15: Re: Building a clock out of a PLD
34360: 01/08/22: Re: Principles of Verifiable RTL Design (2nd ed)
34384: 01/08/22: Re: Logic Emulation
34412: 01/08/23: Re: Principles of Verifiable RTL Design (2nd ed)
34414: 01/08/23: Re: Principles of Verifiable RTL Design (2nd ed)
34458: 01/08/25: Re: Slowing PCI for FPGA
34565: 01/08/29: Re: Logic Emulation
34577: 01/08/29: Re: star-wars ascii-animation:)
34643: 01/08/31: Re: Defending Austin Franklin
34667: 01/09/02: Re: WebPack Con-Game
34681: 01/09/03: Re: DSP in OTP
34819: 01/09/10: Re: Open collector outputs
35732: 01/10/15: Re: System Gates
36092: 01/10/29: OT - prototyping in Canada
36113: 01/10/30: Re: How can I design a bi-deriction bus buffer?
Ben G:
73756: 04/09/29: Re: MicroBlaze & SRAM
73646: 04/09/27: MicroBlaze & SRAM
73684: 04/09/28: Re: MicroBlaze & SRAM
91324: 05/11/03: Re: clock detection
91361: 05/11/04: Re: clock detection
Ben Gelb:
145484: 10/02/11: Synplify out of memory
145503: 10/02/12: Re: Synplify out of memory
Ben Gerblich:
59888: 03/08/31: using CLKDLL, want: myclock <= CLKDV and LOCKED
62098: 03/10/19: ignoring SPO output on dual port ram
Ben Howe:
45652: 02/07/30: Pipelined Multiplier Implemented in Slices in Virtex II
45700: 02/08/01: Re: Pipelined Multiplier Implemented in Slices in Virtex II
65901: 04/02/09: Re: FIR filter coefficient (with COE file)
68294: 04/03/31: Re: Multiple DCM ? (Virtex II)
68322: 04/04/01: Re: Multiple DCM ? (Virtex II)
Ben Jackson:
54451: 03/04/11: Re: Using DP RAM for message passing
54481: 03/04/11: Re: Using DP RAM for message passing
54988: 03/04/23: Re: Challenge: (n mod 3) in hardware???
55041: 03/04/25: Re: Low pin count SOC
55279: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
55329: 03/05/04: cable length on homemade Parallel Cable III
55471: 03/05/09: variable clock source for CPLD, PIC
55599: 03/05/13: Re: XC9536 - how to make my own programing device for this chip ?
55694: 03/05/16: Re: smallest embedded cpu.
55734: 03/05/18: Re: Xilinx Project Navigator in ISE 5.2i
55753: 03/05/18: Re: Altera CPLDs
55955: 03/05/25: Why is there a large gulf between CPLD and FPGA?
55962: 03/05/25: Re: Why is there a large gulf between CPLD and FPGA?
55963: 03/05/25: Re: Why is there a large gulf between CPLD and FPGA?
55968: 03/05/25: Re: Newbie CPLD question
56001: 03/05/26: Re: Newbie CPLD question
56041: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
56352: 03/06/03: Re: Xilinx Spartan download with Parallel III cable
56659: 03/06/11: Re: Xilinx CPLD programming with microcontroller
56853: 03/06/17: Re: An All Digital Phase Lock Loop
58083: 03/07/14: Re: programming a PLD/CPLD with a PIC?
58105: 03/07/15: Re: programming a PLD/CPLD with a PIC?
58106: 03/07/15: Re: JTAG standard connector
73791: 04/09/29: Re: FPGAs as a PCI (target) controller
73288: 04/09/17: Re: FPGA with PCI interface for video processing?
73317: 04/09/19: doing 'slow' calculations in verilog
73383: 04/09/21: Re: Ring Oscillator Redux
73667: 04/09/27: Re: Simple Counter in Verilog
75245: 04/10/31: Re: Board-level clock phase delay calculation in the fpga board?
74180: 04/10/05: Re: Hash algorithm for hardware?
74650: 04/10/15: Re: which xilinx CPLD to select?
74659: 04/10/15: Re: which xilinx CPLD to select?
74729: 04/10/18: Re: a pci implemenation problem, thanks
74763: 04/10/18: Re: Xilinx Virtex II MAC & PHY. ( HELP)
76134: 04/11/25: Re: PCI interrupt negation
76480: 04/12/03: Re: Pci problems
76488: 04/12/04: Re: Pci problems
76868: 04/12/15: Re: algorithm: square operation
76997: 04/12/19: Re: PCB construction for PCI
99414: 06/03/23: Re: PCI Configuration access and Target State Machine...
99520: 06/03/25: Re: PCI Configuration access and Target State Machine...
99667: 06/03/27: Re: deglitching a clock
99748: 06/03/28: iverilog error messages (was: Altera web site inaccessible)
100339: 06/04/06: Re: gameboy camera to FPGA
100341: 06/04/06: Re: gameboy camera to FPGA
102889: 06/05/22: Re: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
103305: 06/05/30: Re: generating IP cores
103306: 06/05/30: Re: Mains pick-up on I/O pins
104238: 06/06/21: Re: cache aware programming
104552: 06/06/29: Re: NCO Clock driven Designs in FPGA
104916: 06/07/09: Re: Is while loop synthesizable if the number of iterations is known
105490: 06/07/24: Re: ByteBlasterMV?
105699: 06/07/28: Re: "This design element is inferred rather than instantiated" (newbie)
105729: 06/07/30: Re: "This design element is inferred rather than instantiated" (newbie)
105904: 06/08/02: Re: generating sine-like waveforms
106581: 06/08/15: Re: Large Spartan3 vs. Small V5
107101: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107934: 06/09/02: Re: I do not know this !
108243: 06/09/06: Re: FPGA multiplier
108396: 06/09/10: Re: Trying to get plb_temac working
108408: 06/09/10: Re: Trying to get plb_temac working
108471: 06/09/11: Re: xilinx bram instantation template in vhdl?
110620: 06/10/18: Re: Executing PPC code from external flash memory
111890: 06/11/12: Re: SPI module in FPGA
113270: 06/12/09: Re: How to develop custom opb devices for Microblaze?
113271: 06/12/09: Re: impossible opb_emc hack?
113305: 06/12/11: Re: @(posedge clk)
113352: 06/12/11: Re: DDR2 DIMM memory termination resistors?
113405: 06/12/13: Re: Problem with connecting higher order address lines of SDRAM to FPGA
113562: 06/12/16: Re: uClinux bootloader on Spartan-3e Starter Kit
113634: 06/12/18: Re: FX12 ethernet resource usage
113749: 06/12/20: Re: Spartan 3E Starter Kit Woes
113906: 06/12/28: Re: SPI slave problem
113974: 06/12/31: Re: xilinx xc9536?
113982: 07/01/01: Re: PPC PLB <=> FPGA fabric
113987: 07/01/02: Re: xilinx xc9536?
114046: 07/01/03: Re: PPC cache errata
114381: 07/01/13: Re: Will FPGAs suit my need?
114403: 07/01/15: Re: Gigabit Ethernet UDP/IP
114620: 07/01/21: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114632: 07/01/21: Re: digilent nexys vga glitches
114755: 07/01/23: Re: FPGA damage from bad bitstream
114757: 07/01/23: Re: R: iMPACT dont shows erase write options with fpga
114769: 07/01/24: Re: R: iMPACT dont shows erase write options with fpga
114824: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
114826: 07/01/24: Re: FPGA clock gating ? Or how to avoid it in this case ?
114899: 07/01/25: Re: Porting MontaVista Linux on ML403
114959: 07/01/27: Re: Minimal design for xilinx?
114993: 07/01/28: Re: Minimal design for xilinx?
115043: 07/01/29: Re: Global Clocks in Xilinx ISE
115146: 07/01/31: Re: cpld version?
115373: 07/02/08: Re: Interrupts and PPC/opb_intc
115505: 07/02/12: Re: Picobalze in the FPGA
116217: 07/03/05: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116492: 07/03/10: Re: Addressing scheme in Block RAM
116802: 07/03/19: Re: FPGA vs. GPP anyone?
116954: 07/03/21: Re: Zero-Valued Data Out of Chipscope ILA?
120214: 07/06/03: Altera Serial Flash Loader (SFL) question
120226: 07/06/03: Re: Altera Serial Flash Loader (SFL) question
120372: 07/06/06: Re: XILINX IPCore
120735: 07/06/15: Re: booting a large V4 PPC program with a minimum of on chip bram
121151: 07/06/26: Re: Desperate to find the right FPGA board
121202: 07/06/28: Re: Bit error counter - how to make it faster
121204: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121236: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121341: 07/07/02: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121342: 07/07/02: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121721: 07/07/12: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121722: 07/07/12: Re: Flex 10k100 & EPC2 redux - forgot the special ingredient?
121852: 07/07/13: Re: Newbie's first FPGA board !
121893: 07/07/14: Re: Newbie's first FPGA board !
121907: 07/07/15: Re: Newbie's first FPGA board !
121972: 07/07/16: Re: Newbie's first FPGA board !
121982: 07/07/16: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122036: 07/07/17: Re: Newbie's first FPGA board !
122038: 07/07/17: Re: chipscope PLB IBA - how to get meaningful labels on signals?
122120: 07/07/19: Re: Xilinx XST 9.2i.01 - still incomplete support for always @*
122359: 07/07/26: Re: pci express pinout
122489: 07/07/28: Re: dual port ram
122505: 07/07/29: Re: dual port ram
123485: 07/08/28: Re: PCB Layers
123782: 07/09/04: Re: Spartan3E and DDR termination
124109: 07/09/12: Re: PCI byte enalbes in read cycles
124110: 07/09/12: Re: Quick question for an Altera wizard
124154: 07/09/12: Re: PCI byte enalbes in read cycles
124155: 07/09/12: Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?
125319: 07/10/20: Re: FPGA input level conversion
126165: 07/11/15: Re: V4FX: Cannot access EMAC1 of Dual MAC system
126188: 07/11/16: Re: V4FX: Cannot access EMAC1 of Dual MAC system
126502: 07/11/25: Re: PCI Mezzanine Card with Xilinx Virtex-II
126503: 07/11/25: Re: Xilinx Dual processor design
126506: 07/11/25: Hook open drain "power good" to nSTATUS or nCONFIG?
126529: 07/11/26: Re: Converting a ByteBlasterMV into a ByteBlaster II?
126552: 07/11/27: Re: yet another Altera Cyclone II EP2C35 dev. board
126797: 07/12/02: Re: Using SRAM Memory CY7C1386C
127338: 07/12/18: Re: Xilinx MAC experience ?
127407: 07/12/20: Re: Routing Vccint on four-layer PCB
127408: 07/12/20: Re: Xilinx Spartan 3 JTAG issues
127662: 08/01/04: Re: Ethernet on recent FPGAs
127663: 08/01/04: Re: WebPack on GNU/Linux
127794: 08/01/08: Re: Bad micro blaze behaviour during power off
127795: 08/01/08: Re: passive serial quaestion
127796: 08/01/08: Re: Processor in CPLD
127881: 08/01/09: Re: Identification of FPGA Development Board
127882: 08/01/09: Re: Using DDR SDRAM as single data rate ..?
127897: 08/01/09: Re: Using DDR SDRAM as single data rate ..?
127952: 08/01/11: Re: Place-and-Route : Intel vs AMD
127953: 08/01/11: Re: Power up Behavior of Virtex5 IOs
128019: 08/01/13: Re: Virtex4 burn-in failure
128029: 08/01/14: Re: Read/Write SRAM on Spartan3 Starter kit
128117: 08/01/15: Re: speed... CORDIC vs. pure arithmetic expression
128187: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128194: 08/01/17: Speed of remote JTAG with Quartus jtagd on linux
128198: 08/01/17: Re: Two's complement Coregen gone?
128248: 08/01/18: Re: SRL16x2 in Virtex5
128301: 08/01/20: Re: Sparkfun Spartean3e Board
128488: 08/01/28: Re: My first Flash FPGA
129005: 08/02/12: Re: Does PC-FPGA communication requires a driver?
129185: 08/02/17: Re: Ballpark PLB frequency
129186: 08/02/17: Re: Over utilization of FPGA resources
129261: 08/02/19: Re: V4FX100 PowerPC PLB issues (and EDK 9.2)
133284: 08/06/23: Re: FPGA based database searching
133514: 08/07/02: Re: How do I program an fpga once it has been designed and layout is complete
134428: 08/08/10: Re: Spartan 3e, LVDS LCD.
134459: 08/08/11: Optimizing a LUT-based pow(val, 2.2)
134480: 08/08/12: Re: Using a Spartan 3 FPGA kit with a USB/DB9
134516: 08/08/15: Re: Q: Demo Altera NIOS II SOPC limitations
134518: 08/08/15: Re: video timing with TFP410
134880: 08/09/04: Re: Strange Spartan2 behaviour
135537: 08/10/06: Re: Xilinx PCIE problem
136434: 08/11/16: Re: Digilent Spartan3e starter kit, Not working.
137827: 09/01/30: Re: byteblaster cloning
138485: 09/02/24: Re: Opencores DDR controller
139930: 09/04/20: Re: Why is XST optimizing away my registers and how do I stop it?
142451: 09/08/11: Re: DDR2 Controllers: Bursting to Odd Addresses
142576: 09/08/17: Re: Soft Processor IP core report
Ben Jones:
83682: 05/05/05: Re: Xilinx FPU for Virtex-4 over FPU
84468: 05/05/19: Re: why is it wrong with "sin"?
84523: 05/05/20: Re: FFT with FPGA
84942: 05/06/01: Re: How to speed up float computing
85155: 05/06/06: Re: 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
85244: 05/06/07: Re: Signed/unsigned divider
85493: 05/06/10: Re: Gated clock question
85505: 05/06/10: Re: Building a MicroBlaze from scratch, unable to run.
85694: 05/06/14: Re: Gated clock question
85708: 05/06/14: Re: Auto pipeline logic??
85742: 05/06/15: Re: Auto pipeline logic??
85789: 05/06/16: Re: Auto pipeline logic??
85854: 05/06/17: Re: Automagic Circuit Pipelining (was: Re: Auto pipeline logic?? )
85881: 05/06/17: Re: IPIF LogiCore?
86057: 05/06/21: Re: Microblaze address space and variables
86120: 05/06/22: Re: FPGAs: Where will they go?
86127: 05/06/22: Re: FPGAs: Where will they go?
86130: 05/06/22: Re: FPGAs: Where will they go?
86155: 05/06/22: Re: Microblaze address space and variables
86524: 05/06/29: Re: Good FPGA for an encryptor
86629: 05/07/01: Re: Clock buffering in VirtexE FPGA
86688: 05/07/04: Re: Clock buffering in VirtexE FPGA
86822: 05/07/07: Re: Problems with Timing Simulation
86838: 05/07/07: Re: Problems with Timing Simulation
86840: 05/07/07: Re: Problems with Timing Simulation
88961: 05/09/01: Re: "Perform Timing-Driven Packing and Placement" error?
89224: 05/09/08: Re: ML361 Documentation....
89397: 05/09/14: Re: XilinX MAC FIR
90129: 05/10/05: Re: EasyPath, demystified
90134: 05/10/05: Re: Floating point multiplication on Spartan3 device
93248: 05/12/16: Re: Xilinx floating point core 1.0
97425: 06/02/22: Re: FPGA - software or hardware -2-
97511: 06/02/23: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97975: 06/03/02: Re: Help wanted
98391: 06/03/09: Re: XST synthesis gripe/sub-optimization
98393: 06/03/09: Re: EDK remote TCP debug
98403: 06/03/09: Re: for all those who believe in ASICs....
99332: 06/03/23: Re: Xilinx Square Root Unit
99334: 06/03/23: Re: Difference between Xilinx shift_extract and shreg_extract constraints?
99339: 06/03/23: Re: Xilinx Square Root Unit
99586: 06/03/27: Re: ERROR:NgdBuild:604
100202: 06/04/05: Re: Xilinx java application freeze
100211: 06/04/05: Re: Xilinx java application freeze
100286: 06/04/06: Re: Inferring SRL in Xilinx FPGA
100373: 06/04/07: Re: Inferring SRL in Xilinx FPGA
100469: 06/04/10: Re: 8:1 MUX implementaion in XILINX and ALTERA
100942: 06/04/21: Re: Video circle generator
100945: 06/04/21: Re: Xilinx Map & Physical Synthesis dies...
101092: 06/04/25: Re: Xilinx Virtex-4 OCM Usage Issues
101094: 06/04/25: Re: XST Internal error: VHDL constant record support
101127: 06/04/26: Re: XST Internal error: VHDL constant record support
101195: 06/04/27: Re: Xilinx Virtex-4 OCM Usage Issues
101207: 06/04/27: Re: How are constants stored ?
101218: 06/04/27: Re: CLock Issue
101256: 06/04/28: Re: Xilinx Virtex-4 OCM Usage Issues
101263: 06/04/28: Re: Xilinx Virtex-4 OCM Usage Issues
102523: 06/05/17: Re: "disappointing" 550Mhz performance of V5 DSP slices
102695: 06/05/19: Re: V5 and carry lookahead
102732: 06/05/19: Re: V5 and carry lookahead
102912: 06/05/23: Re: OPB Timer MicroBlaze
102981: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
102994: 06/05/24: Re: Independent clock FIFOs
103079: 06/05/25: Remote Application delivery for EDA
103088: 06/05/25: Re: Remote Application delivery for EDA
103219: 06/05/29: Re: Superscalar Out-of-Order Processor on an FPGA
103329: 06/05/31: Re: PLB transfers: PPC to IP
103409: 06/06/01: Re: Using ChipScope with EDK flow?
103565: 06/06/06: Re: ISE Timing Analysis Misreporting? Bug?
103586: 06/06/06: Re: ppc instruction count
103587: 06/06/06: Re: ISE Timing Analysis Misreporting? Bug?
104170: 06/06/20: Re: Xilinx ISE 8.1i Trouble
104201: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104373: 06/06/26: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
104381: 06/06/26: Re: still having same error
104525: 06/06/29: Re: Generic synthesis target in Synplify Pro
104650: 06/07/03: Re: Chaos in FF metastability
104687: 06/07/04: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104737: 06/07/05: Re: PPC and Chipscope?
105189: 06/07/17: Re: 2048 input or gate ?
105214: 06/07/18: Re: 2048 input or gate ?
105223: 06/07/18: Re: 2048 input or gate ?
105224: 06/07/18: Re: 2048 input or gate ?
105877: 06/08/02: Re: FPGA LABVIEW programming
106052: 06/08/07: Re: verilog versus vhdl
106126: 06/08/08: Re: verilog versus vhdl
106141: 06/08/08: Re: verilog versus vhdl
106142: 06/08/08: Re: verilog versus vhdl
109686: 06/10/03: Re: FPGA power-up and code relocation (basics)
109720: 06/10/04: Re: FPGA power-up and code relocation (basics)
109788: 06/10/05: Re: FPGA power-up and code relocation (basics)
109843: 06/10/06: Re: An implementation of a clean reset signal
109866: 06/10/06: Re: An implementation of a clean reset signal
110572: 06/10/18: Re: 64 bit division compensate NCO
110653: 06/10/19: Re: How to avoid negative slack.
110705: 06/10/20: Re: 64 bit division compensate NCO
111218: 06/10/31: Re: FPGA's for Ethernet?
111221: 06/10/31: Re: Dual Port RAM
111229: 06/10/31: Re: Dual Port RAM
111232: 06/10/31: Re: A spectre is haunting this newsgroup, the spectre of metastability
111297: 06/11/01: Re: A spectre is haunting this newsgroup, the spectre of metastability
111300: 06/11/01: Interface standards (was Re: Dual Port RAM)
111385: 06/11/02: Re: DSP48 carry logic for multi-precision addition
111392: 06/11/02: Re: A spectre is haunting this newsgroup, the spectre of metastability
111447: 06/11/03: Re: Scientific Computing on FPGA
111474: 06/11/03: Re: DSP48 carry logic for multi-precision addition
111519: 06/11/04: Re: OT Re: Scientific Computing on FPGA
111581: 06/11/06: Re: Interface standards (was Re: Dual Port RAM)
111584: 06/11/06: Re: DSP48 carry logic for multi-precision addition
111652: 06/11/07: Re: Microblaze FPU and IEEE754 single precision number format
111801: 06/11/10: Re: Why 64-bit PLB?
112047: 06/11/15: Re: DSP48 carry logic for multi-precision addition
112983: 06/12/04: Re: Double buffering
113162: 06/12/07: Re: regarding -ve slack while doing post PAR timing analysis
113429: 06/12/13: Re: FPGA : Async FIFO, Programmable full
114097: 07/01/04: Re: OT. Re: Surface mount ic's
114311: 07/01/11: Re: Interlock and stall in CPU design?
114442: 07/01/16: Re: Two newbie Chipscope questions
114578: 07/01/19: Re: Beginner VHDL questions
114801: 07/01/24: Re: system generator from Xilinx
114813: 07/01/24: Re: system generator from Xilinx
114911: 07/01/26: Re: Xilinx ISE 8.2
115359: 07/02/08: Re: question abt DPRAM
115552: 07/02/13: Re: Typical clock frequencies of FPGA designs
115856: 07/02/22: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
117181: 07/03/26: Re: Where is Open Source for FPGA development?
117308: 07/03/28: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117401: 07/03/30: Re: RISC implementation questions
117526: 07/04/03: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
117569: 07/04/04: Re: high number of multipliers / low cost
117583: 07/04/04: Re: TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
117586: 07/04/04: Re: high number of multipliers / low cost
117591: 07/04/04: Re: high number of multipliers / low cost
117827: 07/04/11: Re: Please HELP: timing problems on Virtex-4FX
117872: 07/04/12: Re: Please HELP: timing problems on Virtex-4FX
117880: 07/04/12: Re: Which are the best books about CORDIC algorithms and applications
117909: 07/04/13: Re: Please HELP: timing problems on Virtex-4FX
118000: 07/04/16: Re: PLB Master
118013: 07/04/16: Re: PLB Master
118067: 07/04/17: Re: plb_tft_cntlr_ref for an ML405 EDK Project
118087: 07/04/17: Re: plb_tft_cntlr_ref for an ML405 EDK Project
118099: 07/04/17: Re: plb_tft_cntlr_ref for an ML405 EDK Project
118101: 07/04/17: Re: 80000 Bit Shift Register - The Code
118381: 07/04/25: Re: Increase Memory Resource in SDRAM.
118427: 07/04/26: Re: Is microblaze able to change heap_size?
118470: 07/04/27: Re: Is microblaze able to change heap_size?
118615: 07/05/01: Re: Is microblaze able to change heap_size?
118755: 07/05/03: Re: PLB master with burst mode
118770: 07/05/03: Re: PLB master with burst mode
118775: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118776: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118785: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118787: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118820: 07/05/04: Re: Wait-for / until won't work ? Xilinx Spartan 3
118822: 07/05/04: Re: Prunnning Register missunderstood!!
118997: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119015: 07/05/09: Re: Open Source (was: Xilinx software quality - how low can it go ?!)
119082: 07/05/11: Re: Xilinx software quality - how low can it go ?!
119095: 07/05/11: Re: Xilinx software quality - how low can it go ?!
119349: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119354: 07/05/17: Re: Unusual question about generic port use (optional ports??)
119735: 07/05/25: Re: VGA signal through breadboard?
119747: 07/05/25: Re: VGA signal through breadboard?
120392: 07/06/06: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120450: 07/06/07: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120510: 07/06/08: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
120921: 07/06/20: Re: Linux 2.6.20 on MicroBlaze now available
130886: 08/04/04: Re: synplify pro generates negative slack
143453: 09/10/12: Re: floating point operation in interrupt handler on ML403
143609: 09/10/18: Re: What is the basis on flip-flop replaced by a latch
143704: 09/10/22: Re: Time stability of clock on FPGA board
143742: 09/10/23: Re: Time stability of clock on FPGA board
143788: 09/10/26: Re: feof, fseek, ftell on XilFATFS
143859: 09/10/30: Re: Best way to model a large external ROM in a simulation? (XST
143884: 09/11/01: Re: Best way to model a large external ROM in a simulation? (XST
143930: 09/11/03: Re: Best way to model a large external ROM in a simulation? (XST
143994: 09/11/06: Re: Does anyone ever use placement?
144028: 09/11/08: Re: Sinewave generation
144131: 09/11/12: Re: what is ngc file
144354: 09/11/30: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
144363: 09/12/01: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
144491: 09/12/10: Re: Please Help me
144498: 09/12/11: Re: Please Help me
144543: 09/12/14: Re: Please Help me
144555: 09/12/14: Re: Power dynamic managment in FPGA design
144581: 09/12/16: Re: Please Help me
Ben Klass:
2565: 96/01/03: What does VHDL stand for?
Ben Marpe:
94839: 06/01/18: clock generation with DOPPLER shift
96249: 06/02/01: BPSK modulation on Xilinx FPGA
Ben Mathew:
4882: 96/12/23: Re: ASICs Vs. FPGA in Safety Critical Apps.
Ben Nguyen:
53833: 03/03/24: Synopsys FPGA Compiler 2 (Altera Edition) question
56738: 03/06/12: How to Capture a VGA display EXTERNALLY
57158: 03/06/24: Re: How to Capture a VGA display EXTERNALLY
57216: 03/06/25: Re: How to Capture a VGA display EXTERNALLY
57370: 03/06/28: Can Altera NIOS processor be syntheized on a Flex FPGA
57459: 03/07/01: Re: Can Altera NIOS processor be syntheized on a Flex FPGA
65988: 04/02/10: Can Altera NIOS be synthesized on non-cyclone/stratix FPGAs?
66120: 04/02/12: Re : fpga +cpu + wireless
68593: 04/04/08: Min. Reqmts For Altera Nios -- i.e Will it work on Parallax Cyclone FastPack?
Ben Pfaff:
110745: 06/10/20: Re: How many clocks are needed for a fastest ADD instruction of latest Intel CPU
110763: 06/10/21: Re: How many clocks are needed for a fastest ADD instruction of latest Intel CPU
Ben Popoola:
36020: 01/10/26: Re: Probing BGA Designs
36021: 01/10/26: Re: Probing BGA Designs
36871: 01/11/22: Re: Altera & Actel prices
60354: 03/09/11: Re: FPGA start?
60451: 03/09/13: Re: Leox
61632: 03/10/08: Programmimg Altera serial configuration devices
62247: 03/10/23: Altera cyclone circuit board indicator
62315: 03/10/26: Re: Altera cyclone circuit board indicator
64684: 04/01/11: Re: Altera Cyclone Serial Configuration devices.
64685: 04/01/11: Re: Programming and debugging the Altera Cyclone family
64690: 04/01/11: Re: Programming and debugging the Altera Cyclone family
64693: 04/01/11: Re: Programming and debugging the Altera Cyclone family
65314: 04/01/24: Re: Altera Active Serial
65502: 04/01/31: Re: Altera Active Serial
65509: 04/01/31: Re: Altera Active Serial
68769: 04/04/17: FPGA power supply circuits
76489: 04/12/04: Re: How to subscribe to the newsgroup comp.arch.fpga
76785: 04/12/11: Re: PCI design with vhdl
78028: 05/01/23: Re: Queries regarding PCI with Spartan3
78405: 05/01/31: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
78665: 05/02/05: Re: Spartan-3 Starter Kit supplier in the UK?
78845: 05/02/08: Re: SimmStick FPGA module
78910: 05/02/10: Re: Plea for help with MAX7000S
78979: 05/02/10: Re: Plea for help with MAX7000S
79453: 05/02/19: Re: Protecting IP in China
79848: 05/02/25: Re: Pin Declaration in new EC/ECP FPGAs
85586: 05/06/11: Re: PowerPC crash down
86327: 05/06/25: Re: use lattice and actel synplify together...
86328: 05/06/25: Re: Lattice LFEC
86330: 05/06/25: Re: Need help for Xilinx FPGA
86341: 05/06/25: Re: Lattice LFEC
86342: 05/06/25: Re: interfacing to multiple converters
87713: 05/07/29: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
106346: 06/08/12: Re: Lattice Blogs
106822: 06/08/20: Re: xilinx or altera?
115217: 07/02/03: Re: circle generation algorithm
115229: 07/02/04: Re: Differential pairs per Bank
116496: 07/03/11: Are FPGAs go enough for clock dstribution
117272: 07/03/27: Re: RISC implementation questions
119247: 07/05/15: Re: First MicroBlaze demo design for Spartan-3A Starterkit
Ben Sanchez:
20044: 00/01/25: Re: Xilinx vs. other FPGAs manufactrers
20131: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20135: 00/01/28: Re: LVPECL I/O interface
20152: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
24153: 00/07/27: LFSR as a divider
24158: 00/07/27: Re: Question of Virtex DLL
24179: 00/07/28: Re: Question of Virtex DLL
24180: 00/07/28: Re: LFSR as a divider
24184: 00/07/28: Re: LFSR as a divider
24244: 00/07/31: Re: Virtex DLL and external clocks
24254: 00/08/01: Re: Virtex DLL and external clocks
25800: 00/09/20: Re: Freelance Designer Needed: Protel & FPGA
Ben Stuyts:
3571: 96/06/27: Need recommendation for PCI interface on 68332
3583: 96/07/01: Re: REQ:Old Picture of Bus
Ben Twijnstra:
5617: 97/03/01: Re: Rising_Edge/Falling_Edge Functions
28220: 01/01/01: Re: help
43510: 02/05/22: Re: Altera FPGA (EPM7256AETC100-5) programming
44200: 02/06/13: Re: Altera APEX reconfigurates endlessly
44706: 02/06/27: Re: too hot fpga device
44844: 02/07/03: Re: Converting to Altera Quartus
44845: 02/07/03: Re: Reconfiguring .SOF file
45012: 02/07/10: Re: Xilinix or Altera - which dev-board?
45918: 02/08/10: Re: unloading a fast ADC
46319: 02/08/26: Re: sensing an oscillator
46948: 02/09/12: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46949: 02/09/13: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46999: 02/09/13: Re: QUARTUS II V2.1 LINUX (C) ALTERA
47075: 02/09/16: Re: Modelsim-Altera gate level simulation
48141: 02/10/11: Re: Why can't Altera sw be as good as Xilinx's sw?
48456: 02/10/18: Re: How assingment of IOE by Quratus Ver2.1
48458: 02/10/18: Re: HELP about signal integrity, PLEASE!
49985: 02/11/27: Re: Fast Digital Synthesis Generator
52795: 03/02/22: Re: spartan III what is it?
54377: 03/04/09: Re: OK, where does an FPGA newbie start?
54443: 03/04/11: Re: OK, where does an FPGA newbie start?
54492: 03/04/11: Re: Quartus II and user libraries
54493: 03/04/11: Re: SOPC Builder under Linux?
54633: 03/04/15: Re: NIOS 3.0 Fmax and other Issues
54679: 03/04/16: Re: Quartus II and user libraries
54766: 03/04/17: Re: NIOS 3.0 Fmax and other Issues
54767: 03/04/17: Re: spartan2e vs cyclone
54774: 03/04/17: Re: NIOS 3.0 Fmax and other Issues
54816: 03/04/19: Re: Altera Megawizard from Quartus 2.2 (qmegawiz.exe)
54848: 03/04/20: Re: bidirectional differential pairs, possible?
54941: 03/04/22: Re: NIOS 3.0 Fmax and other Issues
54944: 03/04/22: Re: quartus_cmd under Linux
54946: 03/04/22: Re: Initial values for internal RAM
55029: 03/04/24: Re: open SOC-bus system required!
55030: 03/04/24: Re: bidirectional bus
55086: 03/04/25: Re: question about modelsim
55145: 03/04/28: Re: LVDS I/O with Altera Cyclone
55146: 03/04/28: Re: Use of bidir ports on Flex 10k.
55147: 03/04/28: Re: NIOS Development Board and Flash Protection
55148: 03/04/28: Re: Driving GPIO and FAST pins directly from dedicated clock input (CLKx)
55363: 03/05/05: Re: Ibis for Cyclone?
55453: 03/05/08: Re: LPM_ROM problem with Altera EP1K50 parts
55827: 03/05/20: Re: a (PC) workstation for FPGA development
55890: 03/05/22: Re: a (PC) workstation for FPGA development
55928: 03/05/23: Re: New version,Low Speed
56703: 03/06/11: Re: test vectors storage/generation
57205: 03/06/25: Re: Quartus II for Linux
57206: 03/06/25: Re: Altera FPGA
57745: 03/07/05: Re: Quartus II 3.0 Release & Web Edition Download Links
57746: 03/07/05: Re: Quartus II 3.0 Release & Web Edition Download Links
59228: 03/08/12: Re: Nios Clock Frequency
59229: 03/08/12: Re: Nios Clock Frequency
59230: 03/08/12: Re: speeding up quartus
59282: 03/08/13: Re: Nios Clock Frequency
60439: 03/09/12: Re: Altera's Quartus II "smart compilation" feature killed my design?
62306: 03/10/25: Re: Running Quartus II on ReadHat Linux 9.0
62307: 03/10/25: Re: Running Quartus II on ReadHat Linux 9.0
62349: 03/10/27: Re: SDRAM Controller
62404: 03/10/29: Re: Sort of Running Quartus II on SuSE Linux 8.1-- sp2=fix!
62567: 03/11/01: Re: Running Quartus II on ReadHat Linux 9.0
62806: 03/11/07: Re: latch and shift 15 bits.
63464: 03/11/21: Re: Apex power calculator
63465: 03/11/21: Re: Altera Stratix synthesis error
63795: 03/12/04: Re: overshoot problem of EPM7128S
63946: 03/12/09: Re: Altera's altsyncram MAXIMUM_DEPTH
64816: 04/01/14: Re: Altera NIOS cyclone edition development board problem
67541: 04/03/13: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67542: 04/03/13: Re: ACEX: max current per pin
70259: 04/06/10: Re: can't trap custom ITon NIOS
71581: 04/07/22: Re: Cheap FPGA's
72836: 04/09/03: Re: Is Stratix-II ALM some kind of partitionable LUT
73685: 04/09/28: Re: Quartus and VDHL misbehavior
75095: 04/10/26: Re: inefficient mux synthesis in quartus
74075: 04/10/03: Re: Quartus and VDHL misbehavior
74147: 04/10/04: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74260: 04/10/06: Re: Ripple counter ?
74313: 04/10/07: Re: PLL lock usage into Altera Stratix devices
74369: 04/10/08: Re: PLL lock usage into Altera Stratix devices
74372: 04/10/08: Re: PLL lock usage into Altera Stratix devices
74465: 04/10/12: Re: Routing PLL output
74496: 04/10/12: Re: Routing PLL output
74663: 04/10/15: Re: How many Altera LE's to Xilinx Slices????
74878: 04/10/20: Re: Back-Annotate Assignments
75139: 04/10/26: Re: inefficient mux synthesis in quartus
75222: 04/10/29: Re: Random number generation in testbench
76062: 04/11/23: Re: Quartus II: trace
76160: 04/11/26: Re: Quartus Debian Install
76205: 04/11/28: Re: Quartus II: trace
76676: 04/12/08: Re: Fpga prices
76959: 04/12/17: Re: altera cyclone and fifo synchronisation
77043: 04/12/20: Re: Using low-core-voltage devices in industrial applications
77556: 05/01/11: Re: altera stratix problem
77587: 05/01/11: Re: altera stratix problem
77646: 05/01/13: Re: Programming and copyright
77771: 05/01/17: Re: HardCopy cost
77812: 05/01/17: Re: HardCopy costs- the hidden ones
77912: 05/01/20: Re: Asynchronous memory in Stratix devices
77931: 05/01/20: Re: Hardened Logic and SEUs
77934: 05/01/20: Re: LVDS through connectors
77961: 05/01/21: Re: lasy question about VHDL: logic between a bit and a vector
78525: 05/02/02: Re: MP3 Player Project
78530: 05/02/02: Re: Altera FLEX 8000
78584: 05/02/03: Re: Altera PLL and Timing Analysis
79916: 05/02/25: Re: embedded 2005 in Nuernburg
80025: 05/02/28: Re: packages(2)
80298: 05/03/03: Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
80541: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80586: 05/03/08: Re: What's the Altera Equivalent of a Xilinx .rbt file?
80682: 05/03/10: Re: Xilinx vs Altera high-end solutions
80728: 05/03/10: Re: NIOS SRAM Problem with Stratix
80822: 05/03/11: Cool tool?
80879: 05/03/13: Re: Parallel ATA/Spartan 3 starter board / Student Project
81058: 05/03/17: Re: Altera free web FPGA software license question
81075: 05/03/17: Re: Altera free web FPGA software license question
81101: 05/03/17: Re: Newbie: Slow FPGAs
81111: 05/03/17: Re: Newbie: Slow FPGAs
81170: 05/03/18: Re: Spartan 3E vs. Cyclone2
81226: 05/03/19: Re: Spartan 3E vs. Cyclone2
81238: 05/03/20: Re: Spartan 3E vs. Cyclone2
81306: 05/03/21: Re: Is the Xilinx EDK free?
81313: 05/03/21: Re: Is the Xilinx EDK free?
81349: 05/03/22: Re: PAL problems (again)
81350: 05/03/22: Re: PowerPC soft-core?
81360: 05/03/22: Re: PowerPC soft-core?
81449: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
81484: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
81839: 05/04/01: Re: 4/1
81939: 05/04/04: Re: Stupid question
82229: 05/04/08: Re: Quartus 5
82362: 05/04/11: Re: Altera and VHDL library
82363: 05/04/11: Re: State of MAX7000S I/O pins before programming
82422: 05/04/12: Re: State of MAX7000S I/O pins before programming
82437: 05/04/12: Re: State of MAX7000S I/O pins before programming
82498: 05/04/13: Re: 5V PCI interface
82533: 05/04/13: Re: 5V PCI interface
82658: 05/04/15: Re: different I/O buffers available inXilinx FPGA
82745: 05/04/17: Re: Spartan 3E slower that Spartan 3?
83271: 05/04/26: Re: quartus_pgm under Linux?
83275: 05/04/26: Re: Sync + FIFO
83546: 05/05/02: Re: JTAG communication Problems in Quartus using Signal Tap
83569: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83643: 05/05/04: Re: JTAG communication Problems in Quartus using Signal Tap
83653: 05/05/04: Re: Multiply Accumulate FPGA/DSP
83656: 05/05/04: Re: Saturating an integer
83667: 05/05/04: Re: Multiply Accumulate FPGA/DSP
83786: 05/05/06: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83826: 05/05/07: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83836: 05/05/07: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83863: 05/05/08: Re: Parallel Cable IV operating in "Compatibility Mode" under linux kernel 2.6.x
83865: 05/05/08: Re: Metastability / MUX question
83909: 05/05/09: Re: Altera: Maxplus rules!
84120: 05/05/12: Re: "Mine is bigger than yours..."
84123: 05/05/12: Re: V4 vs. Stratix-II...
84595: 05/05/22: Re: Looking for core that does a vector product
84650: 05/05/24: Re: QUARTUS on Linux.
84700: 05/05/24: Re: Bresenham Algorithms
84701: 05/05/24: Re: Bresenham Algorithms
84706: 05/05/24: Re: Bresenham Algorithms
84837: 05/05/30: Re: Synplify 8.1 vs. Quartus II 5.0 QoR
85076: 05/06/03: Re: Boot problem Stratix Kit EP1S25
85114: 05/06/05: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85389: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85392: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85453: 05/06/09: Re: General gripe session ....
85562: 05/06/10: Re: computer upgrade time.
85765: 05/06/15: Re: Somewhat OT - falling behind the times ...
86027: 05/06/21: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
86063: 05/06/21: Re: Altera SCFIFO
86175: 05/06/22: Re: FPGA Filter Design
86177: 05/06/22: Re: Need help understanding this AHDL code
86213: 05/06/23: Re: Commercial Z180 / 64180 core
86420: 05/06/28: Re: FPGA for video processing
86447: 05/06/28: Re: proth siever in FPGA?
86448: 05/06/28: Re: good bye nios (o;
86702: 05/07/05: Re: nios2 toolchain sources...
86728: 05/07/05: Re: nios2 toolchain sources...
86990: 05/07/12: Re: Clock recovery in FPGA at 300 MHZ
87183: 05/07/18: Re: EHLO, board designers
87284: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
87621: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
87639: 05/07/27: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
87641: 05/07/27: Re: Conversion of ASIC RTL to FPGA RTL
87663: 05/07/27: Re: stratix gx query
87678: 05/07/28: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
87721: 05/07/29: Re: XST and TCL support?
87855: 05/08/02: Re: Programmable frequency synthesizer with Xilinx DCM
87925: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
87986: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
87987: 05/08/04: Re: Quartus II 4.2 Incremental Systhesis
88200: 05/08/12: Re: Using an oscillator in a rugged environment
88483: 05/08/19: Re: PLL
88712: 05/08/26: Re: Altera ByteBlaster II vs ByteBlaster MV
90019: 05/10/03: Re: Altera why so QUIET !?
90086: 05/10/04: Re: Altera why so QUIET !?
90099: 05/10/04: Re: EasyPath, demystified
90119: 05/10/05: Re: EasyPath, demystified
90139: 05/10/05: Re: EasyPath, demystified
90206: 05/10/06: Re: Altera Gate Delay Simulation
90209: 05/10/06: Re: EasyPath, demystified
90945: 05/10/25: Re: a few questions
91078: 05/10/28: Re: Optimizing a State Machine
91081: 05/10/28: Re: Cost to go from FPGA to ASIC
92907: 05/12/09: Re: some new PCIe products
94733: 06/01/17: Re: Getting Gate Counts from Quartus
94787: 06/01/17: Re: Getting Gate Counts from Quartus
97460: 06/02/22: Re: doubt
98631: 06/03/13: Re: Why does Xilinx hate version control?
99139: 06/03/20: Re: FPGA FIR advice
99631: 06/03/27: Re: Altera web site inaccessible
99665: 06/03/28: Re: Altera web site inaccessible
99745: 06/03/29: Re: Altera web site inaccessible
100165: 06/04/04: Re: about the low power design
101395: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101417: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101760: 06/05/05: Re: LVDS inputs on Cyclone II
102063: 06/05/10: Re: Altera Max Plus II to Quartus migration tool
102594: 06/05/18: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102884: 06/05/22: Re: ispLEVER Starter 6.0 FPGA Design Software Available
106937: 06/08/22: Re: Configuring an Altera Serial Prom/Flash using a 8051 CPU
107534: 06/08/30: Re: Spartan-4 ?
107633: 06/08/30: Re: Spartan-4 ?
107634: 06/08/30: Re: Spartan-4 ?
108668: 06/09/15: Re: Altera CPLD 7128S heating up
108877: 06/09/18: Re: upgrading firmware on stratix 2 without NIOS IDE
109091: 06/09/20: Re: Old vs. New FPGAs
109609: 06/09/30: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109887: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
110007: 06/10/09: Re: Quartus II 6.0
110008: 06/10/09: Re: Quartus II 6.0: System clock has been set back
110033: 06/10/09: Re: Quartus II 6.0: System clock has been set back
110034: 06/10/09: Re: Quartus II 6.0
110075: 06/10/10: Re: boundary scan
110807: 06/10/23: Re: How do I erase an Altera EPM7064 with JTAG lockout
110920: 06/10/25: Re: Meta-stable problem with MAX-II ?
110921: 06/10/25: Re: Meta-stable problem with MAX-II ?
110948: 06/10/26: Re: Meta-stable problem with MAX-II ?
111050: 06/10/28: Re: A spectre is haunting this newsgroup, the spectre of metastability
111775: 06/11/10: Re: Nios2 access to EPCS device without using HAL drivers
111842: 06/11/11: Re: Stratix-III announced
111896: 06/11/12: Re: Question about Maxplus 2?
112846: 06/11/30: Re: Stratix II GX Transceivers
112963: 06/12/02: Re: LVDS output pins of Altera Cyclone II
113075: 06/12/06: Re: Altera starter kits
113915: 06/12/29: Re: SPI slave problem
114181: 07/01/06: Re: Help Implementing an 1000Base-T Ethernet on Stratix II GX
114947: 07/01/27: Re: Higher studies
115084: 07/01/30: Re: help with Design Compiler -> Quartus
115278: 07/02/05: Re: query in P&R of FPGA
115870: 07/02/22: Re: ROC PORT
115871: 07/02/22: Re: 2x technique
115872: 07/02/22: Re: internal DCM
117145: 07/03/23: Re: Digital AM/FM Receiver - Systemic Question
117427: 07/03/30: Re: CycloneII altlvds_rx
117673: 07/04/06: Re: Transition from ASIC to FPGA
117684: 07/04/07: Re: Transition from ASIC to FPGA
118460: 07/04/27: Re: Quartus Fitter Seed Setting
118517: 07/04/28: Re: Altera Quartus II v7.0 under openSUSE 10.2
119134: 07/05/12: Re: how to choose the perfect fpga support
119135: 07/05/12: Re: Power Consumption Estimation for PCI card, any advice?
119381: 07/05/17: Re: DDR 2 Memory controller own implementattion
119785: 07/05/25: Re: Went from Xilinx to Altera: Cyclone-II and I/O pullup?
120783: 07/06/16: Re: Using LogicLock in Altera Quartus II
121930: 07/07/15: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121932: 07/07/15: Re: ESR Meter - design contest
121946: 07/07/16: Re: QuartusII Web Edition software question
122395: 07/07/26: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122587: 07/08/01: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
<Ben.Nader@gmail.com>:
108616: 06/09/13: XIlinx Spartan 2E stuck in configuration mode
<ben.s.vaughan@gmail.com>:
109351: 06/09/25: Really slow programming time
<ben.twijnstra@gmail.com>:
161662: 20/02/18: Re: Is FPGA code called firmware?
<ben@hometoolong.inv>:
131325: 08/04/18: Xilinx DDR2 Interface
131402: 08/04/21: Re: Xilinx DDR2 Interface
131451: 08/04/21: Re: Xilinx DDR2 Interface
133811: 08/07/16: Re: No open-drain in V5 to drive an external LED?
137399: 09/01/14: Re: effect of channel capacity on hamming code
Ben_Koh:
73925: 04/10/01: unbreakable conmbination cycle in Handel C
73216: 04/09/15: Handel C writing to flash ram & sampling hey guys clock setting
Ben_M:
99533: 06/03/26: EDK 8.1 Problem: Adding *.h or *.c files ?
105744: 06/07/31: Accessing one SDRAM from two MicroBlazes
105876: 06/08/02: Re: Accessing one SDRAM from two MicroBlazes
Ben_Quem:
139819: 09/04/15: What is the minimum acceptable slack on a signal
139843: 09/04/16: Re: What is the minimum acceptable slack on a signal
139844: 09/04/16: OFFSET OUT
139845: 09/04/16: OFFSET OUT
Benedikt Huber:
9080: 98/02/18: download cable for lattice ISP -> schematics
9663: 98/03/29: ISP Synario SYNDPM.EXE Environment Variables?
10594: 98/06/04: Re: LATTICE 2032 problems
10595: 98/06/04: Re: LATTICE 2032 problems
17137: 99/07/02: Re: ABL-Problem (XILINX CPLD)
Benedikt Wildenhain:
108395: 06/09/10: Trying to get plb_temac working
108399: 06/09/10: Re: Trying to get plb_temac working
108514: 06/09/12: Re: Trying to get plb_temac working
108594: 06/09/13: Re: Trying to get plb_temac working
108860: 06/09/18: Re: how to do the synthesis
109436: 06/09/26: Re: Trying to get plb_temac working
bengineerd:
115606: 07/02/14: Spartan 3 Output Driver Issue
115632: 07/02/15: Re: Spartan 3 Output Driver Issue
115634: 07/02/15: Re: Spartan 3 Output Driver Issue
119021: 07/05/09: Re: Open Source (was: Xilinx software quality - how low can it go ?!)
Bengt Larsson:
66537: 04/02/21: Re: Dual-stack (Forth) processors
66542: 04/02/22: Re: Dual-stack (Forth) processors
benh:
128021: 08/01/13: libusb-driver and Spartan3-AN Eval kit woes
Benjamin Couillard:
135289: 08/09/24: Weird DCM problem with external deskew
135290: 08/09/24: Re: Avalda's Parallel F# to RTL FPGA Compiler
135296: 08/09/24: Re: Weird DCM problem with external deskew
135301: 08/09/24: Re: Weird DCM problem with external deskew
135311: 08/09/25: Re: Weird DCM problem with external deskew
135637: 08/10/10: Re: XMOS XC-1 kits are shipping
135650: 08/10/11: Re: XMOS XC-1 kits are shipping
135651: 08/10/11: Re: XMOS XC-1 kits are shipping
135746: 08/10/14: Re: Complex Event Processing on FPGA
135812: 08/10/16: Re: XMOS XC-1 kits are shipping
136231: 08/11/07: Re: Tilera multicore replaces FPGA?
136234: 08/11/07: Re: Tilera multicore replaces FPGA?
136242: 08/11/07: Re: face recognition
136244: 08/11/07: Re: Tilera multicore replaces FPGA?
136251: 08/11/07: Re: Tilera multicore replaces FPGA?
136279: 08/11/09: Re: face recognition
137930: 09/02/02: Re: Why the second flip-flop in Virtex-6?
137946: 09/02/02: Re: Why the second flip-flop in Virtex-6?
137961: 09/02/03: Re: Why the second flip-flop in Virtex-6?
137965: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138857: 09/03/12: Re: speeding hough tranformation in microblaze
139259: 09/03/24: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by
139262: 09/03/24: Re: chipscope pro 9.2i can't triger immediately !
139816: 09/04/14: Re: Find FPGA updates On Twitter
139944: 09/04/20: ISE 10.1 installation troubles on windows Vista 32bit
139950: 09/04/20: Re: ISE 10.1 installation troubles on windows Vista 32bit
141601: 09/06/29: dual port inference problem
141604: 09/06/29: Re: dual port inference problem
144447: 09/12/08: Possible memory leak in xst in ISE 11.3
144469: 09/12/09: Re: Possible memory leak in xst in ISE 11.3
145753: 10/02/22: Re: System design in FPGA
148789: 10/08/24: Mismatch between Xilinx FIR interpolation filter
149143: 10/10/04: Re: Starting a career with FPGAs
149749: 10/11/22: Synthesis/place and route with Solid-State Drives
149796: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
149800: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
150019: 10/12/06: Re: FPGA project structure definition
150236: 11/01/04: Transfer data from one clock domain to another clock created by the
150238: 11/01/04: Re: Transfer data from one clock domain to another clock created by
150242: 11/01/04: Re: Transfer data from one clock domain to another clock created by
151436: 11/04/07: Reference book on Pci-express (Hardware and software point of view)
151442: 11/04/08: Re: Reference book on Pci-express (Hardware and software point of view)
151460: 11/04/11: Controllling reset duration in EDK - plb bus
152237: 11/07/25: Question on PCI-express verssus Standard PCI performance
152538: 11/09/08: Re: reduce EDK synthesis time
152539: 11/09/08: Re: reduce EDK synthesis time
153047: 11/11/22: Re: RTOS with support for TCP/IP sockets on Spartan 3E
153156: 11/12/16: Clock distribution for ADC and jitter
153160: 11/12/16: Re: Clock distribution for ADC and jitter
153316: 12/01/30: Re: Active-HDL/Xilinx Core FIFO Gen Sim Problem
154110: 12/08/09: Re: xilinx fir compiler
154122: 12/08/14: Re: xilinx fir compiler
159671: 17/01/27: Re: Hardware floating point?
159677: 17/01/27: Re: Hardware floating point?
159684: 17/01/30: Re: Hardware floating point?
160490: 18/02/16: Re: Scripts to maintain list of addresses in VHDL core communicating
160687: 18/10/11: Re: What to do with an improved algorithm?
160690: 18/10/12: Re: What to do with an improved algorithm?
160692: 18/10/17: Re: What to do with an improved algorithm?
161194: 19/02/25: Re: Cyclone V decimation
161280: 19/03/21: High-level synthesis
161286: 19/03/22: Re: High-level synthesis
161289: 19/03/22: Re: High-level synthesis
161311: 19/03/27: Re: High-level synthesis
161396: 19/07/02: How do big compagnies use Verilog/VHDL for processor designs?
Benjamin D Klass:
4121: 96/09/13: Re: Implement FPGA multiplier using VHDL synthesis
4998: 97/01/10: Re: Altera clique
5149: 97/01/27: Re: ABEL->AHDL
Benjamin Gene Cheung:
225: 94/09/28: (fwd) Postings sent as mail ???--------------
226: 94/09/28: What do think about the Intel Flexlogic8160?
245: 94/10/01: Re: What do think about the Intel Flexlogic8160?
246: 94/10/01: Re: What do think about the Intel Flexlogic8160?
427: 94/11/14: Anybody used FPGA as Encryption Device?
444: 94/11/17: Re: Anybody used FPGA as Encryption Device?
Benjamin Gittins:
56510: 03/06/07: Ranking of FPGA synthesis tools, specifically actel support
Benjamin Heart:
42551: 02/04/26: ABEL for the Altera MAX 7000
Benjamin Hoffman:
30038: 01/03/21: Trouble with assigning output pins on Xilinx (foundation)
Benjamin J. Stassart:
82528: 05/04/13: Re: Embedded MicroBlaze solution
82659: 05/04/15: Re: different I/O buffers available inXilinx FPGA
82855: 05/04/18: Re: Soft CPU vs Hard CPU's
84962: 05/06/01: Re: why can't i use opb_spi core in EDK6.3?
85331: 05/06/07: Re: Anonymous structs in Microblaze C compiler
Benjamin Krill:
135272: 08/09/23: Re: Xilinx Mode Select Pins
135294: 08/09/24: Re: Xilinx Mode Select Pins
135372: 08/09/29: Re: Sending UDP packets over Ethernet
135376: 08/09/29: Re: Sending UDP packets over Ethernet
136051: 08/10/29: Re: Register File distributed all over the FPGA
136055: 08/10/29: Re: Register File distributed all over the FPGA
136058: 08/10/29: Re: Register File distributed all over the FPGA
136233: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
140470: 09/05/14: Re: ISE multiple UCF files from commandline
141367: 09/06/20: Re: TimingAnalyzer is now freeware
144771: 10/01/01: Re: verilog multiplexer
148628: 10/08/10: Re: Multiple builds with different top-level generic
148630: 10/08/10: Re: Instantiating non-global clock buffers (Xilinx ISE)
148632: 10/08/10: Re: Instantiating non-global clock buffers (Xilinx ISE)
150185: 10/12/29: Re: Error in Clock Divider!
Benjamin Marpe:
94864: 06/01/18: Re: clock generation with DOPPLER shift
94957: 06/01/19: Re: clock generation with DOPPLER shift
96373: 06/02/02: Re: BPSK modulation on Xilinx FPGA
Benjamin Menküc:
79934: 05/02/26: spartan 3 vs virtex 2
79937: 05/02/26: Re: spartan 3 vs virtex 2
79938: 05/02/26: Re: spartan 3 vs virtex 2
79940: 05/02/26: livedesign or ise
79999: 05/02/28: Re: spartan 3 vs virtex 2
80000: 05/02/28: Re: livedesign or ise
80030: 05/02/28: OT: funny idea
80166: 05/03/02: Re: OT: funny idea
Benjamin Todd:
43808: 02/06/03: Re: Pipelining
44038: 02/06/10: Re: Problem with spartan2 vhdl code
44053: 02/06/11: Problems initialising an FPGA - SPARTAN II
44066: 02/06/11: Re: Problems initialising an FPGA - SPARTAN II
44188: 02/06/13: Re: Multi Pass PAR
44343: 02/06/18: Re: Initial of virtex II block ram
44344: 02/06/18: Re: Initial of virtex II block ram
44450: 02/06/20: Re: Xilinx/Simprims & Modelsim
44959: 02/07/08: Re: problem while generating clk1x,clk2x,clk180 clocks from CLKDLL
44960: 02/07/08: Re: ModelSim License problem
45198: 02/07/15: Re: Which is best method for register with settable and clearable bits
45216: 02/07/16: Re: problem porting sync write, async read RAM to Xilinx...
45387: 02/07/22: Re: I would like to know how to develop a MCU.
45555: 02/07/26: Re: Problem with mapping
65920: 04/02/10: Re: power calculation in fpga
75209: 04/10/29: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
74840: 04/10/20: Re: counter skrews up design
78449: 05/02/01: Re: Metastability MTBF in Cyclone
80347: 05/03/04: Re: 1,5Mhz Clock
80355: 05/03/04: Re: 1,5Mhz Clock
84083: 05/05/12: Re: RS 232 receiver using spartan 3 board
84099: 05/05/12: Re: Counting Clocks
84100: 05/05/12: Re: Counting Clocks
88011: 05/08/05: Re: Xilinx Impact order
88579: 05/08/23: Re: Stdin / stdout through RS232
88580: 05/08/23: Re: DCM does not do anything?
88581: 05/08/23: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88583: 05/08/23: Re: Stdin / stdout through RS232
88584: 05/08/23: Re: Stdin / stdout through RS232
88683: 05/08/25: Re: Spartan and Flash PROM : Boundary Scan
88801: 05/08/29: Re: mails from Aman Mediratta
90803: 05/10/21: Re: Spartn 3 configuration failure
90908: 05/10/25: System ACE equivalent for CPLDs
90915: 05/10/25: Re: System ACE equivalent for CPLDs
90961: 05/10/26: Re: System ACE equivalent for CPLDs
91066: 05/10/28: Re: System ACE equivalent for CPLDs
91190: 05/11/01: Re: System ACE equivalent for CPLDs
91195: 05/11/01: Re: Spartan-3E starter kit
91847: 05/11/15: Re: RoHS
97776: 06/02/27: Re: XC9500 JTAG Initialize problem
97820: 06/02/28: Re: New XC9572 decoupling newbie question :-)
97822: 06/02/28: Re: The 95108 cpld is getting heated when connected by CRO
98456: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98592: 06/03/13: Re: Soldering SMT/BGA
98593: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
98657: 06/03/14: Re: How do I handle this memory related issue?
101582: 06/05/03: Re: ISE8.1 inout, tristate Problem?Please help!
101646: 06/05/04: Re: ISE8.1 inout, tristate Problem?Please help!
105331: 06/07/20: Re: High-speed ADC+ Rocket I/O capability FPGA board
105621: 06/07/27: Rocket IO as a high speed sampler
105668: 06/07/28: Re: Rocket IO as a high speed sampler
105775: 06/07/31: Re: Rocket IO as a high speed sampler
106786: 06/08/19: Re: S3 starter kit, command-line
106889: 06/08/22: Re: ISE 8.1: Process "Map" failed
106897: 06/08/22: Re: ISE 8.1: Process "Map" failed
106966: 06/08/23: Re: Modelsim
107358: 06/08/27: Re: Error message in ISE7.1
107399: 06/08/28: Re: Spartan 3 and 5V input
107432: 06/08/28: Re: EDK 6.3 project file growth
108339: 06/09/08: Re: microblaze programm doesn't fit into bram...
108636: 06/09/14: Re: Prefered ieee libraries?
109763: 06/10/05: Re: An implementation of a clean reset signal
110452: 06/10/16: Re: WiFi signal repeater using any virtix fpga
110848: 06/10/24: Re: iMPACT:923 - Can not find cable, check cable setup !
114665: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
115015: 07/01/29: Re: Minimal design for xilinx?
115116: 07/01/31: Re: cpld version?
115407: 07/02/09: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115463: 07/02/12: Re: Weird problem with WP 9.1sp1 and XC95144XL
115976: 07/02/27: Re: $recovery
116100: 07/03/01: Re: $recovery
116234: 07/03/05: Re: LCD code
116630: 07/03/14: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116962: 07/03/21: Re: FPGA with 5V and PLCC package
116991: 07/03/21: Re: FPGA with 5V and PLCC package
117054: 07/03/22: Re: Parallel Cable IV in Spartan 3E???
117481: 07/04/02: Re: Dear Xilinx
117627: 07/04/05: Re: Xilinx: WARNING:PhysDesignRules:372 (What the heck?)
117922: 07/04/13: Re: JTAG ID code 0xFFFFFFFF
118021: 07/04/16: Re: Why 166Mhz DDR?
118022: 07/04/16: Re: JTAG ID code 0xFFFFFFFF
118583: 07/04/30: Re: Please help me fast !!!!!
118716: 07/05/02: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
119065: 07/05/10: Re: ISE9.1: ERROR:Place:911
119068: 07/05/10: Re: ISE9.1: ERROR:Place:911
119093: 07/05/11: Re: ISE9.1: ERROR:Place:911
119637: 07/05/24: Re: Binary to BCD
Benjamin Ylvisaker:
85059: 05/06/03: MediaBench
91354: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
<benjamin.carrion-schaefer@hl.siemens.de>:
11189: 98/07/24: Interface
11197: 98/07/24: FPGA board interface
11406: 98/08/11: VHDL-C
<Benjamin_Boicourt@css.mot.com>:
14567: 99/02/04: career
<benkhalh@hotmail.com>:
97114: 06/02/16: Need some Advice, please
97162: 06/02/17: Re: Need some Advice, please
97163: 06/02/17: Re: Need some Advice, please
97165: 06/02/17: Re: Need some Advice, please
benn:
130991: 08/04/07: Avalon Bus <-> Wishbone Bus
134883: 08/09/04: uClinux / Microblaze -- Min. Requirements
Benn:
38579: 02/01/18: verilog/vhdl codeing style
38617: 02/01/19: Re: initial value
38631: 02/01/19: Re: initial value
38632: 02/01/19: Re: initial value
<benn686@hotmail.com>:
96136: 06/01/30: Analog FPGA Project -- VIdeo Router
118942: 07/05/07: How to add an IP Core to a Quartus project
Bennet An:
14493: 99/02/01: Re: Q:Installing Xilinx F1.4 license server
17828: 99/09/08: Re: xilinx software
Benni:
38616: 02/01/19: initial value
Benni V.:
123617: 07/08/31: Spartan 3E - Readback via JTAG
123636: 07/08/31: Re: Spartan 3E - Readback via JTAG
Benny:
38618: 02/01/19: Re: initial value
38636: 02/01/19: help me!
38655: 02/01/20: Re: help me!
Benoit:
44998: 02/07/09: test sign
53621: 03/03/18: how to calculate many CRC in FPGA ?
53743: 03/03/21: source code for crc
55994: 03/05/26: Pos Phys L4
56384: 03/06/04: Orcad 2 Quartus
57433: 03/06/30: PLL with LVDS clk in quartus
67640: 04/03/16: Minimal PCI host system design - pci buffer requirements
85288: 05/06/07: Nios Stratix
Benoit MICHEL:
14169: 99/01/16: looking for an internship
Benoit Triquet:
647: 95/01/27: 680x0 and PCI
Benoît:
28071: 00/12/20: insert a BUFGP in a SPARTAN with foundation3.1
Benoît HAMON:
20574: 00/02/15: clock
22645: 00/05/16: Foundation to Mentor
<benradu@gmail.com>:
123749: 07/09/03: Re: opb_timer interrupt self test problem
127300: 07/12/17: Re: Debugging EDK DDR interface
129634: 08/02/29: Re: Making changes to custom IP in EDK
BentC:
68432: 04/04/04: Re: iMPACT "Programming Failed"
<benwang08@gmail.com>:
136845: 08/12/08: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
136864: 08/12/09: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
137037: 08/12/20: Large BRAM synthesis
137044: 08/12/20: Re: Large BRAM synthesis
<benyamin@my-dejanews.com>:
11510: 98/08/20: vector product minimization problem
11532: 98/08/21: Re: vector product minimization problem
11553: 98/08/23: Re: vector product minimization problem
11609: 98/08/26: Re: vector product minimization problem
11622: 98/08/27: Re: vector product minimization problem
13778: 98/12/26: smallest DCT algorithm?
13780: 98/12/26: Re: smallest DCT algorithm?
13831: 98/12/29: Re: smallest DCT algorithm?
beomseok,lee:
85104: 05/06/04: How to get *.mcs file containing both *.bit and *.elf file, to port linux on my memec virtex-ii board.
85112: 05/06/05: *.mcs format file can't contain over 1Mbyte data?
bereg:
138152: 09/02/08: C-NIT source
Beregnyei Balazs:
64549: 04/01/07: Clock domains
Berend Ozceri:
44007: 02/06/09: Inserting flops to help timing (in Virtex-II)
55113: 03/04/27: Re: Any experience (good or bad) with Northwest Logic PCI core?
Berend Ozceri (snip _news_ from address to reply):
55039: 03/04/25: Any experience (good or bad) with Northwest Logic PCI core?
bergeon:
5365: 97/02/11: Inversion 1/T with registers
Berk:
147400: 10/04/26: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
147403: 10/04/26: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
147468: 10/04/28: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
Berk Birand:
125505: 07/10/26: Xilinx Isolate circuitry
Bernard:
57088: 03/06/23: compxlib windows nt and ncsim
93550: 05/12/24: Re: RTL for Z8000 series CPU?
Bernard Bertrand:
22869: 00/05/29: search PCB programmer VHDL
22886: 00/05/30: Re: search PCB programmer VHDL
23642: 00/07/04: search free pcb programmer FPGA or CPLD
23679: 00/07/05: help making // cable III xilinx
Bernard Esteban:
18937: 99/11/22: Re: Altera JAM
19223: 99/12/07: PCI RESET with FPGA
19224: 99/12/07: JTAG on PCI slot
123944: 07/09/07: How to simple convert a hex or mif file from Altera to Xilinx coe
131122: 08/04/11: Re: Starting a PCI Express Application
137904: 09/02/02: Re: Pci Express on Virtex 5: PC doesn't reboot
Bernard Gunther:
9546: 98/03/23: Master Class in Reconfigurable Computing
Bernard Pottier:
477: 94/11/30: Image processing on FPGAs (Comett student period)
Bernard Sng:
3421: 96/05/28: 120mb floppies
Bernardino León:
24223: 00/07/30: Look-up tables in Altera
24253: 00/08/01: RE: Look-up tables in Altera
24259: 00/08/01: RE: Look-up tables in Altera
Bernd "Bernie" Meyer:
2643: 96/01/17: Re: [q][Reverse Engineering Protection]
Bernd C++.Eggink:
2107: 95/10/16: gater,density &
Bernd Meyer:
266: 94/10/10: Any documentation for Xilinx XNF file format?
Bernd Paysan:
2003: 95/09/30: Re: REPOST: Design Contest Write-up (
2564: 96/01/03: Re: Career value: VHDL or Verilog?
3389: 96/05/23: Re: *** The Great ESDA Shootout ***
6031: 97/04/06: Re: PCI Bus Problems
8357: 97/12/10: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
10376: 98/05/15: Re: Minimal ALU instruction set.
10439: 98/05/19: Re: Minimal ALU instruction set.
10485: 98/05/22: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
12910: 98/11/04: Re: New free FPGA CPU
28314: 01/01/06: Re: Nondeterministic FSMs in hardware?
46553: 02/09/03: Re: Hardware Code Morphing?
50398: 02/12/10: Re: Tiny Forth Processors
53911: 03/03/27: Re: FPGA specs
57240: 03/06/26: Re: Eighty layers of metal!
57320: 03/06/27: Re: Eighty layers of metal!
66560: 04/02/22: Re: Dual-stack (Forth) processors
147126: 10/04/14: Re: I'd rather switch than fight!
147175: 10/04/16: Re: I'd rather switch than fight!
147180: 10/04/16: Re: I'd rather switch than fight!
147185: 10/04/17: Re: I'd rather switch than fight!
147334: 10/04/23: Re: I'd rather switch than fight!
147477: 10/04/28: Re: I'd rather switch than fight!
152871: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
Bernd Scheuermann:
36961: 01/11/27: XST design flow for XC4010XL
37231: 01/12/04: Installing ISE 4.1i
37313: 01/12/06: ISE 4.1i / FPGA Express network installation
37407: 01/12/10: FPGA Advantage and Atmel Figaro
37421: 01/12/10: IP Core Update #1
38467: 02/01/15: RS232 on Atmel ATSTK40 board
38476: 02/01/15: Re: RS232 on Atmel ATSTK40 board
64620: 04/01/09: Job offer: "Optimization on reconfigurable architectures"
Bernd Schmidt:
16022: 99/04/28: FPGA thesis experiments
16023: 99/04/28: FPGA survey, please take part
16575: 99/05/28: Dynamically reconfigurable devices
16861: 99/06/15: Search for FPGA curcuits
16990: 99/06/22: FPGA benchmarks
Bernd Stoehr:
5396: 97/02/13: Experience with LOG/iC2
5508: 97/02/21: Re: State Diagram Tools
5987: 97/04/02: Re: xess
Bernhard Holzmayer:
39598: 02/02/14: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
39756: 02/02/19: Re: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
47123: 02/09/18: Simple parallelport IP for Spartan2
47459: 02/09/26: Re: Simple parallelport IP for Spartan2
48563: 02/10/21: Re: Simple parallelport IP for Spartan2
51942: 03/01/27: Re: Simulink to vhdl tools
52507: 03/02/12: Re: Einstein era>>the ultimate killer experiment! (do it your self instantaneous signal propagation above 40 x c speed )***************************
71866: 04/08/03: Re: Best tool(s) for filter float->fixed->VHDL flow?
71984: 04/08/05: Re: Best tool(s) for filter float->fixed->VHDL flow?
73919: 04/10/01: Re: System Generator.
Bernhard Josef Rieder:
23673: 00/07/05: Re: MPEG audio questions...
Bernhard Mäder:
49603: 02/11/17: Re: Asynchronous FIFOs using Handel-C?
49702: 02/11/19: Re: Asynchronous FIFOs using Handel-C?
49703: 02/11/19: Re: Asynchronous FIFOs using Handel-C?
49757: 02/11/20: Re: Asynchronous FIFOs using Handel-C?
50008: 02/11/28: Re: Asynchronous FIFOs using Handel-C?
50067: 02/11/30: Re: Asynchronous FIFOs using Handel-C?
50076: 02/11/30: Re: Asynchronous FIFOs using Handel-C?
Bernhard Rieder:
46095: 02/08/19: Manipulating Altera SOF Files
Bernhard Sputh:
109614: 06/10/01: Declaration of xilkernel_main()
109626: 06/10/01: EDK: Losing messages when using putfsl_interruptable together with
109644: 06/10/02: Re: EDK: Losing messages when using putfsl_interruptable together
109663: 06/10/02: Re: Declaration of xilkernel_main()
Berni Joss:
19697: 00/01/08: Optimizing VHDL for Altera
19715: 00/01/09: Re: Optimizing VHDL for Altera
19740: 00/01/10: Re: Optimizing VHDL for Altera
26952: 00/11/04: Re: Spartan2 prototype boards
27115: 00/11/11: Re: Configuring Xilinx FPGA using PIC16F84
28534: 01/01/16: Re: revision control tools ??
30854: 01/05/01: Re: Shannon Capacity
30901: 01/05/02: Re: Shannon Capacity
Bernt_Hullen:
8967: 98/02/10: Re: Free FPGA tools???
Berry:
109562: 06/09/28: ddr2 SODIMM controller - time simulation problem
109585: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
BERT:
110414: 06/10/15: Systolic Viterbi Decoder ?
117919: 07/04/13: JTAG ID code 0xFFFFFFFF
117923: 07/04/13: Re: JTAG ID code 0xFFFFFFFF
Bert:
68762: 04/04/16: Re: Document State Machines?
123346: 07/08/24: Re: xilinx usb cable question
129684: 08/03/03: Re: Is there any way to disable JTAG for Sptantan3AN
133842: 08/07/17: Re: Xilinx/Altera gate equivalence
138442: 09/02/23: Cyclone2 4-phase clock generation
139208: 09/03/23: ERROR:Pack:1564 on Virtex 4
139246: 09/03/24: Re: ERROR:Pack:1564 on Virtex 4
bert:
123309: 07/08/23: xilinx usb cable question
Bert Cuzeau:
5123: 97/01/25: Re: FPGA Lab.
38546: 02/01/17: Re: Signal processing using FPGAs
38761: 02/01/24: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
38787: 02/01/25: Re: Analog input into Altera FLEX10K using ADC. Can anyone help??
41883: 02/04/10: Checking Synthesis tools.
41892: 02/04/10: Re: Checking Synthesis tools.
50788: 02/12/19: looking for 100-Base-x Interface board w/wo FPGA
81062: 05/03/17: Tornado Board and Education Kit is available.
81623: 05/03/29: Re: newbie verilog question
81624: 05/03/29: Re: Quartus II 4.1 Problem
83167: 05/04/25: Re: "Correct design" and practical trouble and simulation trouble
83248: 05/04/26: Re: Rom Inference
83250: 05/04/26: Re: MAX II UFM data specification and programming
83286: 05/04/27: Re: XC4k parts obsolete ?
83305: 05/04/27: Re: Synplify warning CL209
83357: 05/04/28: Re: XC4k parts obsolete ?
83404: 05/04/29: Re: Sync + FIFO
86107: 05/06/22: Re: Post Translate Timing
86109: 05/06/22: DC vhdl question
86252: 05/06/23: Re: DC vhdl question
Bert Molenkamp:
1494: 95/06/30: Re: aynchronous ripple counter
11691: 98/09/01: Re: Wait statements and while loops
11703: 98/09/02: Re: Wait statements and while loops
Bert THOMPSON:
4480: 96/11/04: FPGA references for beginner?
Bert Wibble:
43115: 02/05/14: Driving high speed external devices from an FPGA
43363: 02/05/20: Re: Driving high speed external devices from an FPGA
43411: 02/05/21: Re: Driving high speed external devices from an FPGA
48412: 02/10/17: Re: Standing on the shores of Stratix-land
Bert_Paris:
139443: 09/03/30: RS232, UART & Igloo nano Kit
139936: 09/04/20: Igloo nano Starter Kit
139981: 09/04/22: Re: ISE 10.1 installation troubles on windows Vista 32bit
140055: 09/04/25: Re: actel libero
140057: 09/04/26: Re: Modelsim Actel Edition and Soft FIFO Controller
140063: 09/04/27: Re: Modelsim Actel Edition and Soft FIFO Controller
140272: 09/05/07: Re: board with 2 gigabit ethernet connectors?
140273: 09/05/07: Re: board with 2 gigabit ethernet connectors?
140274: 09/05/07: Re: Environmental variables to point at libraries with Modelsim?
140429: 09/05/13: Re: cheapest FPGA?
140879: 09/05/28: Re: Cyclone3 and AT45DB serial flash
141117: 09/06/07: Re: digital RGB Video to Analog VGA triple DAC question
141118: 09/06/07: Re: Xilinx GbE performance
141956: 09/07/19: Re: FPGA to PC connection
142021: 09/07/22: Re: FPGA to PC connection
143267: 09/09/29: IP protection for FPGA users
148794: 10/08/25: New Application Note: Multiple configurations for Altera FPGAs
148799: 10/08/26: Re: New Application Note: Multiple configurations for Altera FPGAs
152379: 11/08/17: extracting D from 1 / D*D
152381: 11/08/17: Re: extracting D from 1 / D*D
152383: 11/08/17: Re: extracting D from 1 / D*D
152460: 11/08/26: Re: extracting D from 1 / D*D
berte:
136663: 08/11/29: How to write driver for xilinx spartan iie xc2s50e
136688: 08/11/30: Re: How to write driver for xilinx spartan iie xc2s50e
Berti Schueler:
153479: 12/03/08: Synchronizing Virtex-6 RocketIOs on RX path
berton:
118927: 07/05/07: DMA with ipif / user_logic
118939: 07/05/07: Re: DMA with ipif / user_logic
118952: 07/05/08: Re: DMA with ipif / user_logic
Bertram Geiger:
12581: 98/10/17: ABEL vs. VHDL
13370: 98/11/30: Re: PCB rules for Xilinx ICs
14921: 99/02/25: Re: Xilinx ABEL?
16867: 99/06/15: Re: Help with Foundation/Abel
27360: 00/11/19: Re: xilinx xc9500
29152: 01/02/08: Re: PAL/GAL 22V10 (CE) programmers?
29348: 01/02/15: Re: Programming a CPLD
29581: 01/02/27: Re: cpul vs vhdl
29752: 01/03/07: Re: Programming a CPLD
29822: 01/03/12: Re: clock divider by 1.5
30284: 01/03/31: Re: Anadigms FPAA
30496: 01/04/11: Re: help with ABEL-HDL and CPLDs
30502: 01/04/11: Re: ABEL, syntax for High impedance output
30791: 01/04/29: Re: Verilog + VHDL - and the other?
31069: 01/05/10: Re: Shannon Capacity - An Apology
33382: 01/07/25: Re: Homemade Xilinx parallel cable problem + new question
35996: 01/10/25: Re: GAL compiler
52727: 03/02/20: Re: ABEL Help!
55597: 03/05/13: Re: XC9536 - how to make my own programing device for this chip ?
57009: 03/06/20: Re: PALs, GALs and ABEL
57255: 03/06/26: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
58525: 03/07/25: Re: Should I use ABEL?
60325: 03/09/10: Re: ABEL help needed
61130: 03/09/29: Re: Counting ones
79112: 05/02/14: Re: clock division / multiplication in xilinx cpld
Bertrand:
4908: 96/12/28: Re: I2C Bus Interface in FPGAs
10174: 98/05/01: Re: Lattice 1016 Design Fit
10177: 98/05/01: Re: Lattice 1016 Design Fit
10244: 98/05/06: Re: Oooops
bertrand:
7594: 97/09/25: Re: Lattice Synario and ISPLSI1048
7731: 97/10/08: Help: ABEL program for ISPLSI1000 series.
7804: 97/10/17: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
Bertrand Rousseau:
78174: 05/01/26: Re: Another problem getting ISE 6.3i running on Linux
78175: 05/01/26: Re: trouble setting up ISE 6.3i in linux
78199: 05/01/26: Re: Another problem getting ISE 6.3i running on Linux
78879: 05/02/09: Re: Beginner: running EDK 6.3 in linux
78893: 05/02/09: Newbie: add opb_ddr to a project
78898: 05/02/09: Re: Newbie: add opb_ddr to a project
82470: 05/04/13: opb_ethernet timing constraints
96900: 06/02/13: How to decode FAR register in Virtex-4?
96963: 06/02/14: Re: How to decode FAR register in Virtex-4?
96969: 06/02/14: Re: How to decode FAR register in Virtex-4?
96970: 06/02/14: Re: How to decode FAR register in Virtex-4?
Bertrik Sikken:
60730: 03/09/20: show-ahead FIFOs
60744: 03/09/21: Re: show-ahead FIFOs
bertus:
130568: 08/03/27: zpu processor core
130574: 08/03/27: Re: Simulink(Matlab)/FPGA serial communication
Berty:
82656: 05/04/15: Re: clock input over an I/O pin
83267: 05/04/26: Re: Sync + FIFO
83315: 05/04/27: Re: Sync + FIFO
83418: 05/04/29: Re: Sync + FIFO
83440: 05/04/29: Re: Sync + FIFO
83534: 05/05/02: Re: Sync + FIFO
83535: 05/05/02: Re: Sync + FIFO
83576: 05/05/03: Re: Force sequential assigment
83584: 05/05/03: Re: Negative hold time from Quartus
83588: 05/05/03: Re: DCM, constraints and routing (Xilinx Spartan 3)
84040: 05/05/11: Re: Xilinx ISE 6.3 verilog simulation problem
84043: 05/05/11: Re: crazy behaviour of fpga, timing ?
84264: 05/05/16: Re: initializing fifo pointers to simulate overflow
84265: 05/05/16: Re: floorplanning
84277: 05/05/16: Re: SPI interface cpol & cpha
84415: 05/05/18: Re: Problems with Constraints (Xilinx, ISE 6.3)
84690: 05/05/24: Re: ethernet
84769: 05/05/26: Re: Ethernet / digital logic questions
84807: 05/05/27: Re: Ethernet / digital logic questions
84900: 05/05/31: Re: Implementing sin function in fpga
85315: 05/06/07: Re: FPGA I/O pin current sink
85541: 05/06/10: Re: Gated clock question
85894: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85903: 05/06/17: Re: Xlinix configuration: DONE pin too early?
BEST OF X:
<BestInSoC@gmail.com>:
131580: 08/04/25: Re: Breaking News ... Accellera Verification Working Group Forming
131607: 08/04/25: Re: Breaking News ... Accellera Verification Working Group Forming
BESTune:
(beta-) Frank Nitzsche:
70431: 04/06/16: XCS10-84PC: How JTAG-Pins as I/O ?
70543: 04/06/20: Newbie: Spartan XCS10
Beth Cowie:
56445: 03/06/05: Re: Convolutional Encoder IP: Problem on puncturing
betsy thibault:
27563: 00/11/28: Re: Xilinx Coolrunner going on last time buy?
<betterone11@gmail.com>:
109001: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
Betty Britten:
18031: 99/09/24: Earn free cash for only $6.00
Bevan Weiss:
44122: 02/06/12: Re: Digital FM demodulator in FPGA-continue
44145: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44171: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44445: 02/06/20: Re: 5V tolerance
45294: 02/07/19: Re: I want to buy 4 Xilinx FPGA
64220: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
65587: 04/02/03: Re: A problem about GAL26V12
65588: 04/02/03: Re: A problem about GAL26V12
65908: 04/02/10: Re: VHDL:Dividing a real number by two??
67045: 04/03/05: mersenne twister
67083: 04/03/05: Re: mersenne twister
67089: 04/03/05: Re: mersenne twister
90570: 05/10/18: Re: ADC implementation on fpga? Information and procudures wanted.
90625: 05/10/18: Re: using i2c core
90688: 05/10/19: Re: How to Reduce Interconnects (VDD and VSS)
90705: 05/10/20: Re: using i2c core
90707: 05/10/20: Re: using i2c core
90732: 05/10/20: Re: MAC Architectures
90774: 05/10/21: Re: "Cannot synthesize logic..." ERROR
90776: 05/10/21: Re: Simple PWM Spartan 3
90825: 05/10/22: Re: MAC Architectures
90991: 05/10/27: Re: MAC Architectures
91485: 05/11/08: Re: Why Spartan-3e is the best
91487: 05/11/08: Re: VHDL algorithm/code for implementing QAM on FPGA
91524: 05/11/08: Re: 8x8-bit multiply
91558: 05/11/09: Re: Why Spartan-3e is the best
91562: 05/11/09: Re: What does the IP in IPCORE stand for?
93712: 05/12/29: Re: Virtex-4 CCLK termination
98289: 06/03/09: Re: DCM question
99530: 06/03/26: Re: chip reverse engineering
99539: 06/03/27: Re: chip reverse engineering
101130: 06/04/26: Re: Async FPGA ~2GHz
<bexleynet@spamcop.net>:
77207: 04/12/29: Re: Q, connecting multiple microblazes
Beyond Feng:
28401: 01/01/11: How to do simulation on Synopsys FPGA Express
Bezamat James:
49123: 02/11/01: Re: FPGA convert to ASIC
BF:
35204: 01/09/25: WANTED source code of CPLD on TI 5402 DSK
bfeng:
61022: 03/09/26: Re: Graphics rendering
BFletch:
113: 94/08/16: Re: Field Programmable Interconnect
<bfredc@my-deja.com>:
21252: 00/03/14: Virtex IOB T register
21291: 00/03/15: Re: Virtex IOB T register
21362: 00/03/20: Re: How to eliminate high fan-out in Xilinx FPGA's?
25199: 00/08/30: Preserve_driver vs Duplicate register merge
28004: 00/12/19: Methodology
<bfroemel@gmail.com>:
118487: 07/04/27: Killed a Stratix-II Nios II Altera devkit, How to repair?
118489: 07/04/27: Re: Killed a Stratix-II Nios II Altera devkit, How to repair?
bg:
113738: 06/12/20: A nice CIC-Filter, but I can't find the result in the bitsequence!?
113779: 06/12/21: Re: A nice CIC-Filter, but I can't find the result in the bitsequence!?
bgaughan:
94033: 06/01/04: CORDIC for digital downconversion
<bgaughan@airnetcom.com>:
86861: 05/07/07: Resampling in FPGA with irrational or large rational ratios
bgeer:
6: 94/07/27: Does the iFX780 qualify for discussion here?
29: 94/07/29: Re: Does the iFX780 qualify for discussion here?
<bgelb.mit.edu@gmail.com>:
122199: 07/07/23: DDR2 w/ MIG on Xilinx ML501 Board
122462: 07/07/27: Xilinx MIG DDR2 initialization problems
122463: 07/07/27: Xilinx MIG DDR2 initialization problems
bgeorge:
9046: 98/02/17: This is a test to see if this will post!!!
9052: 98/02/17: STU02
<bgong86@gmail.com>:
134974: 08/09/08: Placing Verilog busses using Xilinx RPMs
134985: 08/09/09: Re: Placing Verilog busses using Xilinx RPMs
135022: 08/09/10: Re: Placing Verilog busses using Xilinx RPMs
bgshea:
114671: 07/01/22: Xilinx ISE 8.2
114747: 07/01/23: Re: Xilinx ISE 8.2
114759: 07/01/23: Re: Xilinx ISE 8.2
114817: 07/01/24: Re: Xilinx ISE 8.2
114827: 07/01/24: Re: Aligning data with clock
114828: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
<bgshea@gmail.com>:
92035: 05/11/20: using generated timing constraints
92036: 05/11/20: Re: using generated timing constraints
bh:
73336: 04/09/20: Re: FPGA with PCI interface for video processing?
73602: 04/09/25: Re: VxWorks and Xilinx Virtex-II Pro
73632: 04/09/27: Re: embedded linux on FPGA?
73917: 04/10/01: Re: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
74197: 04/10/06: Re: Hash algorithm for hardware?
74397: 04/10/10: Temperature considerations of inactive logic blocks
75495: 04/11/08: Personality Module (Z-Dok) proto board for ML310
75769: 04/11/14: Re: Obsolete processors resurected in FPGAs
91615: 05/11/09: Re: How do i detect ethernet frames of layer 2 using ethereal?
93492: 05/12/22: Re: Going insane - Xilinx VGA controller...
103550: 06/06/05: Re: MIL Qualified RTOS for PowerPc 405
103560: 06/06/06: FlipChip BGA Conformal Coating
103615: 06/06/06: Re: FlipChip BGA Conformal Coating
103960: 06/06/15: Re: Anyone get a Pictiva OLED to work?
104136: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
110742: 06/10/20: Re: i486 FPGA replacement
BH:
68425: 04/04/04: Re: iMPACT "Programming Failed"
68956: 04/04/23: Re: Compiling library problem in Xilinx ISE4.0?
bh.ines1806@gmail.com:
145675: 10/02/18: BRAM16 error
145695: 10/02/19: Re: BRAM16 error
Bhadri:
64531: 04/01/06: AFX BG560 board
64532: 04/01/06: Virtex and Spartan
64949: 04/01/16: Re: AFX BG560 board
Bhanu Chandra:
111054: 06/10/27: Usage of RAMB16 prmitives
111711: 06/11/08: pin name misspelling error!
115914: 07/02/25: Making a 32KB BRAM block, virtex-4
115915: 07/02/25: Making a 32KB BRAM block, virtex-4
116500: 07/03/11: Design report does not show BRAM usage
116517: 07/03/12: Re: Design report does not show BRAM usage
116520: 07/03/12: Re: Design report does not show BRAM usage
116521: 07/03/12: Re: Design report does not show BRAM usage
116522: 07/03/12: Re: Design report does not show BRAM usage
116534: 07/03/12: ISE synthesis works, XPS does not resolve symbol?
116576: 07/03/13: Re: ISE synthesis works, XPS does not resolve symbol?
117986: 07/04/15: Writing to BRAM using OPB
Bhanu Kapoor:
236: 94/09/30: PhysComp 94 -- Advance Program
333: 94/10/22: Final Call for Participation -- PhysComp 94
Bhanu Nagendra P.:
60235: 03/09/08: microblaze on XSV800
<bharadwaj.sr@gmail.com>:
112959: 06/12/02: LUT input order
113008: 06/12/04: Re: LUT input order
115211: 07/02/02: Xilinx Interconnects/Routing
Bharat Kurani:
6287: 97/05/08: Need Address/Phone/Fax List of Semiconductor Companies
6750: 97/06/23: Need Good IC Schematics to Chip Layout Engineer
bharat_in:
115197: 07/02/02: circle generation algorithm
115342: 07/02/07: Re: circle generation algorithm
124477: 07/09/24: BRAM bytewide write enable problem
bharathbhushan:
42557: 02/04/27: function usage
Bharathi:
36786: 01/11/19: Synthesis in Active-VHDL
bhaskar:
147588: 10/05/05: Floating point unit in microblaze
Bhaskar Thiagarajan:
16288: 99/05/13: Re: floating points to fixed points on a FPGA
35555: 01/10/10: Re: qpsk clock recovery
59317: 03/08/14: Off topic - Re: FPGA/DSP Expert - business partner for innovative FFT
59351: 03/08/15: Re: Off topic - Re: FPGA/DSP Expert - business partner for innovative FFT
87331: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
bhaskaran vasudev:
13827: 98/12/28: Re: smallest DCT algorithm?
13862: 98/12/29: Re: smallest DCT algorithm?
<bhaskart@my-dejanews.com>:
16028: 99/04/28: floating point converter
bhatti:
148404: 10/07/19: Virtex 4 FX12 minimodule
148552: 10/07/31: FX12 mini module with EDK 10.1
149704: 10/11/18: test peripheral example in xilinx XPS
149709: 10/11/20: Re: test peripheral example in xilinx XPS
149727: 10/11/20: Re: test peripheral example in xilinx XPS
149813: 10/11/25: tutorial on XPS ethernet MAC lite
151522: 11/04/16: ethernet core on FX12 mini module
152042: 11/06/26: digitization of sensor array
152084: 11/07/03: Re: digitization of sensor array
152087: 11/07/03: small size SDSL modem
<bhatti1127@yahoo.com>:
96960: 06/02/14: Block vs. Distributed RAMs
<bhavanireddy@gmail.com>:
112306: 06/11/19: Q on duty cycle
139294: 09/03/25: USB PHY
139298: 09/03/25: Re: USB PHY
bhb:
63566: 03/11/25: memory
65398: 04/01/27: init RAM with .rif
68808: 04/04/19: configuring multiple FPGAs with a sigle config device
123111: 07/08/16: Scilab / Matrix
123308: 07/08/23: comparison with embedded processor
125668: 07/10/31: Spartan-3E display developpement kit
126011: 07/11/12: DDR in spartan 3E
126431: 07/11/22: DDR2 dqs pin // virtex4
126448: 07/11/22: Re: DDR2 dqs pin // virtex4
126532: 07/11/27: Re: DDR2 dqs pin // virtex4
126589: 07/11/28: DDR2 controler
130613: 08/03/28: problem with uartlite in microblaze
bhkim91@yahoo.com:
86245: 05/06/23: iMPACT downloading error
Bhupesh:
30915: 01/05/03: Re: FPGA based PCI cards
30917: 01/05/03: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
30919: 01/05/03: Re: Something about the counter
bhupesh:
31237: 01/05/16: interfacing:keyboard/displays
bhupesh_rrediffmail.com:
30916: 01/05/03: Re: Exemplar: If-elsif synthesises to Muxcy in virtexE
<biancimass@gmail.com>:
133121: 08/06/18: Re: Virtex5 FPGA Board and USB interface
Biancu:
120287: 07/06/04: Mesa 5i21 Xilinx
bibico:
14981: 99/03/01: Re: JTAG HANG UP......
15089: 99/03/05: Re: Can multiple FPGA share same SPROM for configuration?
15457: 99/03/24: Re: DIY Xilinx Download Cable
15458: 99/03/24: Re: DIY Xilinx Download Cable
Bibico Cando:
19513: 99/12/28: Re: status during ISP
<bierre@sasibtlc.inet.it>:
3361: 96/05/20: Viewlogic Xilinx users
3362: 96/05/20: Pcm data management in Fpga Xilinx
Big Boy:
83791: 05/05/06: re:Xilinx Prom programming
83792: 05/05/06: Xilinx ISE 6.3 verilog simulation problem
84032: 05/05/11: re:Xilinx ISE 6.3 verilog simulation problem
84063: 05/05/11: re:Uart16550 can't receive data over 16byte a time
84097: 05/05/12: re:Xilinx ISE 6.3 verilog simulation problem
84098: 05/05/12: re:Minimum circuit to get Spartan-3 running
84161: 05/05/13: re:Uart16550 can't receive data over 16byte a time
84398: 05/05/18: re:Registers replication on Xilinx IOBs
84766: 05/05/26: re:Ethernet / digital logic questions
84876: 05/05/31: Problem with Synplify 7.7.1, startup block vs clock input
84906: 05/05/31: re:Problem with Synplify 7.7.1, startup block vs clock input
85033: 05/06/03: re:Spartan 3 ata interface
85083: 05/06/03: re:some mistakes with EDK7.1i
85084: 05/06/03: re:XP for NIOS2
85287: 05/06/07: ISE/EDK 6.3 vs 7.1...
85468: 05/06/09: re:ISE/EDK 6.3 vs 7.1...
86218: 05/06/23: re:ISE 7.1 - block memory init value issue during simulation
87125: 05/07/15: re:Reading a PS/2 mouse
87212: 05/07/19: re:Virtex-4 5V tolerance
Big Swede:
46304: 02/08/25: Floorplanning 101
=?Big5?B?sU23fr7Ht3ytXrDqpGq+xw==?=:
=?Big5?B?uOqwVLresnqxTbd+qPO3fA==?=:
<big_in_russia@yahoo.com>:
80139: 05/03/01: Re: Resetting Virtex II BlockRAM
80141: 05/03/01: Re: OT: funny idea
80142: 05/03/01: Re: SoC positions in Bangalore
81391: 05/03/22: Re: Xilinx ISE 7.1 - Can this get any worse?
Bigboss:
36260: 01/11/04: Help on which FPGA development boards ?
bigboss25@laposte.net:
123968: 07/09/08: Re: [Nios II] How does the PIO Core generate a interrupt?
<bigcaboy@gmail.com>:
140376: 09/05/11: DSP + FPGA reference design?
140396: 09/05/12: Re: DSP + FPGA reference design?
140448: 09/05/13: FPGA/DSP system design problem
<BigJamesLau@gmail.com>:
128499: 08/01/28: regarding DMA memory to memory copy in NIOS II
128525: 08/01/29: Re: regarding DMA memory to memory copy in NIOS II
BigSlamu:
36723: 01/11/17: Webpack and gate synthesis
BigWorm:
102434: 06/05/16: Xilinx or Altera...
bigyellow:
129210: 08/02/18: TCL testcase in Modelsim.
129213: 08/02/18: Re: TCL testcase in Modelsim.
bijesh v.m.:
58252: 03/07/18: External crystal oscillator for Spartan IIE
58331: 03/07/20: Re: External crystal oscillator for Spartan IIE
58333: 03/07/21: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
58375: 03/07/21: Re: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
58417: 03/07/22: Re: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
bijoy:
71741: 04/07/29: Re: vhdl code : altera vs xilinx
84969: 05/06/01: Clock Generation : FPGA
84977: 05/06/02: Re: Clock Generation : FPGA
84978: 05/06/02: FPGA : Coregenerator Adaptive FIR Filter
85032: 05/06/03: Re: Clock Generation : FPGA
85101: 05/06/04: FPGA : MAC FIR doubt--HELP ME PLEASE
85246: 05/06/07: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
85481: 05/06/09: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
85632: 05/06/12: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
86219: 05/06/23: FPGA :FFT Core in Xilinx
86489: 05/06/28: Re: FPGA :FFT Core in Xilinx
89856: 05/09/28: FPGA : Decimation Filter
89926: 05/09/30: Re: FPGA : Decimation Filter
90299: 05/10/09: Re: FPGA behaviour when its used resource is >90% ?
90478: 05/10/14: FPGA : PCI core needed
90507: 05/10/14: Re: FPGA : PCI core needed
90849: 05/10/22: Re: Spartn 3 configuration failure
91238: 05/11/02: FPGA : PCI-CORE
91240: 05/11/02: Re: FPGA : PCI-CORE
92599: 05/12/02: FPGA : Decimation Filter Implementation
92856: 05/12/07: Re: FPGA : Decimation Filter Implementation
92900: 05/12/08: Re: Job available... 2 projects
92902: 05/12/08: FPGA : MAP slice logic into BLOCK RAM
92911: 05/12/09: Re: FPGA : MAP slice logic into BLOCK RAM
93010: 05/12/11: Re: FPGA : MAP slice logic into BLOCK RAM
97744: 06/02/27: FPGA: Model-SIm XE problem
99350: 06/03/23: FPGA : Spartan-3e configuration failure
99417: 06/03/23: Re: FPGA : Spartan-3e configuration failure
99425: 06/03/23: Re: FPGA : Spartan-3e configuration failure
99427: 06/03/24: FPGA : HSWAP
100533: 06/04/11: FPGA : Chip-scope + spartan-3e
102958: 06/05/23: FPGA : P&R problem - Help !
102959: 06/05/23: FPGA : Constraint for BRAM placements
103139: 06/05/25: FPGA : FFT
105218: 06/07/18: Re: problem in simulating FFT core on ISE 7.1
105797: 06/07/31: FPGA : BUG in ISE- View RTL Schematics ?
105800: 06/08/01: Re: S3E USB2.0 port
106046: 06/08/06: FPGA : PCI-Xilinx Core, PC not booting
106120: 06/08/07: Re: FPGA : PCI-Xilinx Core, PC not booting
108686: 06/09/15: Re: FFT IP CORE: XFFTV2.0
108893: 06/09/18: FPGA : Open core FFT
109030: 06/09/20: Re: FPGA : Open core FFT
111632: 06/11/07: Re: FFT help
112917: 06/12/01: Re: wanted: FPGA programmer
112979: 06/12/03: Re: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
113201: 06/12/07: FPGA : LIFO
113403: 06/12/12: FPGA : Async FIFO, Programmable full
115311: 07/02/07: Re: Xilinx Virtex5 board
119156: 07/05/14: Re: Xilinx LogiCore FFT 3.2
123115: 07/08/16: FPGA :'define not allowed in ISE ?
Biju Nair:
3356: 96/05/18: Introduction to FPGAs
Bik:
151849: 11/05/24: Re: Problem with Xilinx 10.1 PowerPC simulator
151850: 11/05/24: Re: Problem with Xilinx 10.1 PowerPC simulator
152760: 11/10/19: Re: USB hangs on the Xilinx USB II Cable
<biker@wavenet.at>:
126061: 07/11/13: Chipscope Server for PowerPC?
127999: 08/01/12: BRAM Readback
128125: 08/01/16: V5-SYSMON : MAX6043 suitable?
128143: 08/01/16: Re: V5-SYSMON : MAX6043 suitable?
Bill:
11024: 98/07/12: $EARN MONEY FOR FREE$
14668: 99/02/10: Re: Board for XC4085XL
14944: 99/02/26: Xilinx 9500XL
15786: 99/04/14: Re: One hot comes up cold
16844: 99/06/14: Re: Virtex Boards
16942: 99/06/18: Re: Virtex Boards
17099: 99/06/30: Re: Virtex JTAG readback
44829: 02/07/02: Virtex II - Assigning Pins before routing?
44884: 02/07/04: Virtex II - IO TILE, IOB PAD #4
45081: 02/07/11: Virtex II - What to do with unused banks?
45200: 02/07/15: Virtex 2 (XC2V500) Engineering Sample Errata Sheet
45354: 02/07/20: Re: Virtex-II variable vs fixed DCM phase-shift ?
45973: 02/08/13: Hardware Software partition in FPGAs
51738: 03/01/20: fpga accelerated architectures
57592: 03/07/02: Re: Looking for DIMM format FPGA board
57700: 03/07/03: Re: Looking for DIMM format FPGA board
69106: 04/04/27: Re: Design PAR in Stratix
90061: 05/10/04: Avoiding meta stability?
90186: 05/10/06: Re: Avoiding meta stability?
90242: 05/10/07: Re: Avoiding meta stability?
90243: 05/10/07: Re: Avoiding meta stability?
90296: 05/10/09: Re: Avoiding meta stability?
90334: 05/10/10: Eliminates meta stability (yes or no)?
90338: 05/10/10: Re: Eliminates meta stability (yes or no)?
90339: 05/10/10: Re: Eliminates meta stability (yes or no)?
114823: 07/01/24: Aligning data with clock
114837: 07/01/24: Re: Aligning data with clock
114866: 07/01/25: Re: Aligning data with clock
115029: 07/01/29: Linux on Virtex 4?
115035: 07/01/29: Re: Linux on Virtex 4?
153182: 12/01/04: Beginner question on FIFO in "FPGA prototyping by VHDL examples"
bill:
30291: 01/03/31: Student Foundation 1.5
54248: 03/04/05: Confused at Xilinx V2P OCM usage
66916: 04/02/29: What's the rule of instantiating the global buffer
73975: 04/10/01: xilina altera competing history
93848: 06/01/02: Start up condition of flip flops in FPGA?
135932: 08/10/22: problem about an interface between sfifo and sopc avalon MM slave
Bill Austin:
71568: 04/07/22: Looking for ways to keep diagnostic signal from being optimized out (Xilinx)
71601: 04/07/23: Re: Looking for ways to keep diagnostic signal from being optimized out (Xilinx)
Bill Balabanos:
16853: 99/06/14: FPGA Express 3.00
Bill Banzhof:
1606: 95/07/26: Re: Lattice:pds+/Viewlogic Comments please
1919: 95/09/20: Re: Fast FPGA's?
Bill Bishop:
2692: 96/01/24: Re: Multipliers? How many different arch?
18443: 99/10/24: Questions About the Altera PCIT1 Core
46619: 02/09/04: ARC-PCI Board
Bill Blyth:
17719: 99/08/27: Re: Virtex dev boards
17753: 99/08/31: Re: Virtex LPCILOGIC site??
17901: 99/09/16: Re: Xilinx on PMC?
17924: 99/09/17: Re: Xilinx development board > XVC400
19041: 99/11/25: Re: Programming Virtex device via JTAG
19063: 99/11/26: Re: Programming Virtex device via JTAG
19361: 99/12/16: Re: Virtex boards
22136: 00/04/26: Re: Xilinx Virtex problem (schematic)
23892: 00/07/14: Re: Init time of Xilinx Virtex / Spartan II
23902: 00/07/14: Re: Init time of Xilinx Virtex / Spartan II
25023: 00/08/24: Re: Virtex partial reconfiguration feature (?)
25568: 00/09/14: Re: Xilinx and CD databooks (rant)
25521: 00/09/13: Re: virtex shape
28850: 01/01/26: Re: Advice on FPGA board.
30945: 01/05/04: Re: CompactPCI card with Virtex
38916: 02/01/28: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
49983: 02/11/27: Re: Anybody know of vendors of PCI boards with FPGAs?
50130: 02/12/03: Re: question about PCB traces for FPGA board... ?
50143: 02/12/03: Re: question about PCB traces for FPGA board... ?
50145: 02/12/03: Re: question about PCB traces for FPGA board... ?
Bill Brown:
9587: 98/03/25: Re: Cypress ISR
Bill Burris:
112847: 06/11/29: SPI Flash on Avnet Spartan 3E Eval Kit
112937: 06/12/01: Re: SPI Flash on Avnet Spartan 3E Eval Kit
113126: 06/12/06: How to find an FPGA board
113359: 06/12/11: Re: SPI Flash on Avnet Spartan 3E Eval Kit
113360: 06/12/11: Re: How to find an FPGA board
114594: 07/01/19: Re: SPI Flash on Avnet Spartan 3E Eval Kit
Bill Campbell:
18399: 99/10/22: NT users wanted for £625 + palm pilot
Bill Carter:
8696: 98/01/20: this is a test
Bill Clark:
2380: 95/11/26: Re: XBLOX: the good, the bad and the shocking
2399: 95/11/28: Re: XBLOX vs. "CNets", lfsr dividers, etc.
2496: 95/12/18: Re: Floor Planning for Xilinx
2529: 95/12/27: Re: [q][Reverse Engineering Protection]
2528: 95/12/27: Re: [q][Reverse Engineering Protection]
2843: 96/02/15: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
16030: 99/04/28: (nullmsg) FS: Xilinx Alliance tools
Bill Cox:
1457: 95/06/25: Re: Low cost ISA board
1842: 95/09/08: Can someone send me '96 FPGA call for papers?
1887: 95/09/15: Re: Fast FPGA's from 3100?
2698: 96/01/25: Re: XILINX XACT 6.0.0 Tools flaky
77372: 05/01/05: Tracking down HardWired History
Bill Davy:
92404: 05/11/29: Re: Cypress FX2 bandwidth problem
93978: 06/01/04: Re: RTL for Z8000 series CPU?
108259: 06/09/07: Re: Please help me with (insert task here)
124030: 07/09/11: Re: Uses of Gray code in digital design
Bill Dennen:
7645: 97/09/30: Re: vme vs compact pci
Bill Diehls:
45915: 02/08/10: Fun FPGA system
59477: 03/08/20: performance tweaking FPGA designs
Bill Ewing:
7213: 97/08/15: Re: Price of Serial EEPROM is Outrageous
7260: 97/08/19: Re: 89c2051 Price & Capability (was Ourtageous Serial EEPROM $$)
7248: 97/08/18: Re: Price of Serial EEPROM is Outrageous
7401: 97/09/07: Re: Joseph Allen's Ubiquitous tagline (was, in this case Re: Which FPGA ?)
7402: 97/09/07: Re: Xilinx XACT for sale
8012: 97/11/06: Re: I Need help on Lattice's Synario download
Bill Flannery:
23054: 00/06/11: Re: Fast Fourier Transform Processors
Bill Garber:
149229: 10/10/10: Re: Spartan-6 Boards
150385: 11/01/14: Re: Verilog Book for VHDL Users
150736: 11/02/07: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150744: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150745: 11/02/08: Re: Power consumption of Spartan-3A XC3SD1800A
Bill Gates:
16697: 99/06/03: Re: FPGA Introduction is needed, right?
16699: 99/06/03: Re: XILINX/ALTERA compatibility
16703: 99/06/03: Re: Fixed delay in FSM
16701: 99/06/03: Re: The Industry's Largest Independent Information Source of FPGAs and CPLDs (www.optimagic.com)
16832: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
16833: 99/06/11: Re: XILINX/ALTERA compatibility
Bill Giovino:
34768: 01/09/07: New Website: EmbeddedSystems.org
93092: 05/12/13: Future of Microchip Development Tools?
93096: 05/12/13: Re: Future of Microchip Development Tools?
Bill Groves:
18721: 99/11/09: Re: Sample Rate Conversion.
Bill Hanna:
54761: 03/04/17: Boycott All Xilinx products untill they correct all ISE software errors
54811: 03/04/18: Re: Boycott All Xilinx products untill they correct all ISE software errors
54850: 03/04/20: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55249: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE software errors
55563: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
56287: 03/06/02: Re: Need help with Xilinx ISE
56310: 03/06/02: Re: Virtex 2 evaluation board
56614: 03/06/10: Re: Where can i buy virtex II ?
56804: 03/06/16: Re: Xilinx Mapping Problem
57278: 03/06/26: Re: Webpack 5.2i can't synthesize
57437: 03/06/30: Re: SPARTAN-3 vs. VIRTEX-II
58448: 03/07/23: Re: workstation for virtex2 - 8000
62036: 03/10/17: Re: ISE 6.1 Dies Out of the Gate
62554: 03/10/31: Re: ISE5.2 to ISE6.1
64278: 03/12/23: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
72226: 04/08/11: Request for 28 BIT ADDER maximum clock rates for Vertex II FPGAs
75073: 04/10/25: Re: unstable fpga design
75366: 04/11/03: Re: unstable fpga design
Bill Harris:
5521: 97/02/22: Re: Xilinx or Altera?
5522: 97/02/22: Re: Xilinx or Altera?
5529: 97/02/22: Re: replicating structure in MaxPlus
5532: 97/02/22: Re: Xilinx or Altera?
5603: 97/02/28: Re: Xilinx or Altera?
Bill Hull:
738: 95/02/20: Re: PLA? PAL? PLD? GAL?
Bill Kury:
16341: 99/05/17: 4062XL problems and solutions
16405: 99/05/20: Re: Case study: Viewlogic's IntelliFlow
20714: 00/02/18: Advanced Digital Design book
Bill Lenihan:
7706: 97/10/06: Xilinx xc9500 JTAG programming.
8078: 97/11/15: Re: Looking for dynamically reprogrammable FPGA's
8327: 97/12/08: Re: Integration between Xilinx & Synopsys
8328: 97/12/08: PCs vs. workstations
8435: 97/12/14: Re: combinational multipliers
23605: 00/07/02: BIST in FPGAs?
23797: 00/07/10: JTAG headers
23998: 00/07/20: Re: Warning! -- SONY SUBSTANDARD SERVICE
24450: 00/08/09: Virtex I/O going off-board.
24451: 00/08/09: CLKDLL for Virtex PCI?
25221: 00/08/31: Synopsys Synthesis
25675: 00/09/17: Re: virtex shape
26003: 00/09/30: Re: FPGA Express Strikes Again!
26005: 00/09/30: Re: FPGA compiler abort 219
26006: 00/09/30: Re: Pack I/O Reg/Latches into IOBs
26007: 00/09/30: Re: Synopsys FPGA Compiler II on Solaris
26752: 00/10/27: Re: Xilinx configuration: JTAG and SPROM
26753: 00/10/27: Re: Leonardo vs. FPGA Compiler 2
27534: 00/11/28: Virtex ROM ques.
28357: 01/01/10: grey code counters
28460: 01/01/13: Re: grey code counters
28681: 01/01/20: Re: About programming cables
28682: 01/01/20: Re: Synplicity newsgroup?
Bill Lye:
950: 95/04/01: Transfering Viewlogic/XC4000 designs Sun->PC
Bill Mangione-Smith:
1197: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
2184: 95/10/27: Re: Xilinx Configuration Memory Hacking
2855: 96/02/17: Re: New Reconfigurable Computing Threads.
2834: 96/02/14: Re: ARM-based ASICs
2881: 96/02/23: Re: Java and reconfigurable computing
2943: 96/03/04: Re: Languages for reconfigurable computing.
2953: 96/03/05: Re: Comp.Arch.FPGA
2974: 96/03/07: Re: Query re Xilink PCI Interface in XC3164A - App note
4587: 96/11/18: Re: Async with FPGA?
bill manzarek:
8502: 97/12/28: Xilinx XACT 2.10 memory error
8505: 97/12/29: Re: Xilinx XACT 2.10 memory error
8513: 97/12/30: Re: Xilinx XACT 2.10 memory error
Bill Martin:
96508: 06/02/05: Re: Protected power calculation spread sheets
Bill McCulley:
89801: 05/09/26: Re: MAPLD 2005 Postings On-line
Bill McDermith:
35291: 01/09/27: Re: sensitivity list
Bill Mengelson:
1361: 95/06/06: http://www.xilinx.com/Tech_support.html
Bill Moffitt:
14398: 99/01/28: Re: Off topic DRAM/SIMM question....
14965: 99/02/28: MAXPlus Muti-chain JTAG problem
15390: 99/03/22: FLEX 10K question
bill morris:
17289: 99/07/19: Frequency Multiplier in XC4000
17290: 99/07/19: Frequency multiplier in XC4000
17291: 99/07/19: Frequency multiplier in XC4000
Bill Moyer:
42696: 02/04/30: Re: Altera Nios - ptf documentation
42697: 02/04/30: Re: Altera Nios - master/slave peripheral
42725: 02/05/01: Re: Newbie--Where to start learning?
Bill Ngo:
132838: 08/06/08: Deskew Clock on Synchronous Bus
132884: 08/06/09: Re: Deskew Clock on Synchronous Bus
Bill Nowicky:
34994: 01/09/17: Re: Innoveda and ISE Alliance 4.1i ?
Bill Orner:
9964: 98/04/17: Re: Version Control for schematics?
Bill Pringlemeir:
13000: 98/11/10: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
16177: 99/05/07: Re: BGA Prototyping ?
25510: 00/09/13: Re: hardware compatibility and patent infringement
Bill Seiler:
2656: 96/01/20: Re: good interview questions ?
4185: 96/09/23: Source for FPGA and PCI prototype board ???
4264: 96/10/07: Re: Partition tool for FPGAs?
5975: 97/04/01: New Technology
6387: 97/05/20: Gatefield ???
7904: 97/10/28: Info on Gatefield ???
9718: 98/04/01: New Technology !!!!
9930: 98/04/14: Re: Synplicity
10144: 98/04/29: Re: High Speed FPGAs??
10262: 98/05/08: Re: Xilinx Routing Delay
12445: 98/10/12: Re: Digital Sine Generator
12446: 98/10/12: Re: Processor Cores
12460: 98/10/12: DES in FPGA
12954: 98/11/06: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
Bill Sloman:
6218: 97/04/29: Low power PLD?
6336: 97/05/16: Re: Low power PLD?
6429: 97/05/23: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
6432: 97/05/23: Re: Low power PLD?
6813: 97/06/30: Re: fast scopes: how?
6862: 97/07/03: Re: fast scopes: how?
45227: 02/07/17: Re: LVDS interface cable recommendation sought
45267: 02/07/17: Re: LVDS interface cable recommendation sought
45292: 02/07/18: Re: LVDS interface cable recommendation sought
45540: 02/07/25: Re: LVDS interface cable recommendation sought
50720: 02/12/18: A/D converter in FPGA
50757: 02/12/18: Re: A/D converter in FPGA
50774: 02/12/19: Re: A/D converter in FPGA
50819: 02/12/20: Re: A/D converter in FPGA
64412: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
153196: 12/01/06: Re: voltage drop on STRATIX FPGA supply planes
155004: 13/03/26: What a Xilinx fpga could do in 1988
155009: 13/03/27: Re: What a Xilinx fpga could do in 1988
155014: 13/03/28: Re: What a Xilinx fpga could do in 1988
Bill sloman:
14330: 99/01/26: Re: Hysteresis on PLD Clock Inputs
bill smith:
7379: 97/09/04: Re: daisy-chained bitstreams
Bill Smith:
62899: 03/11/10: "clean" or "unprotected" versions of AHDL2X, SYNTHX from Xilinx (ABL2XNF sub tools)
bill turner:
87510: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Bill Turnip:
48856: 02/10/25: Re: Please recommend a FPGA chip!
48932: 02/10/27: Xilinx FPGA <> CPLD implementation "mis-match"
48972: 02/10/28: Re: Xilinx FPGA <> CPLD implementation "mis-match"
49006: 02/10/29: Re: Xilinx FPGA <> CPLD implementation "mis-match"
49116: 02/11/01: Re: Xilinx FPGA <> CPLD implementation "mis-match"
49118: 02/11/01: Re: Xilinx FPGA <> CPLD implementation "mis-match"
49119: 02/11/01: Re: Modelsim help
49298: 02/11/08: Re: ISE web pack multiplier CORE
50096: 02/12/02: Re: WARNING:Xst:646 - Signal <vcc> is assigned but never used ? (ISE 4.2wp2)
50120: 02/12/03: Re: Modelsim:Too few port connections
52189: 03/02/04: What's the difference: WebPack 5.1 vs. Xilinx Student Edition 4.2i ?
52347: 03/02/07: Re: debounce circuit
54246: 03/04/05: Re: Question about Xilinx Classes
Bill Valores:
146821: 10/03/29: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146849: 10/03/30: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146859: 10/03/30: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146893: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
153543: 12/03/27: FPGA communication with a PC (Windows)
153547: 12/03/27: Re: FPGA communication with a PC (Windows)
153554: 12/03/27: Re: FPGA communication with a PC (Windows)
153555: 12/03/27: Re: FPGA communication with a PC (Windows)
Bill Warner:
10459: 98/05/19: Re: XC5200s and Foundation 1.4
11546: 98/08/22: Re: half full flag in a xilinx async fifo?
12899: 98/11/04: Re: Q: fifo flags
Bill Wilkie:
3770: 96/07/29: Re: What about the XC6200 ?
5448: 97/02/17: Re: XC6200 config resources
26083: 00/10/03: Re: FEC in FPGAs?
Bill Williams:
22445: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
Bill Y.-C. Su:
27331: 00/11/17: Xilinx Virtex-E : Interface to Parallel Port...
<bill.sloman@gmail.com>:
155017: 13/03/28: Re: What a Xilinx fpga could do in 1988
<bill.sloman@ieee.org>:
95003: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95156: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95157: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95158: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95159: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95160: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95278: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95279: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95290: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95291: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95293: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95294: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95307: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95366: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95368: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95395: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95398: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95400: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95572: 06/01/24: Re: OT:Shooting Ourselves in the Foot
99656: 06/03/27: Re: deglitching a clock
99686: 06/03/28: Re: deglitching a clock
99735: 06/03/28: Re: deglitching a clock
99775: 06/03/29: Re: deglitching a clock
99850: 06/03/30: Re: deglitching a clock
99899: 06/03/30: Re: deglitching a clock
104956: 06/07/10: Re: High-speed DAC/ADC with FPGA
104969: 06/07/11: Re: High-speed DAC/ADC with FPGA
107654: 06/08/30: Re: Performance Appraisals
107670: 06/08/30: Re: Performance Appraisals
107778: 06/09/01: Re: Performance Appraisals
107887: 06/09/01: Re: Performance Appraisals
107902: 06/09/01: Re: Performance Appraisals
126190: 07/11/16: Re: jitter-sensitive multi-output clk distribution for
<bill@viasic.com>:
77497: 05/01/08: Re: Tracking down HardWired History
77799: 05/01/17: Re: Tracking down HardWired History
Billaltfae:
1232: 95/05/19: Re: FLEXlogic opinions?
1233: 95/05/19: Re: PLDShell Plus
1249: 95/05/22: Re: Searching >Programmable Logic - News and View<
1251: 95/05/22: Re: Is anybody using FPGA's to do PCI interfaces?
1270: 95/05/24: Re: Is anybody using FPGA's to do PCI interfaces?
1273: 95/05/24: Re: FLEXlogic opinions?
<billaud@labri.u-bordeaux.fr>:
80185: 05/03/02: Re: publishing IP
84988: 05/06/02: Re: JTAG Programming Problem
<billh40@aol.com>:
85536: 05/06/10: Re: computer upgrade time.
99838: 06/03/29: Re: Cyclone II EP2C70 dev kits, where are they?
billu:
98924: 06/03/17: Getting started w/ Aurora Core
99969: 06/03/31: Testing sample Aurora design on ML321 board
100394: 06/04/07: Re: Testing sample Aurora design on ML321 board
100551: 06/04/11: Re: Testing sample Aurora design on ML321 board
100810: 06/04/18: Re: Testing sample Aurora design on ML321 board
101247: 06/04/27: Assigning MGT's in sample Aurora Design
103298: 06/05/30: Aurora sample design: Testing/Eye Diagrams
103423: 06/06/01: Re: Aurora sample design: Testing/Eye Diagrams
104749: 06/07/05: High Speed Serial MGTs using Aurora IP
105545: 06/07/25: Issues w/ 8 lane Aurora sample design
105641: 06/07/27: Re: Issues w/ 8 lane Aurora sample design
105721: 06/07/29: Re: Issues w/ 8 lane Aurora sample design
105844: 06/08/01: Re: Issues w/ 8 lane Aurora sample design
115020: 07/01/29: USB 2.0 Streaming using FPGAs
115030: 07/01/29: Re: USB 2.0 Streaming using FPGAs
115049: 07/01/29: Re: USB 2.0 Streaming using FPGAs
115077: 07/01/30: Re: USB 2.0 Streaming using FPGAs
<billwang05@gmail.com>:
118533: 07/04/29: Re: debounce state diagram FSM
118558: 07/04/29: Re: debounce state diagram FSM
Billy Bagshaw:
8622: 98/01/14: Jam - Anyone using it ?
9985: 98/04/21: Compression for 10K20
Billy J. Beckworth:
464: 94/11/25: Re: Should I jump to Actel when using Synopsys/Altera?
Billy Taj:
154074: 12/07/30: manual interconnect changes
154098: 12/08/06: Re: manual interconnect changes
Bin Fang:
8663: 98/01/18: VGA controller model needed
14488: 99/02/01: SPWM model needed
<bin.arthur@gmail.com>:
130300: 08/03/19: Linux 2.6 PCI Device Driver on Virtex 4
130632: 08/03/28: Re: Linux 2.6 PCI Device Driver on Virtex 4
Binary:
93046: 05/12/12: Which decides my design's max frequency?
93572: 05/12/24: Where to find the Altera Schematic
93600: 05/12/26: IEEE package VHDL reference manual
93658: 05/12/27: Can Altera Cyclone device's clock input directly used as CLK with PLL?
93823: 05/12/31: Re: basic DSP with FPGA
binaryboy:
102134: 06/05/10: reverse engineering ?
Binay:
71553: 04/07/21: Xilinx clock net skew vs. MAXSKEW
Bingfeng Mei:
21285: 00/03/15: About atmel's FPGA and JBit
21310: 00/03/16: Re: SystemC vs. VHDL
21315: 00/03/16: Re: Xilinx 6200 devices?
21878: 00/04/05: Area ratio between routing resource and logic block
<bingoeugene@my-deja.com>:
22877: 00/05/29: Altera FPGA downloader/programmer 1.8 - 5.5 V
24465: 00/08/10: Replacement for Altera ByteBlaster & ByteBlasterMV
binupr:
147506: 10/04/29: Virtex5 Aurora
147707: 10/05/18: Basics on Xilinx Auroroa Core
bioradio:
112996: 06/12/04: coherent logic
biot:
89329: 05/09/12: FFT implementation in Xilinx's Spartan 3
89347: 05/09/13: Re: FFT implementation in Xilinx's Spartan 3
89391: 05/09/14: FFT implementation in Xilinx Spartan 3 started kit
89411: 05/09/14: Re: FFT implementation in Xilinx Spartan 3 started kit
89437: 05/09/14: Re: FFT implementation in Xilinx Spartan 3 started kit
bir:
112603: 06/11/25: Re: What's Nonpipelined bus mean?
Birger:
113326: 06/12/11: Re: Coregen GMII embedded ethernet MAC
<birla.manish@gmail.com>:
116378: 07/03/07: Re: Where do I find CMOS image sensors and lenses?
116379: 07/03/07: Re: Where do I find CMOS image sensors and lenses?
116381: 07/03/07: Re: No Clock in ChipScope Pro Analyzer
116572: 07/03/13: Re: ddr sdram controller
bish:
126978: 07/12/07: selecting FPGA
130158: 08/03/17: total cost for virtex II pro FPGA
130208: 08/03/17: Re: total cost for virtex II pro FPGA
130422: 08/03/23: Re: total cost for virtex II pro FPGA
130436: 08/03/24: Re: total cost for virtex II pro FPGA
130476: 08/03/25: Re: total cost for virtex II pro FPGA
132400: 08/05/26: using EXP connector of Spartan 3a board
132523: 08/05/29: Re: using EXP connector of Spartan 3a board
136357: 08/11/12: platform cable usb II problem
136395: 08/11/14: Re: platform cable usb II problem
136416: 08/11/15: Re: platform cable usb II problem
136417: 08/11/15: Re: platform cable usb II problem
136603: 08/11/24: timer interrupt problem: microblaze
136608: 08/11/25: Re: timer interrupt problem: microblaze
136615: 08/11/25: Re: timer interrupt problem: microblaze
136616: 08/11/25: Re: timer interrupt problem: microblaze
136640: 08/11/27: Re: timer interrupt problem: microblaze
136641: 08/11/27: Re: timer interrupt problem: microblaze
136651: 08/11/28: Re: timer interrupt problem: microblaze
136681: 08/11/30: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
136723: 08/12/03: Re: simulation results is correct but synthesis result is not correct
136970: 08/12/16: Re: i2c interface
137193: 08/12/31: error in synthesizing in ise although correct behavioral simulation
137200: 09/01/01: Re: error in synthesizing in ise although correct behavioral
137210: 09/01/02: Re: error in synthesizing in ise although correct behavioral
137313: 09/01/08: Re: beginner synthesize question - my debounce process won't
138750: 09/03/08: Xst:1710 warning problem
138801: 09/03/11: Re: synchronization problem
138820: 09/03/11: Re: synchronization problem
140498: 09/05/15: Re: FPGA/DSP system design problem
140735: 09/05/23: Re: please recommend a soft processor for small image processing
141900: 09/07/16: Re: parallel processing
142276: 09/08/01: Re: Implementing VHDL code in an embedded processor design and
bishopg:
142076: 09/07/23: mpmc kills plb bus on v4fx20
142249: 09/07/30: Re: mpmc kills plb bus on v4fx20
<bishopg12@gmail.com>:
131797: 08/05/02: xilinx remote platform flash program
134291: 08/08/04: RGMII with Xilinx ML405 Board
Biswajit Mishra:
98136: 06/03/06: How to interface ASIC on a PCB and and an FPGA
Biswarup:
141061: 09/06/04: ACTEL 8051s core
141178: 09/06/10: Actel HAL
Bit Farmer:
138988: 09/03/17: Re: Zero operand CPUs
<bit_head>:
12020: 98/09/24: IrDA infrared software protocol stack
12125: 98/09/30: IrDA (infrared) software protocol stack for Embedded systems
Bitan Mallik:
160279: 17/10/18: Request for an example in Verilog
<bitsbytesandbugs@googlemail.com>:
115687: 07/02/16: Where to start???
115735: 07/02/18: Re: Where to start???
Bitter Spock:
32352: 01/06/24: Re: LFSR Taps for 64 bit registers?
bizarrefish:
145722: 10/02/20: Quartus II IDE freezing on Arch 64
145730: 10/02/21: Re: Quartus II IDE freezing on Arch 64
<bjentz@altera.com>:
82975: 05/04/20: Re: Cost of Altera DSP Builder
Bjoern Wesen:
7452: 97/09/11: Cheap (sub $10) hardwired FPGA? Which manufacturers?
7545: 97/09/21: Re: Hacking bitstream formats
7547: 97/09/21: Re: Hacking bitstream formats
<bjong@my-dejanews.com>:
13310: 98/11/25: PCI for Xilinx Virtex
14913: 99/02/25: Re: Batch compliation using Altera maxplus2?
Bjorn B. Larsen:
707: 95/02/13: Re: Low cost Boundary Scan?
Bjorn Sihlbom:
7257: 97/08/19: FPGA prototyping board
<bjorn_lindegren@my-deja.com>:
20441: 00/02/10: Xilinx error message
20442: 00/02/10: Xilinx error message
20787: 00/02/22: CPLD communication->LabVIEW
21898: 00/04/06: Spartan on chip oscillator
28489: 01/01/15: Spartan programming error
28607: 01/01/18: DSP->FPGA development board
28608: 01/01/18: Development board, DSP->FPGA
BJP:
69127: 04/04/27: Error in SoPC Builder
bjrosen:
28355: 01/01/09: Hdlmaker Updated
28356: 01/01/10: Re: Alliance for Linux
28388: 01/01/11: Re: Alliance for Linux
28402: 01/01/11: Re: How to do simulation on Synopsys FPGA Express
28427: 01/01/12: Re: Alliance for Linux
28465: 01/01/14: Re: I wanna Model Sim cracked
28696: 01/01/21: HDLmaker users guide updated
<bjskill@rocketmail.com>:
87098: 05/07/14: NIOS II + USB 2.0 host
87124: 05/07/15: Re: NIOS II + USB 2.0 host
87147: 05/07/17: Re: NIOS II + USB 2.0 host
88518: 05/08/21: Sharing SDRAM on Stratix II DSP Development kit
bjzhangwn:
93385: 05/12/21: Is there anyboay work on the subject with the embeded system in the fpga?
93391: 05/12/21: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93394: 05/12/21: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93398: 05/12/21: Can anyone have the evaluation board from xilinx and altera?
93432: 05/12/21: call for paper,expresscard specification
93495: 05/12/22: microblaze & nios
93496: 05/12/22: Is there anybody that have ported the linux to the nios or microblaze?
93537: 05/12/23: Re: Is there anybody that have ported the linux to the nios or microblaze?
93544: 05/12/23: Can somone work on the pci express project?
93571: 05/12/24: Re: Can somone work on the pci express project?
93579: 05/12/25: Re: Where to find the Altera Schematic
93580: 05/12/25: Is the microblaze or nios2 free?
93776: 05/12/30: call for papers,Expresscard specification?
93778: 05/12/30: Can some give me some advice?
93779: 05/12/30: Re: call for papers,Expresscard specification?
93904: 06/01/03: Re: FPGA running diff with simulation
94044: 06/01/04: How can i get the hex file
94192: 06/01/06: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94277: 06/01/09: tcam implemented in fpga
94342: 06/01/10: Re: tcam implemented in fpga
94679: 06/01/16: ATA controller in fpga
94844: 06/01/18: where to find the bfm files?
95048: 06/01/20: Is there someone have the ata controller?
96500: 06/02/04: Re: ATA controller in fpga
96577: 06/02/06: Re: ATA controller in fpga
96580: 06/02/06: Re: ATA controller in fpga
98086: 06/03/04: The IDE interface
98288: 06/03/08: Re: The IDE interface
98310: 06/03/08: Re: The IDE interface
98771: 06/03/16: Re: The IDE interface
100143: 06/04/04: about the low power design
100181: 06/04/04: Re: about the low power design
100467: 06/04/10: Re: about the low power design
100468: 06/04/10: Re: How to handle the high fanout
100474: 06/04/10: Re: unused pins
100850: 06/04/19: clock mux in spartan2e fpga
100886: 06/04/20: Re: clock mux in spartan2e fpga
101137: 06/04/26: the problem when I design the udma33 interface
101196: 06/04/27: Re: the problem when I design the udma33 interface
102798: 06/05/20: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
103250: 06/05/29: hard disk drivers problem
104612: 06/07/01: register state when power on
104619: 06/07/01: stable reset in fpga
bjzhangwn@gmail.com:
104988: 06/07/11: DLL in spartan2e
114043: 07/01/03: Re: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2
118362: 07/04/24: compact flash slave ip core
118475: 07/04/27: chip to chip high speed interconnet bus
121559: 07/07/08: fifo counter in virtex-4
129572: 08/02/27: sd card slave interface
129573: 08/02/27: sd card slave interface
129757: 08/03/04: Re: sd card slave interface
131237: 08/04/16: 91c111 drivers for NIOSII without ucosII/lwip stack
131754: 08/05/01: NIOS II CFI interface
131786: 08/05/01: Re: NIOS II CFI interface
132018: 08/05/09: udp receive problem under nios
132831: 08/06/07: NIOS-II+LAN91C111
132832: 08/06/07: NIOS-II+LAN91C111
132833: 08/06/08: Re: NIOS-II+LAN91C111
135484: 08/10/04: Xilinx PCIE problem
135490: 08/10/04: Xilinx PCIE problem
135491: 08/10/04: Virtex-5 Integrated Endpoint Block for PCI Express Designs
136706: 08/12/02: problem about V5 PCI Express endpoint
136717: 08/12/02: Re: problem about V5 PCI Express endpoint
138625: 09/03/02: how to communicate with NiosII
143942: 09/11/04: problem fpga aera optimization
144001: 09/11/06: Re: problem fpga aera optimization
152721: 11/10/09: high speed place and route about xilinx
155260: 13/06/19: comparing between Xilinx and altera
BJÖRN LINDEGREN:
21940: 00/04/07: Port "IN2" has no net attached to it-on pad cells inserted at this port.
Björn Lindegren:
20247: 00/02/02: XC9536 and Abel
21000: 00/03/02: xilinx synthesis tool
21084: 00/03/06: Problem with vector copy
21248: 00/03/13: Testbench for a modulator and a demodulator
22609: 00/05/13: SV: foundation
22610: 00/05/13: Prom
22860: 00/05/28: STD_LOGIC_VECTOR problem.....
23178: 00/06/16: SV: Xilinx config over parallel port ?
23445: 00/06/25: Fpga in tristate?
Björn Lindgren:
25603: 00/09/15: Re: hardware compatibility and patent infringement
Bjørn B Larsen:
29436: 01/02/21: Re: RSA on FPGA
<bkelly@altera.com>:
113799: 06/12/22: Re: Virtex-5 Webpack?
<bkk411@hotmail.com>:
23309: 00/06/22: Re: Xilinx Foundation 2.1 error
23310: 00/06/22: Re: Leonardo 2000 Comments?
23367: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23368: 00/06/23: Re: 500 million transistor FPGA's
23418: 00/06/24: Re: F2.1i
23420: 00/06/24: Re: What tools do people use for Xilinx FPGAs?
23547: 00/06/29: Re: Free PCI core
23549: 00/06/29: Re: Maximum Speed on obtainable on FPGAs?
23550: 00/06/29: Re: PCI with Xilinx controller
23639: 00/07/04: Re: division in FPGA - help !
25677: 00/09/17: Re: hardware compatibility and patent infringement
<bkk411@my-deja.com>:
22983: 00/06/07: FC2 v3.4 & Selcet Block RAM in Virtex(E)
23014: 00/06/09: XILINX RAM Useless
23028: 00/06/09: Re: XILINX RAM Useless
23029: 00/06/09: Re: Simulation of VIRTEX BLOCKRAM
23038: 00/06/10: Re: XILINX RAM Useless
<bknpk@hotmail.com>:
137162: 08/12/29: Code Indentation
138267: 09/02/11: Re: Implementing reset / enable in FPGA question
139690: 09/04/09: system C versus VHDL|verilog|specman ....
<bko-no-spam-please@ieee.org>:
70906: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
75799: 04/11/15: Re: Digital LP filter in multiplier free FPGA
<bkurtz@engineer.com>:
130017: 08/03/12: Re: Design complexity in Logic cells - Virtex-5 FPGA
134552: 08/08/17: Re: video timing with TFP410
bkuschak@gmail.com:
89736: 05/09/23: Re: ISE 7.1i incremental synthesis
<bkuschak@gmail.com>:
89564: 05/09/19: ISE 7.1i incremental synthesis
black:
57460: 03/07/01: the skew and race condition
57463: 03/07/01: Re: the skew and race condition
57466: 03/07/01: Re: the skew and race condition
blackduck:
79778: 05/02/24: Multiple additions
79779: 05/02/24: Multiple addition(2)
79784: 05/02/24: Re: Multiple additions
79785: 05/02/24: Re: Multiple addition(2)
79795: 05/02/24: Re: Multiple addition(2)
<blackhole@rtd.com>:
21157: 00/03/08: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
Blackie Beard:
47111: 02/09/18: Re: FPGA work in the Bay Area (CA)?
47180: 02/09/20: Re: Multiple divide by 10
47182: 02/09/20: Re: Multiple divide by 10
47183: 02/09/20: Re: Multiple divide by 10
47184: 02/09/20: Re: IC layout
47185: 02/09/20: Re: Overheat with XCV-600E
47189: 02/09/20: Re: Multiple divide by 10
47190: 02/09/20: Re: Modelsim XE question
47203: 02/09/20: Re: Multiple divide by 10
47204: 02/09/20: Re: Multiple divide by 10
47213: 02/09/20: Re: Multiple divide by 10
47265: 02/09/22: Re: SDRAM<--->FPGA<--->IDE interface
47268: 02/09/22: Re: external switch to CPLD input
47278: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
47403: 02/09/25: Re: Multiple divide by 10
47575: 02/09/29: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47576: 02/09/29: Re: Getting started
47577: 02/09/29: Re: Unused pins in Apex20KE
47590: 02/09/30: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47591: 02/09/30: Re: Getting started
47708: 02/10/02: Re: Moving average filter
47777: 02/10/03: Re: Moving average filter
47873: 02/10/06: Re: Moving average filter
48034: 02/10/10: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
48103: 02/10/11: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48125: 02/10/11: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48144: 02/10/12: Re: Quartus design question
48146: 02/10/12: Re: Quartus design question
48188: 02/10/13: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48707: 02/10/23: Re: LCD driver implement with FPGA
48744: 02/10/23: Re: LCD driver implement with FPGA
48745: 02/10/23: Re: LCD driver implement with FPGA
48747: 02/10/23: Re: PCI ARBITER
71027: 04/07/06: Re: *RANT* Ridiculous EDA software "user license agreements"?
blacksheep:
17642: 99/08/18: programmable switching for telecommunications
BlackSim:
65555: 04/02/02: hold violation cause by crossing clock domain
65562: 04/02/03: Re: hold violation cause by crossing clock domain
Blade:
95074: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95193: 06/01/21: Re: OT:Shooting Ourselves in the Foot
Blagomir Donchev:
33398: 01/07/25: Foundation ISE and VCC software problem
blah:
88849: 05/08/30: Embedded Processors/Serdes
89128: 05/09/06: SI newsgroup
Blaine:
10213: 98/05/05: Re: Altera 10K20 Configuration problem
<blair.bonnett@gmail.com>:
136461: 08/11/17: Re: Xilinx-3E Starter Kit - USB connection with Linux
<Blair@QuickLogic.com>:
6497: 97/05/28: Re: FPGA gate counting: No truth in advertising
6596: 97/06/04: Re: FPGA gate counting: No truth in advertising
6631: 97/06/06: Re: FPGA gate counting: No truth in advertising
blakaxe:
142353: 09/08/05: Re: how to sign extend or round?
blakaxe@gmail.com:
134054: 08/07/23: Quartus2 pin assignment
134079: 08/07/24: Error: EDA Netlist Writer failed to generate FPGA Xchange file
134102: 08/07/25: Re: Prevent synthesis optimizations/simplifications in Xilinx-ISE
134167: 08/07/28: how to import fpga pin group info in Quartus 2
142351: 09/08/05: how to sign extend or round?
Blake:
52349: 03/02/07: Re: Interfacing to a PC using EPP parallel port
52350: 03/02/07: Re: Interfacing to a PC using EPP parallel port
52351: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
Blake Henry:
29361: 01/02/16: Re: VHDL PID
44772: 02/06/30: Re: Looking for FPGA board with USB interface
65133: 04/01/21: Re: liability insurance
65135: 04/01/21: Re: changing values in a fifo
65203: 04/01/22: Re: changing values in a fifo
65204: 04/01/22: Re: OT: liability insurance
Blake Nelson:
11469: 98/08/17: FPGA Programmer Available!
11708: 98/09/02: FPGA Developers Available
12937: 98/11/05: FPGA Developers Available
14382: 99/01/27: Outsource??
17311: 99/07/20: "Contract Outsourcing?!"
<blaster52>:
19779: 00/01/11: freemoneyfast
Bliad Bors:
161676: 20/03/24: Use example of Intel University program in Intel Quartus - problem with Board support package?
161678: 20/03/24: Re: Use example of Intel University program in Intel Quartus -
161680: 20/03/25: Re: Use example of Intel University program in Intel Quartus -
blinkenlights:
134127: 08/07/26: Opencores DDR2 SDRAM controller with spartan3e starter board
134129: 08/07/26: Re: Opencores DDR2 SDRAM controller with spartan3e starter board
134132: 08/07/27: Re: Opencores DDR2 SDRAM controller with spartan3e starter board
134145: 08/07/27: Re: Opencores DDR2 SDRAM controller with spartan3e starter board
blisca:
61793: 03/10/11: from jedec to schematic ??
61965: 03/10/15: tektronix 308 data analyzer
62578: 03/11/02: help ;lattice synario error
103732: 06/06/09: xilinx cable 3 doesn't talk with pc,but test ok
103747: 06/06/10: R: xilinx cable 3 doesn't talk with pc,but test ok
103754: 06/06/10: R: xilinx cable 3 doesn't talk with pc,but test ok
103788: 06/06/11: R: R: xilinx cable 3 doesn't talk with pc,but test ok
104268: 06/06/22: newbie:my ISE doesn't include old xcs30 spartan how........
104274: 06/06/22: R: newbie:my ISE doesn't include old xcs30 spartan how........
104326: 06/06/23: no ram core simulation with free Ise ?
104327: 06/06/23: R: newbie:my ISE doesn't include old xcs30 spartan how........
104369: 06/06/26: R: no ram core simulation with free Ise ?
104380: 06/06/26: R: still having same error
104385: 06/06/26: R: R: still having same error
104388: 06/06/26: R: R: stillcan't access xilinxcorelib,where does modelsim looks for it?
104394: 06/06/26: R: R: R: stillcan't access xilinxcorelib,where does modelsim looksfor it?
104404: 06/06/27: R: still having same error
104559: 06/06/29: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
104596: 06/06/30: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
104600: 06/06/30: minimal connections so that a xcv200e talks with pc
104618: 06/07/01: R: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
104656: 06/07/03: can't read device ID xcv200....what about the PROGRAM pin
104664: 06/07/03: R: can't read device ID xcv200....what about the PROGRAM pin
104669: 06/07/03: R: can't read device ID xcv200E....what about the PROGRAM pin
104670: 06/07/03: R: can't read device ID xcv200....what about the PROGRAM pin
107664: 06/08/31: virtex xcv:no way to see TDO moving:
114699: 07/01/23: iMPACT dont shows erase write options with fpga
114709: 07/01/23: R: iMPACT dont shows erase write options with fpga
124969: 07/10/13: Newbie,the simplest way to program an FPGA at home?
124987: 07/10/14: R: Newbie,the simplest way to program an FPGA at home?
124991: 07/10/15: R: R: Newbie,the simplest way to program an FPGA at home?
125000: 07/10/15: R: Newbie,the simplest way to program an FPGA at home?
125048: 07/10/16: Xilinx:is it possible to install Impact 9.1only?
125142: 07/10/16: R: Xilinx:is it possible to install Impact 9.1only?
125819: 07/11/06: May i program a Spartan 3 fpga with a 1,8 V Digilent cable?
125830: 07/11/06: R: May i program a Spartan 3 fpga with a 1,8 V Digilent cable?
126776: 07/12/02: can't genarate block memory cores in ISE 7.1i
126777: 07/12/02: R: can't genarate block memory cores in ISE 7.1i
126832: 07/12/03: Re: can't genarate block memory cores in ISE 7.1i
127510: 07/12/31: Can i verify RAM content with ISE simulator?
128958: 08/02/11: Xilinx ISE and XP home,possible?
129151: 08/02/15: Re: Xilinx ISE and XP home,possible?
135857: 08/10/18: configuring xc3s1500 from common parallel flash?
135870: 08/10/19: Re: configuring xc3s1500 from common parallel flash?
150781: 11/02/10: JTAG Programming 29LV400 Flash via Altera Cyclone
bliss:
27740: 00/12/06: Title:Interfacing between ECL and LVDS?
<bln5320@googlemail.com>:
154343: 12/10/09: Re: FPGA-Board for Ethernet
154369: 12/10/16: Re: FPGA-Board for Ethernet
154656: 12/12/12: MII SFD Detection with Shematics
154661: 12/12/13: Re: MII SFD Detection with Shematics
bluds:
147089: 10/04/13: Read from the compact flash
147099: 10/04/14: Re: Read from the compact flash
147109: 10/04/14: Re: Read from the compact flash
147112: 10/04/14: Re: Read from the compact flash
147219: 10/04/19: Re: Read from the compact flash
Blue Banshee:
151487: 11/04/13: Re: Altium Limited closing up shop - Altium Designer discontinued
<blueflyer@my-deja.com>:
28186: 00/12/26: Newbie question on clock timing generation
28193: 00/12/27: Re: Newbie question on clock timing generation
28197: 00/12/27: Re: Newbie question on clock timing generation
28221: 01/01/02: Re: help
bluesclues:
116822: 07/03/19: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
<bluesea.xjtu@gmail.com>:
139663: 09/04/08: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
139694: 09/04/09: Re: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
Bluespace Technologies:
103935: 06/06/15: Anyone get a Pictiva OLED to work?
104093: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104112: 06/06/19: Re: Anyone get a Pictiva OLED to work?
bluetooth with FPGA:
101176: 06/04/26: Re: Picoblaze C Compiler
bm:
106699: 06/08/17: Using an FPGA as USB HOST without PHY
106708: 06/08/17: Re: Using an FPGA as USB HOST without PHY
106712: 06/08/17: Re: Using an FPGA as USB HOST without PHY
112094: 06/11/16: Re: USB and AHB
112115: 06/11/16: Re: USB and AHB
112576: 06/11/25: Re: logic analyzer using FPGA
114581: 07/01/19: SPARC V7 CORE
114604: 07/01/20: Re: SPARC V7 CORE
BM:
38284: 02/01/10: Xilinx High speed I/O
106734: 06/08/17: Re: Using an FPGA as USB HOST without PHY
106735: 06/08/17: Re: Using an FPGA as USB HOST without PHY
<bmathew@hotmail.com>:
14865: 99/02/21: Under-clocking SDRAM
bngguy:
119946: 07/05/29: FIR Filter ON FPGA
120072: 07/05/31: FIR ON FPGA
Bo:
77428: 05/01/06: Re: xil_printf not working as expected
77429: 05/01/06: Re: Utilisation of Xilinx FPGAs
77476: 05/01/07: systemACE compact flash FATFs problems
77835: 05/01/18: Re: USB Host
78839: 05/02/08: vxWorks soft boot with ML310/ VirtexIIPro
78840: 05/02/08: Re: V4LX25-ES and systemACE
79276: 05/02/16: PPC405 sleep?
79316: 05/02/17: Re: PPC405 sleep?
79590: 05/02/21: Re: PPC405 sleep?
80220: 05/03/02: sysACE load vs bootloader load of vxWorks on ML310
80279: 05/03/03: Re: sysACE load vs bootloader load of vxWorks on ML310
80359: 05/03/04: intermittent sysACE hang on ML310
86240: 05/06/23: Re: ISE 7.1 Service Pack 2 - Ready yet?
91320: 05/11/03: Re: I have received a job offer
95579: 06/01/24: Re: PE licunsure: was Shooting Ourselves in the Foot
95406: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95578: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95616: 06/01/24: Re: OT:Shooting Ourselves in the Foot
Bo Bjerre:
13617: 98/12/13: Re: xilink Parallel cable III
13687: 98/12/18: Re: Xilinx XC4000 cinfigured from EPC2?
Bo Esbech:
59007: 03/08/06: Re: Block ram simulation
59113: 03/08/08: Re: Block ram simulation
Bo Petersen:
28236: 01/01/03: 2-D DCT implementation
boaz:
24720: 00/08/17: Category : Subject : test benchs and CPU core
boB:
159369: 16/10/17: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a Second
bob:
9532: 98/03/21: Xilinx M1.4 Software
16936: 99/06/18: *.bit, *.ubt, *.rbt
51034: 02/12/27: Actel 32300 power-up behavoiur
62527: 03/10/31: data recorder examples?
64322: 03/12/28: Virtex-II Pro and DDR2 SDRAM differential IO
64720: 04/01/12: fpga database?
65396: 04/01/27: Image sensor?
65418: 04/01/28: Re: Image sensor?
65779: 04/02/06: FPGA Database?
67924: 04/03/23: Apparent Altera Cyclone JTAG problem
72496: 04/08/20: FPGA SPARTAN 2 BOARD SCHEMATIC protel
72558: 04/08/24: FPGA SPARTAN 3 or 2 BOARD SCHEMATIC protel
78741: 05/02/07: Virtex4: where is ICAP?
79209: 05/02/15: SPI serial output counter or latch?
79391: 05/02/18: Shift register example?
79600: 05/02/21: Shift register example?
Bob:
45229: 02/07/17: Re: LVDS interface cable recommendation sought
48404: 02/10/17: Re: multiple clocks
48478: 02/10/18: Re: Locating IOBs with shared routing resources in VirtexII.
48771: 02/10/24: Re: LVDS standard
48826: 02/10/25: Re: LVDS standard
48827: 02/10/25: Re: LVDS standard
48975: 02/10/28: filters on fpgas
49109: 02/11/01: Re: Metastability results are finally posted
49288: 02/11/07: ISE web pack multiplier CORE
49331: 02/11/09: Core generator modules & Copyright
49943: 02/11/26: Re: Problem programming XC9536
49987: 02/11/27: Re: question about PCB traces for FPGA board... ?
50002: 02/11/28: Re: question about PCB traces for FPGA board... ?
50007: 02/11/28: Re: question about PCB traces for FPGA board... ?
50020: 02/11/28: Re: question about PCB traces for FPGA board... ?
50991: 02/12/25: Re: HSTL standards
51085: 02/12/31: Re: xilinx virtex "done" pin problem with jtag
52032: 03/01/29: Re: analog in analog out DSP development board for Xilinx
52720: 03/02/20: Re: hold violation error
52774: 03/02/21: Re: hold violation error
52793: 03/02/22: Re: spartan III what is it?
52801: 03/02/22: Re: spartan III what is it?
53155: 03/03/05: Re: Using Xilinx DCMs out of specifications is not recommended!!!!
53261: 03/03/08: Re: Clocking a spartanIIE with a 5V signal?
53737: 03/03/21: Re: Using DDR placed on the PCB with a Virted II...
53748: 03/03/21: FPGA FFT Questions
53853: 03/03/25: Re: FPGA FFT Questions
54146: 03/04/03: More FFT Questions
54165: 03/04/03: Re: More FFT Questions
54177: 03/04/04: Re: More FFT Questions
54178: 03/04/04: Re: More FFT Questions
54188: 03/04/04: Re: More FFT Questions
54359: 03/04/08: Even more FFT questions ...from previous thread
54965: 03/04/23: DC requirement in FFT
57170: 03/06/24: scaling fixed point fft
58296: 03/07/19: using block rams in FPGAs
59134: 03/08/09: Re: DDR-ram interface (xapp200)
59141: 03/08/10: Re: Xilinx virtex II DCM CLKFX output not working
60531: 03/09/16: Re: 'RSVD' pin on V2/V2P
60634: 03/09/18: Using LUTs for array of coefficients
60657: 03/09/18: Re: Using LUTs for array of coefficients
60739: 03/09/21: Re: show-ahead FIFOs
61091: 03/09/27: Re: Can I use pullup/pulldown to bias LVDS input?
61341: 03/10/02: Re: LVDS_25_DCI : Top Ten List
61516: 03/10/06: synplify vqm not able to fit in Quartus
61580: 03/10/07: Re: synplify vqm not able to fit in Quartus
61637: 03/10/08: use of radix-2 ffts
61653: 03/10/08: Re: synplify vqm not able to fit in Quartus
64230: 03/12/21: Re: Help me converting Mathlab code to VHDL? DSPBuilder or SystemGenerator
64860: 04/01/15: Please help with Xilinx ISE Schematic question
65332: 04/01/25: OT: Flash memory problem on Spirit?
65337: 04/01/25: Re: Cascading of many stages of DCM...
66012: 04/02/11: Re: negative hold time
67508: 04/03/13: Re: LVTTL Spartan-3 pin input current...
67729: 04/03/18: Re: Spartan III availability
69092: 04/04/27: Re: Virtex II Pro and 3rd party devices in one JTAG chain?
69637: 04/05/17: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
69673: 04/05/18: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69976: 04/05/26: Re: Creating Orcad symbol for FPGA with large pin counts
71174: 04/07/10: Re: Do i need to use DCM ?
72855: 04/09/05: Re: PCI Noise
75987: 04/11/22: Re: Spartan 3 output voltage level
76027: 04/11/23: Re: Spartan 3 output voltage level
77240: 05/01/01: Re: Dead FPGA?
77346: 05/01/05: Re: Whither common courtesy ?
78282: 05/01/28: Re: See Peter's High-Wire Act next Tuesday
78492: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
78662: 05/02/05: Re: Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
78719: 05/02/07: Re: GND and VCC pins
78909: 05/02/10: theta(jb) for V2-PRO in FG676
79142: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79421: 05/02/18: Re: Xilinx: Pitfalls of chaining DLLs
79438: 05/02/19: Re: Xilinx: Pitfalls of chaining DLLs
80332: 05/03/04: Xilinx/Howard Johnson's crosstalk web seminar
80863: 05/03/13: Re: (Stupid/Newbie) Question on UART
81489: 05/03/25: Re: LVPECL, Virtex II and the EP445
81521: 05/03/26: Re: cheap Xilinx tricks
81532: 05/03/26: Re: cheap Xilinx tricks
82171: 05/04/08: Re: Xilinx V2-Pro + Select Map programming
82675: 05/04/16: Re: salary ballpark please guys
82826: 05/04/18: Re: Declining a job offer
82936: 05/04/20: Re: Declining a job offer
82942: 05/04/20: Re: Declining a job offer
83473: 05/04/30: Re: VGA sync signals
83554: 05/05/03: Re: VGA sync signals
88361: 05/08/16: image sensor
88377: 05/08/16: image sensor
90081: 05/10/04: Radiation + CoolRunner2 CPLD?
90088: 05/10/04: Re: Radiation + CoolRunner2 CPLD?
91005: 05/10/26: Cost to go from FPGA to ASIC
91011: 05/10/27: Re: Cost to go from FPGA to ASIC
91016: 05/10/27: Re: Cost to go from FPGA to ASIC
92317: 05/11/27: Re: Virtex 4 Configuration
92379: 05/11/29: Re: Virtex 4 Configuration
93334: 05/12/20: Re: Virtex-4 clocking
93664: 05/12/28: Re: Virtex-4 CCLK termination
93668: 05/12/28: Re: Virtex-4 CCLK termination
93680: 05/12/28: Re: Virtex-4 CCLK termination
95917: 06/01/27: Re: Current to sink PROG_B low?
96052: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
96069: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
96096: 06/01/30: Re: Virtex-4 ISERDES and ADS527X ADCs
100412: 06/04/08: Re: DDR Termination
101709: 06/05/05: Re: LVDS inputs on Cyclone II
101958: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
102609: 06/05/18: V4 system synchronous input setup/hold and clock-to-out time calculations?
102796: 06/05/21: Re: JTAG chaining of two different Xilinx Spartan 3E boards
102899: 06/05/23: Xilinx -- please help with Virtex-4 datasheet
103320: 06/05/31: Re: Need help reattaching top to FPGA
103445: 06/06/02: Re: Delay or latency
104051: 06/06/17: Re: Temperature sensing diode on Vertex 4
104662: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
105603: 06/07/27: Re: Hold violation in Virtex 4
105604: 06/07/27: Re: Hold violation in Virtex 4
105661: 06/07/28: Re: IOBDELAY and DCM
107748: 06/08/31: Re: MIG DDR2 controller does not work (reset problems?)
109208: 06/09/21: Spartan-3E USB for I/O?
109913: 06/10/07: Re: Spartan 3 DCI
110092: 06/10/10: Re: Spartan 3 DCI
110537: 06/10/17: Need info: Altera dual-port & fifo act different (func vs VITAL)
110803: 06/10/23: Re: Need info: Altera dual-port & fifo act different (func vs VITAL)
111193: 06/10/30: Re: FFT help
111616: 06/11/06: Re: Chip to Chip LVDS
111675: 06/11/07: Re: Chip to Chip LVDS
112314: 06/11/20: Need examples/instruction: use of altpll_reconfig (Altera)
112684: 06/11/27: Re: vccaux and vccint
112718: 06/11/27: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112737: 06/11/28: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
113362: 06/12/11: Re: Need examples/instruction: use of altpll_reconfig (Altera)
114142: 07/01/05: Re: Spartan3E minimum clock-to-output (hold time)
115521: 07/02/12: Re: Building Coaxial transmission line on PCB?
118429: 07/04/26: Need help: Altera ALTPLL_RECONFIG state machine construction
118459: 07/04/26: N00b question about DCM
118947: 07/05/07: Re: Xilinx software quality - how low can it go ?!
120079: 07/05/31: Re: FIR ON FPGA
120492: 07/06/07: Re: LVPECL output skew
120501: 07/06/07: Re: LVPECL output skew
120653: 07/06/12: Re: Stolen Spartan 3E-1600 Development Board
121380: 07/07/03: Re: DIFF_TERM Question
123615: 07/08/31: Re: Spartan3E and DDR termination
131779: 08/05/01: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131784: 08/05/01: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131795: 08/05/02: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131830: 08/05/02: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131853: 08/05/04: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131861: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131874: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131875: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131891: 08/05/06: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131892: 08/05/06: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131926: 08/05/07: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
131928: 08/05/07: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
135703: 08/10/13: Re: XMOS XC-1 kits are shipping
144445: 09/12/08: Problems reading from PHY registers using plb_temac and hard_temac,
144473: 09/12/09: Re: Problems reading from PHY registers using plb_temac and
144479: 09/12/09: Re: Problems reading from PHY registers using plb_temac and
150413: 11/01/18: ANN: One time offer...ONEoverT Digital Filter Designer..reduced by
Bob - Commtech Services:
20418: 00/02/09: 12+ month contract-NJ
bob allen:
81714: 05/03/30: Using the Xilinx JTAG Interface as a General-Purpose Communication
Bob Armstrng:
41093: 02/03/20: Can't program XC4010 with JTAG without BSCAN???
41208: 02/03/22: Re: Can't program XC4010 with JTAG without BSCAN???
Bob Armstrong:
69485: 04/05/11: Schematic/Service manual needed for EE Tools TopMax Programmer
Bob Baman:
20982: 00/03/02: Re: Xilinx Tools Vs Altera tools
26155: 00/10/05: Re: Simon , decoupling caps
Bob Bauman:
15096: 99/03/05: Current State of FPGA-based PCI Interfaces?
15170: 99/03/10: Re: Current State of FPGA-based PCI Interfaces?
15169: 99/03/10: Re: Current State of FPGA-based PCI Interfaces?
15191: 99/03/11: Re: Infidels Invited, Heathens Highly Welcome !
17228: 99/07/12: Re: PCI interface
Bob Beckwith:
9298: 98/03/05: Re: Using Java for PLI?
9305: 98/03/05: Re: Using Java for PLI?
16712: 99/06/03: Re: Verilog PLI website
Bob Bernatchez:
28797: 01/01/24: Help with Boundary Scan / BSDL
Bob Blick:
2727: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
Bob Burk:
11725: 98/09/03: WANTED: Characteristic models for JTAG (IEEE 1149.1) development
Bob Cain:
20874: 00/02/24: Re: Bit Serial Arithmetic De-mystified
36005: 01/10/25: Re: 2/3 trellis code in vhdl
39250: 02/02/04: Re: solutions manuals, and no they are not for school
39344: 02/02/06: Re: solutions manuals, and no they are not for school
39432: 02/02/08: Re: solutions manuals, and no they are not for school
Bob Crotinger:
9205: 98/03/01: Firmware Eng's WANTED: outstanding career opportunities
Bob Deasy:
12053: 98/09/25: Re: Which FPGA tool is better
12175: 98/10/02: Re: Verilog Simulators
12354: 98/10/09: Re: Software tool
12459: 98/10/12: Re: Schematic entry?
13121: 98/11/16: Re: Software tool
Bob Doyle:
4785: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
19239: 99/12/08: Re: AM2901 bit slice processor
19742: 00/01/11: Re: Virtex Temperature Sensing diode pins DXP, DXN
27784: 00/12/07: Re: XC9500/9500XL CPLD Clocks
28212: 00/12/30: XC9500 and unused inputs
28222: 01/01/01: Re: XC9500 and unused inputs
Bob Efram:
15381: 99/03/21: Re: Free Xilinx Vendor Tools ... NOT :-(
15400: 99/03/22: Re: HDL-307 error
40459: 02/03/07: Re: Is there a ver 7.1 of Sunplify?
61805: 03/10/12: Re: Initilization of block rams to create rom
68292: 04/03/31: Re: Is there any Sync separator IP(Intellectual property) exists?
93696: 05/12/28: Re: Using Synplicity to synthesize EDK user IP's
bob elkind:
3639: 96/07/06: Re: size of fpga
3779: 96/07/30: new thread, was: Question: FPGA versus ASIC design.
3994: 96/08/30: Re: Anyone know about Viewlogic v4 with QEMM?
4136: 96/09/17: Re: Inaccrate Xilinx simulations ???
4255: 96/10/05: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4502: 96/11/06: Re: What is the fastest fpga for ...
4730: 96/12/07: Re: Memory Requirements
4887: 96/12/25: Re: ASICs Vs. FPGA in Safety Critical Apps.
5110: 97/01/24: Re: FPGA Lab.
5157: 97/01/27: Re: FPGA & division
5250: 97/02/01: Re: Altera support better than Xilinx
5251: 97/02/01: Re: FPGA power dissipation
5261: 97/02/03: Re: Problem with XACT and Orcad interface
5311: 97/02/06: BIGGER (was Embedded SRAM in FPGAs)
5314: 97/02/06: Re: Suggestions how wire wrap mount a Xilinx PG223
5411: 97/02/14: Lucent Foundry (PC) bug
5431: 97/02/15: Re: Lucent Foundry (PC) bug
5432: 97/02/15: Re: FPGA power dissipation
5433: 97/02/15: multi-vendor VHDL design tool
5511: 97/02/21: Re: Xilinx or Altera?
5536: 97/02/23: Re: Xilinx or Altera?
5560: 97/02/24: Re: Market share - synthesis tools?
5605: 97/02/28: Re: Is XACT 6 annual maintenance worthwhile?
5659: 97/03/05: Re: Reverse Engineering FPGAs
5666: 97/03/05: Re: Reverse Engineering FPGAs
5759: 97/03/13: Re: viewoffice compatibility - dumb question
5760: 97/03/13: Re: Xilinx/NeoCAD software vs. XC4KE question
6049: 97/04/08: prep benchmarks for FPGAs
6089: 97/04/11: Re: prep benchmarks for FPGAs
6266: 97/05/06: USB, PCI, ISA ref material pointers wanted
6616: 97/06/05: Re: Fine Pitch PQFP : anyone any hassles?
6541: 97/06/02: NT4 and EECAD applications, and SP3
6879: 97/07/05: Re: fast scopes: how?
7107: 97/08/01: Re: MEM_CS16 timing on ISA BUS
7144: 97/08/06: Re: MEM_CS16 timing on ISA BUS
7108: 97/08/01: jtag isp guidance request
7364: 97/09/02: export pins from MAX+ to orcad schem symbol
7375: 97/09/04: Re: export pins from MAX+ to orcad schem symbol
8920: 98/02/06: altera max7000s and JTAG ISP
8999: 98/02/12: re: altera max7000s and JTAG ISP
9000: 98/02/12: re: altera max7000s and JTAG ISP
10717: 98/06/11: Re: AHDL vs. VHDL vs. Verilog HDl
13700: 98/12/18: Re: Xilinx Foundation vs. Altera Max Plus II
13745: 98/12/21: Re: Xilinx Foundation vs. Altera Max Plus II
13407: 98/12/01: Re: Which parts are fastest for 3-state enables?
13432: 98/12/02: Re: Interfaces to an Asynchronous SRAM
13437: 98/12/02: Re: Interfaces to an Asynchronous SRAM
13438: 98/12/02: Re: Interfaces to an Asynchronous SRAM (repost)
13441: 98/12/02: Re: Interfaces to an Asynchronous SRAM
13938: 99/01/04: Re: Gamma correction in YUV space
14341: 99/01/26: Re: Looking for Altera 10K libraries for Protel Adv. Schematic
14343: 99/01/26: Re: Hysteresis on PLD Clock Inputs
14774: 99/02/16: Re: orcad
15095: 99/03/05: programming cplds and serial roms and fpgas
15130: 99/03/08: Re: Design Engineers
15227: 99/03/15: Re: Spartan, delaying a clock.
15292: 99/03/17: Re: Power Estimiation
15566: 99/03/30: Re: FPGAs with ECL-compatible I/Os
15853: 99/04/16: Re: 75% PAL video bars
16185: 99/05/07: Re: AHDL books
16807: 99/06/09: Re: LINE DELAYS USING RAMS
16808: 99/06/09: Re: LINE DELAYS USING RAMS
17129: 99/07/01: Altera, JTAG, and FPGAs WAS: Virtex JTAG readback
17128: 99/07/01: Re: Altera 10K prices
17272: 99/07/15: Re: Dongle problems.
18014: 99/09/23: Re: basic Altera simulation questions
18595: 99/11/02: Re: Need shematic and documentation for in-system programming ALTERA
18596: 99/11/02: Re: Altera Reset Strategy?
18597: 99/11/02: Re: Altera - how to make probe to a routed chip ?
19533: 99/12/29: Re: MAX7256A dies during ICP
21495: 00/03/23: Re: Clock disabling
22140: 00/04/26: Re: How to Prevent theft of FPGA design
23148: 00/06/15: Re: Altera Output Timing Question
25631: 00/09/15: Re: MAX PLUS 2
25633: 00/09/15: Re: Physical Interpretation
25949: 00/09/27: Re: Preserving nets using Maxplus2 (9.5)
26119: 00/10/04: Re: Xilinx Licensing.
26123: 00/10/04: Re: DLL unlocking
26124: 00/10/04: Re: Xilinx Licensing.
26355: 00/10/12: Re: palasm
28142: 00/12/22: Re: Virtex and metastability
28246: 01/01/03: Re: Virtex and metastability
28462: 01/01/14: Re: grey code counters
28463: 01/01/14: Re: grey code counters
28743: 01/01/23: minor bug in MAX+2 v10.0
31547: 01/05/29: Re: ORCAD Capture Symbols
31549: 01/05/29: Re: ORCAD Capture Symbols
31554: 01/05/29: Re: ORCAD Capture Symbols
31978: 01/06/09: Re: Async FIFO in maxplus2
31979: 01/06/09: Re: Pin locking in Maxplus2
31980: 01/06/09: Re: Pin locking in Maxplus2
32066: 01/06/12: Re: Pin locking in Maxplus2
32086: 01/06/13: Re: Pin locking in Maxplus2
32087: 01/06/13: Re: Pin locking in Maxplus2
32129: 01/06/14: Re: Pin locking in Maxplus2
32159: 01/06/16: Re: Pin locking in Maxplus2
32185: 01/06/18: Re: Pin locking in Maxplus2
32227: 01/06/20: Re: Gray counter STRUCTURAL (VHDL)
32258: 01/06/21: NT vs W2K (WAS Re: Pin locking in Maxplus2)
32267: 01/06/21: what tools run OK on windows 2000?
32268: 01/06/21: Re: what tools run OK on windows 2000?
32773: 01/07/08: Re: Altera ACEX
32775: 01/07/08: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32782: 01/07/09: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32818: 01/07/09: Re: What chip!?
32819: 01/07/09: Re: What chip!?
32829: 01/07/10: Re: What chip!?
32855: 01/07/10: Altera synthesis tools WAS: What chip!?
33181: 01/07/18: Re: How do i see buried nodes in maxplus2?
33183: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33185: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33202: 01/07/19: Re: 30 m cable reception with APEX LVDS I/O ?????
33203: 01/07/19: Re: Spartan2XC2S30 vs ACEXEP1K30
33235: 01/07/19: Re: How to see ram contents in maxplus2 simulation?
33259: 01/07/20: Re: Async RS flip-flop (was How to see ram contents in maxplus2
33307: 01/07/22: Re: Spartan2XC2S30 vs ACEXEP1K30
33421: 01/07/25: Re: What chip!?
33959: 01/08/09: Re: Why doesn't DFF stroes the value from the previous clock
33963: 01/08/09: Re: this code doesn't work properly
33993: 01/08/10: Re: Orcad symbol for a Virtex II
33995: 01/08/10: newbie help needed
33996: 01/08/10: Re: newbie help needed
40473: 02/03/07: Re: Quartus II 2.0 fast fit option
40533: 02/03/09: Re: exceeding 2GB limits in xilinx
42998: 02/05/09: Re: DDR reference design
131462: 08/04/22: Altera Cyc II config problems
133233: 08/06/22: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
133236: 08/06/22: Re: Altera, Cyclone III, PCI, LVCMOS, & 3.3V
Bob Elkind:
55: 94/08/04: Re: Mouseproblems using Makebits (Xilinx 4.3)
142: 94/08/30: Re: Xilinx slow on distribution of r5.0
143: 94/08/30: Re: Incremental reconfiguration ?
165: 94/09/06: Re: XC3000 vs XC3100 series FPGAs
218: 94/09/26: Re: Xilinx 4000
227: 94/09/28: Re: Xilinx 4000
242: 94/09/30: ATT/ORCA references desired
270: 94/10/10: Re: Any documentation for Xilinx XNF file format?
304: 94/10/17: Re: SRAM and antifuse for interconnects
320: 94/10/19: Re: Xilinx ROMS
420: 94/11/13: Re: about downloading FPGAs
523: 94/12/19: Re: Any Way to Download a XNF to FPGA
596: 95/01/16: Re: ViewLogic simulation without master reset
597: 95/01/16: Re: Xilinx marketing knuckleheads
598: 95/01/16: Re: PCB design with Xilinx
644: 95/01/26: Re: NeoCAD Experience
656: 95/01/30: Re: NeoCAD Experience
662: 95/01/31: hi-power FPGA applications
663: 95/01/31: hi-power FPGA applications
737: 95/02/20: Re: Real-time fractal gen in h/w
741: 95/02/21: FPGAs and power
914: 95/03/29: Re: 100MHz low power FPGAs
943: 95/03/31: Neocad purchased by Xilinx
979: 95/04/06: Re: AT&T Statement ref Neocad
987: 95/04/07: Re: AT&T Statement ref Neocad
1443: 95/06/23: Re: The "InOut" Port mode in the Xilinx FPGA
3058: 96/03/23: PC-based design tools licenses wanted
3084: 96/03/28: Re: Picdesigner--Archived Design Woes
3132: 96/04/09: Re: FPGA->ASIC conversion
3137: 96/04/11: Re: Help: logic design on a PC
3170: 96/04/18: Re: high gate count FPGA for small volumn production?
3171: 96/04/18: Re: Power consumption of Xilinx device
3215: 96/04/27: Re: high gate count FPGA for small volumn production?
3225: 96/04/29: Re: ECL, PECL gate arrays or FPGA's
3288: 96/05/09: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
3326: 96/05/13: Re: Windows NT & Xilinx & Cypress
3390: 96/05/23: Re: Xilinx and Viewlogic
3403: 96/05/25: Fwd: Xilinx Floorplanner
3411: 96/05/26: Re: FPGA tools
3457: 96/06/02: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3577: 96/06/30: FPGA ==> ASIC (GA and/or Std Cell)
Bob Feng:
60976: 03/09/26: Re: Graphics rendering
60977: 03/09/26: Re: Synchronous Binary counter question.
61024: 03/09/26: Re: Graphics rendering
62691: 03/11/05: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
Bob Fischer:
51339: 03/01/10: Interfacing to a PC using EPP parallel port
52143: 03/02/02: Re: Interfacing to a PC using EPP parallel port
56215: 03/05/30: Using FPGA to conduct novel device research & development
Bob Flatt:
8643: 98/01/15: Re: Using Xiling schematic library macro from VHDL
Bob Garrett:
70239: 04/06/09: Re: Nios II really available ?
Bob Golenda:
116619: 07/03/13: Programming XCF from MicroBlaze over JTAG???
116694: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
116695: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
116715: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
116737: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116743: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116744: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116836: 07/03/19: Re: Programming XCF from MicroBlaze over JTAG???
116845: 07/03/19: Re: Programming XCF from MicroBlaze over JTAG???
117144: 07/03/23: Re: Programming XCF from MicroBlaze over JTAG???
117214: 07/03/26: Re: Programming XCF from MicroBlaze over JTAG???
117215: 07/03/26: Re: Programming XCF from MicroBlaze over JTAG???
Bob Hoffman x8931:
2324: 95/11/20: Re: NeoCAD and AT&T vs. Xilinx
2325: 95/11/20: Re: Vendors For Verilog On The PC
Bob J. Conley:
8287: 97/12/05: HP Spokane R&D ASIC Project Manager
Bob Landers:
66: 94/08/08: Re: How pricey is FPGA development?
Bob McLeod:
570: 95/01/08: CFP Field Programmable Devices Workshop
Bob Monsen:
82553: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82555: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
90726: 05/10/19: Re: MAC Architectures
92677: 05/12/04: Re: Quick question, how do I supply +-5V?
92728: 05/12/05: Re: Quick question, how do I supply +-5V?
Bob Myers:
2532: 95/12/28: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
2575: 96/01/04: Solved -> Re: Need help: Actel "bibuf" working with Q
6865: 97/07/03: Re: fast scopes: how?
10958: 98/07/07: Need to know Xilinx M1.4's routing times -- large(?) designs
10966: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
10980: 98/07/08: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11048: 98/07/15: Re: Found problem -> Re: Need to know Xilinx M1.4's routing times...
11116: 98/07/20: Need info -> implementing high-speed multipliers
11972: 98/09/22: Anyone received Xilinx M1.5 yet???
14552: 99/02/04: Re: Opinions requested : Minc/Synario alternatives
87050: 05/07/13: Virtex 300: what could cause pin to short?
89270: 05/09/09: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89301: 05/09/12: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89468: 05/09/15: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
99363: 06/03/23: Re: Are Quad-processors advantageous?
Bob or Diana Lowell:
3675: 96/07/11: Free Altera Simulator
Bob Pearson:
17497: 99/08/02: Re: Semi-deterministic behaviour in FPGA's
17649: 99/08/18: map hang
17662: 99/08/20: Know how to instnatiate a LUT for Virtex?
Bob Perlman:
8044: 97/11/11: Re: switching between clock domains in Xilinx FPGA's
11886: 98/09/17: Re: sync or async SRAM?
12476: 98/10/13: Re: FOCUS FOCUS FOCUS
12507: 98/10/14: Re: FOCUS FOCUS FOCUS
12527: 98/10/15: Re: FOCUS FOCUS FOCUS
12810: 98/10/30: Re: FPGA Decouple Capacitor values
13787: 98/12/28: Re: 22V10 Metastability - help please
13820: 98/12/29: Re: 22V10 Metastability - help please
13838: 98/12/29: Re: 22V10 Metastability - help please
13859: 98/12/29: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14858: 99/02/20: Re: multiple clock domain problem
15026: 99/03/03: Re: Asynchronous resets: How tricky?
15042: 99/03/04: Re: Asynchronous resets: How tricky?
15234: 99/03/16: Re: Xilinx routing issue
15933: 99/04/22: Re: Altera: Exceeding maximum input rise/fall time
16210: 99/05/10: Re: Spartan Metastability parameters
16292: 99/05/14: Re: Synchronizer design?
17502: 99/08/02: Re: Warning! The eclipse approaches... {5.3a}
18607: 99/11/03: Re: StateCAD versus Viewdraw
18642: 99/11/04: Re: Input metastability
18686: 99/11/07: Re: Input metastability
18882: 99/11/19: Re: Virtex: Getting flip-flops into the pads
19005: 99/11/23: Re: VHDL vs. schematic entry
19067: 99/11/26: Re: HDL editor?
19252: 99/12/08: Re: constraints between clock domains: can't advance
19407: 99/12/20: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19436: 99/12/21: Re: Speed grade
19438: 99/12/21: Re: Necessary to 'synchronise' an asynchronous FSM reset?
19665: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
20040: 00/01/25: Re: Virtex Fine Pitch BGA pcb layout
20081: 00/01/26: Re: Virtex Fine Pitch BGA pcb layout
20160: 00/01/29: Re: Testbenches
20286: 00/02/03: Re: Xilinx Virtex Decoupling Cap Guidelines
20528: 00/02/13: Xilinx M2.1 Floorplanner Question
20653: 00/02/17: Re: Xilinx hold time problems...
20659: 00/02/17: Re: Xilinx hold time problems...
20739: 00/02/20: Re: Xilinx M2.1 Floorplanner Question
20970: 00/03/01: Re: Error in Xilinx application note XAPP131?
21995: 00/04/11: Re: Virtex E Pads Output Impedance
22006: 00/04/12: Re: Virtex E Pads Output Impedance
22510: 00/05/10: Re: SpartanXL driving 5V CMOS input
22515: 00/05/10: Re: SpartanXL driving 5V CMOS input
22880: 00/05/29: Re: question about logic simulator from Xilinx Foundation F2.1i
22904: 00/05/31: Re: question about logic simulator from Xilinx Foundation F2.1i
22919: 00/06/02: Where's OptiMagic?
22929: 00/06/03: Re: Microprocessors in FPGA
23067: 00/06/12: Re: Altera vs Xilinx
23091: 00/06/14: Re: FS: FpgaGuru.com DOMAIN
23201: 00/06/17: Re: spartan and virtex on the same board ?
23375: 00/06/23: Re: dual processor PC for PPR - are they worth the extra cost?
23391: 00/06/23: Re: Xilinx xc4000
23843: 00/07/12: Re: hold time errors in FPGA's ?
24382: 00/08/05: Re: some basic rules on FPGA design
24800: 00/08/18: Re: Fully contrained designs...
24847: 00/08/20: Re: Metastability measurement
24928: 00/08/22: Re: Mealy vs Moore FSM model
24932: 00/08/22: Re: Mealy vs Moore FSM model
24941: 00/08/22: Re: Mealy vs Moore FSM model
25104: 00/08/25: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25113: 00/08/26: Problem instantiating Xilinx primitives in FPGA Express
25125: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25139: 00/08/27: Re: FPGA power pins decoupling <-> PCB autorouting
25409: 00/09/10: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25665: 00/09/16: Re: Simon , decoupling caps
25693: 00/09/17: Re: MAX PLUS 2
25717: 00/09/18: Re: Reassurance on Xilinx Sought
25791: 00/09/20: Re: Simon , decoupling caps
26196: 00/10/07: Re: Long Island Verilog and VHDL people wanted!!
26296: 00/10/10: Re: Long Island Verilog and VHDL people wanted!!
26750: 00/10/26: Lazio Promises End to Long Island FPGA Crisis
26907: 00/11/03: Re: OT: Xilinx T-Shirt
28512: 01/01/16: Re: Virtex-II officially launched
28605: 01/01/18: Re: Virtex-II officially launched
28623: 01/01/18: Re: Virtex-II officially launched
29235: 01/02/10: Re: double precision floating point arithmetic
30443: 01/04/08: Re: Handel-C
31045: 01/05/10: Re: Shannon Capacity - An Apology
31458: 01/05/25: Re: spartan xl rise/fall time ?
32376: 01/06/25: Re: Date Code Problem?
32985: 01/07/14: Re: Xilinx BRAM failures
33223: 01/07/19: Re: Xilinx BRAM failures
35416: 01/10/03: Virtex II multiplier speed?
35705: 01/10/14: Re: how do I avoid glitches in this design?
35786: 01/10/17: Re: LUT Glitches
35846: 01/10/20: Re: Glitch Hunting, a true story ;-)
36011: 01/10/26: Re: LUT Glitches
36295: 01/11/05: Re: Xilinx ISE false timing errors?
37095: 01/11/29: Revised Virtex-II Timing Numbers
37759: 01/12/20: Re: Best-case timing?
37800: 01/12/20: Re: Best-case timing?
37827: 01/12/21: Re: Best-case timing?
38093: 02/01/04: Re: multiplexing a clock
38199: 02/01/08: Re: Repost: Should clock skew be included for setup time analysis?
38252: 02/01/10: Re: Repost: Should clock skew be included for setup time analysis?
38716: 02/01/23: Re: Virtex-II Programming Highs and Lows
38891: 02/01/28: Re: Simple shift register not working (update)
38936: 02/01/28: Re: Simple shift register not working (update)
39305: 02/02/06: Re: FPGA vs GAL : Lattice
39390: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
39515: 02/02/12: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
39527: 02/02/12: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
39893: 02/02/21: Re: Here is an argument and can anyone help me out
40696: 02/03/12: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
41012: 02/03/19: Re: High speed clock routing
41015: 02/03/19: Re: High speed clock routing
41108: 02/03/20: Re: High speed clock routing
41133: 02/03/21: Re: High speed clock routing
41165: 02/03/21: Re: High speed clock routing
41355: 02/03/26: Re: Xilinx 4.2i not working on my design
41924: 02/04/11: ChipScope Speed
42333: 02/04/20: Re: Xilinx Easypath- Selling parts with known defects
42600: 02/04/29: Re: Xilinx Easypath- Selling parts with known defects
42625: 02/04/29: Re: un-constraint path - from Clock pad to FFS clock pin
42661: 02/04/30: Re: simultaneous switching of LVPECL outputs
42670: 02/04/30: Re: simultaneous switching of LVPECL outputs
42685: 02/04/30: Re: simultaneous switching of LVPECL outputs
42721: 02/05/01: Re: simultaneous switching of LVPECL outputs
42728: 02/05/01: Re: simultaneous switching of LVPECL outputs
42740: 02/05/01: Re: simultaneous switching of LVPECL outputs
42789: 02/05/02: Re: simultaneous switching of LVPECL outputs
48450: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48453: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
49631: 02/11/18: Re: Metastability in FPGAs
49655: 02/11/18: Re: Metastability in FPGAs
49669: 02/11/19: Re: Metastability in FPGAs
49988: 02/11/27: Re: question about PCB traces for FPGA board... ?
51779: 03/01/21: Re: Virtex II: noise on Vcco causing loss of DCM lock
52272: 03/02/05: Re: Clock Enables
52382: 03/02/07: Re: LFSR: Galois and Fibonacci
53352: 03/03/11: Re: State of the PCB world
53509: 03/03/14: Re: more footprints...
53985: 03/03/29: Re: More xilinx webpack verilog questions: always @(clock) legal?
53989: 03/03/30: Re: More xilinx webpack verilog questions: always @(clock) legal?
54044: 03/04/01: Re: Input Characteristics : HCMOS vs TTL
54316: 03/04/08: Re: Q: Constraints for high speed I/O signals.
54331: 03/04/08: Re: Q: Constraints for high speed I/O signals.
54338: 03/04/08: Re: Q: Constraints for high speed I/O signals.
54852: 03/04/20: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
54876: 03/04/21: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55315: 03/05/03: Re: I want a 800 k gates FPGA in 40 pin DIL
55813: 03/05/20: Re: a (PC) workstation for FPGA development
55850: 03/05/21: Re: FPGA design: firmware or hardware?
55934: 03/05/23: Re: FPGA design: firmware or hardware?
55949: 03/05/24: Re: FPGA design: firmware or hardware?
56377: 03/06/04: Re: An FPGA is flying to Mars
56647: 03/06/10: Cheap development tools
56690: 03/06/11: Re: Cheap development tools
57041: 03/06/21: Re: Reducing synthesize time for state machines
57227: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57274: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57744: 03/07/05: Re: Excel and FPGA's
58817: 03/08/01: Re: Speed Grade...
59649: 03/08/25: Re: Thinking out loud about metastability
59658: 03/08/25: Re: Thinking out loud about metastability
59821: 03/08/28: Re: Thinking out loud about metastability
59883: 03/08/31: Re: Thinking out loud about metastability
59894: 03/08/31: Re: Thinking out loud about metastability
59922: 03/09/01: Re: Thinking out loud about metastability
60358: 03/09/11: Re: Time Killing Post P&R Simulation
61013: 03/09/26: Re: Synchronous Binary counter question.
61060: 03/09/26: Re: Synchronous Binary counter question.
61358: 03/10/02: Re: Good VHDL/Verilog editor?
61376: 03/10/02: Re: LVDS_25_DCI : Top Ten List
61956: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
62350: 03/10/27: Re: Are clock and divided clock synchronous?
62583: 03/11/02: Re: VHDL Xilinx Flow Engine ERROR
62709: 03/11/05: Re: Voila: Nedit macro to produce verilog module instantiations
63298: 03/11/19: Re: State Machines....
64277: 03/12/23: Re: Xilinx Johnson counter Verilog example bug?
64330: 03/12/29: Re: Spartan3 prices again...
64364: 03/12/30: Re: Spartan3 prices again...
64400: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64702: 04/01/12: Re: Synthesis in VHDL vs. Verilog
64735: 04/01/12: Re: Synthesis in VHDL vs. Verilog
64982: 04/01/18: Re: Can XILINX run in multiple instances?
65012: 04/01/19: Re: Spartan3 prices again...
65047: 04/01/19: Re: Can XILINX run in multiple instances?
65483: 04/01/30: Re: Where to get FPGA devices for testing?
66267: 04/02/16: Re: Plea for help - 29PL141
66276: 04/02/16: Re: Plea for help - 29PL141
66509: 04/02/20: Re: regarding synchronization
67205: 04/03/08: Re: FPGA hangs
67365: 04/03/10: Re: novice for FPGA
68582: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68980: 04/04/23: Re: Best Xilinx toolchains for under $2,000 ?
69636: 04/05/17: Re: Please, I need help with a mpeg layer 1 decoder in vhdl
70936: 04/07/02: Re: Xilinx $99 Spartan-3 kit
70957: 04/07/02: Re: Xilinx $99 Spartan-3 kit
70978: 04/07/03: Re: FPGAs starting with incorrect bitstream !?
71015: 04/07/05: Re: FPGAs starting with incorrect bitstream !?
71156: 04/07/10: Re: xilinx spartan 3 $99 board...help
71448: 04/07/18: Re: FPGAs starting with incorrect bitstream !?
72018: 04/08/05: Re: Comparing Quality of Results of FPGA CAD Tools
73042: 04/09/11: Re: Need some help with some technical claims...
73239: 04/09/16: Re: xdl tool, or Xilinx Design Language
73413: 04/09/21: Re: Understanding output width in signed multipliers
73668: 04/09/27: Re: Simple Counter in Verilog
75491: 04/11/07: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75497: 04/11/08: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75597: 04/11/10: Re: Xilinx Tshirts in football package.....
75702: 04/11/12: Re: constraints coverage
75972: 04/11/21: Re: 18x18 Multipliers - Spartan III
76747: 04/12/10: Re: Open source FPGA EDA Tools
77034: 04/12/20: Re: edk-chipscope 6.2 to 6.3 update
79368: 05/02/18: Re: FPGA Hardware/Cell Diagnostics
80587: 05/03/08: Re: Async FIFO problem...
80664: 05/03/09: Re: Async FIFO problem...
82935: 05/04/20: Re: Perl Preprocessor for HDL
83734: 05/05/06: Re: Multiply Accumulate FPGA/DSP
83770: 05/05/06: Re: Using capacitor to slow the rise time.
83835: 05/05/07: Re: Using capacitor to slow the rise time.
84429: 05/05/19: Re: About back annotated simulations...
84549: 05/05/20: Re: Bullshit Achieves Literary Status
84702: 05/05/24: Re: how to apply different stimulus files to a test bench
84851: 05/05/30: StateCAD 7.1i is broken?
85324: 05/06/07: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85345: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85383: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85548: 05/06/10: Re: computer upgrade time.
85895: 05/06/17: Re: comp.arch.fpga.<mfr>
86482: 05/06/29: Re: V4 and NBTI question, again..
87157: 05/07/18: Re: "Tbufs don't exist"
87352: 05/07/22: Re: Xilinx software update?
87496: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
88037: 05/08/07: Re: Xilinx V4 & DDR2 Memory Interface
88376: 05/08/16: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88923: 05/08/31: Re: Gated clock for FPGA (verilog)???
89621: 05/09/21: Re: Xilinx ISE Passing IO pad attributes using UCF file.
90106: 05/10/05: Re: Avoiding meta stability?
90192: 05/10/06: Re: Avoiding meta stability?
90287: 05/10/08: Re: Question about metastability that's been on my mind for a while
90297: 05/10/09: Re: Question about metastability that's been on my mind for a while
91269: 05/11/02: Re: Newbie. Clocks.
91496: 05/11/07: Re: Verilog Editor.
91604: 05/11/09: Re: Best Case Timing Parameters
91670: 05/11/10: Re: Is this even true???
91804: 05/11/13: Re: Verilog Editor.
91834: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91950: 05/11/17: Re: Suggestions on good books
91953: 05/11/17: Re: Suggestions on good books
92053: 05/11/21: Re: Modelsim Verification : Retain FSM state names
92073: 05/11/21: Re: Modelsim Verification : Retain FSM state names
92448: 05/11/29: Re: first time managing a project
93001: 05/12/11: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93585: 05/12/25: Re: More beginner's verilog questions
93586: 05/12/25: Re: More beginner's verilog questions
94521: 06/01/12: Re: SDRAM Clock Skew
94607: 06/01/13: Re: FPGA Journal Article
94602: 06/01/13: Re: how do I minimize the logic in this function?
94973: 06/01/19: Re: OT:Shooting Ourselves in the Foot
95726: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95832: 06/01/26: Re: Stop. Go. Yield.
97123: 06/02/16: Re: state-of-the-art schematic generation? [Was: SCHEMATICS ... ]
97233: 06/02/19: Re: FPGA - software or hardware?
97308: 06/02/20: Re: Is FPGA code called firmware?
97378: 06/02/21: Re: Is FPGA code called gateware?
98418: 06/03/09: Re: FIFO Simulation Oddities!
98597: 06/03/13: Re: Why does Xilinx hate version control?
99054: 06/03/19: Re: Urgent Help Needed!!!!!
99355: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
99389: 06/03/23: Re: Timing Diagram software recommendations?
99563: 06/03/26: Re: Simple ADS5273 -> Xilinx Interconnect Model
100192: 06/04/04: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
100584: 06/04/12: Re: FPGA FAQ and the spam problem
100600: 06/04/12: Re: timing constraints ?
100965: 06/04/21: Re: Xilinx DCI resistor placement guidelines
101151: 06/04/26: Re: Async FPGA ~2GHz
102307: 06/05/14: Re: How to check IOB register packing?
102880: 06/05/22: Re: xilinx pricing discrepancy
104830: 06/07/06: Re: debouncing a switch (in hardware)
105162: 06/07/15: Re: Need for reset in FPGAs
105265: 06/07/19: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
105343: 06/07/20: Re: tutorial searching
105349: 06/07/20: Re: Last Chance for Tarfessock1 Features
105377: 06/07/20: Re: Hardware book like "Code Complete"?
106174: 06/08/08: Re: Who is your favourite FPGA guru?
106599: 06/08/15: Re: Reset asynchronous assertion synchronous deassertion
108830: 06/09/17: Re: Spartan3: Multiplier Madness
109381: 06/09/25: Re: state machine dead problem
109449: 06/09/26: Re: PERISHABLE PAPER RELATED TO FPGA!
109888: 06/10/06: Re: a clueless bloke tells Xilinx to get a move on
109949: 06/10/08: Re: An implementation of a clean reset signal
110003: 06/10/09: Re: An implementation of a clean reset signal
110022: 06/10/09: Re: An implementation of a clean reset signal
111285: 06/10/31: Spectre of Metastability Update
111322: 06/11/01: Re: Spectre of Metastability Update
114065: 07/01/03: Re: Surface mount ic's
114117: 07/01/04: Re: OT. Re: Surface mount ic's
114221: 07/01/07: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
114223: 07/01/07: Re: (-1)*xn operation in FPGA
114905: 07/01/25: Re: Timing Diagram Tool
116096: 07/03/01: Re: Bypass caps, X2Y and 'puddles'.
117806: 07/04/10: Re: Ross Freeman - inventor of the FPGA
119151: 07/05/13: How to Ask a Question
119177: 07/05/14: Re: How to Ask a Question
121745: 07/07/12: Re: Designing the right clock tree for a multi-FPGA setup
123631: 07/08/31: Re: PCB Impedance Control
124235: 07/09/15: Re: Beginner Advice (Languages, tools etc.)
124269: 07/09/17: Re: Beginner Advice (Languages, tools etc.)
124446: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
127438: 07/12/24: Re: FPGA Project Support
128490: 08/01/28: Power Supply Bypassing Presentation
132804: 08/06/06: Re: Xilinx cuts 250 jobs.
141685: 09/07/03: Re: USB Book
150919: 11/02/21: Re: timing issues at high speed
150957: 11/02/24: Re: timing issues at high speed
152337: 11/08/10: Re: LUT glitches (was Re: ISE bug?)
152735: 11/10/15: Re: Spartan changes in glitch sensitivity
152739: 11/10/15: Re: Spartan changes in glitch sensitivity
153069: 11/11/25: Re: XC7V2000T, the perfect Thanksgiving gift
bob prohaska:
158773: 16/04/08: Re: FPGA Internal or external USB PHY/SIE ??
Bob Sakamoto:
144270: 09/11/23: Re: Virtex 5 ISERDES
Bob Sefton:
13303: 98/11/25: Re: Which parts are fastest for 3-state enables?
13304: 98/11/25: Re: daisy chain help!!!!
13340: 98/11/26: Re: Which parts are fastest for 3-state enables?
13353: 98/11/30: Re: Will XILINX survive?
13361: 98/11/30: Re: Will XILINX survive?
13374: 98/11/30: Re: Will XILINX survive?
13381: 98/11/30: Re: Will XILINX survive?
13680: 98/12/18: Re: Anyone simulate a JEDEC PAL file in Viewsim???
13699: 98/12/18: Re: GSR
13706: 98/12/19: Re: GSR
13764: 98/12/23: Re: PLL in FPGAs?
13816: 98/12/28: Re: 22V10 Metastability - help please
14015: 99/01/07: Re: fpga socket
14756: 99/02/15: Re: M1 error message
14758: 99/02/15: Re: Problems with Xilinx F1.5 & latchs
15023: 99/03/03: Re: Clock divider: 100MHz->40MHz
15034: 99/03/03: Re: Clock divider: 100MHz->40MHz
15039: 99/03/03: Re: Asynchronous resets: How tricky?
15045: 99/03/04: Re: Clock divider: 100MHz->40MHz
15453: 99/03/24: Re: HDL-307 error
15764: 99/04/13: Re: Lattice
15965: 99/04/23: Re: Timing Constraint
15997: 99/04/27: Re: Timing Constraint
16092: 99/05/02: Re: Counters
16394: 99/05/20: Re: Xilinx M1.5 Crash
16461: 99/05/24: Re: Xilinx M1.5 Crash
Bob Smith:
101035: 06/04/24: Re: ISE 8.1i for Linux ?
103480: 06/06/03: Re: WebPack on Linux
113820: 06/12/23: Re: What next next big thing coming for HDL?
123381: 07/08/26: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
123422: 07/08/28: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate"
123677: 07/09/01: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate"
125552: 07/10/29: Xilinx xflow for the ISE Quickstart Tutorial project?
125555: 07/10/28: Re: Xilinx xflow for the ISE Quickstart Tutorial project?
127518: 08/01/01: Sparkfun FPGA board ?
128291: 08/01/20: Sparkfun Spartean3e Board
129164: 08/02/16: Linux and the Digilent Basys ?
129212: 08/02/18: Re: Linux and the Digilent Basys ?
129421: 08/02/23: Xilinx DCM for frequency synthesis -- newbie question
129431: 08/02/23: Re: Xilinx DCM for frequency synthesis -- newbie question
129438: 08/02/24: Re: Xilinx DCM for frequency synthesis -- newbie question
129442: 08/02/24: Re: Xilinx DCM for frequency synthesis -- newbie question
129483: 08/02/25: Re: Xilinx DCM for frequency synthesis -- newbie question
129523: 08/02/26: Re: Xilinx DCM for frequency synthesis -- newbie question
130932: 08/04/05: Re: Protecting design from being downloaded on other (similar) FPGA
134912: 08/09/06: Best way to buy Xilinx FPGAs?
134921: 08/09/07: Re: Some feedback on the Xilinx web site
134929: 08/09/07: Re: Best way to buy Xilinx FPGAs?
137331: 09/01/08: Re: New to FPGA's, please help
137333: 09/01/08: ANN: Linux friendly FPGA dev board
137341: 09/01/09: Re: Linux friendly FPGA dev board
137359: 09/01/10: Re: Linux friendly FPGA dev board
138011: 09/02/03: Sixteen serial ports ?
138063: 09/02/04: Re: Sixteen serial ports ?
138606: 09/03/01: Re: Send data from FPGA to PC via USB
141784: 09/07/08: web alternatives to USENET comp.arch.fpga
143783: 09/10/25: Re: CPLD/FPGA with Linux
144504: 09/12/11: Re: Spartan 3E starter Kit
145976: 10/03/02: Re: FPGA platform??
145978: 10/03/02: Re: FPGA platform??
148446: 10/07/23: Re: Parallel Cable IV under Ubuntu Linux 10.04
148840: 10/09/01: Re: Want to get into FPGA
150055: 10/12/08: Re: Getting libusb-driver to work with Xilinx dev board.
Bob Stephens:
64510: 04/01/06: Re: 4-bit binary divider circuit PLEASE!!!!!!!
65617: 04/02/03: Re: 4 bit divisor with flip-flop ?
65618: 04/02/03: Re: 4 bit divisor with flip-flop ?
95088: 06/01/20: Re: OT:Shooting Ourselves in the Foot
Bob Sugar:
4642: 96/11/25: Re: Moore vs Mealy state machines
16241: 99/05/11: Re: Synchronizer design?
Bob W:
45099: 02/07/12: Question: Xilinx schematic entry, constants, bit swapping
47959: 02/10/08: Why can Xilinx sw be as good as Altera's sw?
47979: 02/10/09: Re: Why can't Altera sw be as good as Xilinx's sw?
47981: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
47982: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
47985: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
47986: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
47987: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
Bob Wagner:
19758: 00/01/11: Re: Lucent Orca designs
19760: 00/01/11: Re: orca3t125 clock problems
Bob Walance:
7139: 97/08/05: Re: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
8115: 97/11/18: Re: XC: bitfile to ASCII file
Bob Warnke:
23212: 00/06/17: Control System Engineering Jobs
Bob Weber:
18161: 99/10/04: ABEL for CPLD Design
18227: 99/10/08: Re: Altera 10K50V in-rush/temp problem...
Bob Widlicka:
65175: 04/01/21: MACH5 eval board - doc needed
Bob Wilson:
4715: 96/12/05: Re: Looking for hc0324
4727: 96/12/06: Re: Looking for hc0324
4748: 96/12/10: Re: Looking for hc0324
bob winters:
3483: 96/06/06: Is someone using...
Bob Woolley:
45822: 02/08/06: CUPL S/N?
45851: 02/08/07: Re: CUPL S/N?
45853: 02/08/07: Re: Lattice GAL22V10 and everything it entails . . . !
<bob.zigon@gmail.com>:
122351: 07/07/25: Why is Xilinx XPS 8.2i so slow?
122544: 07/07/30: Looking for 2 simple Xilinx examples of FSL
122571: 07/07/31: Upgrading from EDK 8.1 to EDK 9.1i
122725: 07/08/04: Confused about my behavioral simulation under ISE 9.1
<boB>:
150866: 11/02/16: Re: Xilinx USB programming cable.
<bob@zeidmanconsulting.com>:
57807: 03/07/07: Beta sites needed
<bob_42690@my-deja.com>:
20004: 00/01/22: Re: Virtex Fine Pitch BGA pcb layout
24996: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25152: 00/08/29: Re: availability of Spartan II
25742: 00/09/19: Re: Xilinx Web Pack
25821: 00/09/22: Re: Alliance 3.1i CAE Libs install hangs under Solaris
25955: 00/09/28: Re: FPGA Express strikes again! Xilinx response
26008: 00/09/30: Re: FPGA Express Strikes Again!
26035: 00/10/01: Re: Altera FPGA experts needed
26073: 00/10/03: Re: FPGA Express strikes again! Xilinx response
26247: 00/10/10: Re: Analogue FPGAs ?
26248: 00/10/10: Re: ModelSim XE/Starter speed issues
27345: 00/11/19: Re: Microprocessor Verilog/VHDL Models
27837: 00/12/12: Re: Altera free development tools
<Bob_Myers@raytheon.com>:
59072: 03/08/07: Need help: getting 3.1i Coregen working on P4-system
Bobby Sardana:
55467: 03/05/08: [Altera or Xilinx] Questions
<bobda@cs.fau.de>:
61223: 03/09/30: Reconfiguration via SelectMap on the RC1000
<bobdittmar@my-deja.com>:
27960: 00/12/18: Re: Verilog or VHDL
27961: 00/12/18: Re: dual port ram for altera
27991: 00/12/19: Re: dual port ram for altera
28015: 00/12/19: Re: dual port ram for altera
BobG:
105687: 06/07/28: Re: Hardware book like "Code Complete"?
BobH:
152478: 11/08/28: Re: Very cheap Spartan3 board that can be configured by simple USB
152492: 11/08/28: Re: Very cheap Spartan3 board that can be configured by simple USB
152722: 11/10/09: Re: high speed place and route about xilinx
152964: 11/11/05: Re: PCI Express development board
152968: 11/11/05: Re: PCI Express development board
154052: 12/07/22: Re: Interface Xilinx KC705 to BeagleBone?
154062: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154063: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154067: 12/07/26: Re: Strange behavior with counter (decreases instead of increasing)
154072: 12/07/29: Re: Spartan 6 IBERT confusion
154075: 12/07/30: Re: Spartan 6 IBERT confusion
154357: 12/10/13: Re: My First CPU but.. one problem
154489: 12/11/17: Re: question about verilog ?, :
154959: 13/03/03: Re: Xilinx XST and initializing block RAMs
156523: 14/04/14: Re: more than 58'000 false paths...
156533: 14/04/15: Re: more than 58'000 false paths...
156795: 14/06/29: Re: [cross-post] dither generator on fpga
156801: 14/06/30: Re: [cross-post] dither generator on fpga
157872: 15/05/01: Re: Spartan-3 stater kit
157878: 15/05/06: Re: Spartan-3 starter kit
158185: 15/09/11: Re: low-level vs. high-level
158218: 15/09/18: Re: low-level vs. high-level
158451: 15/11/30: Re: Simulation vs Synthesis
158457: 15/11/30: Re: Simulation vs Synthesis
158473: 15/12/01: Re: Simulation vs Synthesis
158474: 15/12/01: Re: Simulation vs Synthesis
158483: 15/12/02: Re: Simulation vs Synthesis
158484: 15/12/02: Re: Simulation vs Synthesis
158506: 15/12/04: Re: Simulation vs Synthesis
158508: 15/12/05: Re: Simulation vs Synthesis
158599: 16/01/19: Re: Fully preposterous gate arranger
158620: 16/02/04: Re: Fully preposterous gate arranger
158885: 16/05/14: Re: Constraining data to out-of-phase clocks
158886: 16/05/14: Re: Recoding openCV C++ project in pure verilog
158903: 16/05/16: Re: Constraining data to out-of-phase clocks
158904: 16/05/16: Re: Constraining data to out-of-phase clocks
158906: 16/05/16: Re: Constraining data to out-of-phase clocks
158933: 16/05/25: Re: Explicitly setting a variable to undefined
159102: 16/07/29: Re: pin configuration for I2C on altera Max 10 using i2c_opencores IP
159230: 16/09/05: Re: eliminating a DDS
159321: 16/10/05: Re: How do I preserve Hazard safety terms?
159343: 16/10/13: Re: CORDIC in a land of built-in multipliers
159574: 17/01/02: Re: Slightly OT: Digital watch circuits
159577: 17/01/02: Re: Slightly OT: Digital watch circuits
159652: 17/01/25: Re: Anyone use 1's compliment or signed magnitude?
159664: 17/01/26: Re: Anyone use 1's compliment or signed magnitude?
159678: 17/01/27: Re: Anyone use 1's compliment or signed magnitude?
159944: 17/05/01: Re: RISC-V Support in FPGA
160041: 17/05/16: Re: Configuration fault recovery
160051: 17/05/17: Re: Configuration fault recovery
160052: 17/05/17: Re: Test Driven Design?
160079: 17/05/19: Re: Test Driven Design?
160099: 17/05/25: Re: fpga zigbee interface
160389: 18/01/10: Re: HDL simple survey - what do you actually use
160405: 18/01/13: Re: HDL simple survey - what do you actually use
160410: 18/01/16: Re: HDL simple survey - what do you actually use
bobi:
60202: 03/09/08: FPGA start?
60588: 03/09/17: Re: Digilent board
BobJ:
84648: 05/05/23: Re: Jobs going in New Zealand
bobpainter:
157858: 15/04/21: Re: FPGA / DSP - Urgent need in Orange County, CA
bobrics:
86580: 05/06/30: Re: PROM Generation question
86583: 05/06/30: Re: Clock buffering in VirtexE FPGA
86686: 05/07/04: Re: Clock buffering in VirtexE FPGA
87082: 05/07/14: Re: Clock buffering in VirtexE FPGA
87961: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
90771: 05/10/20: "Cannot synthesize logic..." ERROR
90772: 05/10/20: Re: "Cannot synthesize logic..." ERROR
90795: 05/10/21: RISC pipelining question
90797: 05/10/21: Re: "Cannot synthesize logic..." ERROR
99145: 06/03/20: FATAL_ERROR while creating a test bench waveform (ISE WebPack 8.1.01i)
99486: 06/03/24: Test bench waveform bug
99645: 06/03/27: ERROR:Xst:827 - bad synchronous description
99660: 06/03/27: Re: ERROR:Xst:827 - bad synchronous description
99661: 06/03/27: WARNING:Xst:1778 - Inout <AddrBus>
99663: 06/03/27: Re: WARNING:Xst:1778 - Inout <AddrBus>
100124: 06/04/03: Re: WARNING:Xst:1778 - Inout <AddrBus>
138776: 09/03/10: Verify failed between adress... problem
139442: 09/03/30: Problems with include paths in Eclipse, Nios2, Altera
<bobrics@gmail.com>:
79472: 05/02/19: why to use FIFO on FPGA?
<bobster.thelobster@yahoo.co.nz>:
129018: 08/02/12: Re: ModelSim versus Active-HDL....redux
129071: 08/02/13: Re: State machine outputs and tri-state
129072: 08/02/13: Re: State machine outputs and tri-state
129073: 08/02/13: Re: Virtex-5 User Guide "Lite"
BobSun:
2071: 95/10/10: Re: Good materials schools?
BobW:
124628: 07/09/28: Re: LVDS clock management
124826: 07/10/05: Virtex 13?
124849: 07/10/07: Re: JTAG interconnect testing, prototypes
125810: 07/11/05: Re: not totally repulsive
125829: 07/11/06: Re: not totally repulsive
125846: 07/11/06: Re: not totally repulsive
125847: 07/11/06: Re: not totally repulsive
126171: 07/11/16: Re: newbie to 16v8
126945: 07/12/06: Re: student requiring assistance :)
127311: 07/12/17: Re: Xilinx DCM outputs for DDR
127368: 07/12/19: Re: Xilinx DCM outputs for DDR
128010: 08/01/12: Re: Virtex4 burn-in failure
128528: 08/01/29: Re: Spartan3 I/O question
129180: 08/02/17: Re: Antti needs a job
129184: 08/02/17: Re: Antti needs a job
129367: 08/02/21: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129403: 08/02/22: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129702: 08/03/03: Re: Virtex-5 FXT coming soon?
130430: 08/03/23: Re: counterfeit Xilinx ?
130442: 08/03/24: Re: counterfeit Xilinx ?
130498: 08/03/25: Re: counterfeit Xilinx ?
130517: 08/03/26: Re: Serial Transmission w/o 8B/10B encoding
130547: 08/03/26: Re: Places to visit in Amsterdam and Brussells
130549: 08/03/26: Re: Places to visit in Amsterdam and Brussells
130553: 08/03/26: Re: Places to visit in Amsterdam and Brussells
131611: 08/04/25: Re: Virtex-4 inrush power-on current
131932: 08/05/07: Re: ANNC: FPGA Design Software Webcast
131966: 08/05/08: Re: Virtex XCV1000E-6FG860C
131990: 08/05/09: Re: ANNC: FPGA Design Software Webcast
133006: 08/06/12: Re: Trouble programming V4FX40
133122: 08/06/18: Re: Xilinx Webpack
135749: 08/10/14: Re: About the jitter of Xilinx Virtex-5's DCM output
136177: 08/11/04: Re: Tiny JTAG connector
137426: 09/01/15: Re: Webpack 10.1 on Windows XP
137617: 09/01/23: Re: Altera 3000A: Can I make a freq. generator (1 Hz to 2 kHz) ?
139189: 09/03/22: Re: Spartan 3 LVDS
140719: 09/05/22: Re: SPAM?
141890: 09/07/15: Re: How to implementa an FSM in block ram
142006: 09/07/21: Re: Spartan 3 and DDR2
142112: 09/07/24: Re: Spartan 3 and DDR2
142116: 09/07/25: Re: Spartan 3 and DDR2
142281: 09/08/01: Re: Single ended LVDS into FPGA
142283: 09/08/01: Re: Single ended LVDS into FPGA
142340: 09/08/05: Re: Driving Multiple FPGAs and Fanout (Cyclone III)
152753: 11/10/18: Re: Altera FPGA weirdness
152758: 11/10/19: Re: Altera FPGA weirdness
Bochumfrau@gmx.de:
65153: 04/01/21: Synthesis of Loops
65215: 04/01/22: Re: Synthesis of Loops
BODDU:
112636: 06/11/26: QPROM in FPGA
BODDU Lokesh:
112980: 06/12/03: Re: wanted: FPGA programmer
115051: 07/01/29: Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
-Bodnar,B.L.:
6949: 97/07/14: Re: Generating Sine/Cosine digitally
Bodo:
155097: 13/04/13: XILINX Artix-7
155166: 13/05/18: XILINX Artix-7 DDR2-RAM-Controller
Bogdan Paraschiv:
128286: 08/01/20: Re: Drigmorn1 - The Cheapest FPGA Development Board???
<bogilvie@mathworks.com>:
153655: 12/04/10: Re: Data Transfer from PC to FPGA through USB
boh!:
97190: 06/02/18: Re: DDR SDRAM Controller
<bohr_singh@hotmail.com>:
91702: 05/11/10: SDRAM controller.
94451: 06/01/11: Active Silicon Frame Grabber and IMPACT ...
Bojan:
56814: 03/06/16: FPGA and SDRAM interface
57803: 03/07/07: CPSR register
Boki:
69163: 04/04/29: VHDL / Verilog circuits work in 1-V still correct?
boki:
69184: 04/04/29: Re: VHDL / Verilog circuits work in 1-V still correct?
boku0712@gmail.com:
83285: 05/04/26: Warning appeared while inferring SRAM on xilinx Virtex-E by synplify 7.3.1
<boled>:
115067: 07/01/30: How to use the test bench wave form simulator?
115086: 07/01/30: Re: How to use the test bench wave form simulator?
115094: 07/01/30: Re: How to use the test bench wave form simulator?
Bolis:
38640: 02/01/20: Nios development kit
38641: 02/01/20: Re: Nios development kit
bommels:
131656: 08/04/28: Re: CRC algorithm
132671: 08/06/05: Re: Using ethernet on a Xilnx board (Help appreciated)
134811: 08/09/02: Re: FPGA package size chart (smallest) Xilinx holds 8th place
134815: 08/09/02: Re: FPGA package size chart (smallest) Xilinx holds 8th place
<bompf@my-deja.com>:
23621: 00/07/03: LCD-Controller
Bond:
1153: 95/05/07: Re: IOLOC or Other Xilinx Tools
1280: 95/05/26: Re: What's happening with NeoCAD?
1322: 95/06/01: Re: What's happening with NeoCAD?
141005: 09/06/02: the reach of VHDL
141074: 09/06/04: Re: the reach of VHDL
143471: 09/10/12: integrating chipscope pro in EDK
144048: 09/11/09: Serial interface between PC and FPGA using matlab
144183: 09/11/18: Re: about create or import pheripheral in EDk
Bond , James:
1677: 95/08/15: Re: Xilinx xc4013 routing problems ??
1724: 95/08/20: Re: Xilinx xc4013 routing problems ??
Bond, James:
1382: 95/06/10: Re: Xblox oo !!!!
bonetiger:
72671: 04/08/27: 16-depth FIFO and 64-depth FIFO use the same Ram
bonf:
147895: 10/05/31: Re: Virtex 7?
Bong-Jin Seo:
26821: 00/10/31: The Xilinx Design tools for the customly designed SRAM-based FPGA
<bonics@my-dejanews.com>:
11184: 98/07/23: C- interface
11230: 98/07/28: leapfrog wavform
11249: 98/07/30: VHDL code
Bonio Lopez:
18806: 99/11/17: COM1-FPGA communication
18842: 99/11/18: Not complett multipier LUT in FPGA
18843: 99/11/18: Re: Not complett multipier LUT in FPGA
19012: 99/11/24: Non-dedicated clock
19044: 99/11/25: async latch implementation in Leonardo
19048: 99/11/25: Re: async latch implementation in Leonardo
19051: 99/11/25: Re: async latch implementation in Leonardo
19060: 99/11/26: How one can use level sensitive latches
19130: 99/12/01: Re: Timing constraint not met
19151: 99/12/02: Question to synplicity users and other not Leonardo users,
19155: 99/12/02: Connection of light diode and FPGA
19209: 99/12/06: Re: Problems with routing Virtex device
19261: 99/12/09: Re: constraints between clock domains: can't advance
19380: 99/12/17: JEDEC
19431: 99/12/21: AMD FLASH ?
19434: 99/12/21: Re: AMD FLASH ?
19494: 99/12/27: How can I preset /prereset some Latches
19505: 99/12/28: Re: xilinx help *desperately* needed
19525: 99/12/29: Re: xilinx help *desperately* needed
19549: 99/12/30: License of Atmel free CD ROM Software
19987: 00/01/20: Re: help: signal stuck at 'U' inside generate statement
20105: 00/01/27: Why Sinplicity make combinatorial loops from latches ?
20137: 00/01/28: Re: Why Sinplicity make combinatorial loops from latches ?
<boniolopez@my-deja.com>:
20293: 00/02/04: PMUX primitive in Sinplify
20436: 00/02/10: links about partitioning.
21153: 00/03/08: links about design verification
21367: 00/03/20: relationship of gates quantity for the same design in FPGA (Virtex) and ASIC.
21370: 00/03/20: Clock nets using non-dedicated resources
21381: 00/03/21: Re: Synthesis error
21385: 00/03/21: Re: Clock nets using non-dedicated resources
21389: 00/03/21: Re: Clock nets using non-dedicated resources
21390: 00/03/21: Re: Clock nets using non-dedicated resources
21416: 00/03/22: Re: Clock nets using non-dedicated resources
21418: 00/03/22: Re: Clock nets using non-dedicated resources
21419: 00/03/22: Re: Clock nets using non-dedicated resources
21429: 00/03/22: Re: Clock nets using non-dedicated resources
21430: 00/03/22: Re: Clock nets using non-dedicated resources
21431: 00/03/22: Re: Clock disabling
21782: 00/03/31: Re: Clock nets using non-dedicated resources
22344: 00/05/05: Your opinion Arexsys design tools and SDL description methodology
bonnerfme:
137258: 09/01/06: NGC and RTL into the same FPGA device
142005: 09/07/21: Is it possible to encrypt an existing bit file with BitGen?
144278: 09/11/24: Deskew Reginal clock input
144285: 09/11/24: Re: Deskew Reginal clock input
Boogie:
23590: 00/07/01: How much would a PCI core be worth?
<boosterat@kjgpnyqv.ca>:
11835: 98/09/12: Warning: Strange activity alert.
booth multiplier:
54496: 03/04/11: An Improvement for the Booth multiplier
54592: 03/04/14: Re: An Improvement for the Booth multiplier
54672: 03/04/15: Re: An Improvement for the Booth multiplier
<boothmultipler@hotmail.com>:
85982: 05/06/19: Retrieving code from an old PAL
bootrecord:
8811: 98/01/27: xilinx M1 protection
Borge:
111873: 06/11/12: Power-on reset
111885: 06/11/12: Re: Power-on reset
111888: 06/11/12: Re: Power-on reset
118695: 07/05/02: Area constraint - trust Low Level Synthesis?
119085: 07/05/11: Uart problem, xapp223 + Spartan3A
Boris:
37229: 01/12/04: Triscend E5 vs Atmel FPSLIC
Boris and Cristi Sheikman:
43905: 02/06/05: How to find a big, EEPROM based CPLD in a PGA package?
Boris Foelsch:
52123: 03/02/01: Re: Clock Feedback for DDR-SDRAM (XApp200)
52185: 03/02/03: Re: Clock Feedback for DDR-SDRAM (XApp200)
52186: 03/02/03: Re: Clock Feedback for DDR-SDRAM (XApp200)
Boris Isakhanov:
14991: 99/03/02: Re: LCD driver
Boris Mohar:
53451: 03/03/13: Re: footprints
Borked Pseudo Mailed:
111707: 06/11/08: xilinx spartan timing model
Borneq:
160187: 17/08/02: Alternative for LUT?
160188: 17/08/02: What kit for SPARTAN-3?
Borodin S.V.:
531: 94/12/23: Xilinx Configuration
770: 95/02/27: Re: Lattice ispLSI starter kit
BoroToro:
101786: 06/05/06: Spartan 3e starter kit & Multimedia
102044: 06/05/09: Re: Spartan 3e starter kit & Multimedia
<Borry.Wang@gmail.com>:
106413: 06/08/12: Virtex 4 could not work correct,is it damaged?
boru:
101446: 06/05/01: ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'
101550: 06/05/02: boundary scan through Virtex
Bose:
62189: 03/10/21: Verilog Encounted Errors
62313: 03/10/26: Verilog Program With A Problem
62482: 03/10/30: Xilinx XC95108 Chip
62499: 03/10/30: Re: Xilinx XC95108 Chip
botao:
52857: 03/02/24: Re: fe_shell.exe needed
Botond Kardos:
7299: 97/08/22: Re: ISP Stories
7298: 97/08/22: Re: ISP Stories
10923: 98/07/01: Power consumption question
10928: 98/07/03: Re: Power consumption question
11360: 98/08/06: Negative pulse form Altera FPGA's ?
11425: 98/08/12: Re: Negative pulse form Altera FPGA's ? - to: Tullio Grassi
12209: 98/10/05: Test 8
12210: 98/10/05: Test 11
12211: 98/10/05: Test 13
12212: 98/10/05: Test 14
12213: 98/10/05: Test 18
12214: 98/10/05: Design security again - the Actel solution
12215: 98/10/05: Re: Design security again - the Actel solution
12443: 98/10/12: Re: Design security again - the Actel solution
20429: 00/02/10: SRAM part question
<botond@hotmail.com>:
10306: 98/05/11: Re: Low power FPGA design
Boudewijn Dijkstra:
108009: 06/09/04: Re: Please help me with (insert task here)
126806: 07/12/03: Re: lossless compression in hardware: what to do in case of uncompressibility?
126841: 07/12/04: Re: lossless compression in hardware: what to do in case of uncompressibility?
126868: 07/12/05: Re: lossless compression in hardware: what to do in case of uncompressibility?
126875: 07/12/05: Re: lossless compression in hardware: what to do in case of uncompressibility?
153044: 11/11/21: Re: Production Programming of Flash for FPGAs and MCUs
157638: 15/01/12: Re: [cross-post] nand flash bad blocks management
157641: 15/01/13: Re: [cross-post] nand flash bad blocks management
Bouh:
52125: 03/02/02: FPGA Overclocking
52133: 03/02/02: Re: FPGA Overclocking
Boumjin Park:
17593: 99/08/12: VSS error : couldn't find root
<bourdeau@dsuper.net>:
7308: 97/08/24: PLD Programmer Royal EV6000
7311: 97/08/24: PLD Programmer Royal EV6000
Bourguiba Riad:
15592: 99/04/02: Does any one want to talk about Dynamic Configuration?
15593: 99/04/02: Does any one want to discuss about dynamic configuration?
bouthouri:
147270: 10/04/21: multiboot spartan3E
<boxi.yang@gmail.com>:
103618: 06/06/06: API on Virtex 4 FPGA or the email of Delon Levi wanted
103692: 06/06/08: Re: API on Virtex 4 FPGA or the email of Delon Levi wanted
bp:
93435: 05/12/21: Re: Cypress FX2 bandwidth problem
BQ:
84861: 05/05/31: Problems with SDRAM and Altera Cyclone
84871: 05/05/31: Re: Problems with SDRAM and Altera Cyclone
84872: 05/05/31: Re: Problems with SDRAM and Altera Cyclone
86147: 05/06/22: Frequency divisors
Braam:
17048: 99/06/28: Re: Read/Writes to memories/register files for PIC core
Brac:
100102: 06/04/03: Virtex-4 readback via ICAP
Brad:
43178: 02/05/15: xilinx foundation 2.1 RPC problem on win2000
47038: 02/09/16: FPGA work in the Bay Area (CA)?
82837: 05/04/18: Spartan 3E availability
148961: 10/09/15: Providing FPGA-specific evaluation IP
151791: 11/05/18: Re: J1 forth processor in FPGA - possibility of interactive work?
151799: 11/05/18: Re: J1 forth processor in FPGA - possibility of interactive work?
151800: 11/05/18: Re: J1 forth processor in FPGA - possibility of interactive work?
152863: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
Brad and Renea Ree:
5883: 97/03/22: Re: FIFOs
Brad Eckert:
7674: 97/10/02: Wanted: cheap way to learn VHDL
37007: 01/11/28: FPGA startup current
37034: 01/11/28: Re: FPGA startup current
37944: 01/12/26: ROM die area question
37983: 01/12/28: Spartan LUT question
38042: 02/01/02: Re: Verilog code
38085: 02/01/04: Re: A Fast counter in VHDL?
38190: 02/01/08: ROM synthesis question
38555: 02/01/17: CoreGen question
38591: 02/01/18: Re: CoreGen question
50478: 02/12/11: Power consumption question
52481: 03/02/11: XST choking hazard
53088: 03/03/03: Re: How to select the chip before using FPGA?
55423: 03/05/07: Re: OT: looking for I/Q mixers/modulators for TX and RX
57154: 03/06/24: Re: How to get 27MHz from 10 MHz in FPGA???
58020: 03/07/11: Post-fit simulation question
58077: 03/07/14: Re: Post-fit simulation question
58130: 03/07/15: Re: JTAG standard connector
59079: 03/08/07: Re: Patent granted for "system on a chip" framework?
59356: 03/08/15: ANN: Free soft CPU with tools
61860: 03/10/14: Universities that focus on IC design
62477: 03/10/30: Re: How to protect fpga based design against cloning?
62871: 03/11/10: Xilinx SelectMAP configuration
64202: 03/12/19: Re: Soldering of FPGAs
67421: 04/03/11: Re: Dual-stack (Forth) processors
67692: 04/03/17: Spartan III availability
67797: 04/03/19: Re: Spartan III availability
107949: 06/09/02: Re: Forth-CPU design
Brad Evans:
35266: 01/09/27: Re: fir filter on ASIC
36682: 01/11/15: Re: ASRC (asynchronus sample rate conversion)
Brad Fross:
63: 94/08/08: Re: FPGA based processors ?
75513: 04/11/08: Re: chipscope pro problem (par)
Brad Griffis:
109195: 06/09/21: Re: Dell Laptop for Embedded Work
109212: 06/09/21: Re: Dell Laptop for Embedded Work
Brad Hutchings:
81: 94/08/11: Microprocessors implemented with FPGAs
82: 94/08/11: Re: Proprietary Configuration Data
90: 94/08/12: Re: Proprietary Configuration Data
135: 94/08/26: Density Enhancement via Run-Time Reconfiguration
136: 94/08/26: Re: Self-Programming Devices (was Re: Proprietary Configuration Data)
137: 94/08/26: Re: Density Enhancement via Run-Time Reconfiguration
145: 94/08/31: Re: Dynamic Incremental Reconfiguration
430: 94/11/15: Re: Anybody used FPGA as Encryption Device?
431: 94/11/15: Re: Anybody used FPGA as Encryption Device?
439: 94/11/16: Re: Anybody used FPGA as Encryption Device?
498: 94/12/08: Re: L-Edit and Benchmarks
505: 94/12/13: Re: L-Edit and Benchmarks
806: 95/03/03: RE: FPGA Custom Computing Machine
815: 95/03/06: Re: Limits on on-chip FPGA virtual computing
895: 95/03/22: yet another URL
1089: 95/04/26: Re: Altera new FLEX 10000 - a worlds first
1169: 95/05/10: Re: Compression algo's for FPGA's
1178: 95/05/11: Re: Overheating (was Re: Compression algo's for FPGA's)
1198: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
1201: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
1202: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
1172: 95/05/10: Re: Compression algo's for FPGA's
1440: 95/06/23: Re: Low cost ISA board
1853: 95/09/09: Re: Can someone send me '96 FPGA call for papers?
2031: 95/10/04: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2066: 95/10/09: Re: trends in reconfigurable computing??
2637: 96/01/17: Re: Emulation for a wireless chip
2655: 96/01/19: Re: Emulation for a wireless chip
2905: 96/02/27: Re: Languages for reconfigurable computing.
2928: 96/03/01: Re: Languages for reconfigurable computing.
2929: 96/03/01: Re: High Level Languages
2927: 96/03/01: Re: High Level Languages
2941: 96/03/04: Re: Reconfigurable Computing Languages
3011: 96/03/13: Re: Reconfigurable Computing Languages
3023: 96/03/15: Re: Pointers?
3077: 96/03/27: Re: Sq. Roots and Languages
3080: 96/03/27: Re: Sq. Roots and Languages
4296: 96/10/11: Re: FPGA Web Links
4416: 96/10/25: Re: Synplicity vs. FPGA Express
5320: 97/02/06: Re: Reconfigurable Logic Query
Brad Kelley:
3126: 96/04/08: FPGA->ASIC conversion
6853: 97/07/02: Anyone use Altera Flex6000 yet?
Brad L Taylor:
3602: 96/07/02: Re: LCA to Schematic
Brad L. Hutchings:
17203: 99/07/08: Re: 100 Billion operations per sec.!
Brad Leyz:
61797: 03/10/11: video effects eval boards
Brad Parker:
50651: 02/12/16: OT: know anyone who worked on NCD Explora 451 FPGA?
117407: 07/03/30: xilinx ise/edk/modelsim - what does compilation really do?
Brad Pollard:
27181: 00/11/13: FPGA designers in the Bay Area (San Jose) - Need a new start?
brad ree:
17631: 99/08/16: Re: fpga board : make it or buy it?
17676: 99/08/23: Re: looking for image processing hardware
Brad Ree:
2014: 95/10/03: Re: cheap (free) fpga design software (VHDL)
1988: 95/09/28: Re: FPGA for a 20k gates micro-controller.
7854: 97/10/23: Re: FPGA Floating Point Implementation
8000: 97/11/06: Re: Digital reverberator on FPGA
17708: 99/08/25: Re: Virtex BRAM Initialization
18054: 99/09/26: Re: Altera hierarchical design
18055: 99/09/26: Re: Flex 10k: power-on initialisation of FSM. How to do?
18203: 99/10/07: Re: External Cloking of Altera MAX 7000S
18358: 99/10/18: Re: PREP benchmarks
Brad Rodriguez:
10403: 98/05/16: Re: Minimal ALU instruction set.
Brad Simeral:
7468: 97/09/15: scsi device implementation in Xilinx FPGA
Brad Smallridge:
8079: 97/11/15: Oneshot for Atmel 6K series
8143: 97/11/20: Re: Oneshot for Atmel 6K series
8160: 97/11/22: Re: Need info on runtime configurable FPGAs
8273: 97/12/04: New Up Down Counter Macro for Atmel 6k series
8682: 98/01/19: New Atmel 5.0 software?
8916: 98/02/06: Atmel 6k Speedup procedure
11055: 98/07/15: Shift Invarient Bit Transform
11067: 98/07/16: Re: Shift Invarient Bit Transform
11080: 98/07/17: Re: Shift Invarient Bit Transform
11107: 98/07/19: Re: Shift Invarient Bit Transform
18305: 99/10/13: Part Time, Atmel 6K, Bay Area
53528: 03/03/14: Cypress Users Anyone?
53568: 03/03/16: Re: FPGA dev boards
53815: 03/03/24: Does Xilinx have self-boot option like Cypress?
53818: 03/03/24: Re: Does Xilinx have self-boot option like Cypress?
57724: 03/07/04: Re: Starter Question and Opinion on VHDL
58148: 03/07/15: I/Os with Cypress chip
58177: 03/07/16: Re: I/Os with Cypress chip
59326: 03/08/14: Replacement for Cypress Delta 39K part
59355: 03/08/15: Re: Replacement for Cypress Delta 39K part
69505: 04/05/12: Video Blob Analysis on FPGAs
69582: 04/05/14: Re: Video Blob Analysis on FPGAs
69618: 04/05/15: Re: Video Blob Analysis on FPGAs
69660: 04/05/17: Re: Video Blob Analysis on FPGAs
69663: 04/05/17: Re: Video Blob Analysis on FPGAs
70762: 04/06/26: Simulation Tool with Video Display
71360: 04/07/15: Spartan3 Dev Boards
72058: 04/08/06: Newbie Question Clocks on the Spartan 3
72098: 04/08/08: Re: LEGO mindstorms and FPGA
72099: 04/08/08: Re: Newbie Question Clocks on the Spartan 3
72100: 04/08/08: Newbie Question: Unused pins in the constraint file
72154: 04/08/09: Newbie Xilinx Question: How to keep past designs?
72156: 04/08/09: Sync data between two clock domains
72351: 04/08/16: Spartan 3 Xilinx IO Standards
72356: 04/08/16: Re: Xilinx VQ100 package drawings?
72382: 04/08/17: Re: Spartan 3 Xilinx IO Standards
72394: 04/08/17: Xilinx Spartan 3 XAPP462 DCM (Digital Clock Manager)
72407: 04/08/17: Xilinx Spartan3 DCM Procedure
72530: 04/08/23: Xilinx - Proper VHDL for Bidirectional Pins
72662: 04/08/27: Channel Link signals into Xilinx
72663: 04/08/27: Re: Impact vs. Linux RedHat Linux
72678: 04/08/28: Re: Channel Link signals into Xilinx
73708: 04/09/28: Xilinx Read First Write First
73710: 04/09/28: Re: Xilinx Read First Write First
73712: 04/09/28: Xilinx FIFOs
73731: 04/09/28: Re: Xilinx Read First Write First
73732: 04/09/28: Re: Xilinx FIFOs
73733: 04/09/28: Xilinx Constraints
73776: 04/09/29: Xilinx Timing Constraints
73831: 04/09/29: Re: Xilinx Timing Constraints
73832: 04/09/29: Xilinx SRL16 test
73861: 04/09/30: Re: Xilinx SRL16 test
73869: 04/09/30: Re: Xilinx SRL16 test
73871: 04/09/30: Re: Xilinx SRL16 test
73886: 04/09/30: Xilinx SRL16 example
73887: 04/09/30: Re: Xilinx SRL16 test
73131: 04/09/14: Xilinx S3 Serial Port Code
73136: 04/09/14: Re: Xilinx S3 Serial Port Code
73384: 04/09/20: Re: question about Webpack - PACE
73624: 04/09/26: VHDL inout used for non bidirectional uses
73672: 04/09/27: Re: VHDL inout used for non bidirectional uses
75302: 04/11/01: Xilinx Spartan 3 CoreGen Counters
75303: 04/11/01: Re: "frying" FPGAs
75344: 04/11/02: Xilinx Maximum output required time after clock
74122: 04/10/04: Re: Xilinx SRL16 test
74181: 04/10/05: Xilinx Multiple Clock Domains
74320: 04/10/07: Xilinx DCM and Timing Constraints
74349: 04/10/08: Re: Xilinx DCM and Timing Constraints
74354: 04/10/08: Re: Xilinx Multiple Clock Domains
74358: 04/10/08: Re: Xilinx DCM and Timing Constraints
74360: 04/10/08: Spartan 3 Kit
74363: 04/10/08: Re: Xilinx Multiple Clock Domains
74365: 04/10/08: Re: Xilinx DCM and Timing Constraints
74391: 04/10/10: Re: Spartan 3 Kit
74392: 04/10/10: VHDL code for Type and Components
74393: 04/10/10: Re: Newbie, Altera vs Xilinx
74394: 04/10/10: Re: Spartan 3 Kit
74649: 04/10/15: XAPP253
74675: 04/10/15: ModelSim
74703: 04/10/16: Re: ModelSim
74704: 04/10/16: Re: ModelSim
74772: 04/10/18: Re: ModelSim
75399: 04/11/04: Re: SRL16E_1 primitive instantiation in VHDL
75400: 04/11/04: Re: SRL16E_1 primitive instantiation in VHDL
75613: 04/11/10: Re: C Compiler for Picoblaze !!!!!
75701: 04/11/12: std_logic_vector(0 downto 0)
75844: 04/11/16: ModelSim
75845: 04/11/16: Xilinx, VHDL, Verilog, ModelSim, BMP
75863: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75864: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75970: 04/11/20: Xilinx S3 IO during programming latches Cypress FX2 Reset
75971: 04/11/20: Re: 18x18 Multipliers - Spartan III
76013: 04/11/22: Re: Xilinx S3 IO during programming latches Cypress FX2 Reset
76021: 04/11/22: Beginers Question ModelSim Signals
76058: 04/11/23: Re: Beginers Question ModelSim Signals
76061: 04/11/23: Re: Beginers Question ModelSim Signals
76417: 04/12/01: Re: Beginers Question ModelSim Signals
76817: 04/12/13: Xilinx S3 late arriving DCM clkin
76850: 04/12/14: Re: Xilinx S3 late arriving DCM clkin
76863: 04/12/14: Re: Xilinx S3 late arriving DCM clkin
76904: 04/12/15: Xilinx FIFO
76924: 04/12/15: Re: Xilinx FIFO
76974: 04/12/17: FIFO WREN RDEN and missing clock cycle
77036: 04/12/20: Re: FIFO WREN RDEN and missing clock cycle
77039: 04/12/20: Re: Xilinx FIFO
77040: 04/12/20: Re: Problem with Xilinx Webpack documentation
77042: 04/12/20: Xilinx Warning Dangling Output Warning
77070: 04/12/21: Re: FIFO WREN RDEN and missing clock cycle
77622: 05/01/12: Modelsim Aliases
77697: 05/01/14: Re: Modelsim Aliases
77888: 05/01/19: Re: LVDS through connectors
77937: 05/01/20: Xilinx Sum in VHDL
77945: 05/01/20: Re: Xilinx Sum in VHDL
77972: 05/01/21: Re: Xilinx Sum in VHDL
77973: 05/01/21: Re: Xilinx Sum in VHDL
79073: 05/02/13: Xilinx BRAM FIFO problems ModelSim Post Place and Route
79098: 05/02/14: Re: Xilinx BRAM FIFO problems ModelSim Post Place and Route
79175: 05/02/15: Xilinx Post Place and Route FIFO problems
79179: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79181: 05/02/15: Re: Xilinx Spartan 3 kit - VHDL design question
79193: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79197: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79200: 05/02/15: Re: Xilinx Spartan 3 kit - VHDL design question
79355: 05/02/17: Re: Xilinx Post Place and Route FIFO problems
79356: 05/02/17: ModelSim Timing Strategy
79432: 05/02/18: Re: ModelSim Timing Strategy
79470: 05/02/19: Re: ModelSim Timing Strategy
81331: 05/03/21: Re: Block RAM Initialization - RAMB16_S2
81399: 05/03/22: Xilinx backups
81445: 05/03/23: Re: Xilinx backups
81685: 05/03/29: Re: hook up SRAM to Spartan3
81810: 05/04/01: Searching for Vision Concavity Algorithm
81837: 05/04/01: Re: Searching for Vision Concavity Algorithm
81838: 05/04/01: Re: RAM Synthesized away
81930: 05/04/04: Re: Searching for Vision Concavity Algorithm
82141: 05/04/07: Re: Searching for Vision Concavity Algorithm
82142: 05/04/07: Re: Searching for Vision Concavity Algorithm
84688: 05/05/24: Bresenham Algorithms
85706: 05/06/14: Re: Auto pipeline logic??
86744: 05/07/05: VHDL Clock Domains
87225: 05/07/19: Ones Count 64 bit on Xilinx in VHDL
87227: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
87229: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
87271: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
87362: 05/07/21: Re: Ones Count 64 bit on Xilinx in VHDL
87730: 05/07/29: Spartan3 Done is not going high
87735: 05/07/29: Re: Spartan3 Done is not going high
87738: 05/07/29: Re: Spartan3 Done is not going high
87796: 05/08/01: Xilinx Best Source for Reset
87798: 05/08/01: Re: Bidirectional Bus problem with ModelSim.
87800: 05/08/01: Xilinx Multiple Spartan 3
87922: 05/08/03: Re: Xilinx Multiple Spartan 3
87924: 05/08/03: Re: Xilinx Best Source for Reset
87970: 05/08/04: Xilinx Impact order
87971: 05/08/04: Re: Xilinx Best Source for Reset
88012: 05/08/05: Re: Xilinx Impact order
88013: 05/08/05: Re: Xilinx Best Source for Reset
88928: 05/08/31: Re: Hi-Z input
88935: 05/08/31: Re: Hi-Z input
88937: 05/08/31: Spartan 3 Serdes
88981: 05/09/01: Re: Spartan 3 Serdes
89064: 05/09/04: Re: Spartan 3 Ram Instantiation
89065: 05/09/04: Re: I2C "SCL" line problem
89143: 05/09/06: WARNING:HDLParsers:3481 - No primary, secondary unit in the file
89152: 05/09/06: Re: spartan 3 starter kit auto configuration at power up
89474: 05/09/15: Xilinx ML403
89507: 05/09/16: Re: DCM question
89509: 05/09/16: Re: Xilinx ML403
89560: 05/09/19: Re: Xilinx ML403
89563: 05/09/19: Re: Xilinx ML403
89571: 05/09/19: Re: Xilinx ML403
89647: 05/09/21: Xilinx ModelSim VHDL Running Two Models
89666: 05/09/21: Re: Xilinx ModelSim VHDL Running Two Models
89692: 05/09/22: Re: Xilinx ModelSim VHDL Running Two Models
89693: 05/09/22: Re: Xilinx ModelSim VHDL Running Two Models
89748: 05/09/23: Re: Xilinx ModelSim VHDL Running Two Models
89788: 05/09/26: Re: vhdl state maching problem
89860: 05/09/28: Re: Small C Compiler for Picoblaze
90000: 05/10/01: Re: Xilinx dev board with high quality video?
90068: 05/10/04: Re: vhdl question
90091: 05/10/04: Re: Xilinx IMPACT Problem... detects 101 unknown devices
90467: 05/10/13: Xilinx ML403 Board Beginner
90524: 05/10/15: Re: Xilinx ML403 Board Beginner
90766: 05/10/20: Re: Avnet Technical Support Terrible!!!
90812: 05/10/21: Re: ML401
90896: 05/10/24: Xilinx ML403 Many warnings
90898: 05/10/24: Xilinx ISERDES
90922: 05/10/25: Re: Xilinx ML403 Many warnings
90925: 05/10/25: Re: Xilinx ISERDES
90995: 05/10/26: Re: Xilinx ISERDES
91000: 05/10/26: Xi ISE 7.1 ModelSim
91050: 05/10/27: Re: Xilinx ISERDES
91289: 05/11/02: Xilinx trouble opening ml40x_emb_ref_xx
91326: 05/11/03: Re: Xilinx trouble opening ml40x_emb_ref_xx
91498: 05/11/07: Easy Xilinx Platform Studio Question
91533: 05/11/08: Re: Easy Xilinx Platform Studio Question
91535: 05/11/08: Re: Easy Xilinx Platform Studio Question
91539: 05/11/08: Re: Easy Xilinx Platform Studio Question
91820: 05/11/14: Re: i2c slave does not acknowlege
91956: 05/11/17: Xilinx clock IOB Place Error 645
91995: 05/11/18: Re: Xilinx clock IOB Place Error 645
92000: 05/11/18: Re: Setting the environment variable in ISE 7.1?
92119: 05/11/22: Re: Setting the environment variable in ISE 7.1?
92120: 05/11/22: Re: Setting the environment variable in ISE 7.1?
92181: 05/11/23: Re: Xilinx clock IOB Place Error 645
92192: 05/11/23: Xilinx DCM_ADV 280MHz no lock
92261: 05/11/24: Re: Xilinx DCM_ADV 280MHz no lock
92425: 05/11/29: Re: The reason of implementation of morphological operator in FPGA
92583: 05/12/01: Re: Any fpga tutorials online?
92636: 05/12/02: Xilinx V4 ISERDES problem
92638: 05/12/02: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92639: 05/12/02: Re: Synthesize: Error
92713: 05/12/05: Re: Xilinx V4 ISERDES problem
92715: 05/12/05: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92944: 05/12/09: Xilinx ML40x VGA Documentation
93611: 05/12/26: Xilinx V4 LVDS
93629: 05/12/26: Re: Xilinx V4 LVDS
93630: 05/12/27: Re: Xilinx V4 LVDS
93655: 05/12/27: Re: Xilinx V4 LVDS
93656: 05/12/27: Re: Virtex-4 CCLK termination
93691: 05/12/28: Re: Xilinx V4 LVDS
93693: 05/12/28: Xilinx LVDS termination resistor
93703: 05/12/28: Re: Xilinx LVDS termination resistor
93707: 05/12/28: Re: Xilinx V4 LVDS
93714: 05/12/28: Re: Xilinx LVDS termination resistor
93715: 05/12/28: Re: Xilinx V4 LVDS
93755: 05/12/29: Xilinx ML402 DRAM control
94097: 06/01/05: Re: Timing constraints (again)
94376: 06/01/10: Xilinx 7.1 ISE ModelSim input files
94446: 06/01/11: Re: UCF-File problem
94489: 06/01/12: Xilinx simullation error
94522: 06/01/12: Xilinx 8.i and ML402
94556: 06/01/13: Re: Xilinx 8.i and ML402
94557: 06/01/13: Xilinx ISE 8.i Editor
94563: 06/01/13: Xilinx Virtex-4 BRAM-16 Simulation
94587: 06/01/13: Re: Xilinx Virtex-4 BRAM-16 Simulation
94619: 06/01/14: Re: Xilinx Virtex-4 BRAM-16 Simulation
94645: 06/01/15: Re: Xilinx Virtex-4 BRAM-16 Simulation
94593: 06/01/13: Re: A Better Way?
94765: 06/01/17: Xilinx Virtex-4 RAMB16
94968: 06/01/19: Strange Q1 Output on Xilinx V-4 ISERDES
94969: 06/01/19: Xilinx DDR SDRAM for ML40x
95446: 06/01/23: Virtex-4 BiDirectional Ports
95525: 06/01/23: Re: LVDS Input buffer in VHDL (ISE)
96097: 06/01/30: Re: Acquiring video frames and processing pixels in Xilinx
96548: 06/02/06: Xilinx MIG
96549: 06/02/06: Re: Xilinx MIG
96630: 06/02/07: ISE Simulator
96674: 06/02/08: Re: ISE Simulator
96684: 06/02/08: Re: ISE Simulator
96745: 06/02/09: Xilinx ISERDES Q1 issues
96747: 06/02/09: Re: Xilinx ISERDES Q1 issues
96748: 06/02/09: Re: Xilinx ISERDES Q1 issues
97211: 06/02/18: Xilinx ISE Simulator Arrays
97416: 06/02/21: Virtex-4 Output Primitive
97629: 06/02/24: V4 FIFO16 and SRAM
97648: 06/02/25: Re: V4 FIFO16 and SRAM
97706: 06/02/26: Re: V4 FIFO16 and SRAM
97708: 06/02/26: Re: V4 FIFO16 and SRAM
97711: 06/02/26: Re: V4 FIFO16 and SRAM
97713: 06/02/26: Re: V4 FIFO16 and SRAM
97908: 06/03/01: Xilinx MIG
98178: 06/03/06: Re: Asynchronous FIFO design question
98482: 06/03/10: Re: synthesis time with XST
98484: 06/03/10: ModelSim 6.0 v 5.7 Can't read file
98488: 06/03/10: Re: synthesis time with XST
98516: 06/03/11: Re: ModelSim 6.0 v 5.7 Can't read file
99963: 06/03/31: Re: FIFO Vs Shift Register
99964: 06/03/31: ModelSim 6.0 missing Structure
100110: 06/04/03: Re: ModelSim 6.0 missing Structure
101479: 06/05/01: Re: ML403 ZBT SRAM
101585: 06/05/03: Re: ML403 ZBT SRAM
102405: 06/05/15: USB2 camera to Xilinx ML40x boards
102639: 06/05/18: Re: Clocking ZBT RAM via DCM on ML40x board
102750: 06/05/19: Re: Clocking ZBT RAM via DCM on ML40x board
102940: 06/05/23: I2C on Xilinx V4
103032: 06/05/24: Re: I2C on Xilinx V4
103461: 06/06/02: Re: Driving two DCMs with BUFG?
105302: 06/07/19: Inferring a Xilinx FIFO
105792: 06/07/31: Quick way to change Xilinx BRAM init values
106175: 06/08/08: Re: Who is your favourite FPGA guru?
106779: 06/08/18: Xilinx ise ml402 bram interface
106809: 06/08/19: Re: Warningmessage in ISE
106882: 06/08/21: Xilinx .002ns timing error
106886: 06/08/21: Re: Xilinx .002ns timing error
106938: 06/08/22: Re: Xilinx .002ns timing error
106981: 06/08/23: Xilinx Floorplanner
107079: 06/08/24: Re: Xilinx Floorplanner
107254: 06/08/25: Re: I2C on Xilinx Virtex-4/ML403
107451: 06/08/28: Re: Question on Virtex-4 CLB
107526: 06/08/29: Re: Question on Virtex-4 CLB
107637: 06/08/30: Re: Question on Virtex-4 CLB
107644: 06/08/30: Re: Question on Virtex-4 CLB
108517: 06/09/12: Re: xilinx bram instantation template in vhdl?
108945: 06/09/19: Re: VHDL oddity
108953: 06/09/19: Re: VHDL oddity
110031: 06/10/09: FPGA and ZBT/NoBL SRAM timing issue
110171: 06/10/11: Re: FPGA and ZBT/NoBL SRAM timing issue
110337: 06/10/13: Xilinx V4 not registering T at OLOGIC
110340: 06/10/13: Re: Xilinx V4 not registering T at OLOGIC
110341: 06/10/13: Re: DDR Address
110818: 06/10/23: Xilinx Virtex4 DDR clock output
110820: 06/10/23: Re: Camera link specification
110847: 06/10/24: Re: Xilinx Virtex4 DDR clock output
110988: 06/10/26: Xilinx Virtex4 Outputs for Camera Link
111060: 06/10/27: Re: Xilinx Virtex4 Outputs for Camera Link
111080: 06/10/28: Re: Xilinx Virtex4 Outputs for Camera Link
111167: 06/10/30: Re: Xilinx Virtex4 Outputs for Camera Link
111168: 06/10/30: Re: Xilinx Virtex4 Outputs for Camera Link
111710: 06/11/08: Xilinx ISE ucf management
111935: 06/11/13: Re: regarding changing serial data out to LVDS form
111938: 06/11/13: Re: Xilinx ISE ucf management
111941: 06/11/13: Re: regarding changing serial data out to LVDS form
111942: 06/11/13: Re: regarding changing serial data out to LVDS form
111944: 06/11/13: Seemingly random delays on Xilinx OSERDES
112060: 06/11/15: Xilinx 2 DCMs with delay on lock
112090: 06/11/15: Re: Xilinx 2 DCMs with delay on lock
112195: 06/11/17: Re: Seemingly random delays on Xilinx OSERDES
112771: 06/11/28: Xilinx XST Incremental Design Change
112849: 06/11/29: Re: Xilinx XST Incremental Design Change
113834: 06/12/23: Re: Help with xilinx simulation?
113869: 06/12/26: Re: Help with xilinx simulation?
114148: 07/01/05: Re: Virtex 4 FIFO question
114164: 07/01/05: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114317: 07/01/11: Xilinx Synchronous FIFOs
114318: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
114332: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
114495: 07/01/17: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114502: 07/01/17: Re: Process on both edges
114863: 07/01/25: Re: ML403 board - VGA schematics - wrong pins
114898: 07/01/25: ModelSim Leaf Instances
115426: 07/02/09: Xilinx ML40x SRAM to/from Flash
115789: 07/02/20: Re: Xilinx ML402 Virtex-4 Eval kit - I2C Bus
115874: 07/02/22: Re: internal DCM
115897: 07/02/23: Re: internal DCM
117018: 07/03/21: Re: Data width in Block ram
118976: 07/05/08: Xilinx VHDL Attribute syntax error
118981: 07/05/08: Re: Xilinx VHDL Attribute syntax error
119026: 07/05/09: Re: 'EVENT (or rising_edge) static prefix requirement....
119450: 07/05/19: Re: video soltion provider
122329: 07/07/25: Xilinx VHDL multidimensional array synthesis
122390: 07/07/26: Re: Xilinx VHDL multidimensional array synthesis
122405: 07/07/26: Re: Xilinx VHDL multidimensional array synthesis
123043: 07/08/14: Xilinx PACKER warning bout carry
123121: 07/08/16: Re: Xilinx PACKER warning bout carry
123122: 07/08/16: Re: Xilinx PACKER warning bout carry
123124: 07/08/16: Re: Xilinx PACKER warning bout carry
123139: 07/08/16: Re: Xilinx PACKER warning bout carry
123140: 07/08/16: Re: Xilinx PACKER warning bout carry
123645: 07/08/31: Xilinx ML40x Mouse VHDL Wanted
124011: 07/09/10: Re: VHDL Synthesis Error
124068: 07/09/11: FPGA Archives
124079: 07/09/11: Re: Address sensitive process, Xilinx virtex2pro
124080: 07/09/11: Re: ML410 Board & 1GB DDR2 DIMM Problem
124134: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
124139: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
124140: 07/09/12: Re: FPGA Archives
124147: 07/09/12: XAPP851 fifo36 missing
124148: 07/09/12: Re: XAPP851 fifo36 missing
124151: 07/09/12: Re: XAPP851 fifo36 missing
124185: 07/09/13: MicroBlaze Tutorial
124219: 07/09/14: Re: MicroBlaze Tutorial
124238: 07/09/15: XAPP806 issues DCM Phase Shift
124285: 07/09/17: Re: Unexplained behavior with DDR2 controller on Xilinx V5
127895: 08/01/09: Xilinx ISE 7.1 to 9.2 Width Mismatch
127896: 08/01/09: Re: Synthesizing big RAMs
127978: 08/01/11: Re: Synthesizing big RAMs
128111: 08/01/15: Re: Xilinx ISE 7.1 to 9.2 Width Mismatch
128189: 08/01/17: Xilinx ISE9.2 iMPACT manual
128225: 08/01/18: Re: Xilinx ISE9.2 iMPACT manual
129506: 08/02/26: ModelSim Natural arg value is negative
129635: 08/02/29: Re: ModelSim Natural arg value is negative
130100: 08/03/14: Xilinx Tristate Registration
130102: 08/03/14: Re: Detecting a pulse with minimum width
130137: 08/03/16: Re: Xilinx Tristate Registration
130200: 08/03/17: Re: Xilinx Tristate Registration
130906: 08/04/04: Xilinx inferred FIFOs
130946: 08/04/06: Re: Xilinx inferred FIFOs
131721: 08/04/29: Re: Functional Simulation of Virtex-4 Block Memory
131748: 08/04/30: Re: Functional Simulation of Virtex-4 Block Memory
131828: 08/05/02: Re: Forking in One-Hot FSMs
131863: 08/05/05: Re: Forking in One-Hot FSMs
132147: 08/05/15: Re: Camera link interface
132194: 08/05/16: Re: Camera link interface
133690: 08/07/09: Re: logical net 'NET' has no load
134755: 08/08/28: How many mux input on a Xilinx V4 are pratical
134779: 08/08/29: Re: How many mux input on a Xilinx V4 are pratical
135115: 08/09/16: Xilinx Spartan E
135136: 08/09/17: Re: Xilinx Spartan E
135144: 08/09/17: Re: Xilinx Spartan E
135147: 08/09/17: Re: Xilinx Spartan E
135185: 08/09/19: Re: Xilinx Spartan E
135577: 08/10/08: Xilinx VHDL inferred RAMs
135578: 08/10/08: Re: I need a good reference for VHDL
135603: 08/10/09: Re: Xilinx VHDL inferred RAMs
136772: 08/12/04: Re: Project/File corruption problem with ISE 10.1
136936: 08/12/14: Re: i2c interface
136975: 08/12/16: Re: i2c interface
136976: 08/12/16: Re: Problem with infering BRAM in XST
136994: 08/12/17: Re: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit hidden by declaration of 'ps' at line 651
137364: 09/01/11: Re: error during ise simulation
138386: 09/02/18: VHDL long elsif state machine
140484: 09/05/14: Re: arrays in VHDL
140594: 09/05/19: Re: i2c Start and stop detection
142674: 09/08/25: Re: Why there is multi-source error in these VHDL code?
143928: 09/11/03: Re: ModelSim view internal signals in instantiated verilog modules
144428: 09/12/06: Re: Controlling the I2C master from Opencores.org
144559: 09/12/14: Re: Controlling the I2C master from Opencores.org
144694: 09/12/23: Re: Controlling the I2C master from Opencores.org
146408: 10/03/16: Xilinx Spartan6 Virtex6 Rollout
146673: 10/03/25: Re: Xilinx Spartan6 Virtex6 Rollout
148985: 10/09/18: Re: New release of HDLmaker
152041: 11/06/24: Re: Depth of logical Circuit
152659: 11/09/24: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
152686: 11/09/30: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
152688: 11/10/01: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
Brad Taylor:
2859: 96/02/18: Use of tracking delays instead of min delays.
2880: 96/02/22: Re: Floating Point and Reconfigurable Architectures
2917: 96/02/28: Re: Xilinx is NOT specified MINIMUM delay -
2994: 96/03/10: new languages and C
3001: 96/03/11: Re: Reconfigurable Computing Languages
3028: 96/03/16: Re: Pointers?
3075: 96/03/26: Re: Sq. Roots and Languages
3216: 96/04/27: Re: high gate count FPGA for small volumn production?
3335: 96/05/14: Re: Xilinx 4013 80% utilized but won't route
3355: 96/05/18: Re: Xilinx 4013 80% utilized but won't route
3925: 96/08/20: Re: XC6200 FPGAs
4430: 96/10/28: Re: Integer Multiplier
4494: 96/11/05: Re: UART FOR FPGAS
4526: 96/11/08: Re: Info on FPGA Internal Architecture/ Programming
4560: 96/11/13: Re: AAL5 SAR Design?
4612: 96/11/20: Re: FPGA Gate Counts: No Truth in Advertising
4729: 96/12/06: Re: ASICs Vs. FPGA in Safety Critical Apps.
4800: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
4816: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
5032: 97/01/14: Re: ASICs Vs. FPGA in Safety Critical Apps.
5107: 97/01/23: Re: Altera support better than Xilinx
5260: 97/02/02: Re: FPGA power dissipation
5288: 97/02/03: Re: Xilinx keys break on fast machines
5541: 97/02/23: Re: Xilinx or Altera?
5670: 97/03/05: Re: Reverse Engineering FPGAs
5718: 97/03/10: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
5815: 97/03/17: Re: PLC
5828: 97/03/18: Re: Multiple clocks in Xilinx
5829: 97/03/18: Re: Multiple clocks in Xilinx
5852: 97/03/20: Re: Multiple clocks in Xilinx
6020: 97/04/05: Re: PCI Bus Problems
6333: 97/05/15: Scientific American article on FPGAs
6386: 97/05/20: Re: X-BLOX
6527: 97/05/30: Re: VHDL PCI FPGA Implementation
6727: 97/06/19: Re: 100MHz SDRAMs with Xilinx?
7752: 97/10/10: Re: How fast can fully pipelined XC4000 logic go?
8380: 97/12/11: Re: what is metastability time of a flip_flop
8700: 98/01/20: Re: XC4000Xl IOB switch. charact. ???
9882: 98/04/10: Re: Smoking Crater in a Xilinx 3k FPGA
10056: 98/04/24: Re: XC4000XL and Ground Bouncing
12118: 98/09/30: Re: Efficient max-function architecture? -- "parallel bitwise max"
12141: 98/09/30: Re: Efficient max-function architecture? -- "parallel bitwise max"
13458: 98/12/03: Re: Big-Endian vs Little-Endian
14017: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14024: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
13978: 99/01/05: Re: Gamma correction in YUV space
14023: 99/01/07: Re: fpga socket
14348: 99/01/26: Re: Hysteresis on PLD Clock Inputs
14693: 99/02/11: Re: Current of I/O driver
15097: 99/03/05: Re: I/O standards revisited
15804: 99/04/14: craig
15821: 99/04/15: Re: craig
16075: 99/04/30: Re: High speed PLL inside FPGA
17288: 99/07/17: Chemical FPGAs
Brad Wallace:
4049: 96/09/06: FPGA design project
Brad Whitlock:
157851: 15/04/20: Re: Choosing the right FPGA board
157990: 15/06/11: Re: Is it possible to have a parameterized verilog module name in
brade@colmek.com:
79210: 05/02/15: Avnet Spartan 3 Evaluation Board and PCI
79294: 05/02/16: Re: Avnet Spartan 3 Evaluation Board and PCI
Bradley Yearwood:
5141: 97/01/26: Re: Safety Critical Apps -> Xilinx Checker.
Brady Gaughan:
37191: 01/12/03: Xilinx Parallel FIR Implementations
40114: 02/02/27: FPGAs with differential LVDS terminations?
94319: 06/01/09: Re: CORDIC for digital downconversion
94344: 06/01/10: Re: CORDIC for digital downconversion
94503: 06/01/12: Re: CORDIC for digital downconversion
94317: 06/01/09: Re: CORDIC for digital downconversion
97621: 06/02/24: How about a "File Exchange" for System Generator designs?
<brady00@my-deja.com>:
18405: 99/10/22: Configuring a CPLD and Virtex, and programming a Flash
BRAHmS:
66010: 04/02/11: IP suppiler
<brainsite@altern.org>:
18631: 99/11/04: FREE XXX-PICS!! Without membership!!
BrakePiston:
65096: 04/01/20: BIST FPGA testing - Applying a test vector
65145: 04/01/21: Re: BIST FPGA testing - Applying a test vector
65148: 04/01/21: PowerPC and JTAG
65447: 04/01/29: Showing design in vpr
65719: 04/02/05: Modelsim Error Code 211
68277: 04/03/31: The mapper is getting rid of all my logic!!
68368: 04/04/02: Re: The mapper is getting rid of all my logic!!
69493: 04/05/12: Re: Easypath
69506: 04/05/12: Re: Easypath
Bram Stolk:
56727: 03/06/12: RISC CPU plus FPGA in small package
56746: 03/06/13: Re: RISC CPU plus FPGA in small package
57310: 03/06/27: Re: I need a commercial PCI FPGA board, please help
57837: 03/07/08: Re: Looking for DIMM format FPGA board
Bram van de Kerkhof:
34434: 01/08/24: Re: SmartMedia
53332: 03/03/11: DDR example designs of xilinx or altera
56274: 03/06/02: Virtex 2 evaluation board
60808: 03/09/23: DCM virtex 2 doesn't lose lock
61934: 03/10/15: Powersupply virtex 2 and spartan 3
105117: 06/07/14: EDK adding custom vhdl with multiple arch/entity
Brandon:
87251: 05/07/20: Generics of type time and XST synthesis
87694: 05/07/28: XST and TCL support?
87884: 05/08/03: Legality of type conversion on instance ports?
87886: 05/08/03: Re: XST and TCL support?
87982: 05/08/04: Re: Legality of type conversion on instance ports?
88017: 05/08/05: Re: Legality of type conversion on instance ports?
88451: 05/08/18: XST Help - Device Utilization Woes
88540: 05/08/22: Re: XST Help - Device Utilization Woes
88642: 05/08/24: Re: XST Help - Device Utilization Woes
89858: 05/09/28: Re: Version Control Software
89886: 05/09/29: Re: Version Control Software
102378: 06/05/15: New Virtex4 Project, CoreGen
103405: 06/06/01: Driving two DCMs with BUFG?
Brandon Azbell:
5969: 97/04/01: Re: clock edge specification for Synopsys synthesis
Brandon Jasionowski:
103462: 06/06/02: Re: Changing the random seed in Xilinx tools
103549: 06/06/05: ISE Timing Analysis Misreporting? Bug?
103585: 06/06/06: Re: ISE Timing Analysis Misreporting? Bug?
104850: 06/07/07: Obtain old ver ISE Foundation?
105970: 06/08/03: Component Instantiation ERROR:HDLParsers:3281 in ISE 8.1i
106284: 06/08/10: TIG on Xilinx Asynch FIFO?
106317: 06/08/11: Re: TIG on Xilinx Asynch FIFO?
106858: 06/08/21: Need some assistance with ISE OFFSET constraint.
106862: 06/08/21: Re: Need some assistance with ISE OFFSET constraint.
106908: 06/08/22: OFFSET with DCM NET or derived NET?
106926: 06/08/22: Re: OFFSET with DCM NET or derived NET?
110132: 06/10/11: TIG Being Ignored?
110327: 06/10/13: Re: TIG Being Ignored?
110483: 06/10/16: Re: TIG Being Ignored?
111383: 06/11/02: Warning LIT:176, DCM in Virtex 4?
111384: 06/11/02: Re: Warning LIT:176, DCM in Virtex 4?
113053: 06/12/05: Usage of BUFIO in Virtex 4?
113107: 06/12/06: Re: Usage of BUFIO in Virtex 4?
113182: 06/12/07: Re: Usage of BUFIO in Virtex 4?
114444: 07/01/16: Setup time path on V4 SX w/ IDELAY
115382: 07/02/08: Need advice to help improve timing on V4 FX
115404: 07/02/09: Re: Need advice to help improve timing on V4 FX
115405: 07/02/09: Re: Need advice to help improve timing on V4 FX
115412: 07/02/09: Re: Need advice to help improve timing on V4 FX
115903: 07/02/24: How to specify ISE INST constraint with GENERATE statements?
115911: 07/02/24: Re: How to specify ISE INST constraint with GENERATE statements?
115958: 07/02/26: OFFSET and Data Clock Skew?
116072: 07/02/28: Regional Clock Network and Large Designs
116106: 07/03/01: Re: Regional Clock Network and Large Designs
116151: 07/03/02: Instance Name Being Removed?
116162: 07/03/02: Re: Instance Name Being Removed?
116164: 07/03/02: Re: help read a pixel for picture
116175: 07/03/03: Re: Instance Name Being Removed?
116176: 07/03/03: Re: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
116238: 07/03/05: Re: Instance Name Being Removed?
116909: 07/03/20: Zero-Valued Data Out of Chipscope ILA?
Brandon Unger:
6663: 97/06/10: SUN AND SGI FOR SALE
7485: 97/09/16: SPECIALS SUN & SGI
<brandon@detachedsolutions.com>:
74385: 04/10/10: Coregen difficulties with DCT
74396: 04/10/10: Re: Coregen difficulties with DCT
BrandonD:
147972: 10/06/09: Design passes synthesis and routing but fails on FPGA
147975: 10/06/09: Re: Design passes synthesis and routing but fails on FPGA
147977: 10/06/09: Re: Design passes synthesis and routing but fails on FPGA
147983: 10/06/10: Re: Design passes synthesis and routing but fails on FPGA
147986: 10/06/10: Re: Design passes synthesis and routing but fails on FPGA
147992: 10/06/10: Is it possible to get consistent implementation results?
148003: 10/06/11: Re: Is it possible to get consistent implementation results?
148005: 10/06/11: Re: Is it possible to get consistent implementation results?
BRANE-NEWS:
57860: 03/07/08: Re: SPARTAN-3 vs. VIRTEX-II
Brane2:
84473: 05/05/19: Xilinx Webpack on Gentoo-64bit ?
85091: 05/06/04: Re: ispLSI1016
141131: 09/06/08: Where are new Xilinx FPGAs ?
141633: 09/07/01: Cheapest FPGA with decent PCI- e interface ?
141694: 09/07/03: Re: Cheapest FPGA with decent PCI- e interface ?
141695: 09/07/03: Re: Cheapest FPGA with decent PCI- e interface ?
148857: 10/09/04: Spartan6 distributed RAM- why no x4 and x8 configurations ?
156316: 14/03/01: New Lattice FPGAs on 40nm ?
156317: 14/03/01: FLASH on MachXO2/3
156320: 14/03/04: Re: New Lattice FPGAs on 40nm ?
156394: 14/03/28: lattice Diamond on Linux - programming doesn't work...
156400: 14/03/28: Re: lattice Diamond on Linux - programming doesn't work...
156402: 14/03/29: Lattice MachXO3L - is it available anywhere ?
156403: 14/03/29: Re: Lattice MachXO3L - is it available anywhere ?
156412: 14/03/31: Re: lattice Diamond on Linux - programming doesn't work...
156413: 14/04/01: Re: Lattice MachXO3L - is it available anywhere ?
156431: 14/04/04: Re: Tristates in synthesis
156466: 14/04/08: Re: Lattice MachXO3L - is it available anywhere ?
156470: 14/04/08: Re: Lattice MachXO3L - is it available anywhere ?
156491: 14/04/10: Re: Lattice MachXO3L - is it available anywhere ?
156494: 14/04/10: Re: Lattice MachXO3L - is it available anywhere ?
156498: 14/04/11: Re: Lattice MachXO3L - is it available anywhere ?
156540: 14/04/18: Re: New Lattice FPGAs on 40nm ?
156541: 14/04/18: Re: New Lattice FPGAs on 40nm ?
156565: 14/05/01: Old Spartan-II demo board from Insight - seeking docs..
156568: 14/05/02: Re: Old Spartan-II demo board from Insight - seeking docs..
156570: 14/05/02: Re: Old Spartan-II demo board from Insight - seeking docs..
156583: 14/05/04: Re: The USB FPGA?
156587: 14/05/05: Re: The USB FPGA?
156811: 14/07/03: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit Linux
156813: 14/07/03: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
156815: 14/07/04: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
156823: 14/07/05: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
156830: 14/07/06: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
156836: 14/07/07: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
156839: 14/07/08: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
157770: 15/03/10: Lattice MachXO3L - new "F"sub-subfamily...
159048: 16/07/08: Lattice MachXO2 breakout board - replacing FPGA with different one ?
159051: 16/07/09: Re: Lattice Diamond and VHDL-2008
159055: 16/07/12: Re: Lattice MachXO2 breakout board - replacing FPGA with different
159973: 17/05/03: Lattice ECP5 succesor ( with DDR4 phy) ?
159992: 17/05/05: Re: Lattice ECP5 succesor ( with DDR4 phy) ?
159994: 17/05/05: Re: Lattice ECP5 succesor ( with DDR4 phy) ?
160551: 18/03/30: Altera Cyclone V SoC availability...
160552: 18/03/30: Re: Altera Cyclone V SoC availability...
161484: 19/11/07: Lattice MachXO2/XO3/XO3D vs ECP5
161485: 19/11/07: Re: Lattice XO3D New
161488: 19/11/07: Re: Lattice MachXO2/XO3/XO3D vs ECP5
161504: 19/11/11: Re: Lattice XO3D New
161512: 19/11/14: Re: Gowin Semiconductor, Real or Fake?
161515: 19/11/14: Re: Gowin Semiconductor, Real or Fake?
161517: 19/11/16: Re: AGM AG6K SoC
161545: 19/11/28: Efinix and their Trion FPGAs
161546: 19/11/28: Efinix and their new Trion FPGAs -
161547: 19/11/28: Lattice's ECP5 - half of the program went MIA - WTF ?
161548: 19/11/29: Re: Efinix and their Trion FPGAs
161563: 19/11/29: Re: Lattice's ECP5 - half of the program went MIA - WTF ?
branek:
103170: 06/05/26: tft and uClinux
103177: 06/05/26: Re: tft and uClinux
103196: 06/05/28: Re: tft and uClinux
Branko Badrljica:
23578: 00/06/30: Re: Which notebook is for you?
Brannon:
83771: 05/05/06: Re: Parallel Cable IV opened in "Compatibility Mode"
87181: 05/07/18: EHLO, board designers
89408: 05/09/14: Re: CPU benchmark for Xilinx PAR
90645: 05/10/18: Carry Chain Design
90647: 05/10/18: gast division carry chain usage
90652: 05/10/18: Re: Anyone used the Xilinx' floating point core?
90653: 05/10/18: Re: ADC implementation on fpga? Information and procudures wanted.
90668: 05/10/18: Re: Carry Chain Design
90713: 05/10/19: Re: Carry Chain Design
92191: 05/11/23: Re: virtex II global buffer
93351: 05/12/20: Re: real-time compression algorithms on fpga
94573: 06/01/13: how do I minimize the logic in this function?
94583: 06/01/13: Re: how do I minimize the logic in this function?
94589: 06/01/13: Re: how do I minimize the logic in this function?
96726: 06/02/09: Re: vhdl to edif
96986: 06/02/14: Re: Which SelectIO for FPGA <-> FPGA buses?
97368: 06/02/21: Re: "par.exe" halted without error (partial configuratio)
97370: 06/02/21: Re: Is FPGA code called firmware?
97371: 06/02/21: Re: Is FPGA code called firmware?
97395: 06/02/21: bypass between ilogic and ologic
97862: 06/02/28: floating point MAC, duh!
98776: 06/03/16: Re: Where are FPGA heading?
99151: 06/03/20: Re: Looking for a V4FX development board
99217: 06/03/21: Re: Got the XST (ISE8.1) EQUIVALENT_REGISTER_REMOVAL blues
99219: 06/03/21: Re: Xilinx Square Root Unit
99286: 06/03/22: Re: Xilinx Square Root Unit
99287: 06/03/22: Re: Are Quad-processors advantageous?
99293: 06/03/22: this JTAG thing is a joke
99303: 06/03/22: Re: Are Quad-processors advantageous?
99623: 06/03/27: Re: Xilinx Square Root Unit
100227: 06/04/05: Re: Compressing DVI stream
100308: 06/04/06: Re: Got the XST (ISE8.1) EQUIVALENT_REGISTER_REMOVAL blues
100617: 06/04/13: Re: PCI speed.
100654: 06/04/14: Re: Counting bits
100858: 06/04/19: Re: Multiple Independent Circuits on a Single FPGA
100944: 06/04/21: Re: Xilinx Map & Physical Synthesis dies...
100947: 06/04/21: XST duplicate register option does not work
102248: 06/05/12: Re: How to decide Fanout limit?
103294: 06/05/30: Re: PCI Header types !!!
105040: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105096: 06/07/13: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105098: 06/07/13: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105104: 06/07/13: Re: Development Boards -Your chance to suggest features
105143: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105145: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105156: 06/07/14: Re: design partition across multiple FPGAs
105160: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105534: 06/07/25: Re: An idea for a product (FPGA/ASIC based)
105586: 06/07/26: Re: An idea for a product (FPGA/ASIC based)
105587: 06/07/26: Re: An idea for a product (FPGA/ASIC based)
105619: 06/07/27: Re: An idea for a product (FPGA/ASIC based)
105620: 06/07/27: Re: Guided MAP/PAR in ISE
106083: 06/08/07: Re: FPGA : PCI-Xilinx Core, PC not booting
106580: 06/08/15: Large Spartan3 vs. Small V5
106592: 06/08/15: Re: Large Spartan3 vs. Small V5
106593: 06/08/15: Re: Large Spartan3 vs. Small V5
106594: 06/08/15: Re: Large Spartan3 vs. Small V5
106596: 06/08/15: Re: Large Spartan3 vs. Small V5
106627: 06/08/16: Re: Alternatives to 2v6000
106991: 06/08/23: Re: virtex4fx board and ethernet
107078: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
107835: 06/09/01: Re: logic partioning -- why not after mapping
108277: 06/09/07: Re: Xilinx LogiCORE PCI32
108942: 06/09/19: Re: Using a global clock as a flip-flop enable?
109187: 06/09/21: Re: iMPACT: Problem in downloading bit file
109583: 06/09/29: Re: Xilinx Virtex-2 Pro MUXCY does not drive local FF
109773: 06/10/05: Re: How to accelerate bitstream file generation?
109774: 06/10/05: Re: EDIF
109807: 06/10/05: a clueless bloke tells Xilinx to get a move on
109815: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
109820: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
Brannon King:
47005: 02/09/13: Re: Looking for programming algorithm for Xilinx 18v00 family
47006: 02/09/13: Re: LabVIEW -> FPGA
47101: 02/09/17: Re: C\C++ to VHDL Converter
47218: 02/09/20: Xilinx logiCore PCIX controller issues w/ Virtex2
48662: 02/10/22: CLK question for the VHDL daddy
48663: 02/10/22: Re: Xilinx logiCore PCIX controller issues w/ Virtex2
48669: 02/10/22: Re: CLK question for the VHDL daddy
48859: 02/10/25: DCM and CLK on Virtex2 PCIX controller
48868: 02/10/25: Re: DCM and CLK on Virtex2 PCIX controller
48982: 02/10/28: Re: DCM and CLK on Virtex2 PCIX controller
58277: 03/07/18: Re: Problem Xilinx edif2ngd
58278: 03/07/18: Re: Xilinx XST - how to create an EDIF?
59220: 03/08/12: Re: Win2k service packs for running Xilinx tools
59641: 03/08/25: Re: EDIF input to Xilinx ISE
62262: 03/10/23: interpreting OFFSET
62419: 03/10/29: Re: LogiCORE PCI-X question
64192: 03/12/19: Re: Xilinx IOSTANDARD for PCI-X 100MHz interface
64463: 04/01/05: Re: Xilinx Logicore PCI64 Problem
64464: 04/01/05: Re: Xilinx Logicore PCI64 Problem
64465: 04/01/05: Re: Xilinx Parallel cable
64489: 04/01/05: fast mod (remainder) algorithm for V2?
64491: 04/01/05: Re: fast mod (remainder) algorithm for V2?
64513: 04/01/06: Re: Xilinx Virtex II Output Register
64633: 04/01/09: Re: FPGA Size
64777: 04/01/13: Re: logicore PCIX issue/question
64868: 04/01/15: DMA w/ Xilinx PCIX core: speed results and question
64869: 04/01/15: yo, Mr. FPGA Engineer
64871: 04/01/15: mapper optimization
64875: 04/01/15: Re: yo, Mr. FPGA Engineer
64878: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
64892: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
64929: 04/01/16: Re: DMA w/ Xilinx PCIX core: speed results and question
64932: 04/01/16: mapper optimization
64939: 04/01/16: Re: Can XILINX run in multiple instances?
65307: 04/01/23: Xilinx Map & Par time spent
65572: 04/02/02: Re: Is it possible that a Virtex II device performs below its spec?
67135: 04/03/06: Re: DMA PCI-X core
67933: 04/03/22: Re: Virtex-4
67957: 04/03/23: Re: Quick Syntax question...
68229: 04/03/30: speed vs. temperature
68613: 04/04/09: help with constraint, please
70252: 04/06/10: Virtex4: I don't understand their thinking....
70427: 04/06/16: Re: >Math Skills = >Engineer ?
70521: 04/06/18: Re: How to create an EDIF file from ISE Foundation?
70522: 04/06/18: Re: IOBs in NGC - problem with OBUFT
70719: 04/06/24: Xilinx's interp on EDIF properties
70919: 04/07/01: Re: PCI-X DMA problem w/ Xeon?
71229: 04/07/12: Re: Xilinx Place and Route with changing LUT values
71230: 04/07/12: Xilinx PAR guide files
72721: 04/08/30: Re: ISE EDIF export
73739: 04/09/28: suggestions for Xilinx tool enhancements
73770: 04/09/29: Re: suggestions for Xilinx tool enhancements
73144: 04/09/14: constraints coverage
73548: 04/09/23: MUXCY and XORCY local outputs (LO)
73549: 04/09/23: equal to zero
74764: 04/10/18: location of Stratix primitives list
75397: 04/11/04: Re: XST - Memory Problems
77856: 05/01/18: FPGA Engineer Job Posting
Brant Soudan:
30214: 01/03/28: Re: Xilinx par -m
31259: 01/05/16: Re: Ideas for Faster XILINX compilations ?
brassaro@iro.umontreal.ca:
91911: 05/11/16: xst synthesis
91914: 05/11/16: Re: xst synthesis
91949: 05/11/17: Re: xst synthesis
92057: 05/11/21: Re: xst synthesis
92058: 05/11/21: XST options in XPS
92065: 05/11/21: Re: XST options in XPS
braver:
142493: 09/08/13: why synthesize not work?
142514: 09/08/13: Re: why synthesize not work?
Brazil:
53164: 03/03/05: PCMCIA to IDE interface
56394: 03/06/04: IDE CUSTOM DRIVER
<brehob@gmail.com>:
101476: 06/05/01: quartus 5.1 assignment_defaults.qdf
154205: 12/09/09: Looking for an extremely cheap FPGA board (in quantity, academic use)
Brendan Bridgford:
41623: 02/04/03: Re: Configuring the Virtex II FPGA
42134: 02/04/16: Re: Need help with Insight Spartan II demo board and the counter demo.
44376: 02/06/18: Re: About Programming CPLD using Xilinx Programming Cable IV
Brendan Cullen:
41125: 02/03/21: Re: XPOWER accuracy?
49916: 02/11/25: Re: How do I measure power consumption?
51219: 03/01/07: Re: Power Estimation - supported simulators
51456: 03/01/14: Re: Power usage of CLOCK in FPGA
52654: 03/02/18: Re: How do I measure power consumption?
52887: 03/02/25: Re: setting constraints for Xilinx xpower
56752: 03/06/13: Re: Power consumed in a non configured FPGA?
61270: 03/10/01: Re: Xpower report
61271: 03/10/01: Re: Questions about XPower
63021: 03/11/12: Re: Power calculation using Xpower
63727: 03/12/02: Re: Power calculation using Xpower
65664: 04/02/04: Re: Power extimation?
66007: 04/02/11: Re: power calculation in fpga
68684: 04/04/14: Re: XPower: -tb switch
72964: 04/09/09: Re: Xpower - Clock Power
72965: 04/09/09: Re: Xilinx Xpower Issues - Help from xilinx team please
73172: 04/09/15: Re: Xpower - Clock Power
73686: 04/09/28: Re: Xpower - Clock Power
77406: 05/01/06: Re: Synchronous design and power consumption
77916: 05/01/20: Re: San Jose job offer - advice needed
80620: 05/03/09: Re: xilinx xpower - frequency estimation of internal nodes
81151: 05/03/18: Re: xilinx xpower - frequency estimation of internal nodes
82049: 05/04/06: Re: Xilinx XPower - Accuracy Information
82465: 05/04/13: Re: Xilinx XPower - Accuracy Information
82891: 05/04/19: Re: Xilinx XPower - Accuracy Information
83221: 05/04/26: Re: Virtex 4 Power consumption
83601: 05/05/03: Re: Xilinx V4 Power Calculations
83607: 05/05/03: Re: Virtex 4 Power consumption
90918: 05/10/25: Re: xpower : logic power=0
91074: 05/10/28: Re: xpower : logic power=0
92621: 05/12/02: Re: first time managing a project
96991: 06/02/14: Re: XPower report precision
Brendan Illingworth:
94007: 06/01/04: VHDL FF Question
94096: 06/01/05: Re: ISE Timing
94112: 06/01/05: Signal Skew
94185: 06/01/06: ISE 7.1 & ModelSim - Simulating Internal Signals
94302: 06/01/09: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94316: 06/01/09: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94356: 06/01/10: Xilinx Routing & Clock/Data Skew
97169: 06/02/17: DDR SDRAM Controller
97299: 06/02/20: Re: DDR SDRAM Controller
97654: 06/02/25: VHDL to create LUT based delay
99871: 06/03/30: USB Interface to Virtex-4
99877: 06/03/30: Re: USB Interface to Virtex-4
107115: 06/08/24: Re: RocketIO over cable
Brendan Lynskey:
26370: 00/10/13: CRC calculation
28915: 01/01/29: Re: Xilinx NODELAY attribute question
29363: 01/02/16: Re: Rijndael
30520: 01/04/12: Re: Handel-C
31236: 01/05/16: Handel C question
31238: 01/05/16: Re: Handel C question
33220: 01/07/19: Re: SystemC
51187: 03/01/06: Contracting in the UK
53165: 03/03/05: Re: Bus Functional Model
53805: 03/03/24: Xilinx FPGAs available?
54638: 03/04/15: Selling CPU cores
55168: 03/04/29: DSP/FPGA board
55200: 03/04/30: [little OT] SystemC
55211: 03/04/30: Re: DSP/FPGA board
<brendan.rankin@gmail.com>:
89217: 05/09/08: Re: Bootloading with flash-config devices
98001: 06/03/02: Re: DMA and PCI in SoPC Builder
98116: 06/03/05: Re: DMA and PCI in SoPC Builder
98194: 06/03/06: Re: DMA and PCI in SoPC Builder
<brendanjsimon@gmail.com>:
156290: 14/02/06: Re: To Xilinx: Regarding the download manager
Brent:
23149: 00/06/15: VHDL synthesis.
23157: 00/06/16: XC4005XL OTP?
brent:
151832: 11/05/21: Quadrature Modulation Tutorial
151843: 11/05/23: Re: Quadrature Modulation Tutorial
152947: 11/11/03: Re: Fundamental DSP/speech processing patent for sale
152950: 11/11/03: Re: Fundamental DSP/speech processing patent for sale
Brent A. Hayhoe:
10251: 98/05/07: Re: EPF10K100ABC356-1 HELP US !
10252: 98/05/07: Re: EPF10K100ABC356-1 HELP US !
10311: 98/05/11: Re: Altera relative placement
11796: 98/09/10: Re: Assigning IOE on Altera's FLEX10k
15179: 99/03/11: Re: LUT
16642: 99/06/01: Re: virtex vs apex20k family comparison for DSP ?
23860: 00/07/13: Re: Altera's promises unfulfilled???
25232: 00/08/31: Re: "generate" and instance name indexes in Synopsys
Brent Hayhoe:
63049: 03/11/13: Re: Reading O value
Brent Kucera:
87325: 05/07/21: Re: Does anyone have a NIOS Ethernet Development Kit?
87642: 05/07/27: Re: Does anyone have a NIOS Ethernet Development Kit?
<brentkucera@gmail.com>:
87321: 05/07/21: Does anyone have a NIOS Ethernet Development Kit?
Bret:
119073: 07/05/10: Re: ISE 8.1.03: Bizarre MAP removes almost everything of my design!!!
119098: 07/05/11: Re: ISE9.1: ERROR:Place:911
Bret Eddinger:
17480: 99/07/30: nuneric_std package in Foundation 1.5
Bret Indrelee:
357: 94/10/27: Re: SRAM and antifuse for interconnects
Bret Wade:
16432: 99/05/21: Re: Xilinx M1.5 Crash
21874: 00/04/04: Re: Replication control in Xilinx P&R
21947: 00/04/07: Re: multiprocessor support of IC design tools
23175: 00/06/16: Re: Virtex ".FFX" contraint???
23205: 00/06/17: Re: Virtex ".FFX" contraint???
25000: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25096: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other
25146: 00/08/28: Re: run time doubled with Xilinx 3.1i upgrade
30980: 01/05/07: Re: Internal Error of routing in iSE3.3i
30981: 01/05/07: Re: Internal Error of routing in iSE3.3i
34267: 01/08/17: Re: Replication of FFs in Xilinx XC4000
37674: 01/12/18: Re: Kindergarten Stuff
37726: 01/12/19: Re: Kindergarten Stuff
37727: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37753: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37754: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37875: 01/12/22: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37883: 01/12/22: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
38248: 02/01/09: Re: How can I relate Virtex2 pin names and Slice XY loc?
38281: 02/01/10: Re: Avoid routing through a certain area (Xilinx)
38320: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
38327: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
38338: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
38422: 02/01/14: Re: How can I relate Virtex2 pin names and Slice XY loc?
38423: 02/01/14: Re: Xilinx PAR and Editor speed up
38481: 02/01/15: Re: Hard macro for Xilinx FPGA
39668: 02/02/15: Re: Thingy has the property IOB=TRUE
39684: 02/02/15: Re: Thingy has the property IOB=TRUE
42135: 02/04/16: Re: creating my own hard macro or similar
45535: 02/07/25: Re: RLOC Origin problems in ISE4.2sp3?
45564: 02/07/26: Re: RLOC Origin problems in ISE4.2sp3?
47329: 02/09/23: Re: MAP problem: Trivial RPM fails
47373: 02/09/24: Re: MAP problem: Trivial RPM fails
47973: 02/10/08: Re: shared clock routing resource virtex 2 - adjacent IOB
48063: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
55707: 03/05/16: Re: OK I am pissed off with Xilinx webpack.
55817: 03/05/20: Re: OK I am pissed off with Xilinx webpack.
64636: 04/01/09: Re: Xilinx Virtex II Output Register
65255: 04/01/22: Re: map gives yet another error!
65259: 04/01/22: Re: Why is router software not multi-threaded?
65366: 04/01/26: Re: Problem with TBUF-Placing
65407: 04/01/27: Re: building macros for Virtex-II with FPGA editor...
65423: 04/01/28: Re: building macros for Virtex-II with FPGA editor...
65451: 04/01/29: Re: building macros for Virtex-II with FPGA editor...
65495: 04/01/30: Re: Partial Reconfig Spartan 2 - Bus Macros, which one?
65813: 04/02/06: Re: Xilinx PAD name to (X,Y) RPM coordinate
66146: 04/02/12: Re: Xilinx FPGA Editor - can one see the switch box detail?
68335: 04/04/01: Re: The mapper is getting rid of all my logic!!
68493: 04/04/06: Re: The mapper is getting rid of all my logic!!
70909: 04/07/01: Re: How to prevent MAP from removing floating inputs?
71051: 04/07/06: Re: MAP: what are route-through look up tables
71726: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71796: 04/07/30: Re: XST vhdl adder with carry out : broken carry chain
72204: 04/08/11: Re: ISE 6.2 : Place problem with V2PRO
73435: 04/09/21: Re: XST vhdl adder with carry out : broken carry chain
75664: 04/11/11: Re: Virtex2P: lock down DCM and Global buffer
76273: 04/11/29: Re: XST question
76442: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
76449: 04/12/02: Re: FF/Latch trimming : Xilinx ISE 6.3 i
76457: 04/12/02: Re: EDIF -> Map & Place -> EDIF ?
76801: 04/12/12: Re: LUT and MUXF5 placement
76805: 04/12/13: Re: LUT and MUXF5 placement
76922: 04/12/15: Re: Xilinx ISE 6.3.03i service pack size
77354: 05/01/04: Re: ISE Toolflow : hardmacro, incremental or modular
77385: 05/01/05: Re: ISE Toolflow : hardmacro, incremental or modular
77434: 05/01/06: Re: ISE Toolflow : hardmacro, incremental or modular
77448: 05/01/06: Re: MAP failes after inserting ILA and ICON cores to the design
77450: 05/01/06: Re: ISE Toolflow : hardmacro, incremental or modular
77488: 05/01/07: Re: ISE Toolflow : hardmacro, incremental or modular
77515: 05/01/08: Re: ISE Toolflow : hardmacro, incremental or modular
77520: 05/01/08: Re: ISE Toolflow : hardmacro, incremental or modular
77664: 05/01/13: Re: Xilinx FPGA editor
77679: 05/01/13: Re: Xilinx FPGA editor
77688: 05/01/13: Re: Xilinx FPGA editor
77730: 05/01/15: Re: No respect of external pins (xilinx)
77747: 05/01/15: Re: No respect of external pins (xilinx)
77770: 05/01/17: Re: No respect of external pins (xilinx)
77782: 05/01/17: Re: No respect of external pins (xilinx)
78531: 05/02/02: Re: Modifying a post PAR xilinx design
78786: 05/02/07: Re: MAP problem
79347: 05/02/17: Re: IOBs in virtex4?
81842: 05/04/01: Re: Xilinx tools, bugs all around?
81887: 05/04/04: Re: how to use both FFs in a CLB's slice using LOC or RLOC
81935: 05/04/04: Re: Xilinx tools, bugs all around?
82245: 05/04/09: Re: ise 7.1 sp1 BEWARE !
82301: 05/04/10: Re: ise 7.1 sp1 BEWARE !
86781: 05/07/06: Re: Xilinx IOB flop mapping vs. -bp switch
89470: 05/09/15: Re: CPU benchmark for Xilinx PAR
<bret.wade@gmail.com>:
87917: 05/08/03: Re: Area Group IOB Range
88244: 05/08/12: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88266: 05/08/13: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
Brett Christopher WALKER:
2256: 95/11/11: FPGA references and good starting points?
Brett Cline:
47674: 02/10/02: Re: C\C++ to VHDL Converter
47869: 02/10/06: Re: C\C++ to VHDL Converter
47907: 02/10/07: Re: C\C++ to VHDL Converter
Brett Foster:
56037: 03/05/27: Re: JTAG madness
56054: 03/05/28: Re: JTAG madness
56055: 03/05/28: Re: JTAG madness
56075: 03/05/28: Re: JTAG madness
56108: 03/05/28: Re: JTAG madness
Brett George:
13750: 98/12/22: PLL in FPGAs?
13751: 98/12/22: Re: Starting with FPGAs
13752: 98/12/22: Re: Magazine IEEE for FPGA ???
14130: 99/01/15: Re: AHDL VS. VHDL
14225: 99/01/21: Re: Free max+plus ll simulator on win95
14383: 99/01/28: Re: testing (english?)
14413: 99/01/29: Re: Off topic....
14986: 99/03/02: ALTERA pin assignment
15114: 99/03/08: Re: SPI Interface
Brett Stutz:
167: 94/09/06: Re: Xilinx and 8.4 -- not!
Brett Wall:
Brian:
43817: 02/06/03: Re: Upgrade to ISE4.1/4.2 ?
52531: 03/02/12: Coolrunner II I/O speeds?
52554: 03/02/13: Re: Coolrunner II I/O speeds?
52584: 03/02/14: Re: Coolrunner II I/O speeds?
55918: 03/05/23: Re: FPGA design: firmware or hardware?
56302: 03/06/02: Re: power consumption in CMOS..
73496: 04/09/22: 5V Tolerant?
73538: 04/09/23: Re: 5V Tolerant?
73559: 04/09/23: Re: 5V Tolerant?
92909: 05/12/09: Re: What graphical entry/documentation tools?
92997: 05/12/11: Re: Xilinx Coregen IP Customizer Causes Exception During Customization
103514: 06/06/05: Jumps in Reading out
103626: 06/06/06: Noise-like Vibration in Measurement Result
108490: 06/09/12: problems with viewdraw
108736: 06/09/15: Re: Fusion
127618: 08/01/03: Re: Split Plane
140345: 09/05/09: Re: Dual Port RAM Inference
149590: 10/11/09: Re: Chance to win a SP601 board in Xcell Journal Caption Contest
brian:
96185: 06/01/31: scrambling
Brian "Cheebie" Merchant:
3721: 96/07/22: Re: What does the timing report from Synthesizer mean?
10065: 98/04/25: Re: Synopsys FPGA compiler
Brian Antao:
1929: 95/09/20: Custom Integrated Circuits Conference -- Call for Papers
Brian Bach Mortensen:
Brian Boorman:
12985: 98/11/09: Re: Q: 3.3 V regulators suitable for XILINX - ?
12988: 98/11/09: Re: Free I2C model
13104: 98/11/16: Re: Example of clock circuit needed !
13105: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
13262: 98/11/22: Re: Combining busses Xilinx
13424: 98/12/02: Re: Will XILINX survive?
13426: 98/12/02: Re: Is it normal to have to edit the xnf file???
13425: 98/12/02: Re: Interfaces to an Asynchronous SRAM
13436: 98/12/02: Re: Interfaces to an Asynchronous SRAM
13533: 98/12/08: Verilog/FPGA Express Synth Problem
13579: 98/12/10: Re: Verilog/FPGA Express Synth Problem
13649: 98/12/16: Re: Fast *Industrial* 22V10?
13695: 98/12/18: Re: Problem with clock IOB placement
14067: 99/01/11: Re: DES Hardware Implementation!!
14244: 99/01/21: Re: Free max+plus ll simulator on win95
14337: 99/01/26: Re: DTMF Decoder in a FPGA/XILINX ?
14394: 99/01/28: Re: Ratings for Synplicity Synplify
14432: 99/01/29: Re: ALTERA: Configuration problem of 10K50VRC240-3 + EPC1PC8
14487: 99/02/01: Re: Q:Installing Xilinx F1.4 license server
14554: 99/02/04: Re: VHDL problem (Xilinx-problem)
14574: 99/02/04: Re: Synplify/Xilinx4085XLA question
14589: 99/02/05: Re: Synplify/Xilinx4085XLA question
14590: 99/02/05: Re: can I trust Altera Simulator?
14624: 99/02/06: Re: VHDL synthesis
14641: 99/02/08: Re: Xilinx de-compiler
15092: 99/03/05: Re: Problem with xilinx M1
15093: 99/03/05: Re: Foundation V1.5 Crash
14970: 99/03/01: Re: JTAG HANG UP......
14975: 99/03/01: Re: 4002A .bit -> .hex
15424: 99/03/23: Re: FPGA Express FSM Synthesis Concern
15499: 99/03/26: Re: FPGA Express FSM Synthesis Concern
15752: 99/04/12: Re: Lattice
16303: 99/05/14: Re: High speed reconfigurability
16112: 99/05/04: Re: Configuring Xilinx FPGAs
16128: 99/05/05: Re: Anyone use 27256 for config?
16232: 99/05/11: Re: BGA Prototyping ?
16653: 99/06/01: Re: FPGA express + VHDL: strange SR implementation?
16812: 99/06/10: Re: Q: Spartan XL pull-ups
16822: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
16831: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
16947: 99/06/18: FW: Xilinx Acquisition of CoolRunners
17181: 99/07/07: Re: ENJOY MY AMATEUR WEB SITE.
17214: 99/07/09: Re: how to choose only a set of pins
17378: 99/07/23: Re: Low Cost latched I/O
17606: 99/08/13: Re: Philips Semiconductors (NL) seeks digital designers
17650: 99/08/18: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17762: 99/09/01: Re: Xilinx Spartan Configuration Prom
17976: 99/09/20: Re: Programming Spartan XL
18294: 99/10/12: Re: GSR on ORCA FPGAs
18295: 99/10/12: Re: ALTERA design ---> XILINX
18508: 99/10/28: Re: Looking for exemplar_1164 package
18722: 99/11/09: test
18838: 99/11/18: Re: How to use multiple resets?
23080: 00/06/13: Re: Virtex IRDY and TRDY
Brian Borts:
29349: 01/02/15: Alpha Job Consulting News
Brian Boutel:
146074: 10/03/05: Re: using an FPGA to emulate a vintage computer
Brian C. Lane:
2954: 96/03/05: [NEWBIE] FPGA Project?
Brian C. Van Essen:
88847: 05/08/30: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
88898: 05/08/30: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
Brian Carlson:
9576: 98/03/24: Altera FPGA prototype / development board
Brian Carruthersq:
29701: 01/03/05: Spartan XL & Spartan II Slave Serial Configuration
Brian Childs:
2669: 96/01/22: Re: How Big Chips Will Be Designed In The Not Too Distant Future
2684: 96/01/24: Re: In Search of Graphical VHDL Code Generators for FPGA Design
Brian Dam Pedersen:
14492: 99/02/01: Re: Hazard
14517: 99/02/02: Re: Off topic DRAM/SIMM question....
14520: 99/02/03: Re: Off topic DRAM/SIMM question....
14542: 99/02/04: Re: Off topic DRAM/SIMM question....
14557: 99/02/04: Re: Off topic DRAM/SIMM question....
14815: 99/02/18: Re: four signals into array?
72324: 04/08/15: Re: why?
72698: 04/08/29: Re: Xilinx in Linux
76067: 04/11/23: xc3sprog and nuhorizons
77485: 05/01/07: Xilinx CPLD configuration under Linux ?
77504: 05/01/08: Re: Xilinx CPLD configuration under Linux ?
77505: 05/01/08: Re: Xilinx CPLD configuration under Linux ?
77709: 05/01/15: Re: Starting with xilinix and Linux
87814: 05/08/02: Re: Spartan3 with WebPack?
87835: 05/08/02: Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript
87845: 05/08/02: Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript
87979: 05/08/04: Re: How to import EDIF netlist into ISE webpack 7.1
88308: 05/08/15: 18-bit ROM in verilog
88330: 05/08/15: Re: 18-bit ROM in verilog
91260: 05/11/02: Re: Newbie. Clocks.
91385: 05/11/04: Re: icarus verilog
93844: 06/01/02: Re: basic DSP with FPGA
101309: 06/04/28: Re: initializing array of registers in XST
Brian Davis:
27328: 00/11/18: Re: Xilinx config bits
29764: 01/03/08: Re: More detailed Spartan II CLB drawings?
35651: 01/10/12: Re: High level synthesis will never work well :)
35694: 01/10/13: Re: Synplicity/Leonardo License Agreement Information
35696: 01/10/13: Re: Synplicity/Leonardo License Agreement Information
36556: 01/11/12: Floorplanner Package Pin View
37250: 01/12/04: Re: Phase noise (jitter) of XILINX logic elements - ?
37265: 01/12/05: Re: Phase noise (jitter) of XILINX logic elements - ?
38000: 01/12/29: Re: How to set block ram contents ?
39544: 02/02/12: Re: Spartan Program/Verify
41250: 02/03/22: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41279: 02/03/24: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41326: 02/03/25: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41327: 02/03/25: Re: A petition for Synplify's new fature (FPGA synthesis tool)
43704: 02/05/30: Re: Frequency synthesiser
43720: 02/05/30: Re: Frequency synthesiser
44168: 02/06/12: Re: MAP problem with RLOC'ed macros
45642: 02/07/30: Re: Dual Port Block RAM
49190: 02/11/04: Re: 16-bit FGPA CPU core (commercial)
49263: 02/11/06: Re: 16-bit FGPA CPU core (commercial)
50526: 02/12/11: Re: FPGA/PCI on low budget
50528: 02/12/11: Re: FPGA/PCI on low budget
57544: 03/07/02: Re: Cyclone vs Spartan-3
58205: 03/07/16: Re: Xilinx XST - how to create an EDIF?
60933: 03/09/25: Re: Corrupt Xilinx 18vxx poms
61337: 03/10/01: LVDS_25_DCI : Top Ten List
61402: 03/10/02: Re: LVDS_25_DCI : Top Ten List
61403: 03/10/02: Re: LVDS_25_DCI : Top Ten List
61467: 03/10/04: Re: LVDS_25_DCI : Top Ten List
61569: 03/10/06: Re: LVDS_25_DCI : Top Ten List
61625: 03/10/07: Re: LVDS_25_DCI : Top Ten List
61652: 03/10/08: Re: More RPM / RLOC fun
61688: 03/10/08: Re: ....and he left with his marbles.....
61750: 03/10/09: Re: Input capacitance
62766: 03/11/06: Re: Virtex II DCM & ZBT SRAM
62788: 03/11/07: Re: Virtex II DCM & ZBT SRAM
63107: 03/11/14: Re: Xilinx UART Macro ERROR???
63404: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63439: 03/11/21: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
64836: 04/01/14: Re: Virtex II - LVDS_33_DCI?
65074: 04/01/19: Re: Which version of ISE Webpack has FPGA Editor on it?
65333: 04/01/24: Re: Xilinx LVDS_25_DT termination issues????
66353: 04/02/17: Re: Plea for help - 29PL141
66971: 04/03/02: Re: area constrains in UCF (or PACE)
70976: 04/07/03: Re: Xilinx $99 Spartan-3 kit
71256: 04/07/13: Re: Spartan 3 termination question (DCI)
71309: 04/07/14: Re: Spartan 3 termination question (DCI)
71334: 04/07/14: Re: Spartan 3 termination question (DCI)
71399: 04/07/16: Re: Spartan 3 termination question (DCI)
72197: 04/08/11: Re: Spartan 3 termination question (DCI)
73764: 04/09/29: Re: Spartan-3 VCCIO ramp up time
73824: 04/09/29: Re: Spartan-3 VCCIO ramp up time
73015: 04/09/10: Re: Initializing memory from a testbench
73688: 04/09/28: Re: Spartan-3 VCCIO ramp up time
73691: 04/09/28: Re: AVNET's Xilinx prototyping modules (AvBus cable?!?)
74199: 04/10/05: Re: FPGA vs ASIC area
74289: 04/10/07: Re: FPGA vs ASIC area
74337: 04/10/08: Re: FPGA vs ASIC area
74340: 04/10/08: Re: Xilinx Multiple Clock Domains
74802: 04/10/19: Re: spartan 3 on 4 layers
74821: 04/10/19: Re: spartan 3 on 4 layers
74822: 04/10/19: Re: spartan 3 on 4 layers
74836: 04/10/20: Re: spartan 3 on 4 layers
74902: 04/10/21: Re: spartan 3 on 4 layers
75913: 04/11/18: Re: Async and sync resets
75948: 04/11/19: Re: Async and sync resets
76781: 04/12/10: Re: default changes with new release
77015: 04/12/20: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
77349: 05/01/04: Re: Using LM317S adjustable linear regulator for Spartan 3?
77367: 05/01/05: Spartan-3 PQ/TQ/VQ SSO guidelines
77397: 05/01/05: Re: Spartan-3 PQ/TQ/VQ SSO guidelines
78256: 05/01/27: Re: LVPECL and SelectIO banking rules in V2P
78386: 05/01/31: Re: LVDS without termination
78390: 05/01/31: Re: LVDS without termination
78491: 05/02/01: Re: LVDS without termination
78524: 05/02/02: Re: LVDS without termination
79022: 05/02/11: Re: ISE versus Modelsim inconsistency and attribute definition
79135: 05/02/14: Re: ISE versus Modelsim inconsistency and attribute definition
79137: 05/02/14: Re: ISE versus Modelsim inconsistency and attribute definition
79647: 05/02/22: Re: Xilinx: Pitfalls of chaining DLLs
79920: 05/02/25: Re: dealing with NGO files
80288: 05/03/03: V4 SI: The package is thrilling, but the Cin is bleak
80360: 05/03/04: Re: V4 SI: The package is thrilling, but the Cin is bleak
80421: 05/03/05: Re: V4 SI: The package is thrilling Explanation of Cin
80911: 05/03/14: Re: XC3000 non-recoverable lockup problem
80964: 05/03/15: Re: XC3000 non-recoverable lockup problem
81002: 05/03/15: Re: XC3000 non-recoverable lockup problem
81033: 05/03/16: Re: XC3000 non-recoverable lockup problem
81284: 05/03/21: Re: XC3000 non-recoverable lockup problem
81507: 05/03/25: Re: LVPECL, Virtex II and the EP445
81654: 05/03/29: Re: XC3000 non-recoverable lockup problem
83991: 05/05/10: Re: Virtex4 running at 360Mhz DDR
84064: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84068: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84235: 05/05/15: Re: Virtex4 running at 360Mhz DDR
84847: 05/05/30: Re: Control asynchronous SRAM like synchronous SRAM
85875: 05/06/17: Re: Xilinx Spartan 3 DCI Power Consumption
88795: 05/08/28: Re: CPLD Jitter
89258: 05/09/09: Re: Fastest input IOB on a Spartan-3?
89704: 05/09/22: Re: Xilinx Spartan-3
89775: 05/09/26: Re: Xilinx Spartan-3
90008: 05/10/01: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
90445: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2 and virtex4
90973: 05/10/26: Re: cic filter
91299: 05/11/02: Re: Spartan-3E starter kit
91358: 05/11/03: Re: Spartan-3E starter kit
91695: 05/11/10: Re: Can't pack into OLOGIC
91858: 05/11/15: Re: Can't pack into OLOGIC
92094: 05/11/22: Re: Uart core for a virtex-4
92998: 05/12/11: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93000: 05/12/11: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93003: 05/12/11: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93213: 05/12/15: Re: Digilent SRAM Controller
93244: 05/12/16: Re: Avnet hav2 s3e starter kit?
94155: 06/01/06: Re: S3e starter kits available
94236: 06/01/08: Re: S3e starter kits available
94258: 06/01/09: Re: S3e starter kits available
94328: 06/01/09: Re: PCI compliance ?
94358: 06/01/10: Re: PCI compliance ?
94381: 06/01/10: Re: PCI compliance ?
94437: 06/01/11: Yet Another Misleading Post from Austin, a Xilinx(R) Employee
94438: 06/01/11: DCI power variations
94456: 06/01/11: Re: DCI power variations
94460: 06/01/11: Re: DCI power variations
94455: 06/01/11: Re: Unoffensive Title about Certain Posting Habits
94457: 06/01/11: Re: Another Unoffensive Title about Certain Posting Habits
94715: 06/01/16: Re: Directed routing in Xilinx V2PRO.
94743: 06/01/17: Re: Directed routing in Xilinx V2PRO.
94716: 06/01/16: Re: how do I minimize the logic in this function?
94835: 06/01/18: Re: xilinx free Sample Pack info now also on Xilinx own webpages
95359: 06/01/22: Re: Xilinx padding LC numbers, how do you feel about it?
95770: 06/01/25: Re: Xilinx padding LC numbers, how do you feel about it?
95361: 06/01/22: Re: need for a group FAQ?
95557: 06/01/23: Re: LVDS Input buffer in VHDL (ISE)
95633: 06/01/24: Re: LVDS Input buffer in VHDL (ISE)
95952: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95992: 06/01/27: Re: Virtex-4 ISERDES and ADS527X ADCs
96016: 06/01/27: Re: Virtex-4 ISERDES and ADS527X ADCs
96002: 06/01/27: Re: Virtex-4 ISERDES and ADS527X ADCs
96074: 06/01/29: Re: Virtex-4 ISERDES and ADS527X ADCs
96346: 06/02/02: Re: Spartan3 pullups
96635: 06/02/07: Re: latest XILINX WebPack is totally broken
96975: 06/02/14: 8.1i SP2 download problems
97071: 06/02/15: DIFF_OUT buffer example
97073: 06/02/15: Re: 8.1i SP2 download problems
97082: 06/02/16: Re: DIFF_OUT buffer example
97091: 06/02/16: Re: DIFF_OUT buffer example
97403: 06/02/21: Re: DIFF_OUT buffer example
97405: 06/02/21: Re: DIFF_OUT buffer example
97415: 06/02/21: Re: Virtex-4 ISERDES and ADS527X ADCs
97645: 06/02/25: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97825: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97844: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97845: 06/02/28: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
98009: 06/03/02: Simple ADS5273 -> Xilinx Interconnect Model
98022: 06/03/03: Re: Simple ADS5273 -> Xilinx Interconnect Model
98075: 06/03/03: Re: Simple ADS5273 -> Xilinx Interconnect Model
98076: 06/03/03: Re: Simple ADS5273 -> Xilinx Interconnect Model
98117: 06/03/05: Re: Simple ADS5273 -> Xilinx Interconnect Model
98292: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
98302: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
98313: 06/03/08: V4 LVDS_25 IBIS models
98432: 06/03/09: Re: Simple ADS5273 -> Xilinx Interconnect Model
98753: 06/03/15: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
99192: 06/03/21: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99220: 06/03/21: Re: DDS
99435: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
99482: 06/03/24: Re: Xilinx hi-speed interconnect/routing question
99517: 06/03/25: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99518: 06/03/25: Re: XST takes unusually long
99567: 06/03/26: Re: Xilinx hi-speed interconnect/routing question
99569: 06/03/26: Re: Clock multiplication without using the Xilinx DCM's
99571: 06/03/26: Re: Clock multiplication without using the Xilinx DCM's
99573: 06/03/26: Re: Xilinx hi-speed interconnect/routing question
99574: 06/03/26: Re: Clock multiplication without using the Xilinx DCM's
99603: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
99671: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
99762: 06/03/28: Re: Clock multiplication without using the Xilinx DCM's
100075: 06/04/03: Re: deglitching a clock
100208: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100264: 06/04/05: Re: LVDS in Cyclone-II
100302: 06/04/06: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100372: 06/04/07: Re: LVDS in Cyclone-II (or in Spartan-3E)
100465: 06/04/10: Re: LVDS in Cyclone-II (or in Spartan-3E)
100633: 06/04/13: Re: Did National cheat with the Virtex 4
100725: 06/04/17: Re: Did National cheat with the Virtex 4
100758: 06/04/17: Re: Did National cheat with the Virtex 4
100928: 06/04/21: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor
100939: 06/04/21: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor
102611: 06/05/17: Update: Simple ADS5273 -> Xilinx Interconnect Model
102842: 06/05/22: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
102862: 06/05/22: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
102983: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
103336: 06/05/31: Re: Need help reattaching top to FPGA
103922: 06/06/14: open inputs and Unisim libraries
103957: 06/06/15: Re: Virtex2-Pro local clocking...
106191: 06/08/08: Re: Spartan 3 StarterKit Weirdness
106435: 06/08/13: Re: Embedded clocks
106538: 06/08/14: Re: Embedded clocks
108753: 06/09/15: Re: XIlinx Spartan 2E stuck in configuration mode
109148: 06/09/21: Re: DCM multiplier and EDK design
109828: 06/10/05: .ise project files, episode N+1
110468: 06/10/16: Re: longest webcase record
110813: 06/10/23: Re: PowerPC somehow unstable at 300 MHz
111064: 06/10/27: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111125: 06/10/29: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111135: 06/10/30: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111199: 06/10/30: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111301: 06/11/01: Re: Spectre of Metastability Update
111505: 06/11/03: Re: digilent spartan-3 board sram timing
112716: 06/11/27: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112732: 06/11/28: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
112745: 06/11/28: Re: more S3E DIFF_TERM quirks ( was: vccaux and vccint )
113553: 06/12/15: Re: electrical level conversion
113581: 06/12/17: Re: electrical level conversion
113588: 06/12/17: Re: electrical level conversion
113651: 06/12/18: Re: electrical level conversion
113800: 06/12/22: Re: DCM start up
114066: 07/01/03: OT. Re: Surface mount ic's
114086: 07/01/04: Re: OT. Re: Surface mount ic's
114125: 07/01/04: ISE 8.2sp3 clobbering source file timestamps?
114144: 07/01/05: Re: ISE 8.2sp3 clobbering source file timestamps?
116566: 07/03/12: Re: odd warning in Xilinx ISE webpack
117946: 07/04/13: Re: SETUP & HOLD time confusion
119765: 07/05/25: Re: Use BRAM as ROM (Xilinx)
119947: 07/05/29: Re: Use BRAM as ROM (Xilinx)
119973: 07/05/30: Re: Use BRAM as ROM (Xilinx)
120011: 07/05/30: Re: LVDS termination scheme to nonstandard ribbon cable
120025: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120046: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120076: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120081: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120240: 07/06/04: Re: 180 differential inputs each 800Mbps using V5
120256: 07/06/04: Re: 180 differential inputs each 800Mbps using V5
120360: 07/06/05: Re: Virtex4 CLKX2 DCM Jitter
120570: 07/06/10: Re: LVPECL output skew
120572: 07/06/10: Re: XST net splitting blocks placement
120573: 07/06/10: Re: Lattce SC Purspeed I/O
120574: 07/06/10: Re: Virtex4 CLKX2 DCM Jitter
120575: 07/06/10: DVI-D Tx directly from FPGA?
120649: 07/06/12: Re: DVI-D Tx directly from FPGA?
120651: 07/06/12: Re: LVPECL output skew
121875: 07/07/13: Re: CML output swing for V5
124217: 07/09/14: Re: Spartan-3E Slave Serial Configuration
125094: 07/10/16: Re: FPGA quiz: what can be wrong
125103: 07/10/16: Re: FPGA quiz: what can be wrong
125110: 07/10/16: Re: FPGA quiz: what can be wrong
125232: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
126755: 07/11/30: Re: ISE WARNING Xst:647
126833: 07/12/03: Re: ISE WARNING Xst:647
127098: 07/12/11: Re: DDS generator with interpolated samples for Spartan3E development
127205: 07/12/13: Re: DDS generator with interpolated samples for Spartan3E development
127343: 07/12/18: Re: Xilinx DCM outputs for DDR
127379: 07/12/19: Re: Xilinx DCM outputs for DDR
127572: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127582: 08/01/03: Re: Where are the LCD or OLED bitmapped displays?
128783: 08/02/06: Re: Possible CRC error on XC3S400 - now what?
129133: 08/02/15: Re: Spartan 3 configuration download error
130139: 08/03/16: Re: Xilinx Tristate Registration
130356: 08/03/20: Synoplify ???
130754: 08/03/31: Re: Using USB programming cables from Xilinx and Lattice on one
131288: 08/04/17: Re: XST design frequency setting
132539: 08/05/30: Re: (won't even attempt to try again .. .. ..)
134586: 08/08/19: Re: Setting a control parameter in Active HDL
135068: 08/09/12: Re: Problem with Virtex-4 IBIS model
135094: 08/09/15: Re: Problem with Virtex-4 IBIS model
135095: 08/09/15: Re: Problem with Virtex-4 IBIS model
135337: 08/09/26: Re: Does XST support global signals?
135582: 08/10/08: Re: Does XST support global signals?
135917: 08/10/21: Re: Spartan 3 IO banking rules problem in ISE
135919: 08/10/21: Re: Problem with Virtex-4 IBIS model
135921: 08/10/21: Re: Does XST support global signals?
135955: 08/10/23: Re: Would like to try ISIM, simple question
135981: 08/10/24: Re: Would like to try ISIM, simple question
136149: 08/11/03: Re: ISE 9.2.03i problem
136482: 08/11/18: Re: Aligned PLL clocks in RTL simulation
139341: 09/03/26: Re: virtex-5 lvds termination issue?
139979: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140529: 09/05/15: Re: FPGA+FX2 API for Digilent Nexys 2 (was Programming... from Linux)
142083: 09/07/23: Re: How to implementa an FSM in block ram
142109: 09/07/24: Re: How to implementa an FSM in block ram
142119: 09/07/25: Re: How to implementa an FSM in block ram
142134: 09/07/26: Re: How to implementa an FSM in block ram
142260: 09/07/30: Re: How to implementa an FSM in block ram
142261: 09/07/30: Re: How to implementa an FSM in block ram
142263: 09/07/30: Re: Daisychaining fpga with SPI flash?
142299: 09/08/02: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142312: 09/08/03: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142542: 09/08/16: Re: Using carry chain of counters for term count detect
143512: 09/10/13: Re: FPGA on-die LVDS termination issues
143587: 09/10/16: Re: FPGA on-die LVDS termination issues
145240: 10/02/02: Re: Constraining minimum hold times (Xilinx)
145344: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145379: 10/02/07: Re: Simulating Spartan 3A pins in ltspice
145380: 10/02/07: Re: DONE_cycle:6 setting neccessary in bitgen
145447: 10/02/09: Re: DONE_cycle:6 setting neccessary in bitgen
145490: 10/02/11: Re: DONE_cycle:6 setting neccessary in bitgen
145639: 10/02/16: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
148134: 10/06/22: Re: Xilinx Timing Constraings
148135: 10/06/22: Re: Xilinx DCM Block Stability Issues
148232: 10/06/30: Re: Automatic BUFG insertion on a non clock signal in ISE 12.1
149399: 10/10/21: Re: LVDS simulation in Hyperlynx
151041: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151128: 11/03/08: Re: Anti-benchmarking clauses
151190: 11/03/14: Re: Command line for fuse (behavioral sim), for ISE WebPack
151206: 11/03/15: Re: Command line for fuse (behavioral sim), for ISE WebPack
152687: 11/10/01: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
152690: 11/10/02: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
152692: 11/10/02: Re: Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions
153672: 12/04/13: Re: The Xilinx Definition Language
154096: 12/08/04: Re: how much costs the Artix 7 devices?
154131: 12/08/15: Re: "Decimals" word in binary space
154247: 12/09/12: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
154360: 12/10/14: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
154380: 12/10/17: Re: .do files... why?
155085: 13/04/07: Re: MISC - Stack Based vs. Register Based
155780: 13/09/02: Re: Lattice Announces EOL for XP and EC/P Product Lines
155782: 13/09/03: Re: Lattice Announces EOL for XP and EC/P Product Lines
155790: 13/09/04: Re: Lattice Announces EOL for XP and EC/P Product Lines
157873: 15/05/02: Re: Spartan-3 stater kit
159090: 16/07/27: Re: Lattice Diamond 3.7 and Synplify
159104: 16/07/29: Re: Lattice Diamond 3.7 and Synplify
159531: 16/12/02: Re: Phrasing!
160235: 17/08/11: Re: sram
160238: 17/08/14: Re: sram
160240: 17/08/15: Re: sram
160667: 18/09/07: Re: What to do with an improved algorithm?
160668: 18/09/07: Re: What to do with an improved algorithm?
Brian Dickinson:
33744: 01/08/03: Re: Spanning the heirarchy
Brian Dipert:
6209: 97/04/27: Re: prep benchmarks for FPGAs
6959: 97/07/16: Re: Selection Criteria for CPLD's/FPGA's
6971: 97/07/17: Re: Selection Criteria for CPLD's/FPGA's
7211: 97/08/15: Re: FPGA power consumption
7884: 97/10/27: Re: design sites
8159: 97/11/22: New programmable logic article
8248: 97/12/03: Re: Whatever happened to PREP?
8298: 97/12/06: Re: A suggestion for Xilinx
8859: 98/02/02: Re: FPGA/ASIC - same difference?
11315: 98/08/04: Re: Caluclation of gates in FPGA
11888: 98/09/17: Re: Good EDN article on FPGA Synthesis
17016: 99/06/24: Re: FPGA benchmarks
17460: 99/07/29: Re: Partial Reconfiguration?
18592: 99/11/02: Re: PREP benchmarks
19299: 99/12/11: Re: FPGA Benchmarks
19923: 00/01/18: Re: Benchmarks
19924: 00/01/18: Re: Partly reprogrammable FPGAs
20183: 00/01/30: Re: Spartan II availability and pricing
26704: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26705: 00/10/25: Re: Design theft story in EDN. New security ?
26734: 00/10/26: Re: Design theft story in EDN. New security ?
30377: 01/04/04: Re: some info. on FPGA
31533: 01/05/29: Re: The FAQ is Live and so is the Archive
56652: 03/06/10: Re: Cheap development tools
64895: 04/01/16: Re: clarity on Gibson Guitar Story(ies)
Brian Drummond:
2469: 95/12/11: Lattice ISP download cable?
3320: 96/05/13: Re: Looking for free FPGA softw./Xilinx
4531: 96/11/10: Re: Info on FPGA Internal Architecture/ Programming
4787: 96/12/14: Re: ASICs Vs. FPGA in Safety Critical Apps.
5035: 97/01/15: Newsgroups for ASIC design and tools?
6784: 97/06/27: Re: Generating Sine/Cosine digitally
7722: 97/10/07: Re: bidirectional bus problem
7746: 97/10/10: Re: How fast can fully pipelined XC4000 logic go?
7756: 97/10/11: Re: How fast can fully pipelined XC4000 logic go?
8571: 98/01/09: Re: Synthesize large LUT
10620: 98/06/06: Re: Is there tiling software?
11066: 98/07/16: Re: Shift Invarient Bit Transform
12439: 98/10/12: Re: Digital Sine Generator
12851: 98/11/02: Re: New free FPGA CPU
12876: 98/11/03: Re: New free FPGA CPU
13142: 98/11/17: Re: Big-Endian vs Little-Endian
13196: 98/11/19: Re: Content Addressable Memorys
13248: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13531: 98/12/08: Re: computer requirements for CAE systems
14160: 99/01/16: Re: FPGA/core PCI interface system
14182: 99/01/18: Re: FPGA/core PCI interface system
14621: 99/02/06: Re: dual port RAM on XC4000
14643: 99/02/08: Re: dual port RAM on XC4000
14642: 99/02/08: Re: dual port RAM on XC4000
14670: 99/02/10: Re: dual port RAM on XC4000
14742: 99/02/14: Re: Derived Clocks and Clock enables in XILINX parts
14813: 99/02/18: Re: Synplify resource usage report for Virtex devices
15254: 99/03/16: Re: How can I improve an adder?
15339: 99/03/19: Re: How can I improve an adder?
16178: 99/05/07: Re: Fpga gates, PLD gates ASIC gates: Help us please.
16956: 99/06/19: Re: Simple PCI card prototyping.
16985: 99/06/22: Re: Simple PCI card prototyping.
17006: 99/06/23: Re: Simple PCI card prototyping.
17457: 99/07/29: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
18633: 99/11/04: Re: Fpga Compiler Altera Edition & Leonardo Spectrum
19118: 99/11/30: Re: VHDL vs. schematic entry
20992: 00/03/02: Re: Extremely fault tolerant strategies
21355: 00/03/18: Re: SpartanXL Express mode configuration
21483: 00/03/23: Re: FPGA openness
21513: 00/03/24: Re: FPGA openness
21534: 00/03/24: Re: FPGA openness
21535: 00/03/24: Re: FPGA openness
21536: 00/03/24: Re: FPGA openness
21945: 00/04/07: Re: Port "IN2" has no net attached to it-on pad cells inserted at this port.
22367: 00/05/06: Re: Q: simplest FPGA structure for novel technology demonstration
22852: 00/05/27: Re: Where can I find resource for USB?
23216: 00/06/18: Re: 3.1i
23417: 00/06/24: Re: Problem copying text from the Spartan II data sheet
25789: 00/09/20: Re: hardware compatibility and patent infringement
26568: 00/10/20: Re: VHDL vs Verilog
26763: 00/10/27: Re: Lazio Promises End to Long Island FPGA Crisis
27248: 00/11/16: Re: Schematics & VHDL
28576: 01/01/17: Re: Xilinx UCF/ngdbuild problem
28891: 01/01/27: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
29159: 01/02/08: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
29167: 01/02/08: Re: 8B/10B Encoding
29692: 01/03/05: Re: Bad Xilinx bitstream=big bang?
29729: 01/03/06: Re: Bad Xilinx bitstream=big bang?
29863: 01/03/14: Re: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
30310: 01/04/02: Re: pinout in text format for Virtex-E XCV200E
30814: 01/04/30: Re: C++ To Gates
31058: 01/05/10: Re: Shannon Capacity - An Apology
31089: 01/05/11: Re: Shannon Capacity, a quote from the paper
32082: 01/06/13: Re: Force tristate enable register into IOB
32136: 01/06/15: Re: From EDF to VHDL?
32497: 01/06/28: Re: IOB FF in Synplicity
32567: 01/06/30: Re: IOB FF in Synplicity
32601: 01/07/02: Re: IOB FF in Synplicity
33244: 01/07/20: Re: xilinx web pack problem
34293: 01/08/19: Re: Spartan2 5V PCI IO
35860: 01/10/21: Re: Verilog vs. VHDL
36268: 01/11/04: Re: Leonardo bugs
40743: 02/03/14: Re: XST duplicates unnecessary IOB OE FFs
42558: 02/04/27: Re: Does Vertex II PRO Really work?
42888: 02/05/06: Re: Frequency synthesiser
43563: 02/05/24: Re: How to generate fractional-N clock ?
48717: 02/10/23: Re: slow slew rate signal...
49858: 02/11/22: Re: 8B/10B patent problems? IBM Patent # 4486739
50971: 02/12/24: Re: thermal issues on FPGA
51005: 02/12/26: Re: thermal issues on FPGA
51346: 03/01/11: Re: Generating a 4x Clock using DLLs with Spartan-II
51558: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
52885: 03/02/25: Simulating Coregen ROM?
53438: 03/03/13: Re: write a single byte in to DRAM
53439: 03/03/13: Re: Help understanding 7408 and gate chip
53497: 03/03/14: Re: Adding delay to a signal?
53538: 03/03/15: Re: IFDs in Xilinx Foundation 4.1i
53583: 03/03/17: Re: Help understanding 7408 and gate chip
54323: 03/04/08: Re: Q: Constraints for high speed I/O signals.
54380: 03/04/09: Re: Q: Constraints for high speed I/O signals.
55271: 03/05/02: Re: Boycott All Xilinx products untill they correct all ISE software errors
56679: 03/06/11: Re: Shift registers
56680: 03/06/11: Re: What's in a bitstream?
56681: 03/06/11: Re: PC-104 dev Boards
57637: 03/07/03: Re: Suitable motherboard for Spartan-IIE PCI design
57638: 03/07/03: Re: Process variable setup times and propogations
57760: 03/07/06: Re: Excel and FPGA's
59015: 03/08/06: Re: More VHDL issues.. with ModelSim
59100: 03/08/08: Re: Need help: getting 3.1i Coregen working on P4-system
60260: 03/09/09: Re: frequency constraint changes routability
60432: 03/09/12: Re: Crystal Input to FPGA
60433: 03/09/12: Re: Time Killing Post P&R Simulation
60829: 03/09/23: Re: FPGA implementation in (V)HDL
61508: 03/10/06: Re: Timing from 1x to 2x and back
61509: 03/10/06: Re: Interesting article about FPGAs
62469: 03/10/30: Re: Some FPGA questions
62652: 03/11/04: Re: Vendor supplied symbol/part models?
63223: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
64221: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
64977: 04/01/17: Re: mapper optimization
66224: 04/02/15: Re: RFC: ARM+FPGA tiny board
66689: 04/02/25: Re: Free PCI-bridge in VHDL for Spartan-IIE
67355: 04/03/10: Re: long PAR run time for a v.v.small design in virtex II
67999: 04/03/24: Re: Virtex-4
68412: 04/04/03: Re: vertex II vs Stratix
69449: 04/05/11: Re: Easypath question (was "Hard-tocopy" rant)
69450: 04/05/11: Re: Monolithic state machine or structured state machine?
69503: 04/05/12: Re: Easypath question (was "Hard-tocopy" rant)
74900: 04/10/21: Re: spartan 3 on 4 layers
75662: 04/11/11: Re: Research Project Re: Graphics Processor
75859: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
76043: 04/11/23: Re: 18x18 Multipliers - Spartan III
76044: 04/11/23: Re: Beginers Question ModelSim Signals
76075: 04/11/24: Placement problem (floorplanner, UCF, RPM ) in Spartan-3.
76087: 04/11/24: Re: Favourite Design Entry Optomisation Method?
76472: 04/12/03: Re: EDIF -> Map & Place -> EDIF ?
76758: 04/12/10: Re: Floorplanning with only usage estimates. Is it possible?
77312: 05/01/04: Re: Multipliers implementation (xilinx)
77417: 05/01/06: Re: ISE Toolflow : hardmacro, incremental or modular
77446: 05/01/06: Re: ISE Toolflow : hardmacro, incremental or modular
77463: 05/01/07: Re: ISE Toolflow : hardmacro, incremental or modular
77516: 05/01/09: Re: ISE Toolflow : hardmacro, incremental or modular
77517: 05/01/09: Re: ISE Toolflow : hardmacro, incremental or modular
77521: 05/01/09: Re: ISE Toolflow : hardmacro, incremental or modular
77522: 05/01/09: Re: WebPack download problem
78946: 05/02/10: Re: Learning resources for Xilinx memory controllers
79263: 05/02/16: Re: Cyclone clock
79289: 05/02/16: Re: Avnet Spartan 3 Evaluation Board and PCI
79290: 05/02/16: Re: What do future FPGA's need? (was: Updated S2 Power specs)
79311: 05/02/17: Re: See the next high-wire act, this time on power consumption
79313: 05/02/17: Re: Xilinx RPM in Makefile?
79500: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
79501: 05/02/20: Re: Issues with a batch of Virtex-II chips
79570: 05/02/21: Re: hdl:lament
79623: 05/02/22: Re: Issues with a batch of Virtex-II chips
80451: 05/03/06: Re: Maximum Current utilized by Spartan-3
80968: 05/03/15: Re: Creating own RPMs using Xilinx ISE
80969: 05/03/15: Re: XCF01's in the UK
81902: 05/04/04: Re: how to use both FFs in a CLB's slice using LOC or RLOC
82493: 05/04/13: Re: RLOC question
83090: 05/04/23: Re: Xilinx multiplier out of slices
92487: 05/11/30: Re: subtractor
92663: 05/12/03: Re: What if....
92701: 05/12/05: Virtex-4 DSP48 placement restrictions?
92717: 05/12/05: Re: Virtex-4 DSP48 placement restrictions?
92750: 05/12/06: Re: What's wrong with the document?
92751: 05/12/06: Re: Virtex-4 DSP48 placement restrictions?
92978: 05/12/10: Re: ISE purchase
94149: 06/01/06: Re: RTL for Z8000 series CPU?
94122: 06/01/06: Re: VHDL FF Question
94204: 06/01/07: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94315: 06/01/09: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94254: 06/01/09: Re: dma on fpga pci card
94255: 06/01/09: Re: "failed to create empty document"
94499: 06/01/12: Re: FPGA Journal Article
94673: 06/01/16: Re: FPGA Journal Article
94887: 06/01/19: Re: FPGA Journal Article
95008: 06/01/20: Re: FPGA Journal Article
94678: 06/01/16: Re: Mistake in Xilinx dsp-book.pdf?
95801: 06/01/26: Re: Mistake in Xilinx dsp-book.pdf?
94888: 06/01/19: Re: data2bram and coregen
95030: 06/01/20: Re: Sorting large amounts of floats
95126: 06/01/21: Re: need for a group FAQ?
95211: 06/01/21: Re: working with XDL
95319: 06/01/22: Re: working with XDL
95397: 06/01/23: Re: working with XDL
95212: 06/01/21: Re: Modelsim problem
95321: 06/01/22: Re: Virtual Pin in Xilinx ISE
95668: 06/01/25: Re: custom ip using EDK
95802: 06/01/26: Re: custom ip using EDK
95803: 06/01/26: Re: So what happened to JHDLBits?
95805: 06/01/26: Re: Spartan-3 Starter Board
96110: 06/01/30: Re: Digilent FPGA & Handel-C
96206: 06/01/31: Re: Digilent FPGA & Handel-C
96205: 06/01/31: Re: Digilent FPGA & Handel-C
96222: 06/02/01: Re: Digilent FPGA & Handel-C
96060: 06/01/29: Re: XDL Tools wiki site
96169: 06/01/31: Re: Xilinx Legal
96410: 06/02/03: Re: BGA central ground matrix
96428: 06/02/03: Re: BGA central ground matrix
96429: 06/02/03: Re: Xilinx: generic tristates and multiplexers
96470: 06/02/04: Re: Xilinx: generic tristates and multiplexers
96810: 06/02/10: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96869: 06/02/12: Re: Simulation problem using CONV_INTEGER
97183: 06/02/18: Re: Xilinx UCF area constraints disappearing
97362: 06/02/21: Re: FPGA - software or hardware -2-
97526: 06/02/23: Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
97602: 06/02/24: Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
97604: 06/02/24: Re: Variables in VHDL and simulation
97759: 06/02/27: Re: tricks to make large PLAs fast?
98301: 06/03/08: Re: Internal Signals in OPB EMC In XIlinx PLatform studio
98399: 06/03/09: Re: VHDL
98524: 06/03/12: Re: FIFO Simulation Oddities!
99493: 06/03/25: Re: How to do profiling on hardware target on Microblaze
99781: 06/03/29: Re: Linux on ml403
100009: 06/04/01: Re: deglitching a clock
100010: 06/04/01: Re: ModelSim Designer
100049: 06/04/02: Re: ModelSim Designer
101079: 06/04/25: Re: Where is the xilinx online store gone?
101260: 06/04/28: Re: Xilinx Virtex-4 OCM Usage Issues
101262: 06/04/28: Re: Development Platform for begginer
101350: 06/04/29: Re: Xilinx Virtex-4 OCM Usage Issues
101736: 06/05/05: Re: RFID chip has battary in it or not
102450: 06/05/16: Re: WARNING:iMPACT:923 - Can not find cable, check cable setup !
106372: 06/08/12: Re: Embedded clocks
106373: 06/08/12: Re: Embedded clocks
106374: 06/08/12: Re: EDK: OPB_IPIF, too many versions...
107353: 06/08/27: Re: What is the truth about the Virtex5 ?
107421: 06/08/28: Re: What is the truth about the Virtex5 ?
107918: 06/09/02: Re: Impossible to download WebPACK?
107960: 06/09/03: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
108262: 06/09/07: Re: Global constants definition problem
108263: 06/09/07: Re: How to bound a Cores generated output in Modelsim
108501: 06/09/12: Re: Simulating EDK 8.1i System using ModelSim 6.1e
108570: 06/09/13: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108571: 06/09/13: Re: Simulating EDK 8.1i System using ModelSim 6.1e
108574: 06/09/13: Re: Xilinx Platform Studio, build up System: "block-RAM components require the adjacent multiplier"
108575: 06/09/13: Re: Xilinx Platform Studio, build up System: "block-RAM components require the adjacent multiplier"
108761: 06/09/16: Re: problems with IOSTANDARD
108810: 06/09/17: Re: problems with IOSTANDARD
108909: 06/09/19: Re: Xilinx xapp802.pdf mistake?
109033: 06/09/20: Re: synchronous clocks
109137: 06/09/21: Re: Question about initializing on-chip block mem in XPS?
109519: 06/09/27: Re: Pack registers (from submodule) into IOB for bidirectionnal signal
109520: 06/09/27: Re: MicroBlaze : Linkerscript for splitting the text block into 64kByte blocks
109580: 06/09/29: Re: ModelSim path problem as fed by Xilinx ISE ver 8.2.03i
110049: 06/10/10: Re: CPLD's and labels
110359: 06/10/14: Re: [ISE8.2] DIFF_TERM and unused pin
110360: 06/10/14: Re: Xilinx V4 not registering T at OLOGIC
110464: 06/10/16: Re: SPAM or Not - Re: Platform USB Cable schematic
110550: 06/10/17: Re: Virtex-5 LXT launched today !
110577: 06/10/18: Re: Virtex-5 LXT launched today !
110755: 06/10/21: Re: SDF sim failure: 8.2i/Spartan-3
110756: 06/10/21: Re: Code synthesizes to one FPGA but not to another?
110832: 06/10/24: Re: iMPACT:923 - Can not find cable, check cable setup !
111250: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111513: 06/11/04: Re: digilent spartan-3 board sram timing
112436: 06/11/22: Re: DDR_VDHL_models
112734: 06/11/28: Re: problems with verilog SDRAM models
113085: 06/12/06: Re: RLOC weirdness
113432: 06/12/13: Re: . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
113524: 06/12/15: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
113731: 06/12/20: Re: Xilinx Quiz: 150/3 = ?
113732: 06/12/20: Re: PowerPC_simulation
113798: 06/12/22: Re: DCM start up
113860: 06/12/26: Re: better ways for debugging?
114136: 07/01/05: Re: Surface mount ic's
114139: 07/01/05: Re: PPC cache errata
114172: 07/01/06: Re: [XST 8.2.3] DSP48 inference multiply/add
114175: 07/01/06: Re: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs
114351: 07/01/12: Re: Xilinx Floorplanner 'Replace All With Placement' and still logic left over!
114352: 07/01/12: Re: Medwedjew - who was that guy?
114428: 07/01/15: Re: Transport Delays in Modelsim
114570: 07/01/19: Re: Beginner VHDL questions
114915: 07/01/26: Re: xilinx 8.2 xps debug problems
114916: 07/01/26: Re: how do you code this?
115358: 07/02/08: Re: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
115440: 07/02/11: Re: ModelSim - Do Files
115729: 07/02/18: Re: Do you like Virtex-5 ?
115912: 07/02/25: Re: How to specify ISE INST constraint with GENERATE statements?
116416: 07/03/08: Re: Spartan3AN - Roadmap
116417: 07/03/08: Re: Introducing picosecond delay between two output signals
116418: 07/03/08: Re: using XIlinx impact in batch mode to generate EEPROM files
116640: 07/03/14: Re: Xilin X-Fest Lunacy
117312: 07/03/28: Re: (Xilinx) OPB watchdog timer fails to release RESET
117359: 07/03/29: Re: Watershed Transform
117564: 07/04/04: Re: Boot PowerPC on VirtexIIPro
117624: 07/04/05: Re: Implement IIR Filter on FPGA
118080: 07/04/17: Re: par [placer] consistency
118970: 07/05/08: Re: First MicroBlaze demo design for Spartan-3A Starterkit
119002: 07/05/09: Re: First MicroBlaze demo design for Spartan-3A Starterkit
119003: 07/05/09: Re: An Open-Source suggestion for Xilinx
119231: 07/05/15: Re: coregen -> simulation error in modelsim
119234: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119289: 07/05/16: Re: ise project navigator can't dereference edk pcores from XilinxProcessorIPLib
119290: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119360: 07/05/17: Re: VHDL newbie: building sequential circuits with basic gates
119556: 07/05/22: Re: First MicroBlaze demo design for Spartan-3A Starterkit
119587: 07/05/23: Re: How to include pcores librarys from XilinxProcessorIPLib (EDK) into ISE project???
119653: 07/05/24: Re: problem while reading from DDR 2 memory
119742: 07/05/25: Re: problem while reading from DDR 2 memory
119746: 07/05/25: Re: Xilinx 8.2 : Multippass P&R
119802: 07/05/26: Re: VGA signal through breadboard?
119855: 07/05/28: Re: 6502 FPGA core
119898: 07/05/29: Re: 6502 FPGA core
119899: 07/05/29: Re: 6502 FPGA core
120022: 07/05/31: Re: 6502 FPGA core
120203: 07/06/03: Re: 180 differential inputs each 800Mbps using V5
120302: 07/06/05: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120303: 07/06/05: Re: ISE and total equivalent gate count
120546: 07/06/09: Re: XST net splitting blocks placement
120547: 07/06/09: Re: Affordable pcie card ?
120782: 07/06/16: Re: help on clock fowarding between 2 FPGAs
121162: 07/06/27: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
121312: 07/07/02: Re: intermitent boot in V4
121583: 07/07/09: Re: Debugging in EDK
122292: 07/07/25: Re: hard_temac : mdio conflict
122604: 07/08/01: Re: DDR Simulation Model
122652: 07/08/02: Re: hard_temac : mdio conflict
122654: 07/08/02: Re: Xilinx/ModelSim bug ? Clocking headache ...
122655: 07/08/02: Re: DDR Simulation Model
122656: 07/08/02: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
122882: 07/08/09: Re: Xilinx Webpack 9.1: How do I export a netlist to another project?
123024: 07/08/14: Re: xst fails...
123248: 07/08/21: Re: Voltage translation question
123563: 07/08/30: Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
123624: 07/08/31: Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
123625: 07/08/31: Re: Spartan3E and DDR termination
123626: 07/08/31: Re: PCB Impedance Control
123871: 07/09/06: Re: New keyword 'orif' and its implications
123874: 07/09/06: Re: high bandwitch ethernet communication
123941: 07/09/07: Re: New keyword 'orif' and its implications
124686: 07/09/30: Re: XUPV2P from digilentinc
124701: 07/10/01: Re: Synplicity and the Xilinx MAP Memory Monster
124905: 07/10/10: Re: Starting FPGA
124906: 07/10/10: Re: DDR DIMM clock distribution
125488: 07/10/26: Re: HELP, how to time constraint part of a design?
125489: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
125526: 07/10/27: Re: Changing refresh rate for DRAM while in operation?
125528: 07/10/27: Re: Xilinx Isolate circuitry
125541: 07/10/28: Re: Power supply filter capacitors
125699: 07/11/01: Re: HELP, how to time constraint part of a design?
125887: 07/11/08: Re: Non-volatile FPGA in a small package
126044: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
126135: 07/11/15: Re: newbie to 16v8
126137: 07/11/15: Re: FPGA for hobby use
126138: 07/11/15: Re: Xilinx Virtex-II Newbie
126179: 07/11/16: Re: FPGA for hobby use
126180: 07/11/16: Re: Xilinx Virtex-II Newbie
126181: 07/11/16: Re: Xilinx Virtex-II Newbie
126283: 07/11/19: Re: simulating xilinx block ram with modelsim
126366: 07/11/20: Re: simulating xilinx block ram with modelsim
126401: 07/11/21: Re: simulating xilinx block ram with modelsim
126425: 07/11/21: Re: Xilinx XST 8.2, Error on multi-source, bug?
126541: 07/11/27: Re: xilinx spartan 3 + 16 adc
126542: 07/11/27: Re: scanf and printf in EDK's BSP
126596: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126672: 07/11/29: Re: Global Reset using Global Buffer
126731: 07/11/30: Re: CPU design uses too many slices
127077: 07/12/11: Re: Net hierarchy with Xilinx 9.1
127119: 07/12/12: Re: DDS generator with interpolated samples for Spartan3E development board
127176: 07/12/13: Re: Newbee Microblaze system BRAM utlization confusion
127177: 07/12/13: Re: Poor quality Xilinx boards ? Your experience ?
127178: 07/12/13: Re: spartan 3e VQ100 serious question
127180: 07/12/13: Re: WARNING:PAR:289 and bitgen error.
127218: 07/12/14: Re: FPGA Board design basics
127220: 07/12/14: Re: Newbee Microblaze system BRAM utlization confusion
127239: 07/12/15: Re: spartan 3e VQ100 serious question
127358: 07/12/19: Re: sampling error between 2 clocks
127457: 07/12/27: Re: Core Generators...
127458: 07/12/27: Re: Xilinx XST questions
127482: 07/12/28: Re: Core Generators...
127483: 07/12/28: Re: Xilinx XST questions
127484: 07/12/28: Re: Xilinx XST questions
127502: 07/12/29: Re: Core Generators...
127523: 08/01/01: Re: State machine with stack to implement "subroutines"
127632: 08/01/04: Re: Split Plane
127635: 08/01/04: Re: [Resolved]WebPack on GNU/Linux
127637: 08/01/04: Re: simulation problems
127907: 08/01/10: Re: Identification of FPGA Development Board
128258: 08/01/19: Re: How is FIFO implemented in FPGA and ASIC?
128311: 08/01/21: Re: VHDL Micron memorymodel.
128512: 08/01/29: Re: Grisoft AVG false positve virus detection in Xilinx software.
128543: 08/01/30: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128544: 08/01/30: Re: Grisoft AVG false positve virus detection in Xilinx software.
128545: 08/01/30: Re: difference between net skew in the clock report and clock skew in trce log
128907: 08/02/09: Re: function/process to generate sine and cosine wave
129098: 08/02/14: Re: signal generation in VHDL on FPGA.... Check my code please
130220: 08/03/18: Re: Chipscope
130221: 08/03/18: Re: FSL or DMA w/ FIFO?
130276: 08/03/19: Re: Optimizing an inferred counter
130363: 08/03/21: Re: A Challenge for serialized processor design and implementation
130565: 08/03/27: Re: Xilinx ISE 9.2i out of memory
130645: 08/03/29: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
130646: 08/03/29: Re: async clk input, clock glitches
130768: 08/04/01: Re: Xilinx and Modelsim?
130840: 08/04/03: Re: coregenerator bram in synplify pro error
130928: 08/04/05: Re: Antii, can you give us an update?
130970: 08/04/07: Re: Antii, can you give us an update?
131056: 08/04/09: Re: Modify POF with new ESB (ROM) content?
131156: 08/04/13: Re: Serial Transmission w/o 8B/10B encoding
131173: 08/04/14: Re: XST support for User Defined Primitives
131197: 08/04/15: Re: DOS script file to synthesize a VHDL design
131236: 08/04/16: Re: Which to learn: Verilog vs. VHDL?
131259: 08/04/17: Re: Help, router can't rout all connections (XILINX)
131401: 08/04/21: Re: Very simple VHDL problem
131471: 08/04/22: Re: Problem writing quadrature decoder
131472: 08/04/22: Re: opb_intc + PowerPC
131498: 08/04/23: Re: opb_intc + PowerPC
131618: 08/04/26: Re: noob question
131851: 08/05/04: Re: FPGA Processor for Signal Processing ?
131985: 08/05/09: Re: 5 V oscillator output to GCLK
132042: 08/05/11: Re: how to set trigger in ChipScopePro for this
132172: 08/05/16: Re: FPGA imp
132173: 08/05/16: Re: Incorporating FPGAs on PCBs
132174: 08/05/16: Re: What could be the problem?
132199: 08/05/17: Re: Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25, ML401 board
132211: 08/05/18: Re: Problem with conversions.vhd
132213: 08/05/18: Re: Problem with conversions.vhd
132231: 08/05/19: Re: Problem with conversions.vhd
132307: 08/05/21: Re: timing constraint is impossible to meet
132511: 08/05/29: Re: asic gate count
132512: 08/05/29: Re: Xilinx LogicCore Direct Instantiation
132513: 08/05/29: Re: error when 'generating simulation hdl files' in xilinx xps
132514: 08/05/29: Re: RGB video panel
132682: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132683: 08/06/05: Re: Xilinx vs Altera
132789: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
133105: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133152: 08/06/19: Re: Synthesis results when testing for 'X' and 'U'
133154: 08/06/19: Re: Synthesis results when testing for 'X' and 'U'
133155: 08/06/19: Re: Fixed point number hardware implementation
133158: 08/06/19: Re: NVIDIA’s Tesla T10P Blurs Some Lines
133159: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133223: 08/06/21: Re: altera technical question?
133408: 08/06/27: Re: synthesis error
133455: 08/06/30: Re: arithmetic problem
133535: 08/07/03: Re: minipci breadboard with fpga
133553: 08/07/03: Re: minipci breadboard with fpga
133565: 08/07/04: Re: External Clock Generator
133617: 08/07/07: Re: basic chipscope pro query
133647: 08/07/08: Re: V4FX20 upgrade to FX40 problem (was: Xilinx ISE speed files compatibilit)
133733: 08/07/12: Re: How to simulate baud rate generator?
133770: 08/07/14: Re: How to prevent mapper stripping when synthesizing without IO buffers?
133857: 08/07/17: Re: Xilinx/Altera gate equivalence
133921: 08/07/19: Re: Additional Hardware Module with Xilinx MicroBlaze Processor
134025: 08/07/22: Re: audio serial port i2s
134109: 08/07/26: Re: Creating new operators
134153: 08/07/28: Re: Creating new operators
134154: 08/07/28: Re: Creating new operators
134155: 08/07/28: Re: Chipscope Error
134171: 08/07/29: Re: Chipscope Error
134172: 08/07/29: Re: Creating new operators
134218: 08/07/31: Re: ISE new file wizard
134384: 08/08/08: Re: RTL Schematic as EDIF
134430: 08/08/10: Re: Block Rams
134619: 08/08/21: Re: VHDL models for DDR2 SDRAM?
134697: 08/08/26: Re: Side-BUFG, BRAMS and clock routing
134708: 08/08/27: Re: Saving PAR Constraints
134804: 08/09/02: Re: ED 9.2 too new cygwin error
134833: 08/09/03: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134834: 08/09/03: Re: what is the maximum number of DDR controllers
134854: 08/09/04: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134855: 08/09/04: Re: Strange Spartan2 behaviour
134869: 08/09/04: Re: Hide VHDL code.
134946: 08/09/08: Re: Best way to buy Xilinx FPGAs?
134947: 08/09/08: Re: Signed multiplication
134973: 08/09/09: Re: Signed multiplication
135004: 08/09/10: Re: Are Xilinx tools that bad, or am I missing something?
135178: 08/09/19: Re: Help~ How to develope with FPGA board?
135199: 08/09/20: Re: Peter says Good Bye
135200: 08/09/20: Re: WebPack on CentOS 5 ?
135246: 08/09/23: Re: SDRAM question
135247: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
135249: 08/09/23: Re: Use of divided clocks inside modules
135279: 08/09/24: Re: Is it possible to get an RTL netlist from Xilinx tools?
135284: 08/09/24: Re: SDRAM question
135300: 08/09/25: Re: Weird DCM problem with external deskew
135340: 08/09/27: Re: Open source IP core development with configuration GUI
135385: 08/09/30: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
135393: 08/09/30: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
135432: 08/10/02: Re: Problem with mpmc(4.02.a) simulation -- DDR never initializes
135448: 08/10/02: Re: Low frequency clock generation - need help
135449: 08/10/02: Re: floating point round off errors
135464: 08/10/03: Re: floating point round off errors
135473: 08/10/03: Re: floating point round off errors
135474: 08/10/03: Re: WEBPACK for linux
135519: 08/10/06: Re: Barrel Shifter: Newbie's Attempt
135520: 08/10/06: Re: Connecting MPD I/O ports in xps_sysace
135538: 08/10/07: Re: Low frequency clock generation - need help
135539: 08/10/07: Re: Low frequency clock generation - need help
135540: 08/10/07: Re: Barrel Shifter: Newbie's Attempt
135590: 08/10/09: Re: Do two clock system blocks with one clock running half of other's need asynchronous input/output buffers?
135671: 08/10/12: Re: XMOS XC-1 kits are shipping
135688: 08/10/13: Re: Complex Event Processing on FPGA
135689: 08/10/13: Re: Complex Event Processing on FPGA
135784: 08/10/16: Re: Simulation
135808: 08/10/16: Re: Simulation
135912: 08/10/22: Re: Question on timing constraints
135913: 08/10/22: Re: Would like to try ISIM, simple question
135928: 08/10/22: Re: Spartan 3 IO banking rules problem in ISE
135961: 08/10/24: Re: Would like to try ISIM, simple question
135962: 08/10/24: Re: Spartan 3 IO banking rules problem in ISE
136025: 08/10/28: Re: Question on timing constraints
136047: 08/10/29: Re: ISE 9.2.03i problem
136048: 08/10/29: Re: PLBv4.6 with more than 16 slaves
136074: 08/10/30: Re: Register File distributed all over the FPGA
136076: 08/10/30: Re: Register File distributed all over the FPGA
136094: 08/10/31: Re: ISE 9.2.03i problem
136095: 08/10/31: Re: ISE 9.2.03i problem
136105: 08/11/01: Re: classic Spartan-3 DDR2 and IOBs
136106: 08/11/01: Re: ISE 9.2.03i problem
136111: 08/11/02: Re: timing issue with ISE10 SP3
136115: 08/11/02: Re: ISE 9.2.03i problem
136122: 08/11/03: Re: requesting solution for error:HDLParsers:810
136128: 08/11/03: Re: requesting solution for error:HDLParsers:810
136147: 08/11/04: Re: ISE 9.2.03i problem
136155: 08/11/04: Re: ISE 9.2.03i problem
136157: 08/11/04: Re: How to move project files from ISE 7.1 to ISE 10.1
136206: 08/11/05: Re: Would like to try ISIM, simple question
136347: 08/11/12: Re: Polmaddie1 - VHDL and Verilog Training Board
136348: 08/11/12: Re: ISE 9.2.03i problem
136364: 08/11/13: Re: ISE 9.2.03i problem
136371: 08/11/13: Re: clock problem
136425: 08/11/16: Re: Would like to try ISIM, simple question
136445: 08/11/17: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
136528: 08/11/20: Re: how to implement an application with external memory in ISE?
136735: 08/12/03: Re: Dynamical alteration of signal path
136736: 08/12/03: Re: Back-annotated simulation for Xilinx devices
136802: 08/12/06: Re: Project/File corruption problem with ISE 10.1
136893: 08/12/11: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136894: 08/12/11: Re: mapping to custom architecture
136904: 08/12/11: Re: mapping to custom architecture
137009: 08/12/18: Re: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit hidden by declaration of 'ps' at line 651
137175: 08/12/30: Re: How do I xor two signals in VHDL?
137197: 09/01/01: Re: error in synthesizing in ise although correct behavioral simulation
137256: 09/01/06: Re: beginner synthesize question - my debounce process won't synthesize.
137259: 09/01/06: Re: beginner synthesize question - my debounce process won't synthesize.
137268: 09/01/07: Re: beginner synthesize question - my debounce process won't synthesize.
137269: 09/01/07: Re: beginner synthesize question - my debounce process won't synthesize.
137309: 09/01/08: Re: Which revision control do fpga designers use (2009)
137319: 09/01/08: Re: beginner synthesize question - my debounce process won't synthesize.
137322: 09/01/08: Re: beginner synthesize question - my debounce process won't synthesize.
137323: 09/01/08: Re: beginner synthesize question - my debounce process won't synthesize.
137352: 09/01/10: Re: beginner synthesize question - my debounce process won't synthesize.
137374: 09/01/13: Re: ISE Simulator and State Machines
137391: 09/01/14: Re: beginner synthesize question - my debounce process won't synthesize.
137509: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137539: 09/01/22: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137540: 09/01/22: Re: FPGA granularity
137541: 09/01/22: Re: FPGA granularity
137542: 09/01/22: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
137566: 09/01/22: Re: Running 32 bit ISE on 64 bit linux
137567: 09/01/22: Re: xst: Multiple drivers but one is dangling, how to ignore?
137698: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137699: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137702: 09/01/28: Re: What software do you use for PCB with FPGA ?
137726: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137727: 09/01/28: Re: What software do you use for PCB with FPGA ?
137728: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137752: 09/01/28: Re: Spartan-6
137755: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137756: 09/01/29: Re: new source wizard doesn't seem to work.
137781: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137782: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137783: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137806: 09/01/30: Re: new source wizard doesn't seem to work.
137898: 09/02/02: Re: Selecting a starter FPGA board
137937: 09/02/02: Re: auto reset / rs 232
138036: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138037: 09/02/04: Re: Why the second flip-flop in Virtex-6?
138207: 09/02/09: Re: Is this phase accumulator trick well-known???
138211: 09/02/09: Re: Is this phase accumulator trick well-known???
138212: 09/02/09: Re: Is this phase accumulator trick well-known???
138225: 09/02/09: Re: Is this phase accumulator trick well-known???
138226: 09/02/10: Re: Is this phase accumulator trick well-known???
138237: 09/02/10: Re: problem in place and route
138352: 09/02/17: Re: Precedence of signal assignment in a clocked process
138381: 09/02/18: Re: Problem with ModelSim and Xilinx PCIe endpoint block plus simulation
138436: 09/02/23: Re: Spartan 3E Slave Serial problems
138502: 09/02/25: Re: mb-gcc producing incorrect code ???
138522: 09/02/26: Re: Configure FPGA via PCIe
138840: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
139115: 09/03/21: Re: How big is my vhdl and am I approaching some size limitation on the chip.
139138: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on the chip.
139156: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on the chip.
139421: 09/03/29: Re: partitions and incremental design with xilinx ISE
139531: 09/04/02: Re: Maximum frequency
139549: 09/04/03: Re: Switching an AC power socket from an FPGA
139551: 09/04/03: Re: SSO
139608: 09/04/07: Re: Modulo-10 counter
139658: 09/04/08: Re: Two stage synchroniser,how does it work?
139677: 09/04/09: Re: @@@@@@@@About DSP48 used for 24bit * 18bit @@@@@@@@
139782: 09/04/14: Re: Processor returns-Explanation
139886: 09/04/18: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139900: 09/04/18: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139901: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139913: 09/04/19: Re: Dual-frequency quartz oscillator with a FPGA ?
139914: 09/04/19: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139928: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139937: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139938: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA ?)
139961: 09/04/21: Re: FPGA lockup with pinout report view. was: fpga locks up with slow signal, spartan chip, pin type issues.
139995: 09/04/23: Re: ISE 10.1 installation troubles on windows Vista 32bit
140020: 09/04/24: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140102: 09/04/28: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140122: 09/04/29: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140462: 09/05/14: Re: XML for LUT+FF netlist representation in (academic) tools
140502: 09/05/15: Re: sync vs async reset
140580: 09/05/19: Re: sync vs async reset
140661: 09/05/21: Re: ISIM and CONV_INTEGER warnings
140663: 09/05/21: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140788: 09/05/26: Re: When is it to generate transparent latch or usual combinational logic?
140789: 09/05/26: Re: Multple architectures in ISE top level module?
141238: 09/06/12: Re: ISE 10.1 Free Downlaod Web Install
141244: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141264: 09/06/14: Re: Correlation Algorithm: converting user type integer array into std_logic_vector
141506: 09/06/26: Re: Virtex-6 shipping?
141552: 09/06/27: Re: 6/6 infos
141710: 09/07/04: Re: Active-HDL simulator recompile... or not recompiling
142331: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142397: 09/08/09: Re: EVERAGE ?
142512: 09/08/14: Re: Mixed language simulation on the cheap
142577: 09/08/18: Re: Embedded Memory Controller
142590: 09/08/19: Re: Help with crystal oscillator (MG-7010SA replacement)?
142672: 09/08/25: Re: Why there is multi-source error in these VHDL code?
142783: 09/09/01: Re: Polynomial Function ...
142802: 09/09/02: Re: program spartan3 under linux
142903: 09/09/07: Re: Choice of Language for FPGA programming
142908: 09/09/08: Re: Choice of Language for FPGA programming
142957: 09/09/10: Re: Traversing hierarchy in UCF works for OBUF, but not IOBUF, please help
143009: 09/09/15: Re: ANN: Coding style guidance for FPGA memory
143193: 09/09/25: Re: Shift left arithmetic?
143366: 09/10/06: Re: Virtx 4 and FPGA programming
143423: 09/10/11: Re: Getting started...
143435: 09/10/11: Re: Getting started...
143456: 09/10/12: Re: Getting started...
143507: 09/10/14: Re: FPGA on-die LVDS termination issues
143508: 09/10/14: Re: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild:604
143563: 09/10/16: Re: The performance of endpoint block plus for PCIe regression when upgrading to V1.12 ?
143607: 09/10/18: Re: Any interest in a group Xilinx FPGA board build/buy ??
143649: 09/10/20: Re: The performance of endpoint block plus for PCIe regression when upgrading to V1.12 ?
143847: 09/10/29: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
143848: 09/10/29: Re: Best way to model a large external ROM in a simulation? (XST simulator)
143849: 09/10/29: Re: error while opening hex file
143872: 09/10/30: Re: Best way to model a large external ROM in a simulation? (XST simulator)
143885: 09/11/02: Re: Best way to model a large external ROM in a simulation? (XST simulator)
143955: 09/11/04: Re: Data2MEM Error - 33 : Matching ADDRESS_SPACE not found
143963: 09/11/05: Re: Data2MEM Error - 33 : Matching ADDRESS_SPACE not found
144018: 09/11/07: Re: Does anyone ever use placement?
144023: 09/11/07: Re: Does anyone ever use placement?
144341: 09/11/28: Re: webpack crashed how do I get these things back?
144525: 09/12/13: Re: Data2MEM - finding the blockrams after PAR?
144548: 09/12/14: Re: Please Help me
144673: 09/12/22: Re: Please help, Xilinx FIFO problem!
144718: 09/12/28: Re: Info on heritage Nallatech board?
144736: 09/12/30: Re: Xilinx and Multi-port memories
144905: 10/01/14: Re: black box module integration
144921: 10/01/15: Re: Which WebPack for old Spartan and Spartan-2?
144961: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
144964: 10/01/17: Re: Simulation of VHDL code for a vending machine
144997: 10/01/19: Re: compiler output to fpga.
145592: 10/02/15: Re: How relevant is the Residue Number System (RNS)?
145593: 10/02/15: Re: optimal no of inputs to be given in a test bench
145637: 10/02/17: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
145671: 10/02/18: Re: Unpredictable design
145698: 10/02/19: Re: Derived clock violation in Virtex4
145787: 10/02/23: Re: Derived clock violation in Virtex4
146148: 10/03/07: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146168: 10/03/07: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146366: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
146378: 10/03/15: Re: how can i add memory
146379: 10/03/15: Re: how to use the design results of the vhdl code for a program in C code
146396: 10/03/16: Re: how to use the design results of the vhdl code for a program in C code
146951: 10/04/03: Re: Is there a way to implement division by variables other than 2 in single clock with XST ?
146971: 10/04/06: Re: Extract single bit from std_logic_vector ...
147137: 10/04/15: Re: I'd rather switch than fight!
147165: 10/04/16: Re: I'd rather switch than fight!
147336: 10/04/23: Re: I'd rather switch than fight!
147389: 10/04/26: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147426: 10/04/27: Re: I'd rather switch than fight!
147427: 10/04/27: Re: Booting Linux from my own bootloader
147453: 10/04/27: Re: Question about PCB CAD for FPGA-based project
147472: 10/04/28: Re: I'd rather switch than fight!
147473: 10/04/28: Re: Booting Linux from my own bootloader
147492: 10/04/28: Re: I'd rather switch than fight!
147494: 10/04/28: Re: I'd rather switch than fight!
147495: 10/04/28: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
147507: 10/04/29: Re: I'd rather switch than fight!
147520: 10/04/29: Re: Large Fanout
147522: 10/04/29: Re: I'd rather switch than fight!
147523: 10/04/29: Re: I'd rather switch than fight!
147539: 10/04/30: Re: I'd rather switch than fight!
147547: 10/05/01: Re: I'd rather switch than fight!
147548: 10/05/01: Re: Cheap FPGAs for tutorial
147732: 10/05/20: Re: BLK_MEM_GEN_v2_8.I948.10 error when using BRAM Xilinx ISE 10.1
147751: 10/05/21: Re: Debugging SDRAM interfaces
147767: 10/05/23: Re: Debugging SDRAM interfaces
147768: 10/05/23: Re: Last Xilinx Webpack that was big-brother free?
147770: 10/05/23: Re: Last Xilinx Webpack that was big-brother free?
147776: 10/05/24: Re: Debugging SDRAM interfaces
147813: 10/05/25: Re: mux behavior
147815: 10/05/25: Re: mux behavior
147826: 10/05/26: Re: Advice on Xilinx Spelunking
147831: 10/05/26: Re: Advice on Xilinx Spelunking
147862: 10/05/27: Re: MIG v3.0 inputs signal
147879: 10/05/28: Re: Advice on Xilinx Spelunking
147951: 10/06/04: Re: Verifying/comparing the FFT output between Xilinx Coregen block and Matlab’s fft function
147953: 10/06/04: Re: OT and Newbie: SDRAM Auto Refresh
147961: 10/06/04: Re: Verifying/comparing the FFT output between Xilinx Coregen block and Matlab’s fft function
148089: 10/06/20: Re: Xilinx DCM Block Stability Issues
148116: 10/06/22: Re: Xilinx Timing Constraings
148190: 10/06/25: Re: Binary integer to ASCII string in HDL?
148423: 10/07/22: Re: Parallel Cable IV under Ubuntu Linux 10.04
148437: 10/07/22: Re: Parallel Cable IV under Ubuntu Linux 10.04
148438: 10/07/22: Re: Using std_ulogic at synthesis level
148499: 10/07/28: Re: Problems with VHDL lookup table in Quartus
148723: 10/08/18: Re: SDK example from Xilinx do not compile
148725: 10/08/18: Re: FPGA PCI BOARD .. Few Questions
148826: 10/08/30: Re: FPGA DAC Interface
148862: 10/09/05: Re: Want to get into FPGA
148950: 10/09/15: Re: Question about OC PCI Cores
149097: 10/09/30: Re: SDRAM for specific use - performance and timing questions
149240: 10/10/11: Re: Spartan-6 Boards
149289: 10/10/14: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149297: 10/10/14: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149302: 10/10/15: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149307: 10/10/15: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149401: 10/10/22: Re: Analysis of the same path by two different tools in ISE yields different results.
149429: 10/10/25: Re: 0x80000000 Integer not supported??
149449: 10/10/26: Re: Ncvhdl Problem with simple logical operators
149462: 10/10/27: Re: Ncvhdl Problem with simple logical operators
149505: 10/11/01: Re: Timing error for EDK project using a DCM?
149511: 10/11/01: Re: Timing error for EDK project using a DCM?
149512: 10/11/01: Re: Timing error for EDK project using a DCM?
149525: 10/11/02: Re: Xilinx ConstraintSystem:59
149537: 10/11/03: Re: Timing error for EDK project using a DCM?
149550: 10/11/04: Re: Good Dev Board
150094: 10/12/12: Re: PCI Architecture Question for Data Acquisition Board
150128: 10/12/15: Re: ISIM simulation speed
150129: 10/12/15: Re: Xilinx support makes me want to scream
150204: 10/12/31: Re: I Give Up!
150272: 11/01/07: Re: Cheap Altera dev board with LVDS-compatible connector?
150400: 11/01/16: Re: Location constraints questions
150763: 11/02/09: Re: FPGA changes behaviour when the resource's usage percentage changes
150777: 11/02/10: Re: Simple clock question
150779: 11/02/10: Re: PCI Express Transfer
150944: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
151381: 11/03/30: Re: MAX II CPLD and I2S Clock divider jitter
151506: 11/04/15: Re: ML505 NOT RECOGNIZED BY THE PC THROUGH PCI EXPRESS
151751: 11/05/14: Re: Best syntheses
151759: 11/05/15: Re: Best syntheses
151780: 11/05/18: Re: Counter clocks on both edges sometimes, but not when different
151980: 11/06/17: Re: Area Optimization
152027: 11/06/23: Re: Depth of logical Circuit
152036: 11/06/23: Re: Depth of logical Circuit
152072: 11/06/30: Re: XST 13.1 explodes with generic of enum type with only one
152109: 11/07/07: Re: Spartan3DSP TphDCM spec question
152208: 11/07/21: Re: source synchronous DDR bus with non-continuous clock
152218: 11/07/22: Re: FSL Problem:Data Return and Use
152229: 11/07/25: Re: FSL Problem:Data Return and Use
152290: 11/08/03: Re: XST 13.1 explodes with generic of enum type with only one
152590: 11/09/16: Re: clock enable for fixed interval
152630: 11/09/19: Re: Xilinx Tin Whiskers ?
152642: 11/09/20: Re: SIM card 1.8V / 3V sensing
152709: 11/10/05: Re: Testbench
152790: 11/10/23: Re: FPGA development
152859: 11/10/28: Re: FPGA development
153026: 11/11/16: Re: Migrating to Actel Libero
153043: 11/11/21: Re: Xilinx PCI Express - Am I starting too low?
153095: 11/11/29: Re: Classic Disk Drive simulation and binary file IO.
153195: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
153677: 12/04/15: Re: recomendation on a processor core
153960: 12/07/03: Re: accumulator (again)
153975: 12/07/06: Re: accumulator (again)
154114: 12/08/10: Re: Spartan 3AN prevent readback ?
154149: 12/08/21: Re: recruit FPGA design engineer in Scotland
154176: 12/08/28: Re: recruit FPGA design engineer in Scotland
154265: 12/09/19: Re: Global Reset using Global Buffer
154269: 12/09/19: Re: Global Reset using Global Buffer
154270: 12/09/19: Re: Global Reset using Global Buffer
154326: 12/09/28: Re: Replacing Logic with an FPGA/CPLD in a 510K device.
154562: 12/11/28: Re: VHDL expert puzzle
154569: 12/11/29: Re: VHDL expert puzzle
154615: 12/12/01: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154620: 12/12/02: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154641: 12/12/08: Re: Is this Multicycle?
154648: 12/12/10: Re: Is this Multicycle?
154709: 12/12/21: Re: Xilinx FIFO usage
154733: 12/12/31: Re: Which to learn: Verilog vs. VHDL?
154747: 13/01/03: Re: Which to learn: Verilog vs. VHDL?
154748: 13/01/04: Re: Which to learn: Verilog vs. VHDL?
154780: 13/01/08: Re: Which to learn: Verilog vs. VHDL?
154786: 13/01/10: Re: Which to learn: Verilog vs. VHDL?
154788: 13/01/10: Re: Which to learn: Verilog vs. VHDL?
154794: 13/01/11: Re: Which to learn: Verilog vs. VHDL?
154834: 13/01/17: Re: Combination loops and false paths
154955: 13/03/03: Re: Xilinx XST and initializing block RAMs
154962: 13/03/04: Re: Xilinx XST and initializing block RAMs
155142: 13/04/26: Re: DEP function development on a low budget
156225: 14/01/18: Re: Math is hard
156284: 14/02/05: Re: Xilinx Xpower Issues - Help from xilinx team please
156305: 14/02/13: Re: Monostable multivibrator
156367: 14/03/19: Re: license issue on synplify pro AE
156401: 14/03/29: Re: [cross-post][long] svn workflow for fpga development
156582: 14/05/04: Re: in my xps implementaion elf file is not generated only the
156723: 14/06/08: Re: Access custom VHDL types in TCL script
156782: 14/06/25: Re: A free VHDL simulator
156791: 14/06/26: Re: A free VHDL simulator
157700: 15/02/07: Re: data memory mapping microblaze
157793: 15/03/28: Re: Intel in Talks to buy Altera
157801: 15/03/30: Re: Bad condition in wait statement, or only one clock per process.
158046: 15/07/28: Re: Finally! A Completely Open Complete FPGA Toolchain
158073: 15/07/31: Re: Picking the best synthesis result before implementation
158074: 15/07/31: Re: fifo or sdram bug?
158084: 15/08/03: Re: Picking the best synthesis result before implementation
158432: 15/11/23: Re: ML403 board - VGA schematics - wrong pins
158460: 15/12/01: Re: Simulation vs Synthesis
158558: 15/12/24: Re: FPGA for a beginner
158589: 16/01/09: Re: hamsterworks + lauriVosandi + X = Error
158624: 16/02/07: Re: Source control and ip cores
Brian Fairchild:
60026: 03/09/03: New to FPGA, seeking advice
60070: 03/09/04: Re: New to FPGA, seeking advice
Brian Fox:
5194: 97/01/29: Re: Safety Critical Apps -> Xilinx Checker.
Brian Gladman:
13034: 98/11/12: Re: DES in VHDL?
Brian Gogan:
29153: 01/02/08: Re: Xilinx vs Altera
32021: 01/06/11: Re: Xilinx webpack annoyances (long and whiny)
32135: 01/06/15: Re: Xilinx webpack annoyances (long and whiny)
47095: 02/09/17: Re: ieee.math_real for presynthesis table calculation in vhdl
Brian Goudy:
29455: 01/02/22: Re: Programming Altera CPLD?
29476: 01/02/22: Re: Programming Altera CPLD?
29510: 01/02/24: Re: Samll quantities ordering
29522: 01/02/24: Re: cpul vs vhdl
29826: 01/03/12: Re: Configuration devices
Brian Guralnick:
48145: 02/10/11: Re: Quartus design question
48147: 02/10/11: Re: Quartus design question
48706: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
48718: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
48719: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
48960: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
50906: 02/12/22: Re: Compiling Altera LPM on leonardo
52275: 03/02/05: Re: Clock Enables
Brian Heber:
6695: 97/06/16: Help: Interfacing a Xilinx 4k to a microprocessor
brian hubeau:
70678: 04/06/23: Communication FPGA & MII
Brian Inglis:
64389: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
Brian Jackson:
49194: 02/11/04: Re: Incremental design question
49196: 02/11/04: WANTED: Technology partner to help verify new FPGA floorplanner
Brian Jentz:
68674: 04/04/13: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
Brian Kane:
22076: 00/04/18: Boston SNUG 2000 -- Call For Papers
30124: 01/03/23: Call For Papers - Boston Synopsys Users' Group
41993: 02/04/12: Call For Papers - Boston Synopsys Users' Group
Brian Lehman:
11993: 98/09/23: Re: How to reduce ringing/ground bounce from FPGA output pin?
Brian Lloyd Bishop:
6075: 97/04/09: Wanted - Industry Experts to Write for Engineering Magazine
Brian McFarland:
104806: 06/07/06: debouncing a switch (in hardware)
105235: 06/07/18: Which PCI core for Cyclone II board?
105277: 06/07/19: Re: Which PCI core for Cyclone II board?
105399: 06/07/21: Re: Which PCI core for Cyclone II board?
105574: 06/07/26: Re: Which PCI core for Cyclone II board?
105696: 06/07/28: Re: "This design element is inferred rather than instantiated" (newbie)
106297: 06/08/10: Re: A Newbie question
Brian P Hunter:
6682: 97/06/13: Verilog Simulation and Synthesis for FPGA Devices
Brian P. Bailey:
4593: 96/11/19: BREAKTHROUGH COMPUTER SYSTEM TO BE INTRODUCED ON DEC 2
Brian Pedersen:
15068: 99/03/04: Re: A few questions - beginner
16163: 99/05/07: Re: DSP in FPGA
Brian Philofsky:
5205: 97/01/30: Re: Xilinx/Synario question
5334: 97/02/07: Re: Problems with SYNOPSYS - XILINX Interface
8174: 97/11/24: Re: barrel shifter
8258: 97/12/03: Re: Xilinx pullup / pulldown resistors
8257: 97/12/03: Re: Integration between Xilinx & Synopsys
8277: 97/12/04: Re: VHDL -> XNF via Synopsys
8550: 98/01/07: Re: seeking example for PWM using PLDs
9642: 98/03/27: Re: VHDL shareware editor?
10160: 98/04/30: Re: Q: XILINX Foundation
10176: 98/05/01: Re: Q: XILINX Foundation
10397: 98/05/15: Re: "Inferred" I/O flip-flops in XC4000E
10815: 98/06/22: Re: [Question] Xilinx Foundation FPGA Express..
10854: 98/06/25: Re: Xilinx carry logic (XC4000)
13484: 98/12/04: Re: Array Range Legal?
15893: 99/04/19: Re: One hot comes up cold
15894: 99/04/19: Re: Wire-AND in longline of 4000 series?
15948: 99/04/22: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
15960: 99/04/23: Re: Timing Constraint
16033: 99/04/28: Re: Need HELP!!! Hurry
16287: 99/05/13: Re: Verilog example for Xilinx?
16359: 99/05/18: Re: 4062XL problems and solutions
17082: 99/06/29: Re: FGPA Servo Motor Controller
17182: 99/07/07: Re: Tristate Register in Xilinx 4000XLA IO block
17184: 99/07/07: Re: Programming Xilinx without Foundation
17215: 99/07/09: Re: how to choose only a set of pins
17360: 99/07/22: Re: License sharing for synopsys/cadence/modeltech
18541: 99/10/29: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18640: 99/11/04: Re: Simulation of FPGA design. Please Help!
18719: 99/11/09: Re: Simulation of FPGA design. Please Help!
18995: 99/11/23: Re: Virtex FIFO w/ Block RAM
21890: 00/04/05: Re: Clocks and BUFGP
21891: 00/04/05: Re: Clocks and BUFGP
21942: 00/04/07: Re: Port "IN2" has no net attached to it-on pad cells inserted at this
21944: 00/04/07: Re: multiprocessor support of IC design tools
22073: 00/04/18: Re: Scripting Xilinx Foundation's hitop
22118: 00/04/25: Re: Segregation between synthesis code and simulation code
23105: 00/06/14: Re: Virtex questions
25839: 00/09/22: Re: Pack I/O Reg/Latches into IOBs
26518: 00/10/18: Re: scripting with xilinx tools (foundation) ????
26534: 00/10/19: Re: scripting with xilinx tools (foundation) ????
27043: 00/11/08: Re: Boundary Scan fundamentals
27223: 00/11/15: Re: Problem with Endianess in Xilinx Tools.
28269: 01/01/04: Re: how do you design with + compile separate entity +architecture files
29031: 01/02/02: Re: Virtex : Timing Problem
29078: 01/02/05: Re: in-out pad uasage in fpga compiler II
29079: 01/02/05: Re: Xilinx post-synthesis (leonardo) simulation (modelsim)
29080: 01/02/05: Re: Help for a novice. Where to begin?
29110: 01/02/06: Re: Xilinx XC4010
29139: 01/02/07: Re: Xilinx XC4010
29164: 01/02/08: Re: Wired-or on Virtex FPGAs
29217: 01/02/09: Re: Wired-or on Virtex FPGAs
29296: 01/02/13: Re: The usage of 'Guide files' in Xilinx foundation 2.1i
29953: 01/03/19: Re: VHDL code required for a given decimator system
30952: 01/05/04: Re: BUFG output is constant0 at 200MHz in post timing
31018: 01/05/09: Re: SYnopsys Library Compiler and LUT synthesis
31180: 01/05/14: Re: Post timing: $setup( negedge RST:1372505 ps, posed
31182: 01/05/14: Re: Fine phase shift in Virtex2
31218: 01/05/15: Re: Fine phase shift in Virtex2
32848: 01/07/10: Re: Xilinx System Generator Simulation Problem
33093: 01/07/17: Re: PROBLEM!!!
33095: 01/07/17: Re: processor core
33553: 01/07/30: Re: IOB FF in Synplicity
33970: 01/08/09: Re: Xilinx/Altera "behavioral" verilog
33972: 01/08/09: Re: post synthesis simulation
33973: 01/08/09: Re: Alliance tools going away?
33974: 01/08/09: Re: newbie
33975: 01/08/09: Re: General question on VHDL code
33978: 01/08/09: Re: Map report question
33980: 01/08/09: Re: Alliance tools going away?
34439: 01/08/24: Re: Reading Text in Verilog
34701: 01/09/04: Re: FPGA: time_sim.sdf does not have the setup times f
35323: 01/09/28: Re: Meta-stability
35831: 01/10/18: Re: PWM Signal in VHDL ?
36291: 01/11/05: Re: spartan synthesis with synopsis
36625: 01/11/13: Re: 'Timing' simulation in ModelSIM
36637: 01/11/13: Re: Xilinx problems using constants in the input ports of entities
36976: 01/11/27: Re: Device Support in Webpack
36978: 01/11/27: Re: 'Timing' simulation in ModelSIM
37192: 01/12/03: Re: XNF file is rewritten and rendered useless
37262: 01/12/05: Re: quartus post simulation setup problem
37293: 01/12/06: Re: quartus post simulation setup problem
37410: 01/12/10: Re: IP Updates and Modelsim
37458: 01/12/11: Re: IP Core Update #1
37459: 01/12/11: Re: apologies.. and functional simulation of DCMs
37460: 01/12/11: Re: i want "RAMB4_S1_S16.VHD"
37755: 01/12/19: Re: multi-cycle constraint
38154: 02/01/07: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38156: 02/01/07: Re: Synplify and Xilinx clock discovery
38159: 02/01/07: Re: Regarding frequency achieving in fpga design
38160: 02/01/07: Re: WARNING
38184: 02/01/08: Re: WARNING
38232: 02/01/09: Re: Interpreting Xilinx Timing Analyser report files
38234: 02/01/09: Re: comp.arch.fpga : Problem with modelsim and ISE4.1
38590: 02/01/18: Re: Xilinx 4.1 Implementation report questions
38610: 02/01/18: Re: Simple shift register not working
38673: 02/01/21: Re: help me!
38699: 02/01/22: Re: Gate level simu in ModelSim.
38934: 02/01/28: Re: path for Vital component in assert?
39267: 02/02/05: Re: Core generator Asynchronous FIFO
39816: 02/02/20: Re: Modelsim questions
39818: 02/02/20: Re: Some problem initializing a RAMB4S1
39819: 02/02/20: Re: Some problem initializing a RAMB4S1
40464: 02/03/07: Re: Ports disappear after generating post place and route simulation
42118: 02/04/16: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42122: 02/04/16: Re: DLL property control in UCF
42170: 02/04/17: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42398: 02/04/22: Re: INIT constrain
42634: 02/04/29: Re: Changing ROM contents
42770: 02/05/02: Re: static logic vs LUT
43117: 02/05/14: Re: Issue with X_SUH (using 4.1 sp 3)
43119: 02/05/14: Re: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
43470: 02/05/21: Re: Reading GSR signal of Spartan-II
43798: 02/06/03: Re: Pipelining
66724: 04/02/25: Re: Usage of Xilinx Library elements in ModelSim simulation
66725: 04/02/25: Re: ModelSim, Virtex DCM, and clk0 phase problem
66856: 04/02/27: [Fwd: Re: ngd2edif vs. ngc2edif]
66941: 04/03/01: Re: netlist - technology remapping
66946: 04/03/01: Re: XST ff merging - how do I "preserve" flip flops
67050: 04/03/04: Re: XST ff merging - how do I "preserve" flip flops
67074: 04/03/04: Re: Global reset question?
67226: 04/03/08: Re: What's the rule of instantiating the global buffer
67227: 04/03/08: Re: XST ff merging - how do I "preserve" flip flops
67228: 04/03/08: Re: Global reset question?
67361: 04/03/10: Re: fatal error : help required
67364: 04/03/10: Re: licence for Xilinx 2.1i
67366: 04/03/10: Re: fpga
67423: 04/03/11: Re: licence for Xilinx 2.1i
67688: 04/03/17: Re: ModelSim vs HDL Bencher
67689: 04/03/17: Re: Xilinx RAMB16_Sm_Sn timing diagram
67691: 04/03/17: Re: Modelsim & ISE Foundation: Hierarchical update
67769: 04/03/18: Re: Xilinx RAMB16_Sm_Sn timing diagram
67807: 04/03/19: Re: duration of reset
68104: 04/03/26: Re: Back Annotated Gate Level Simms (Xilinx)
68106: 04/03/26: Re: Spartan-3 Mapping error with ISE 6.1i
68115: 04/03/26: Re: Back Annotated Gate Level Simms (Xilinx)
68192: 04/03/29: Re: Back Annotated Gate Level Simms (Xilinx)
68240: 04/03/30: Re: speed vs. temperature
68380: 04/04/02: Re: Help with Xilinx Ram16X1S example VHDL code
68391: 04/04/02: Re: Metastablility
68394: 04/04/02: Re: Verifying multi-cyclicity of multi-cycle paths
68400: 04/04/02: Re: XAPP134's VHDL code
68644: 04/04/12: Re: Help need writing Single Port Block Ram in verilog
69181: 04/04/29: Re: Post-Place & Route Simulation with ISE
69327: 04/05/06: Re: V2p block ram clock -> Q delay help
70585: 04/06/21: Re: pulse generation using SRL16E on a Virtex-II
70587: 04/06/21: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70590: 04/06/21: Re: Is there a verilog version of PicoBlaze?
70592: 04/06/21: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
70595: 04/06/21: Re: Spartan/SpartanXL Device Selection
70627: 04/06/22: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70633: 04/06/22: Re: ROM instantiation question
70647: 04/06/22: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70689: 04/06/23: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70839: 04/06/29: Re: simprim X_FF component
70840: 04/06/29: Re: Answer Record # 18857 compiling modelsim library
70842: 04/06/29: Re: Trouble with $readmemh in ModelSim
70860: 04/06/30: Re: simprim X_FF component
70863: 04/06/30: Re: Trouble with $readmemh in ModelSim
70964: 04/07/02: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70965: 04/07/02: Re: DCM ISE6.2.3 sim problem
70966: 04/07/02: Re: Compile 30% of my multipliers with LUT?
71228: 04/07/12: Re: Urgent : Xilinx PACE question
71677: 04/07/27: Re: IOBs in NGC - problem with OBUFT
71969: 04/08/04: Re: Manipulation on netlist for faster simulation.
72015: 04/08/05: Re: Manipulation on netlist for faster simulation.
72042: 04/08/06: Re: Manipulation on netlist for faster simulation.
72063: 04/08/06: Re: Error Using Block Ram in model sim XE 5.7
72112: 04/08/09: Re: Manipulation on netlist for faster simulation.
72272: 04/08/12: Re: Problem instantiating xilinx blockram ramb4_s1_s16
72275: 04/08/12: Re: Problem instantiating xilinx blockram ramb4_s1_s16
72607: 04/08/26: Re: X propagation in Timing Simulation
72610: 04/08/26: Re: Xilinx Command Prompt
72616: 04/08/26: Re: 6.1 vs. 6.2
72620: 04/08/26: Re: problem with DDR
72627: 04/08/26: Re: 6.1 vs. 6.2
72651: 04/08/27: Re: problem with DDR
72653: 04/08/27: Re: 6.1 vs. 6.2 - one more question
74577: 04/10/14: Re: 64 bit version of xilinx ISE
80813: 05/03/11: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
80941: 05/03/14: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
86741: 05/07/05: Re: ModelSim Timing Simulation Signal Names
90222: 05/10/06: Re: Avoiding meta stability? Finally...? Don't use SRL16 as a synchronizer
92185: 05/11/23: Re: Modelsim Verification : Retain FSM state names
100494: 06/04/10: Re: asynchronous FIFO design
100501: 06/04/10: Re: rather simple gsr Q
132474: 08/05/28: Re: Sequentially syncrhronous
Brian R Cartwright:
4733: 96/12/09: suggestions for arithmetic experiment?
Brian Schott:
12: 94/07/28: Re: Welcome new XILINX users
184: 94/09/15: XACT 5.0 and XSI
1810: 95/09/05: Re: Help Needed-FPGA Apps Eng.-AllentownPA.-Recruiter
14905: 99/02/24: synlibs for XC40150XV Synopsys fpga_shell
Brian Small:
7418: 97/09/08: Re: Which FPGA ?
7696: 97/10/03: Applications Engineering Position at Quicklogic
15751: 99/04/12: Re: FIFO
Brian Tithecott:
50044: 02/11/29: Re: Anybody know of vendors of PCI boards with FPGAs?
<brian.jackson@xilinx.com>:
129474: 08/02/25: Re: Planahead IP export
<brian.magnusen@gmail.com>:
116908: 07/03/20: Re: Unable to load FPGA image from the prom
<Brian.Sullivan.EMA@gmail.com>:
131660: 08/04/28: Re: Survey: FPGA PCB layout
<brian13074@my-deja.com>:
26173: 00/10/06: Project Leader, Architecture Modeling
<brian_boorman@my-deja.com>:
23057: 00/06/12: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
<brian_m_davis@my-deja.com>:
17172: 99/07/07: Re: Synplify problem - is it just me?
18378: 99/10/21: VHDL carry chain RPMs
18411: 99/10/23: Re: VHDL carry chain RPMs
25060: 00/08/25: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
<brian_n_miller@yahoo.com>:
16429: 99/05/21: Re: High Speed Reconfigurability
16430: 99/05/21: Re: High Speed Reconfigurability
16449: 99/05/23: Re: High Speed Reconfigurability
16484: 99/05/25: Re: High Speed Reconfigurability
16486: 99/05/25: Re: High Speed Reconfigurability
16521: 99/05/26: Re: High Speed Reconfigurability
16522: 99/05/26: Re: High Speed Reconfigurability
16529: 99/05/26: Re: High Speed Reconfigurability
16549: 99/05/27: Re: High Speed Reconfigurability
16552: 99/05/27: Re: High Speed Reconfigurability
Brian_Sullivan:
31733: 01/06/04: Re: one state machine
31766: 01/06/05: Re: Help needed on Max7000 pin assignments (Max-plus II)
31769: 01/06/05: Re: one state machine
31804: 01/06/06: Re: What am I doing wrong?
31819: 01/06/06: Re: any ideas?
31822: 01/06/06: Re: auto increment register
31930: 01/06/08: Re: safe state machine design problem
32114: 01/06/14: Re: Altera PCI developement Kit (PCI-BOARD/A4E)
32271: 01/06/21: Re: Force routing on an Apex
32273: 01/06/21: Re: Verilog or VHDL?
32312: 01/06/22: Re: Verilog or VHDL?
brianwfarmer:
145644: 10/02/17: what is incorrect about my usage of array with port entity?
<brianwfarmer@gmail.com>:
125720: 07/11/01: Xilinx's System Generator versus Mathworks' Link for Modelsim
BRIERCLIFF:
13943: 99/01/04: Immediate Opening/FPGA/Boston Area
brif:
68894: 04/04/21: FPGA within demonstration
brijesh:
55900: 03/05/23: Re: CLKDLL: Dividing
56187: 03/05/30: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
57290: 03/06/26: Re: Interfacing IDE
Brijesh:
46640: 02/09/05: Re: CLK DLL problem
47084: 02/09/16: Viewing internal signals during Post route simulation.
47288: 02/09/22: Re: Timing accuracy with Modelsim
47452: 02/09/26: any simulation models for hard disk or ATA interface?
48470: 02/10/18: Locating IOBs with shared routing resources in VirtexII.
48822: 02/10/25: Re: LVDS standard
48823: 02/10/25: Re: Pin locking Virtex 2 FPGA
68591: 04/04/08: Problem using EDK tutorial for Memec board with Synplicity.
68592: 04/04/08: Re: Problem using EDK tutorial for Memec board with Synplicity.
68607: 04/04/09: Re: Problem using EDK tutorial for Memec board with Synplicity.
70361: 04/06/14: FPGA serial programming troubles. (Virtex II)
70397: 04/06/15: Re: FPGA serial programming troubles. (Virtex II)
80935: 05/03/14: Problem loading virtex2 FPGA in master serial mode.
82143: 05/04/07: Slow rising strobe used to clock IOB's, can it cause trouble?
82157: 05/04/07: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82159: 05/04/07: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82203: 05/04/08: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82333: 05/04/11: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82336: 05/04/11: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82338: 05/04/11: Re: Shared bus on FPGA
82913: 05/04/19: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
83005: 05/04/21: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
83007: 05/04/21: Re: LVDS pin assignment
83008: 05/04/21: Re: Simulation in modelsim.... Multiple Drivers.......
83701: 05/05/05: Re: how to constrain this
83759: 05/05/06: Re: cascaded dcms
83762: 05/05/06: Using capacitor to slow the rise time.
83781: 05/05/06: Re: Using capacitor to slow the rise time.
83887: 05/05/09: Re: Using capacitor to slow the rise time.
84026: 05/05/11: Re: signals in modelsim
84050: 05/05/11: Re: signals in modelsim
86257: 05/06/23: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
86302: 05/06/24: Re: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
86303: 05/06/24: Re: Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.
87167: 05/07/18: Re: post-place & route simulation of simple project problem.
90267: 05/10/07: ISE 7.1i installing issues on Windows XP Pro Sp2.
90872: 05/10/24: Re: Implementation of 1024 point FFT in Actel FPGA
102535: 06/05/17: Hold Time Violations in Virtex4
Brill Pappin:
BriMDavis:
29615: 01/03/01: Re: Xilinx tools: RLOC hierarchy with HDL design?
30100: 01/03/23: Re: Globals are plenty fast
30717: 01/04/26: Virtex-II LUT aspect ratio
34086: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
<brimdavis@aol.com>:
136784: 08/12/04: V5 JTAG download weirdness
136807: 08/12/05: Re: V5 JTAG download weirdness
136817: 08/12/06: Re: V5 JTAG download weirdness
<brimdavis@gmail.com>:
157633: 15/01/10: Re: Name this pipelining technique
160186: 17/08/01: Re: sram
160223: 17/08/08: Re: sram
160227: 17/08/10: Re: sram
Brinda:
37214: 01/12/03: Webpack Version 3: Exit with error code 0002
Britestar, Inc.:
1463: 95/06/26: Save Your Computer!
Britt Snodgrass:
66368: 04/02/18: Re: Dual-stack (Forth) processors
Britta Fuhrmann:
52482: 03/02/11: Re: FFT Size and speed
Britten Kilduff:
<briwalk@gmail.com>:
102257: 06/05/12: Re: More Xilinx S/W problems... ISE won't start
bronzefury:
111070: 06/10/28: Re: Survey: simulator usage
111358: 06/11/02: Re: Yet Another Survey: What are code generators worth?(was: Re: Survey: simulator usage)
111442: 06/11/03: Re: Yet Another Survey: What are code generators worth?(was: Re: Survey: simulator usage)
Broom:
161085: 19/01/30: Xilinx Artix-7 SoM with 8 x GTPs
Brother David, FFCS:
16741: 99/06/06: Modems ... & stuff
BROTO Laurent:
45027: 02/07/10: LogiCore and PLX
45285: 02/07/18: Problem with OpenCore PCI IP Core
45289: 02/07/18: Re: Problem with OpenCore PCI IP Core
45424: 02/07/23: Re: Problem with OpenCore PCI IP Core
45458: 02/07/24: Re: 32-bit PCI Target core
45532: 02/07/25: Problem with mapping
45554: 02/07/26: Re: Problem with mapping
46547: 02/09/03: Question about IOB, BUFG, IBUF and IBUG.
46679: 02/09/05: Re: Question about IOB, BUFG, IBUF and IBUG.
Bruce:
11913: 98/09/18: programming xilinx fpga
47154: 02/09/19: VHDL : Lookup Table
72291: 04/08/13: Infiniband
Bruce (newbie):
47012: 02/09/14: Clcok divison : Rational clock divider
Bruce C. Headley:
27540: 00/11/28: Re: Another simple Xilinx question
Bruce Hoult:
10517: 98/05/27: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
12831: 98/10/31: Re: New free FPGA CPU
12862: 98/11/03: Re: New free FPGA CPU
12895: 98/11/04: Re: New free FPGA CPU
17257: 99/07/15: Re: Alto in an FPGA (was CPU's directly executing HLL's)
17258: 99/07/15: Re: Alto in an FPGA (was CPU's directly executing HLL's)
Bruce Jorgens:
58129: 03/07/15: Re: PROM size for spartan
59817: 03/08/28: Re: Is Platform Flash PROM an electrically erasable??
bruce kidd:
7512: 97/09/18: vme interface
Bruce L:
18736: 99/11/10: Re: CAN tools reccomendations?
Bruce McArdle:
20842: 00/02/23: Re: PCI problem
Bruce McFarling:
137128: 08/12/24: Re: Bit width in CPU cores
Bruce Nepple:
7147: 97/08/07: Price of Serial EEPROM is Outrageous
7162: 97/08/08: Price of Serial EPROM is Outrageous - Better Explanation
11180: 98/07/22: Re: Any VHDL counter with up & down functions
11268: 98/07/31: Delay Element in XC4000XL (was Re: Delay Element for async design.)
11344: 98/08/05: Delay element in XC4000
13844: 98/12/29: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13857: 98/12/29: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13863: 98/12/29: Re: 22V10 Metastability - help please
13891: 98/12/31: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13896: 98/12/31: Can a cross coupled latch "oscillate"? was Re: ..........
13897: 98/12/31: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13930: 99/01/03: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13931: 99/01/03: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13981: 99/01/05: Re: 22V10 Metastability - my 1c
14077: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14079: 99/01/11: Metastability Described
14027: 99/01/07: Re: which FPGA to choose ?
14026: 99/01/07: Re: How to use Special Pins as IO on Xilinx FPGA???
14204: 99/01/19: I don't trust Orcad
14249: 99/01/21: hdl vs. schematics - was <snip>
14323: 99/01/25: Re: Metastability implementation
14324: 99/01/25: Re: FPGA express warning
14342: 99/01/26: Re: Hysteresis on PLD Clock Inputs
14399: 99/01/28: Re: FPGA express warning
14400: 99/01/28: Re: Power Consumption in FPGAs
14535: 99/02/03: Re: Hazard
14495: 99/02/01: Re: FPGA Express Evaluation...
14573: 99/02/04: Re: VHDL problem (Xilinx-problem)
14579: 99/02/04: Re: VHDL clocked one-shot Implementation Problem
14771: 99/02/16: Re: xnf de-compiler
14933: 99/02/25: Re: Where do I connect my reset pins to?
14934: 99/02/25: Re: Xilinx ABEL?
15350: 99/03/19: Xilinx Makefile?
15387: 99/03/22: Re: Xilinx Batchfile?
15464: 99/03/24: Re: Xilinx Version Control?
15242: 99/03/15: Re: Pin constraints of Xilinx - BIG WEAKNESS
15327: 99/03/18: Re: FPGA Express FSM Synthesis Concern
15328: 99/03/18: Re: Xilinx routing problem: removing "reset" increases cycle time.
15349: 99/03/19: Re: FPGA Express FSM Synthesis Concern
15388: 99/03/22: Re: FPGA Express FSM Synthesis Concern
15482: 99/03/25: Re: FPGA Express FSM Synthesis Concern
15697: 99/04/08: Illegal States in 1 Hot State Machines
15722: 99/04/09: Re: Levels of logic
15914: 99/04/20: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
15915: 99/04/20: Re: Any good book suggestions
17792: 99/09/03: Re: synthesis comparion between Synplify and FPGA express
17816: 99/09/07: Re: synthesis comparion between Synplify and FPGA express
17817: 99/09/07: Re: synthesis comparion between Synplify and FPGA express
18890: 99/11/19: Re: Synplify vs. FPGA Compiler II (v3.3)
18891: 99/11/19: Maybe this will help Xilinx Service Pack Downloads
19028: 99/11/24: Re: Anybody using Lucent OR3TP12?
19144: 99/12/01: Re: backup fifo's
19220: 99/12/06: Re: Synplify vs. FPGA Compiler II (v3.3)
19221: 99/12/06: Re: backup fifo's
19238: 99/12/07: Re: backup fifo's(2)
Bruce Oakley:
4301: 96/10/11: Xilinx XACT Performance Appl. Note?
21490: 00/03/23: FPGA Design Productivity Metrics
26919: 00/11/03: High Slice Usage in Virtex-E
Bruce P.:
62836: 03/11/09: Home grown CPU core legal?
62872: 03/11/10: Re: Home grown CPU core legal?
62892: 03/11/10: Re: Home grown CPU core legal?
62979: 03/11/11: Re: Home grown CPU core legal?
63316: 03/11/19: Re: CPLD : Generating reset signal
Bruce Pirger:
6179: 97/04/23: Reconfigurable Computing
6560: 97/06/03: Re: New Reconfigurable Computing newsgroup?
8055: 97/11/12: Re: scsi host adapter
Bruce Ray:
71196: 04/07/11: Altium CircuitStudio 2004 vs for FPGA support
Bruce Reid:
13226: 98/11/20: Re: Why doesn't Xilinx's simulator work?
13475: 98/12/04: Re: parallel cable III -> Spartan
Bruce Sam:
74222: 04/10/06: Is the Xilinx's silicon better than Altera's?
Bruce Varley:
155140: 13/04/26: DEP function development on a low budget
155141: 13/04/26: Re: DEP function development on a low budget
156161: 14/01/02: Optimising pin allocation
156519: 14/04/14: Help: Altera megafunctions, Quartus II
Bruce Warkentin:
64190: 03/12/19: V2Pro floating point
<Bruce>:
156719: 14/06/08: HELP: Edge triggering of mode register, Verilog
156725: 14/06/08: Re: HELP: Edge triggering of mode register, Verilog
156740: 14/06/10: Re: HELP: Edge triggering of mode register, Verilog
156964: 14/08/08: Basic question: sequence of execution within FPGAs
156971: 14/08/09: Re: Basic question: sequence of execution within FPGAs
157141: 14/10/18: Fast and slow clocks
<bruce_hw_guy@hotmail.com>:
123035: 07/08/14: Xilinx DDR2 SDRAM controller performance
123060: 07/08/15: Re: Xilinx DDR2 SDRAM controller performance
123164: 07/08/17: Re: FIFO16 on virtex4 error?
brucejs777:
115817: 07/02/21: Re: Can't assign pins in Webpack 8.2i schematic design
BruceMcF:
151798: 11/05/18: Re: J1 forth processor in FPGA - possibility of interactive work?
<brucenutbrown@yahoo.com>:
107693: 06/08/31: easics - crc equations
bruconty:
Bruderer:
45518: 02/07/25: LVDS on virtex-II with leonardo
Bruno:
67393: 04/03/10: Re: very strange error
67406: 04/03/11: Re: very strange error
67573: 04/03/14: Re: very strange error
85722: 05/06/14: Where to buy a Xilinx XCR3384XL tq144 CPLD?
85724: 05/06/14: Re: Problem for xilinx!!!
85826: 05/06/16: Re: Where to buy a Xilinx XCR3384XL tq144 CPLD?
bruno:
18360: 99/10/19: ANNOUNCE: FPGA Starter kit
Bruno Bohrer Cozer:
44972: 02/07/08: Altera SOPC Connectors
Bruno Cardeira:
68434: 04/04/04: Xilinx XC9500 CPLD Wired-OR; Wired-ND
68553: 04/04/07: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
71083: 04/07/07: RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
71231: 04/07/12: Re: RC Servo PWM Digital Capture in a Xilinx xc9500 CPLD?
71476: 04/07/19: Xilinx XC9500 CPLD internal pull-up??
71532: 04/07/21: Re: Xilinx XC9500 CPLD internal pull-up??
85121: 05/06/05: TI TMS320 DSP as a soft-processor in FPGA?
Bruno Fierens:
8226: 97/12/01: Bugs in M1.3.7 mapper ?
8789: 98/01/27: M1.4 problems
10418: 98/05/18: Re: XC5200s and Foundation 1.4
10443: 98/05/19: Re: XC5200s and Foundation 1.4
12266: 98/10/07: schematics design entry /simulation : Viewlogic or Veribest ?
12538: 98/10/15: Re: 100 MHz FPGA
Bruno Gebert:
35105: 01/09/21: Control the programming of a Xilinx 9500 CPLD from an application
Bruno Sauter:
6996: 97/07/21: Re: PCI burst transfers
Bruno Vermeersch:
67315: 04/03/10: very strange error
Bryan:
27643: 00/11/30: Re: Orca 3t sram gsr question
34316: 01/08/20: Re: hardware damage to a Virtex or Spartan-II?
34333: 01/08/21: Re: hardware damage to a Virtex or Spartan-II?
34361: 01/08/22: Re: hardware damage to a Virtex or Spartan-II?
35000: 01/09/17: Re: Virtex-2 availability
35199: 01/09/25: Re: Virtex2 slice level instantiation in verilog question
36203: 01/11/01: Re: Hard macro in xilinx
37027: 01/11/28: Re: reducing PAR time
37489: 01/12/12: Re: ROM prog problem Virtex2 eval board
37669: 01/12/18: Re: Kindergarten Stuff
37718: 01/12/19: Re: Kindergarten Stuff
37719: 01/12/19: Re: Kindergarten Stuff
37815: 01/12/20: Re: You take the low road and I'll ......
37850: 01/12/21: Re: Kindergarten Stuff
38333: 02/01/11: Xilinx PAR and Editor speed up
38334: 02/01/11: Re: Xilinx PAR and Editor speed up
38421: 02/01/14: Re: Xilinx PAR and Editor speed up
39212: 02/02/04: Re: can comparisons glitch?
42498: 02/04/25: Re: Newbie with signals
42827: 02/05/03: Re: Hard macro with Xilinx
43211: 02/05/16: Re: Architecture for high-level reconfigurable computing
44602: 02/06/24: Re: skew control between different signals ?
45312: 02/07/18: Re: Virtex-II variable vs fixed DCM phase-shift ?
46250: 02/08/22: Re: Downloading bit streams in Xilinx
46253: 02/08/22: Re: Downloading bit streams in Xilinx
49828: 02/11/21: Slice count for BCH(31,16,7) in virtex-II
51487: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
83385: 05/04/28: Re: Sync + FIFO
83415: 05/04/29: Re: Sync + FIFO
83421: 05/04/29: Re: Sync + FIFO
83433: 05/04/29: Re: Sync + FIFO
83435: 05/04/29: Re: Sync + FIFO
83477: 05/04/30: Re: Sync + FIFO
83532: 05/05/02: Re: Sync + FIFO
91753: 05/11/11: Difficulty compiling on Quartus 2 version 5
118328: 07/04/24: XTREME DSP Development Kit2 JTAG Problem
118363: 07/04/25: Incorrect response from MAC FIR Low Pass Filter
118406: 07/04/26: Re: Incorrect response from MAC FIR Low Pass Filter
118817: 07/05/04: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118894: 07/05/07: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
119406: 07/05/18: How to port simulink design to FPGA?
125248: 07/10/18: Re: ethernet phy or mac
125781: 07/11/05: Audio Output from Spartan 3 Starter Kit
125915: 07/11/08: Re: P160 Communication Module 3
125916: 07/11/08: Re: Spartan 3E config
127560: 08/01/02: Re: no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02
128171: 08/01/17: Re: Documentation on Insight VIRTEX-E Reference Board
129262: 08/02/19: Re: FPGA Programming solution
129510: 08/02/26: Re: Using ICAP in s3a to reconfigure
129552: 08/02/27: Re: SPI indirect programming using spartan 3e
129755: 08/03/04: Re: Avnet/Memec V4FX12LC proto card and SysGen
129927: 08/03/10: Re: Spartan-3A DSP Starter: JX Connector Part number
129992: 08/03/12: Re: avnet virtex-5 lx eval kit ddr problem
130091: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
132152: 08/05/15: Re: How do I get Xilinx EDK to load a 'custom' XBD file?
132454: 08/05/27: Re: using EXP connector of Spartan 3a board
134165: 08/07/28: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming
134224: 08/07/31: Re: Is there a totally command-line driven way to use Xilinx Webpack?
134244: 08/07/31: Re: Is there a totally command-line driven way to use Xilinx Webpack?
134280: 08/08/04: Re: What's the deal with PSoC programmers?
134385: 08/08/08: Re: What's the deal with PSoC programmers?
134403: 08/08/08: Re: Development board with SD card.
134495: 08/08/13: Re: Microblaze Projects
135898: 08/10/20: Re: Field update
136537: 08/11/21: Re: how to display on LCD of FPGA board?
136611: 08/11/25: Re: timer interrupt problem: microblaze
136625: 08/11/26: Re: timer interrupt problem: microblaze
136692: 08/12/01: Re: DDR2 SDRAM RELEATED PROBLEM IN SPARTAN 3A DSP 1800 + EDK 9.2i
136794: 08/12/05: Re: Project/File corruption problem with ISE 10.1
136836: 08/12/08: Re: Xiic with low lvl interrupts
136899: 08/12/11: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
137988: 09/02/03: Re: Selecting a starter FPGA board
138903: 09/03/13: Re: DDR access on Spartan 3E 500 Starter Kit
139820: 09/04/15: Re: Mobile low power DDR SDRAM and MIG
140570: 09/05/18: Re: Survey: What's a good FPGA-related conference?
140988: 09/06/01: Re: Survey: What's a good FPGA-related conference?
146740: 10/03/26: Re: PROM for Spartan 6 FPGA
147436: 10/04/27: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
147493: 10/04/28: Re: Xilinx MIG v2.3 Spartan3A-DSP DDR2 Interface
148235: 10/06/30: Re: Xilinx BULLSHITIX-8, when?
148299: 10/07/05: Re: Xilinx BULLSHITIX-8, when?
148338: 10/07/08: Re: FPGA Video processing board (HDMI).. who makes one?
148728: 10/08/18: Re: FPGA PCI BOARD .. Few Questions
148746: 10/08/19: Re: Getting started with FPGA
148917: 10/09/09: Re: PSOC3/5
148951: 10/09/14: Re: PSOC3/5
149069: 10/09/28: Re: Virtex5 minimodule
149366: 10/10/19: Re: Newbie question IO pin and Spartan6
149547: 10/11/04: Re: Good Dev Board
150008: 10/12/06: Re: FPGA BOARD QUESTION
150142: 10/12/18: Re: FPGA modules/cards with peripheral functions
150152: 10/12/20: Re: microblaze spi core problem
150162: 10/12/22: Re: microblaze spi core problem
150838: 11/02/15: Re: Xilinx USB programming cable.
151209: 11/03/15: Re: Alternative To Altera's Cyclone III Starter Board
151547: 11/04/18: Re: ethernet core on FX12 mini module
151557: 11/04/19: Re: ethernet core on FX12 mini module
152618: 11/09/18: Re: Virtex 6 dev. board suppliers?
153087: 11/11/28: Re: Compatible Xilinx USB Cables: worth to bother?
Bryan Bushart:
3708: 96/07/18: Re: FPGA vs CPLD
Bryan Butler:
203: 94/09/20: Re: Lattice ISP software: really bad or just different?
229: 94/09/28: Re: Software costs (was Re: Lattice ISP software)
235: 94/09/29: Re: What do think about the Intel Flexlogic8160?
253: 94/10/03: Re: What do think about the Intel Flexlogic8160?
645: 95/01/26: Problems programming Intel FX780
727: 95/02/18: Re: PLA? PAL? PLD? GAL?
748: 95/02/22: Re: PLA? PAL? PLD? GAL?
978: 95/04/06: Re: Excuse me while I vent about Data I/O & Abel...
1010: 95/04/13: Re: Need "fusemap" information from vendor, likely?
Bryan Chase:
188: 94/09/16: Re: GigaOps video-compute-engine
189: 94/09/16: Re: Need General Ptr's on FPGA's
396: 94/11/07: Re: about downloading FPGAs
506: 94/12/13: Re: Any Good HDL Tools for the PC?
534: 94/12/26: Re: multipliers!
Bryan Hackney:
13161: 98/11/18: Re: CPUs: Big Endianness vs Small Endianness
94979: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95011: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95012: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95017: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95046: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95162: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95245: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95246: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95295: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95296: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95297: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95302: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95304: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95322: 06/01/22: Re: OT:Shooting Ourselves in the Foot
105175: 06/07/16: Re: FPGA consultants
Bryan Harstad:
3745: 96/07/23: Looking for an Eval Board for XILINX
Bryan Jones:
23261: 00/06/19: Re: Xilinx Foundation 2.1 error
23273: 00/06/20: Re: Xilinx Foundation 2.1 error
Bryan Williams:
4760: 96/12/12: Re: Xilinx configuration PROM
4784: 96/12/14: Re: Xilinx configuration PROM
4865: 96/12/21: Re: PCI Bus Based designs using FPGA's
4988: 97/01/08: Re: What Does ASIC Stand For?
8188: 97/11/26: Re: AT17C256 problems
9541: 98/03/22: "CORE Competency" ???
10067: 98/04/25: Re: XC4000XL and Ground Bouncing
13155: 98/11/17: Re: FPGA Decouple Capacitor values
19010: 99/11/24: Re: Anybody using Lucent OR3TP12?
19083: 99/11/28: Re: Lucent: OR3TP12, Some work arounds that we have found.
23475: 00/06/26: Re: IDE-Interface for FPGA
24157: 00/07/27: Re: Spartan-II power consumption
<bryan.at.avnet@gmail.com>:
157927: 15/05/14: Re: ZYNQ temperature
BryanW:
Bryn Wolfe:
7419: 97/09/08: HELP: FIFO's on an FPGA
7423: 97/09/09: Re: HELP: FIFO's on an FPGA
7426: 97/09/09: Re: HELP: FIFO's on an FPGA
7428: 97/09/09: Re: HELP: FIFO's on an FPGA
7446: 97/09/10: Re: HELP: FIFO's on an FPGA
10830: 98/06/24: Q: I squared C on an FPGA
11636: 98/08/27: FPGA Manufacturer's gate counts
12619: 98/10/20: Altera BGA packages
bs:
7409: 97/09/07: Re: fpga configuration over PCI
7405: 97/09/07: Re: FPGA-to-ASIC Conversion Advice Appreciated
106903: 06/08/22: Davies-meyer in VHDL
<bsmith@wci.com>:
1383: 95/06/11: Re: LowCost CPLD/FPGA tools ???
<bsmithtech@mail.com>:
100457: 06/04/09: New FPGA Technology Reaches New Heights
bsod:
67941: 04/03/22: Re: cpu and linux on a fpga (new to FPGAs)
<bsp0524@gmail.com>:
136879: 08/12/10: Re: Sampling a clock
<bstelle@my-deja.com>:
25296: 00/09/05: Re: Balls!
bta3:
73521: 04/09/22: Quartus II v4.1 & GNU
83610: 05/05/03: Altera Excalibur EBI problem
83723: 05/05/05: Re: Altera Excalibur EBI problem
<bthiruma@my-dejanews.com>:
13185: 98/11/19: Re: Help for WorkView Office
<btr@trenet.com>:
4601: 96/11/20: Be a Beta Tester!
Bubb:
99383: 06/03/23: Digital filter design software?
103584: 06/06/06: Re: Jtag Programmer
Bubba:
88659: 05/08/24: Help coding a bigger project
88706: 05/08/25: Re: Help coding a bigger project
88746: 05/08/27: 36x36 signed multiplier?
88751: 05/08/27: Re: 36x36 signed multiplier?
130852: 08/04/03: No synchronization word in prom file (XILINX)?
130874: 08/04/04: Re: No synchronization word in prom file (XILINX)?
130877: 08/04/04: Re: No synchronization word in prom file (XILINX)?
bubba:
26306: 00/10/11: Re: Modular Exponentiation
Bucephalus:
128267: 08/01/19: New user of ModelSim XE III v6.2 Starter - problems simulating a
128270: 08/01/19: Re: New user of ModelSim XE III v6.2 Starter - problems simulating a
128272: 08/01/19: VHDL Micron memorymodel.
128287: 08/01/20: Re: VHDL Micron memorymodel.
128288: 08/01/20: Re: VHDL Micron memorymodel.
Buckin:
30785: 01/04/28: CPLD
33853: 01/08/06: eine Frage
BuckSavage:
14376: 99/01/27: Re: The development of a free FPGA synthesis tool
14388: 99/01/27: Re: The development of a free FPGA synthesis tool
14406: 99/01/28: Re: The development of a free FPGA synthesis tool
14431: 99/01/29: Re: The development of a free FPGA synthesis tool
14437: 99/01/29: Re: The development of a free FPGA synthesis tool
budakbijak:
148028: 10/06/15: VIRTEX5 (XUPV5-LX110T) Ethernet
Buddy Smith:
42409: 02/04/23: Altera error: non-locally static bounds are not supported
43107: 02/05/14: Re: Architecture for high-level reconfigurable computing
45408: 02/07/22: Re: VHDL xor address decode implementation in Altera
45978: 02/08/13: Academics vs 'real' FPGA use
46203: 02/08/21: Re: Academics vs 'real' FPGA use
52268: 03/02/05: Re: Help needed
53566: 03/03/16: FPGA dev boards
53753: 03/03/21: schematics/layouts for basic PCB circuit w/ an FPGA?
73504: 04/09/22: Re: [ALTERA] NIOS-II + MMU + FPU
buddylee9898:
150322: 11/01/10: FPGA to PHY/MAC chip
150329: 11/01/10: Re: FPGA to PHY/MAC chip
bugbear:
33043: 01/07/16: conditional expression optimization
33079: 01/07/17: Re: conditional expression optimization
33136: 01/07/18: Re: conditional expression optimization
bugfinder:
143076: 09/09/18: HWICAP in virtex-5
143077: 09/09/18: Re: HWICAP in virtex-5
bugjay:
83495: 05/05/01: Re: MIcroblaze FSL Datasheet
buke2:
71697: 04/07/28: VHDL file equation
72194: 04/08/11: How crate symbol from VHD?
72243: 04/08/12: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
72284: 04/08/13: Re: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
72285: 04/08/13: What schematic tool (VHDL) is the best?
72365: 04/08/17: Re: What schematic tool (VHDL) is the best?
bukka:
153855: 12/06/07: FPGA Interconnect
Bulent UNALMIS:
6712: 97/06/18: HELP: FOR 6000 SERIES
7395: 97/09/05: Which FPGA ?
7461: 97/09/13: Q: Lattice Synario and ISPLSI1048
7618: 97/09/28: Help: ABEL program for ISPLSI1000 series.
8136: 97/11/20: Q: FPGA price ?
buli:
70452: 04/06/17: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
bulletdog7:
47388: 02/09/25: Re: Multiple divide by 10
47584: 02/09/30: Re: Multiple divide by 10
47586: 02/09/30: Re: Multiple divide by 10
47989: 02/10/09: Re: USB2 in FPGA?
BumsukLee:
41248: 02/03/23: Xilinx Async Fifo trouble
bunnyboy:
16333: 99/05/16: Re: Fancy Dram problem
bunty:
123867: 07/09/06: REGARDING ILA in FPGA EDITOR
127213: 07/12/14: Re: xilinx v5 configeration problem
Burke Baumann:
4539: 96/11/11: Re: UART FOR FPGAS
Burkhard Schermer:
74975: 04/10/22: Re: programming a LC5512MB using the IEEE1532 extension
74592: 04/10/14: programming a LC5512MB using the IEEE1532 extension
<burn.sir@gmail.com>:
93582: 05/12/25: Re: More beginner's verilog questions
93869: 06/01/02: optimization tips (badly) needed
93925: 06/01/03: Re: optimization tips (badly) needed
99039: 06/03/19: microprocessor design: where to go from here?
99138: 06/03/20: Re: microprocessor design: where to go from here?
99333: 06/03/23: false paths in Actel flow
100405: 06/04/08: FPGA FAQ and the spam problem
100407: 06/04/08: Why does Synplify add clock buffers?
100413: 06/04/08: Re: Why does Synplify add clock buffers?
100436: 06/04/09: Re: C-Compiler for free VHDL controller core ?
100583: 06/04/12: Re: FPGA FAQ and the spam problem
103608: 06/06/06: Re: Verilog vs VHDL
103667: 06/06/07: STOP IT :)
103867: 06/06/13: Re: How to get lowest price for a ModelSim license?
104543: 06/06/29: Altium Designer LiveDesign Evaluation Kits (once again)
104766: 06/07/05: Re: Altium Designer LiveDesign Evaluation Kits (once again)
105897: 06/08/02: Re: Programmable pulse generator
105898: 06/08/02: generating sine-like waveforms
105901: 06/08/02: Re: generating sine-like waveforms
105903: 06/08/02: Re: generating sine-like waveforms
105906: 06/08/02: Re: generating sine-like waveforms
105912: 06/08/02: Re: generating sine-like waveforms
105913: 06/08/02: Re: generating sine-like waveforms
105957: 06/08/03: Re: generating sine-like waveforms
106103: 06/08/07: Re: Who is your favourite FPGA guru?
106155: 06/08/08: Re: Who is your favourite FPGA guru?
106380: 06/08/12: Re: Clock domain crossing (again)
106429: 06/08/13: Re: Clock domain crossing (again)
106651: 06/08/16: S3 starter kit, command-line
106721: 06/08/17: Re: S3 starter kit, command-line
107022: 06/08/23: Re: fastest FPGA
107026: 06/08/23: Re: fastest FPGA
107033: 06/08/23: Re: fastest FPGA
109794: 06/10/05: nicer code => slower code??
109801: 06/10/05: Re: nicer code => slower code??
109902: 06/10/07: Re: nicer code => slower code??
111045: 06/10/27: Re: FPGA-based music synthesizer (with MyHDL)
111076: 06/10/28: Re: FPGA-based music synthesizer (with MyHDL)
112385: 06/11/21: Re: Spartan 3 Starter Kit .mcs upload problem
112621: 06/11/26: Mico32, how good is it?
112691: 06/11/27: Re: Mico32, how good is it?
112695: 06/11/27: Re: nios2 toolchain sources
112696: 06/11/27: Re: Mico32, how good is it?
112784: 06/11/29: Re: So who has used Lattice FPGAs recently?
112785: 06/11/29: Re: Mico32, how good is it?
112786: 06/11/29: Re: pre-synthezis simulation in ModelSim for Actel
112805: 06/11/29: Re: So who has used Lattice FPGAs recently?
113244: 06/12/08: Re: About Unstable Operation of ACTEL(A3P1000)....
113245: 06/12/08: Re: Looking for simple Cycone 2 example design
113291: 06/12/10: approximation of an exponential ramp?
burn.sir@spam-me-not-gmail.com:
93237: 05/12/16: verification tools?
Burnett:
38609: 02/01/18: microcontroller manager question
38745: 02/01/23: boot manager
<buse.victorstefan@decathlon.com>:
161351: 19/04/21: Up/Down Binary Counter with Dynamic Count-to Flag
Bushy:
1509: 95/07/05: JEDEC File format
busonerd:
91544: 05/11/08: Re: looking for FPGA pin header board
Buttoid:
764: 95/02/25: Re: Cadence FPGA Designer
buzz:
75394: 04/11/04: Spartan3 Engineering Sample Performance?
75587: 04/11/10: Virtex2Pro config question
bvkrock:
128933: 08/02/11: Re: loading unisim in modelsim problem while testin xilinx ipcore
130211: 08/03/18: Re: dual clock fifo
bw:
154134: 12/08/16: Re: My Spartan3 video
BW:
149694: 10/11/17: hot- or cold-plugging altera cyclone-3 LVDS inputs causing damage?
<bwickman@QUACKQUACKSPAMumich.edu>:
50142: 02/12/03: Clock fan-out and other issues
<bwickman@quackspamumich.edu>:
50223: 02/12/05: Re: Clock fan-out and other issues
bwilson79@gmail.com:
116891: 07/03/20: Re: IOSTANDARD default value in Xilinx UCF-Files?
119388: 07/05/17: Proper/recommended method for driving clock out from FPGA
119400: 07/05/17: Re: Proper/recommended method for driving clock out from FPGA
119548: 07/05/22: System-synchronous interface clocking between FPGA's
120052: 07/05/31: Seeing DCM LOCKED getting asserted in simulation at the same time CLKDV and CLKFX/CLKFX180 begin toggling
121072: 07/06/25: Intermittent failures seen when bringing a clock into V4LX160 through IBUF to DCM
121853: 07/07/13: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
121857: 07/07/13: Re: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
122998: 07/08/13: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
123020: 07/08/14: Re: Virtex-4 router failures when trying to mux multiple clocks (WARNING:Route:438)
123227: 07/08/20: At what frequencies is it acceptable to generate a clock from a register?
123301: 07/08/23: Re: At what frequencies is it acceptable to generate a clock from a register?
123334: 07/08/24: Re: At what frequencies is it acceptable to generate a clock from a register?
123366: 07/08/24: Re: At what frequencies is it acceptable to generate a clock from a register?
bxbxb3:
84238: 05/05/16: wide ROM
<by_the_lake@jboat.com>:
11217: 98/07/27: When did You last give Your wife a romantic holiday?
bybell:
122609: 07/08/01: Re: VCD file doesn't show anything in GtkWave
128627: 08/01/31: Re: GTKWave 3.1.4 for win32/linux
<bybell@gmail.com>:
128553: 08/01/30: Re: GTKWave 3.1.3 for win32
137134: 08/12/24: gtkwave website has moved
<bybell@rocketmail.com>:
90739: 05/10/19: Re: Modelsim XE, what's the latest version?
<byseid@yahoo.com>:
72164: 04/08/10: let me have logic design for traffic light
bzigon:
134650: 08/08/23: Sample vhdl to write and read a value from a Spartan 3 block ram?
134663: 08/08/25: Re: Sample vhdl to write and read a value from a Spartan 3 block ram?
135644: 08/10/10: Looking for a soft core 32 bit processor in VHDL
Børge Strand:
42704: 02/05/01: Xilinx: delete file problem
42706: 02/05/01: Re: Xilinx: delete file problem
42707: 02/05/01: Re: Xilinx: delete file problem
42715: 02/05/01: Re: Newbie--Where to start learning?
42965: 02/05/08: Re: Xilinx: delete file problem
42967: 02/05/08: VHDL: FIFO
43613: 02/05/27: Re: Small FIFOs in Spartan
45304: 02/07/18: Getting started with WebPACK and Verilog
45388: 02/07/22: Verilog newbie question
45433: 02/07/23: Editing constraints in WebPack
45434: 02/07/23: Re: Translate the design from FPGA to Custom IC
45516: 02/07/25: Re: How to implement efficient wide word comparator?
45523: 02/07/25: Is the WebPack Constraints Editor evil?
45524: 02/07/25: Re: Is the WebPack Constraints Editor evil?
45531: 02/07/25: Re: Is the WebPack Constraints Editor evil?
45663: 02/07/31: Re: Is the WebPack Constraints Editor evil?
45664: 02/07/31: Re: can 555 be used as clock input to cplds
45669: 02/07/31: Name of reset net
45942: 02/08/12: ModelSim takes forever
45943: 02/08/12: Re: ModelSim takes forever
46048: 02/08/15: Problem with Xilinx mapper
46049: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46072: 02/08/16: Re: Problem with Xilinx mapper
46321: 02/08/26: Export from ModelSim to Excel?
46324: 02/08/26: Re: Export from ModelSim to Excel?
51514: 03/01/15: Short FIFO in Verilog / Spartan IIE
51518: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
51545: 03/01/16: Re: Short FIFO in Verilog / Spartan IIE
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