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I need more information wirelength results given by VPR
for ex:
Wirelength results (all in units of 1 clb segments):
Total wirelength: 24 Average net length: 2.40000
Maximum net length: 5
Wirelength results in terms of physical segments:
Total wiring segments used: 24 Av. wire segments per net:
2.40000
Maximum segments used by a net: 5
Kindly help me
Tanx in advance
junaid
Article: 86726Dear Sidney, I started writing this yesterday, so i apologize if this has already been answered... First, no VHDL gurus would solve a hardware problem, which is exactly your type of problem. I understand your concern about this FIFO synthesis stuff. This could be a problem in the tool's interpretation, but...! Think about that BRAM has registered addresses, so maybe when you uncomment the line you specified, Xilinx can synthesize BRAM and not LUT-based RAM. Furthermore, since you do not reset the pointers, you can never know where is the starting point for them. That's why you might get some garbage in the order of the data. Now I have a question: If you want to synthesize BRAM, why not generate it using CoreGen and ... ? Vladislav "Sidney Cadot" <sidney@jigsaw.nl> wrote in message news:b9e71$42c80b47$915e9a26$2732@news1.tudelft.nl... > Dear all, > > Lately I have been trying to design and implement a synchronous FIFO using > a cyclic buffer, that can be synthesized by XST to use Block RAMs. > > I now have a version that works (it does so in simulation using GHDL). I > have attached it below. However, since it doesn't follow the prescribed > pattern for BLOCK RAM inference, the code as shown synthesizes to an > implementation that uses "distributed RAM" instead. > > Fortunately, I can easily get it in a form where BRAM can be inferred by > enabling the currently-commented-out line marked "ENABLE FOR BRAM", around > line 70. > > The thing is that if I do this, the entity stops functioning as intended. > This is particularly strange since (as far as I can tell) the change > shouldn't affect the architecture's semantics in any way! > > Any help/pointers by one of the VHDL gurus here would be much appreciated. > > Best regards, > > Sidney > > ------------- ramfifo.vhdl > > > library ieee; > > use ieee.std_logic_1164.all, > ieee.numeric_std.all; > > entity RAMFIFO is > port( > CLK : in std_logic; > data_in : in std_logic_vector(7 downto 0); > data_out : out std_logic_vector(7 downto 0); > status : out std_logic_vector(7 downto 0); > reset : in std_logic; > shift_in : in std_logic; > shift_out : in std_logic > ); > end entity RAMFIFO; > > architecture arch of RAMFIFO is > > signal cur_address_r : unsigned(3 downto 0) := "0000"; > signal cur_address_r2 : unsigned(3 downto 0) := "0000"; > signal cur_num_entries : unsigned(3 downto 0) := "0000"; > signal cur_address_w : unsigned(3 downto 0); > > signal nxt_address_r : unsigned(3 downto 0); > signal nxt_num_entries : unsigned(3 downto 0); > > signal sig_data_r : std_logic_vector(7 downto 0); > > type RAMType is array(0 to 15) of std_logic_vector(7 downto 0); > > -- initialize the ram below with sensible ascii values for debugging > signal ram : RAMType := ( > x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37", > x"38", x"39", x"41", x"42", x"43", x"44", x"45", x"46" > ); > > signal shift_in_possible : std_logic; > signal shift_out_possible : std_logic; > signal shift_in_will_happen : std_logic; > signal shift_out_will_happen : std_logic; > > begin > > status <= std_logic_vector(cur_address_r) & > std_logic_vector(cur_num_entries); > > process (CLK) is > begin > if rising_edge(CLK) then > if reset = '1' then > cur_num_entries <= "0000"; > else > if shift_in_will_happen = '1' then > ram(to_integer(cur_address_w)) <= data_in; > end if; > cur_address_r <= nxt_address_r; > cur_num_entries <= nxt_num_entries; > > -- if the line below is commented out, > -- XST generates DISTRIBUTED RAM, > -- and the FIFO works properly. > -- > -- if the line below is enabled, > -- XST generates BLOCK RAM, > -- and the fifo does not work properly. > > -- cur_address_r2 <= nxt_address_r; -- ENABLE FOR BRAM > > end if; > end if; > end process; > > sig_data_r <= ram(to_integer(cur_address_r)); > > with cur_num_entries select > data_out <= x"00" when "0000", > sig_data_r when others; > > nxt_address_r <= cur_address_r + 1 when shift_out_will_happen = '1' > else cur_address_r; > > nxt_num_entries <= cur_num_entries + 1 when shift_in_will_happen = '1' > and shift_out_will_happen = '0' > else cur_num_entries - 1 when shift_in_will_happen = '0' > and shift_out_will_happen = '1' > else cur_num_entries; > > cur_address_w <= cur_address_r + cur_num_entries; > > shift_in_will_happen <= shift_in and shift_in_possible; > shift_out_will_happen <= shift_out and shift_out_possible; > > shift_in_possible <= '1' when (cur_num_entries /= "1111") or > shift_out = '1' else '0'; > shift_out_possible <= '1' when (cur_num_entries /= "0000") else '0'; > > end architecture arch;Article: 86727
Hi Marco > I posted because I don't have found the core manual very clear... > > I have another doubt: ADC is 16 bit, but XSpi_Transfer works with 8 bit data > buffer. > > That means to obtain a 16 data I must use 2 8bit buffers? In example a > vector of 2 elements? Try reading your ADC manual. Because SPI is more a matter of "Send 1 byte" "Read 1 byte" than what the byte mean ... that all depends of the connected device. SylvainArticle: 86728
Hi Antti, > Altera CAN NOT say anything. > > The stuff is GPL so its ok to make it available in public as long as you > comply to GPL no matter what way you obtained the sources True, but it would sure be nice if they would be releasing this stuff proactively. My guess is that the development team is quite willing to help out, but is suffering from a condition known as Red-Tape-itis(TM) (which gets a whole new meaning after seeing War of the Worlds). Anyway, with Altera closed until tomorrow, I doubt anything will happen this week... Best regards, BenArticle: 86729
Ben Twijnstra wrote: > Hi Antti, > > >>Altera CAN NOT say anything. >> >>The stuff is GPL so its ok to make it available in public as long as you >>comply to GPL no matter what way you obtained the sources > > > True, but it would sure be nice if they would be releasing this stuff > proactively. > > My guess is that the development team is quite willing to help out, but is > suffering from a condition known as Red-Tape-itis(TM) (which gets a whole > new meaning after seeing War of the Worlds). > > Anyway, with Altera closed until tomorrow, I doubt anything will happen this > week... > Uploaded here: http://www.uclinux.net/download/nios2/nios2_5.0_src.tar.gz ...including nios2 elf2flt patched sources...not tried yet since I have to finish move the IDE messed up uclinux kernel to Linux first (o; rickArticle: 86730
"Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag news:dael9c$vcg$1@news.ngi.it... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:daecos$1nk$02$1@news.t-online.com... > > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag > > news:dae9vd$r6d$1@news.ngi.it... > >> > >> "Antti Lukats" <antti@openchip.org> wrote in message > >> news:dae8h6$pm0$01$1@news.t-online.com... > >> > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag > >> > news:dae5ja$pij$1@news.ngi.it... > >> >> Hallo, > >> >> I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. > >> >> > >> >> Where I could find some software examples? > >> >> > >> >> I have made some searches into Google but I don't have found anything. > >> >> > >> >> The only example into EDK documentation is about an eeprom. > >> >> > >> >> What is the meaning of : > >> >> Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | > >> >> XSP_MANUAL_SSELECT_OPTION); > >> >> > >> >> In this way ADC is a master? > >> >> > >> >> When acquiring data, ADC must be set as a master? > >> >> > >> >> Many Thanks in Advance > >> >> Marco > >> >> > >> >> > >> > > >> > 1 there are no examples to be found by googling (my guess) > >> > 2 the meaning of what you asked is defined in the opb ip core manual, > > you > >> > better read it > >> > > >> > your setup seems to be OK, eg you set master and manual SS, that is you > >> > must > >> > yourself > >> > write to SS register to assert-deassert the ADC select signal > >> > > >> > Antti > >> > PS I almost always use a GPIO bit bang SPI emulation at first testing, > > the > >> > soft SPI code is a only a few lines of C code. only when the software > > SPI > >> > works with the connected hardware I proceed with special SPI hardware, > >> > controlling hardware SPI is usually more complex (need to read the > >> > manuals!!) then doing it 100% in sw. > >> > > >> > > >> > >> I posted because I don't have found the core manual very clear... > >> > >> I have another doubt: ADC is 16 bit, but XSpi_Transfer works with 8 bit > > data > >> buffer. > >> > >> That means to obtain a 16 data I must use 2 8bit buffers? In example a > >> vector of 2 elements? > >> > > > > no > > you use MANUAL SS assertion, you already had that setup in your code > > snippet > > actually > > > > so you set SS active > > do 8 bit transfer > > do another 8 bit transfer > > de assert SS > > > > ADC 'sees' one 16 bit transfer > > > > but I would says doing it that way is more complex and takes more time > > than > > bitbang software method > > > > Antti > > > > > > Could you explain what is bitbang software method, please? you connect your ADC SPI to 'normal' GPIO ports and set/clear the bits in software. the C code is maybe 10 lines for the SPI AnttiArticle: 86731
"Antti Lukats" <antti@openchip.org> wrote in message news:daecos$1nk$02$1@news.t-online.com... > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag > news:dae9vd$r6d$1@news.ngi.it... >> >> "Antti Lukats" <antti@openchip.org> wrote in message >> news:dae8h6$pm0$01$1@news.t-online.com... >> > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag >> > news:dae5ja$pij$1@news.ngi.it... >> >> Hallo, >> >> I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. >> >> >> >> Where I could find some software examples? >> >> >> >> I have made some searches into Google but I don't have found anything. >> >> >> >> The only example into EDK documentation is about an eeprom. >> >> >> >> What is the meaning of : >> >> Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | >> >> XSP_MANUAL_SSELECT_OPTION); >> >> >> >> In this way ADC is a master? >> >> >> >> When acquiring data, ADC must be set as a master? >> >> >> >> Many Thanks in Advance >> >> Marco >> >> >> >> >> > >> > 1 there are no examples to be found by googling (my guess) >> > 2 the meaning of what you asked is defined in the opb ip core manual, > you >> > better read it >> > >> > your setup seems to be OK, eg you set master and manual SS, that is you >> > must >> > yourself >> > write to SS register to assert-deassert the ADC select signal >> > >> > Antti >> > PS I almost always use a GPIO bit bang SPI emulation at first testing, > the >> > soft SPI code is a only a few lines of C code. only when the software > SPI >> > works with the connected hardware I proceed with special SPI hardware, >> > controlling hardware SPI is usually more complex (need to read the >> > manuals!!) then doing it 100% in sw. >> > >> > >> >> I posted because I don't have found the core manual very clear... >> >> I have another doubt: ADC is 16 bit, but XSpi_Transfer works with 8 bit > data >> buffer. >> >> That means to obtain a 16 data I must use 2 8bit buffers? In example a >> vector of 2 elements? >> > > no > you use MANUAL SS assertion, you already had that setup in your code > snippet > actually > > so you set SS active > do 8 bit transfer > do another 8 bit transfer > de assert SS > > ADC 'sees' one 16 bit transfer > > but I would says doing it that way is more complex and takes more time > than > bitbang software method > > Antti > > Could you explain what is bitbang software method, please?Article: 86732
Peter Alfke wrote: > Why would an adder be slower than an increment. > In Xilinx, I see no difference. It's all a matter of carry propagation > ( and it is pretty fast in either case.) > Or is this a case of generics and portability? > My analogy for generics is Fast Food. Throw a coin whether you go to > McDon or to BurgerKing. it's all the same mediocre or below stuff. > Same with a design that is fearful of being Xilinx specific. Using only > the ingredients that everybody has, means lowering yourself to the > lowest common denominator. > Have guts and be specific! There is more stuff than Altera ever dreamt > of. Sorry, couldn't resist the plug. Peter, I'm rather impressed that you were able to turn a comment about increment vs adder speed into a dis on both VHDL generics AND Altera. Seriously, though, generics (and Verilog parameters) provide a convenient way of configuring your design without modifying the source code. I can think of a couple of recent design I've done where generics/parameters let me, well, genericize the design to support build-time variants. One example is this solid-state "disk" built with NAND flash devices. Stuffing options included the number of chips to put on the board as well as each chip's capacity. I used both of these options as Verilog parameters, which were used to ensure that addressing and chip selects worked properly. Another example is a glue logic chip that connected a video digitizer chip to a graphics processor's VIP (video-in port) bus. The glue did two things: one, it muxed two incoming 8-bit buses (Y on one bus, alternating Cr and Cb on the other) into a single 8-bit bus running at twice the pixel clock rate. The second thing was to insert the required SAV and EAV codes into the data stream at the appropriate time. The graphics processor required an exact number of pixels between SAV and EAV for each line (if off by even one pixel, the processor's video capture logic ignored the data). We wanted to support various video formats at build time, so I made the pixel and line active and blanking counter terminal counts all generic. The standard build supported 1024 active pixels in a line. One customer wanted 512 active pixels in a line, so all I had to do was copy my build script, change PIXPERLINE = 1024 to PIXPERLINE = 512 and rebuild. Another convenient use of generics/parameters is to embed version and other ID info in the design. This stuff appears as a read-only register to whatever host talks to the design. Your build script sets the version and ECO level and whatever. In all cases, the source code remains unmodified for all versions. All that's needed to do these wonderful things is to put a generic list along with the chip's top-level port list, and override them using the synthesis tool, either in a script or from within the GUI. This makes source-code control a whole lot easier -- you don't have to keep track of 16 different versions of the source if you need to support 16 different builds! Funny how with XST, you can't set/override a generic from the command line or from within the ISE GUI. Funnier still how you CAN do this with Quartus' synthesis tool. Perhaps a reason for the antipathy towards generics? -aArticle: 86733
"Antti Lukats" <antti@openchip.org> wrote in message news:daelcs$vh$00$1@news.t-online.com... > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag > news:dael9c$vcg$1@news.ngi.it... >> >> "Antti Lukats" <antti@openchip.org> wrote in message >> news:daecos$1nk$02$1@news.t-online.com... >> > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag >> > news:dae9vd$r6d$1@news.ngi.it... >> >> >> >> "Antti Lukats" <antti@openchip.org> wrote in message >> >> news:dae8h6$pm0$01$1@news.t-online.com... >> >> > "Marco" <marcotoschi@_no_spam_email.it> schrieb im Newsbeitrag >> >> > news:dae5ja$pij$1@news.ngi.it... >> >> >> Hallo, >> >> >> I'm trying to connect a Spi 16 bit ADC to Opb_Spi core. >> >> >> >> >> >> Where I could find some software examples? >> >> >> >> >> >> I have made some searches into Google but I don't have found > anything. >> >> >> >> >> >> The only example into EDK documentation is about an eeprom. >> >> >> >> >> >> What is the meaning of : >> >> >> Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | >> >> >> XSP_MANUAL_SSELECT_OPTION); >> >> >> >> >> >> In this way ADC is a master? >> >> >> >> >> >> When acquiring data, ADC must be set as a master? >> >> >> >> >> >> Many Thanks in Advance >> >> >> Marco >> >> >> >> >> >> >> >> > >> >> > 1 there are no examples to be found by googling (my guess) >> >> > 2 the meaning of what you asked is defined in the opb ip core >> >> > manual, >> > you >> >> > better read it >> >> > >> >> > your setup seems to be OK, eg you set master and manual SS, that is > you >> >> > must >> >> > yourself >> >> > write to SS register to assert-deassert the ADC select signal >> >> > >> >> > Antti >> >> > PS I almost always use a GPIO bit bang SPI emulation at first > testing, >> > the >> >> > soft SPI code is a only a few lines of C code. only when the >> >> > software >> > SPI >> >> > works with the connected hardware I proceed with special SPI > hardware, >> >> > controlling hardware SPI is usually more complex (need to read the >> >> > manuals!!) then doing it 100% in sw. >> >> > >> >> > >> >> >> >> I posted because I don't have found the core manual very clear... >> >> >> >> I have another doubt: ADC is 16 bit, but XSpi_Transfer works with 8 >> >> bit >> > data >> >> buffer. >> >> >> >> That means to obtain a 16 data I must use 2 8bit buffers? In example a >> >> vector of 2 elements? >> >> >> > >> > no >> > you use MANUAL SS assertion, you already had that setup in your code >> > snippet >> > actually >> > >> > so you set SS active >> > do 8 bit transfer >> > do another 8 bit transfer >> > de assert SS >> > >> > ADC 'sees' one 16 bit transfer >> > >> > but I would says doing it that way is more complex and takes more time >> > than >> > bitbang software method >> > >> > Antti >> > >> > >> >> Could you explain what is bitbang software method, please? > > you connect your ADC SPI to 'normal' GPIO ports and set/clear the bits in > software. > > the C code is maybe 10 lines for the SPI > > Antti > > Ok, I'll try it! Many Thanks to everyone for help and patience MarcoArticle: 86734
Hi I think some others have seen this problem with ISE 7.1 as well, the 'auto BUFG' insertion logic is changed from 6.3 to 7.1 this makes some designs that used to work with 6.3 to not pass route in 7.1 (Global clock overmapping) if that happens there is a very simple way to avoid this the false nets where the BUFG should not be used must be flagged with "buffer_type" attribute set to "none" that fixes the problem Antti PS I found the problem while testing 7.1 for S3E readiness, but then the problem also appeared with the same design on S3, so its the overall issue of the 6.3 vs 7.1 - I guess its not even a bug but feature, and not a problem when you know it.Article: 86735
Hi. Take a look at http://www.xess.com/ , there are some PS/2 examples for the XESS FPGA boards. Those examples are for a keyboard connected to the FPGA. Hern=E1n S=E1nchezArticle: 86736
You could try and implement a simple LC-3 Van Neuman Architecture. After you are happy with that you could proceed and implement a hardware driver for peripheral devices like a RTC Timer, SRAM etc. You can check the class webpages for some of the cool projects we implemented at my university for that. http://www.ee.byu.edu/class/ee320/ http://www.ee.byu.edu/class/ee224/ Best Wishes. -Yaju NArticle: 86737
Hi Katherine, You don't have to assert EOF_N if you don't want to: infinite frames are ok (that's actually how the streaming core works). As you stated, the REM signal will always be ignored if you don't assert EOF_N. Regards, Nanditha "katherine" <weston_katherine@yahoo.co.uk> wrote in message news:1120143042.627028.197650@g49g2000cwa.googlegroups.com... > All > > > Does anyone know whether with aurora framing mode you HAVE to assert > end_of_frame ever (I can see why you might want it but I don't). It > seems that the only point from the aurora cores perspective is that the > data_remainder flags are active. > > regards > > Katherine >Article: 86738
Hi Rick, The XP3/6 devices will be available in ispLEVER 5.0 SP1. SP1 will be releaed in the next couple of weeks. Chris Jedi wrote: > Hello > > Does someone knows when XP3/6 devices can be used in ispLever Base 5.0? > Lattice said that samples for them should already be available now > and I need to verify in design before doing my XP3/6 PacMan design (o; > > > rickArticle: 86739
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1120528515.181261.17840@g47g2000cwa.googlegroups.com... > Why would an adder be slower than an increment. > In Xilinx, I see no difference. It's all a matter of carry propagation > ( and it is pretty fast in either case.) > Or is this a case of generics and portability? > My analogy for generics is Fast Food. Throw a coin whether you go to > McDon or to BurgerKing. it's all the same mediocre or below stuff. > Same with a design that is fearful of being Xilinx specific. Using only > the ingredients that everybody has, means lowering yourself to the > lowest common denominator. > Have guts and be specific! There is more stuff than Altera ever dreamt > of. Sorry, couldn't resist the plug. > Peter Alfke > Hi Peter, I agree that the adder wouold be equally fast, but the routing won't. Also, he's using the sum unregistered. I know, it's not the addition as such. But using registered addresses for RAM access just happens to avoid problems later on (especially in asics). As for going low level: I tend to disagree as well. Portable code can be re-used (not that it often is) and as synthesis tools get better and better, we can spend more time on verification (or finish faster). Those small areas where performance becomes critical, some fiddling becomes usefull (I remember an integrator, 80 bits wide in a V2-4 at 100MHz, Synplify-XST didn't do this some 3 years ago). I such cases, I prefer to separate the tuned code in a separate block, so that it's implementation can be replaced by the generic code quite easily. Imagine having to re-use a spartan-2 design that uses the fast comparison trick (if I remember this correctly): it wouldn't synthesize as fast for a spartan-3 because there are no OR lines any more. RAMs are also good candidates (I do like dual-port, read before/after/not on write) as there are enough differences between vendors and technologies. But by no means I would suggest that Xilinx or Altera should stop improving their devices! Faster, bigger and cheaper are always good. Writing generic code for the Proth seive from a few days back that allows SLRs to be inferred (processing the numbers in 8-bit chuncks) would allow for a very small and fast seive. Still, the code could be synthesized for any target. In this case, there is more gain to be made in the algorithm (hint: what if you evaluate r-p instead of r?). As for generics, they're great for configuring word lengths or some constants. As for doing dramatic configuration changes, I'd say that different architectures are better suited. Regards, Alvin Andries.Article: 86740
Alvin, I do not see why the routing would care about the difference between an incrementer and an adder. But your preference for registering shows the disadvantage of generics: In Xilinx, the address is automatically registered in the BRAM. External registering just adds one unnecessary level of pipelining. Designing WITH the available features achieves better results than ignoring the features and designing generically. As time goes on, the newer chips have more sophisticated features ( DSP blocks, Ethernet controllers), just like they sprouted SRL16s, BRAM read-while-write, and 18 x 18 multipliers before. Unless the synthesizer is ultra-smart, it will ignore such things. Well, I am obviously biased. But I hate to see our best ideas go to waste because designers don't use them for not being "generic". Peter AlfkeArticle: 86741
Using the ISE 7.1i tools, you can preserve any hierarchy in the design and all associated port names around it for timing simulation and other verification by specifying the KEEP_HIERARCHY attribute for each instance in the design you wish to retain. The reason for this mechanism is that when you retain hierarchy for verification purposes, it can limit the optimization the tools can do for both area and timing around these boundaries and thus you should only keep the hierarchy which you need for verification, not necessarily all hierarchy in the design. Since you say you are using VHDL, the way to do this is to add to your VHDL code that is instantiating the hierarchies you wish to retain two lines in the architecture before the begin statement that look like: attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of <instance_name_of_hierarchy_you_want_to_keep>: label is "TRUE"; When you do this, you are telling the synthesis tool (XST) and the ISE tools to preserve that hierarchy and you should be able to see it and the associated port names in the timing simulation. You can also instruct ISE to write out each hierarchy in a different file using the -mhf switch (Generate Multiple Files) and you can simulate just that sub-level of hierarchy if you choose. More info on this can be found in the Synthesis and Verification design Guide: http://toolbox.xilinx.com/docsan/xilinx7/books/docs/sim/sim.pdf -- Brian peter@geckoaudio.com wrote: > First time post... > > Quick question regarding post PAR simulation. What can be done to > retain sensible signal names when doing post place-and-route (timing) > simulation in ModelSim? > > Behavioural simulation retains the nice hierarchical structure of all > instances and their respective signal names, and I would like to find > out whether this is possible for timing simulation, or what is the > closest setup that can be achieved. I have "Retain Hierarchy" > selected under the Simulation Model Properties, and my Simulation Model > Target is ModelSimXE (VHDL). Am using Xilinx ISE 7.1 (SP2) and MXE6.0. >Article: 86742
Hi, Anyone know if I can configure the output pins of a Stratix FPGA to be open-drain? I need open-drain outputs to interface with an SMBus slave device. Thanks, ErnieArticle: 86743
ernie wrote:
> Hi,
>
> Anyone know if I can configure the output pins of a Stratix FPGA to be
> open-drain?
>
> I need open-drain outputs to interface with an SMBus slave device.
>
>
> Thanks,
> Ernie
>
I'm no expert in stratix but I guess you can model the output buffer with :
OE ------,
|\_____ Out
IN ----|/
Just tie IN to GND and use OE as you command signal.
my_od_out <= '0' when my_od_sig else 'Z'.
Maybe there is even weak pull ups so you don't need external ones.
Sylvain
Article: 86744
Hello group,
I am attempting to get data (column_in) from a fast
clock domain(clk_wr) to a slow clock domain(clk_rd).
Is this the best method?
fast_clock_process: process(clk_wr)
begin
if(clk_wr'event and clk_wr='1') then
if( fast_event='1' and slow_event='1') then
fast_event <= '0';
elsif( strobe_in='1' ) then
fast_event <= '1';
fast_column <= column_in;
end if;
end if;
end process;
slow_clock_process: process(clk_rd)
begin
if(clk_rd'event and clk_rd='1') then
slow_event <= '0';
if( fast_event='1' ) then
slow_event <='1';
slow_column <= fast_column;
end if;
end if;
end process;
Brad Smallridge
Article: 86745This is a multi-part message in MIME format. ------=_NextPart_000_000D_01C581AB.EC351660 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Yes, the Stratix device can. You can also put a weak-pull up on the = output pin if you wish. Open-Drain Output Stratix devices provide an optional open-drain (equivalent to an = opencollector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and = writeenable signals) that can be asserted by any of several devices. =20 "ernie" <ernielin@gmail.com> wrote in message = news:1120608329.870272.298770@o13g2000cwo.googlegroups.com... > Hi, >=20 > Anyone know if I can configure the output pins of a Stratix FPGA to be > open-drain? >=20 > I need open-drain outputs to interface with an SMBus slave device. >=20 >=20 > Thanks, > Ernie > ------=_NextPart_000_000D_01C581AB.EC351660 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2900.2668" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV> <P class=3DMsoNormal><SPAN style=3D"FONT-SIZE: 12pt"><?xml:namespace = prefix =3D o ns =3D=20 "urn:schemas-microsoft-com:office:office" /><o:p><FONT face=3DArial = size=3D2>Yes,=20 the Stratix device can. You can also put a weak-pull up on = the output=20 pin if you wish.</FONT></o:p></SPAN></P> <P class=3DMsoNormal><SPAN style=3D"FONT-SIZE: 12pt"><o:p><B><FONT=20 face=3DHelvetica-Condensed-Bold size=3D2><SPAN=20 style=3D"FONT-WEIGHT: bold; FONT-SIZE: 11pt; FONT-FAMILY: = Helvetica-Condensed-Bold">Open-Drain=20 Output<o:p></o:p></SPAN></FONT></B></P> <P class=3DMsoNormal><FONT face=3DPalatino-Roman size=3D1><SPAN=20 style=3D"FONT-SIZE: 9pt; FONT-FAMILY: Palatino-Roman">Stratix devices = provide an=20 optional open-drain (equivalent to an=20 opencollector)<o:p></o:p></SPAN></FONT></P> <P class=3DMsoNormal><FONT face=3DPalatino-Roman size=3D1><SPAN=20 style=3D"FONT-SIZE: 9pt; FONT-FAMILY: Palatino-Roman">output for each = I/O pin.=20 This open-drain output enables the<o:p></o:p></SPAN></FONT></P> <P class=3DMsoNormal><FONT face=3DPalatino-Roman size=3D1><SPAN=20 style=3D"FONT-SIZE: 9pt; FONT-FAMILY: Palatino-Roman">device to provide=20 system-level control signals (e.g., interrupt and=20 writeenable<o:p></o:p></SPAN></FONT></P> <P class=3DMsoNormal><FONT face=3DPalatino-Roman size=3D1><SPAN=20 style=3D"FONT-SIZE: 9pt; FONT-FAMILY: Palatino-Roman">signals) that can = be=20 asserted by any of several devices.</SPAN></FONT><FONT=20 face=3DHelvetica-Condensed-Bold size=3D2><SPAN=20 style=3D"FONT-SIZE: 10pt; FONT-FAMILY: = Helvetica-Condensed-Bold"><o:p></o:p></SPAN></FONT></P> <P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D3><SPAN=20 style=3D"FONT-SIZE: = 12pt"><o:p> </o:p></SPAN></FONT> </o:p></SPAN></P></DIV> <DIV><FONT face=3DArial size=3D2>"ernie" <</FONT><A=20 href=3D"mailto:ernielin@gmail.com"><FONT face=3DArial=20 size=3D2>ernielin@gmail.com</FONT></A><FONT face=3DArial size=3D2>> = wrote in=20 message </FONT><A=20 href=3D"news:1120608329.870272.298770@o13g2000cwo.googlegroups.com"><FONT= =20 face=3DArial=20 size=3D2>news:1120608329.870272.298770@o13g2000cwo.googlegroups.com</FONT= ></A><FONT=20 face=3DArial size=3D2>...</FONT></DIV><FONT face=3DArial size=3D2>> = Hi,<BR>>=20 <BR>> Anyone know if I can configure the output pins of a Stratix = FPGA to=20 be<BR>> open-drain?<BR>> <BR>> I need open-drain outputs to = interface=20 with an SMBus slave device.<BR>> <BR>> <BR>> Thanks,<BR>>=20 Ernie<BR>></FONT></BODY></HTML> ------=_NextPart_000_000D_01C581AB.EC351660--Article: 86746
Jai, could you post PDFs of your schematics and boards? I'd like to know why you're interested in running cores like 8051 and ARM, there was a recent thread discussing how CPUs designed specifically for FPGAs like Microblaze and NIOS will make more efficient use of the fabric compared to "regular" CPUs.Article: 86747
This sounds more like curve fitting than filtering (rate conversion). If the sample rate is high compared to your FPGA speed grade, you need to build the polynomial multiplier and scaling blocks directly and "wire" them up with adders. If your FPGA can run significantly faster than the sample rate, you can multiplex the same logic over multiple computations to save area. Alternately, you can take the AWG approach and compute the waveform into a large bank of memory, then play it back repeatedly. In this case, you can get away with using a processor IP to do the calculations, an external (or internal, for a large enough device) RAM to store the waveform, and logic to read out this waveform to the DAC.Article: 86748
Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit reprogrammable format? Their data sheet claims 450MHz PPC and 500MHz DSP. The -12 speed grade of the XC4VFX40 or 60 devcies sound like they won't be available until next year, though. I couldn't find definitive data in the Altera literature about the speed of the Stratix II parts. Do these parts run at speeds approaching the Virtex 4 parts? Does Lattice offer high-speed devices with built-in microprocessor, DSP, and RAM support? It appears the EC family supports RAM at up to 200MHz. Thanks. DaveArticle: 86749
Hi, I'm using ModelSim SE 6.0a with ISE 7.1 (SP 2) and EDK (SP 1). I get the following error with the PPC SmartModel. # Loading work.ppc405_0_wrapper(structure) # Loading C:/simlib/EDK_Lib/ppc405_v2_00_c/.ppc405_top(structure) # Loading C:/simlib/unisim/.ppc405(ppc405_v) # Loading C:/simlib/unisim/.ppc405_swift_bus(ppc405_swift_bus_v) # Loading C:/simlib/unisim/.ppc405_swift(smartmodel) # Loading c:\Modeltech_6.0a\win32/libsm.dll # ** Error: Unable to read LMC SmartModel library file "** Fatal: Foreign module requested halt. # Time: 0 ps Iteration: 0 Instance: /system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst File: C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd # FATAL ERROR while loading design # Error loading design # Error: Error loading design The VHDL file, C:/Xilinx/smartmodel/nt/wrappers/mtivhdl/smartmodel_wrappers.vhd, is where it is supposed to be and it looks legit when I open it. Also, I recently upgraded from EDK 6.3, in which the SmartModel worked well. In the upgrade, I followed the usual set of procedures (http://www.xilinx.com/ise/embedded/ps_ug.pdf, page 120). Additionally, all the simulations were re-compiled for the new versions of ISE and EDK. Has anyone experienced similar issues with getting the SmartModel to work in 7.1 for a Win XP machine? Any undocumented quirks with the tools? Thanks, NN
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