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Hi Alessandro, > My doubts are the following: > - is a good choise to connect directly the oscillator output to the > FPGA pin or for this kind of environment is suggested to build a > more reliable circuit around the oscillator ? It would be best to have higher-frequency differential oscillator at,say, 32 or 64MHz, but basically, this should not be a huge problem. > - is a good choise using the internal PLL ? Is it reliable in a > rugged environment ? (I have chosen an external low frequency > oscillator to reduce EMI emissions) A colleague of mine is using a 33MHz single-ended clock in combination with the Cyclone PLL to control train engine inverters by directly controlling the gates of a few _big_ IGBTs that steer about 1000A over 3200V. So far it has been working flawlessly. The PLL even filters out spikes in the clock signal to some extent. The only thing that happened was during a torture test when he directly put the PCB with the Cyclone on it in in a 4500V electric field, with about 1" between cathode and anode where the PLL stopped running. On the other hand, as you can imagine, lots of other electronics on the board went weird under this condition as well, and this situation _should_ never occur in trains. BTW: once the field was removed, the PLL started running again as if nothing had happened. Best regards, BenArticle: 88201
Alessandro, this is a generic question, and Altera does not help you, so I will: Your temperature range is just Industrial, nothing special, just buy an I-grade part. You talk about "strong EMI interference". To me that sounds like the outside world trying to influence the FPGA (not the FPGA radiating EMI. That's a completely different issue). A slow and single-ended oscillator signal is the worst thing to have, making you sensitive to external noise. I would use a high-frequency differential oscillator (LVDs or LVPECL) where external noise is treated as a common-mode signal. Regarding external EMI, put some metallic shielding around your circuit. Good luck, you will be fine (even better if you used Xilinx. Just kidding...) Peter Alfke, Xilinx Applications =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D alessandro.strazzero@gmail.com wrote: > Dear everybody, > > I have to design an ALTERA Cyclone FPGA based board which will be > used in a rugged environment in terms of operating temperature > (-40 to +85 =B0C) and strong EMI interference. > I have to provide for the clock to the FPGA and I would like to use > a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone > internal PLL in order to obtain a 128 MHz clock for the NIOS II > processor. > > My doubts are the following: > - is a good choise to connect directly the oscillator output to the > FPGA pin or for this kind of environment is suggested to build a > more reliable circuit around the oscillator ? > - is a good choise using the internal PLL ? Is it reliable in a > rugged environment ? (I have chosen an external low frequency > oscillator to reduce EMI emissions) > - are there exist on the market any oscillator specifically designed > for rugged environment ? > > Hope someone of you have already experienced these kind of > problematics in order to suggest me the best way to run. >=20 > Best Regards >=20 > /Alessandro StrazzeroArticle: 88202
Antti Lukats wrote: > Hi > > I wonder if Xilinx does any testing of their releases at all - creating Hard > Macros seems to be impossible in 7.1 as the FPGAeditor self terminates > itself on any attemp to add extpin. Well it seems to be that 6.3 made hard > macros are compatible and useable in 7.1 but its very awkward to keep a copy > of 6.3 only for that purpose. > > Antti > PS to Xilinx, yes I did open a WebCase. I have plenty of webcases open. So > far NO HELP. Antti, I had all your open webacases reviewed. Since you have only the most basic service level, the webcase goal is to respond in less than two days. So far we are keeping within that goal. Except the time you went on vacation, and we couldn't get to you for a week. A couple of your cases have been escalated further, as you are doing things yourself, instead of using Impact tools (eg the flash programming), and we have to find out what other things are happening...and we will to help find out if you are doing something wrong, or if we just didn't document all the steps that our software performs. If you are dissatisfied with this level of service, you may always sign up for something other than webcase support, and get less than 2 day max turnaround. I accept you have issues, and get frustrated, but it looks like our support folks here are doing a great job supporting you at the most basic (ie free) level of service, and well within our service goals. So, I know you are not happy right now, but, we are on your side, and we are providing the support you require, in a timely fashion. AustinArticle: 88203
Samsung claims crossover for DDR2 chips
Mark LaPedus
(08/10/2005 10:05 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=168600638
SAN JOSE, Calif. After a slow start due to high costs, DRAM makers are
finally experiencing the long-awaited demand for double-data-rate (DDR)
2 SDRAM products.
Samsung Electronics Co. Ltd., for one, on Wednesday (August 11) said
that it has entered the DRAM crossover point between DDR1 and DDR2
devices as main memory for PCs.
As of July, some 40 percent of the company's total DRAM output is DDR2
and approximately 30 percent is DDR1. This marks the first month that
production of DDR2 has crossed over to take the lead from DDR1 in bits
produced, according to Samsung (Seoul).
"The industry has been waiting for a clear indication that DDR2 has
become the dominant memory for electronic data processing applications.
We are seeing an upsurge in interest in DDR2 from system OEMs as well as
system integrators, something that will continue to accelerate into
2006," said Tom Quinn, senior vice president of memory sales and
marketing at Samsung Semiconductor (San Jose), in a statement.
The company has seen a 30-fold growth for DDR2 in the past 12 months.
DDR2 technology claims to provide faster speeds, better signal
integrity, improved thermal characteristics and reduced power
consumption over DDR1.
DDR2 took some time to develop. "DDR2 market penetration may not have
been quite as fast as some expected, but it's accelerating rapidly now,
spiking demand for higher performance to drive increased unit sales of
PCs, notebooks and servers," said VSamsung claims crossover for DDR2
chips
Jeremy Stringer wrote:
>
> >>>From fpga interface prespective, which of them is advantagious ?
> >
> > Depends on what FPGA you want to use... If it's a Xilinx Virtex2Pro or
> > Virtex-4, then you can use free, ready-to-use IP-cores from Xilinx for
> > both DDR and DDR2, no need to design the controller yourself. And, trust
> > me, you don't really want to design a DDR memory controller yourself if
> > it isn't absolutely neccessary. Designs like that are usually a PITA
> > with all the phase-shifting and data valid windows and crap like that...
>
> It could be worth looking into the technology a bit more, and reading a
> few application notes. DDR2 is newer and is designed to be able to go
> faster - if (and I'm no expert) this allows for greater data valid
> windows, then it may be better to go for DDR2 for the better margins.
>
> It's also going to depend on which FPGA you use - V4s, for instance,
> have better support for source-synchronous IO than some of early
> {Xilinx} designs, which may make the job easier - not too much of a
> problem if you use a core though, and don't actually have to do the
> design yourself.
>
> my 2c
> Jeremy
Article: 88204Makes perfect sense Peter, I hadn't even considered the cost of the decode. I guess I haven't been around long enough :-) In my past life doing VLSI research I built single AND gates with up to 64 inputs (!) (using threshold-logic that actually worked, and was about three times faster and disippated far less power than an equivalent tree of domino CMOS). Thanks for your help again. PeterC.Article: 88205
> jjlindula@hotmail.comwrote: I just wanted to say that I write all of my code in text form, but I > create a symbol of the text code. Then in my schematic page, I just > insert the newly created symbol. I thought I needed to add this piece > of information. When everything is done I have a nice functional > diagram and when I click on the symbol it opens up my text code, > written in .VHDL, or Verilog, or Altera's AHDL (which is very easy to > write). I'm using Quartus and MaxPlus both from Altera. I don't know if > you can do this in Xlinx or other FPGA IDE's. A great idea to help > manage a complex design. > > I'm so happy to hear people discussing this topic and appreciate all > responses. > > thanks, > > I feel it much interesting but have not done it before as i am new in that field and also donot know that xilinx provides this feature or not.I am using xilinx spartan-2 and so working on ISE 7.1 . > I feel that its great for me as i was searching for that kind of things to make documentation for my final year project side by side with project , and also it may things more clear. > > Thanks to jjlindula@hotmail.com for that suggestion 8) > > > > > jjlindula@hotmail.com wrote: > Hello, I know this is a off-the-wall question, but bear with me. In my > effort to become more efficient and improve my design process in my > FPGA design I always create a top block diagram that is either a Block > Design File (.bdf) or a Graphic Design File (.gdf). If you are not > familiar with these files, they are basically a schematic where you can > graphically add symbols and connect symbols via wires or buses. I > believe using these files reduces complexity, and creates documentation > while you design. I know it does take some time placing the wires, > which is why some don't uses these files in their fpga design. In > addition, using these graphical files allows you to create a > hierarchical design which again helps manage complexity and makes the > design easier to modify/maintain. I'm just wondering how many people > use some sort of graphic design in their FPGA programs? I see so many > benefits of doing so, but my co-workers see it as a waste of time > placing those wires and symbols they would just rather have a design > contain lots of .vhdl, .v, and .tdf files. Any thoughts, comments, > suggestions, experiences on the topic? I'm not trying to be picky, its > just when I see a tool that can help reduce complexity if can't > understand why people wouldn't use it. > > thanks, > joe[/quote:1d6095278b]Article: 88206
Hey all...i am trying to incorporate a noise generator using FPGA. I can easily generate and control noise through Xilinx ISE. I am usig the P160 analog module provided by Memec on a Virtex II 1000. I would like to use Microblaze to control the noise generator. however, i am having problems interfacing with the P160 module through microblaze. Since the interface is not provided by Xilinx, i believe i have to create my own interface to the P160 module. Any help is greatly appreciated thanks ChintanArticle: 88207
Thanks. Yes, I'm back although via Google (which has it's own advantages). XC3S100E and XC3S500E samples are generally available today. If you are having a problem obtaining them after placing an order, please let me know. Samples of the rest of the family are through September and October. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 88208
Don't overlook Altera's HardCopy program (analogous to a structured ASIC), for FPGA's. I've seem some pretty impressive numbers, especially in the HardCopyII program. You can go right from FPGA to HardCopy and have your timings guaranteed. Engineers often forget about the cycles need to verify the ASIC's timings, etc. The other nice thing is that the footprints for both the FPGA and the HardCopy device can be backward compatible. The company I work for is currently going through the process and it is as easy as Altera claims it is. And as Francesco said, the time to market is much quicker than turning around a full ASIC. <francesco.poderico@trendcomms.com> wrote in message news:1123747651.607447.118570@g49g2000cwa.googlegroups.com... > Dear Dave, > why not use a FPGA or a CPLD instead of an ASIC? > the Spartan3 and coolrunner (from Xilinx) for example seems reasonable > cheep. > The advantage using FPGA are: > 1. reduced risk (if you do a mistake you can fix it even after the > production and distribution) > 2. the costs in the design are lower (much lower) > 3. the time to market is shorter > > If the application is so straight forward maybe a CPLD like coolrunner > is enougth. > Also another advantage iss that now you can download all the SW you > need to program and simulate the CPLD and many FPGA from the Xilinx > Website for free and in my experience the tool ISE7.1 is now very very > stable. > > Regards, > Francesco >Article: 88209
=====================================================================
[ CPA-2005 (WoTUG-28) Call for Delegates ]
=====================================================================
========================================================
[ ]
[ Title: Communicating Process Architectures - 2005 ]
[ ]
========================================================
========================================================
[ ]
[ When: Sunday 18th September (late afternoon) ]
[ until Wednesday 21st September ]
[ (lunchtime / end of afternoon when joining ]
[ complimentary visit to the Philips Museum) ]
[ ]
========================================================
========================================================
[ ]
[ Where: Technical University of Eindhoven, ]
[ Eindhoven, (The Netherlands) ]
[ ]
========================================================
========================================================
[ ]
[ Web site: http://www.wotug.org/cpa2005/ ]
[ E-mail: cpa2005@wotug.org ]
[ ]
[ Please see the above URL for details of conference ]
[ structure, accepted papers, location, registration, ]
[ programme committee, secretary, fees, bursaries etc. ]
[ ]
[ A brief summary of the Rationale behind this meeting ]
[ is given below. ]
[ ]
========================================================
========================================================
[ ]
[ Cost: 300 EURO (conference fee) ]
[ 110 EURO per night (hotel accommodation)* ]
[ ]
[ The conference fee covers admission to ]
[ sessions (keynotes/papers/fringes), all ]
[ meals (including the conference dinner), ]
[ the excursion and Proceedings. ]
[ ]
[ The conference hotel is the 5 star Crown ]
[ hotel <www.crownhotel.nl>, where the ]
[ evening Fringe sessions will be held. ]
[ A few double rooms, at 130 EURO per night ]
[ are also available. ]
[ ]
[ ]
[ WoTUG are sponsoring a limited number of ]
[ 150 EURO bursaries for student delegates ]
[ - see the web site. ]
[ ]
========================================================
=======================
[ Keynotes ]
=======================
Ad Peeters, CEO Handshake Solutions, <http://www.handshakesolutions.com>
Title: "Handshake Technology: High Way to Low Power"
H. Peter Hofstee,
CELL Chief Scientist and CELL Synergistic Processor Chief Architect
IBM Systems and Technology Group
<http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell>
Title: "Communication and synchronization in the CELL processor"
Guy Broadfoot, Lead Consultant, Verum, <http://www.verum.com>
Title: "If Concurrency in Software is so Simple, Why is it so Hard?"
Paul Stravers, Philips Research, <www.philips.com>
Homogeneous Multiprocessing for Consumer Electronics
Also there will be a paper presentation by John Jakson on his FPGA
Transputer efforts.
=====================================================================
[ The Rationale behind Communicating Process Architectures - 2005 ]
=====================================================================
At all levels of abstraction, modern computing systems are built in
terms of components and communication (or, at least, synchronisation)
between components.
Communicating systems imply concurrency but, traditionally, concurrency
has been taught and considered and experienced as an advanced and
difficult topic. The thesis underlying this conference is that that
tradition is wrong. The natural world operates through the continuous
interaction of massive numbers of autonomous agents at all levels of
granularity (sub-atomic, human, astronomic). If modern computer science
finds this hard to grasp, then perhaps it is not doing it right.
It is time for concurrency to mature into a core engineering discipline
that can be used on an everyday basis to *simplify* problem solutions,
as well as to enable them.
Communicating Process Architectures 2005 addresses these issues head on.
The goal of the conference is to stimulate discussion and ideas as to
the role concurrency will play in future generations of scaleable computer
infrastructure and applications - where scaling means the ability to ramp
up functionality (i.e. stay in control as complexity increases) as well
as physical metrics (such as performance).
This conference brings together researchers and practitioners from an
astonishing range of disciplines: theory (primarily based upon Hoare's
algebra of Communicating Sequential Processes), hardware architecture,
software architecture, hardware/software co-design (including FPGAs),
languages for concurrency (including Java, occam, Handel-C and C#),
libraries, formal verification, tools, multithreaded run-time kernels,
embedded systems, distributed systems, Internet programming and
supercomputing.
The WoTUG forum aims to continue the successful series of yearly
conferences, this one, CPA2005, being the sixth under the name
of CPA, and the 28th in the series of WoTUG conferences.
We hope you enjoy Communicating Process Architectures 2005 and your
visit to the Technical University of Eindhoven. There will be a mix
of submitted and invited papers during the day, with workshops and/or
tutorials in the evenings. Submitted papers have been refereed by the
Programme Committee - only 24 were accepted so that their presentations
take place in a single stream attended by all the delegates. The plan
is for everyone to listen and talk to each other. It is already apparent
(and will be reported at this meeting) that significant mutual benefits
can be obtained when hardware and software architects appreciate and
depend on each other. We want more of this - you can always sleep on
the journey home ...
===============================
[ Local Conference Organizers ]
===============================
Ir. Herman Roebbers
Philips TASS BV
P.O. Box 80060
5600 KA
Eindhoven
The Netherlands
Ir. Harold Weffers PDEng
Eindhoven University of Technology
Department of Mathematics and Computer Science
Stan Ackermans Institute / Software Technology
HG 6.38, P.O. Box 513, NL-5600 MB, Eindhoven
T.: +31 40 247 4334 / F.: +31 40 247 5895
Ms. Maggy de Wert
Secretary CPA2005
Eindhoven University of Technology
Dept. of Mathematics and Computer Science
Stan Ackermans Institute / Software Technology
Tel: +31 40 247 4334
Fax: +31 40 247 5895
=======================
[ Registration ]
=======================
* We have reserved a limited number of hotel rooms for the conference
at the above reduced rate.
Places are available on a first come, first served basis.
Please register before August, 18.
=======================
[ Programme Committee ]
=======================
Prof. Peter Welch, University of Kent, UK (Chair)
Prof. Hamid Arabnia, University of Georgia, USA
Prof. Peter Clayton, Rhodes University, South Africa
Prof. Jon Kerridge, Napier University, UK
Prof. Brian O'Neill, Nottingham Trent University, UK
Prof. Chris Nevison, Colgate University, New York, USA
Prof. Patrick Nixon, University of Strathclyde, UK
Prof. Nan Schaller, Rochester Institute of Technology, New York, USA
Prof. Dyke Stiles, Utah State University, USA
Prof. Rod Tosten, Gettysburg University, USA
Prof. Paul Tynman, Rochester Institute of Technology, New York, USA
Prof. Jim Woodcock, University of York, UK
Dr. Alastair Allen, Aberdeen University, UK
Dr. Fred Barnes, University of Kent, UK
Dr. Richard Beton, Roke Manor Research Ltd, UK
Dr. Marcel Boosten, Philips Medical Systems, The Netherlands
Dr. Jan Broenink, University of Twente, The Netherlands
Dr. Alan Chalmers, University of Bristol, UK
Dr. Barry Cook, 4Links Ltd., UK
Ruth Ivimey-Cook, Stuga Ltd., UK
Dr. Ian East, Oxford Brookes University, UK
Dr. Michael Goldsmith, Formal Systems (Europe) Ltd., Oxford, UK.
Dr. Kees Goossens, Philips Research, The Netherlands
Dr. Gerald Hilderink, Enschede, The Netherlands
Christopher Jones, British Aerospace, UK
Dr. Tom Lake, InterGlossa, UK
Dr. Adrian Lawrence, Loughborough University, UK
Dr. Roger Loader, Reading, UK
Dr. Jeremy Martin, GSK Ltd., UK
Dr. Stephen Maudsley, Bristol, UK
Dr. Dennis Nicole, University of Southampton, UK
Dr. James Pascoe, Bristol, UK
Dr. Matt Baekgaard Pedersen, University of Nevada, Las Vegas
Dr. Roger Peel, University of Surrey, UK
Herman Roebbers, Philips TASS, The Netherlands
Dr. Marc Smith, Colby College, Maine, USA
Dr. Johan Sunter, Philips Semiconductors, The Netherlands
Oyvind Teig, Autronica Fire and Security, Norway
Dr. Stephen Turner, Nanyang Technological University, Singapore
Dr. Brian Vinter, University of Southern Denmark
Dr. Paul Walker, 4Links Ltd., UK
=========================
[ Published Proceedings ]
=========================
The Proceedings will be published by IOS Press, Netherlands
<http://www.iospress.nl> as part of their Concurrent Systems Engineering
<http://www.iospress.nl/html/cse.html> Series (ISSN 1383-7575).
We look forward to welcoming you at CPA2005 in September!
Herman/Harold/Maggy
--
Article: 88210"austin" <austin@xilinx.com> schrieb im Newsbeitrag news:1123801073.519240.126420@g44g2000cwa.googlegroups.com... > Antti Lukats wrote: > > Hi > > > > I wonder if Xilinx does any testing of their releases at all - creating Hard > > Macros seems to be impossible in 7.1 as the FPGAeditor self terminates > > itself on any attemp to add extpin. Well it seems to be that 6.3 made hard > > macros are compatible and useable in 7.1 but its very awkward to keep a copy > > of 6.3 only for that purpose. > > > > Antti > > PS to Xilinx, yes I did open a WebCase. I have plenty of webcases open. So > > far NO HELP. > > Antti, > > I had all your open webacases reviewed. > > Since you have only the most basic service level, the webcase goal is > to respond in less than two days. > > So far we are keeping within that goal. Except the time you went on > vacation, and we couldn't get to you for a week. > > A couple of your cases have been escalated further, as you are doing > things yourself, instead of using Impact tools (eg the flash > programming), and we have to find out what other things are > happening...and we will to help find out if you are doing something > wrong, or if we just didn't document all the steps that our software > performs. > > If you are dissatisfied with this level of service, you may always sign > up for something other than webcase support, and get less than 2 day > max turnaround. > > I accept you have issues, and get frustrated, but it looks like our > support folks here are doing a great job supporting you at the most > basic (ie free) level of service, and well within our service goals. > > So, I know you are not happy right now, but, we are on your side, and > we are providing the support you require, in a timely fashion. > > Austin > Thanks, I actually did not mean to sound so negative - and I have to admit private problems have 'charged' me with negative charge, so that comes out in the wrong way. I understand that the WebCase people are doing their best, but, hm maybe I better not discuss my view on that in public. As from the open WebCases actually only one is that is relevant to me all other will only help Xilinx to improve the tools. I have taken great time to open the webcases in the issues that i have encountered also in the cases where the problem is not so critical for me or where I can wait or workaround. But the issues are all real, and it is to the best of Xilinx to fix them. I assume many more people see and find bugs and problems and are silent about them. ok, my "NO HELP" was overstatement, I should have read my posting second time, and I would most likely have done self censoring. BTW I was not on vaccation, in the matter of fact I have not taken a paid vaccation in all my life (I am 40). The WebCase person did go to vaccation, then I had to send the same files to another person all over, then other case was delayed because of Bank holiday in Ireland, etc. What said about 'platinum' services is possible true. The base level support people have very little experience with xilinx devices and tools and internal clearance to conctact the Xilinx experts himself those they have to apply to fab FAE who then in turn will contact the experts. If we add the time zone delay then it all ends up in a 2 week response time til solution, that is the very same time I have said to apply loong time ago. On the base level webcase no help is to be expected sooner as in 2 weeks unless the problem is really trivial. So in short: I appologize, and withdraw my 'NO HELP' - I agree that the webcase people are doing their best (what isnt much as they dont have the required experience and as I am not paing then the people with experience are not involved at least in early stages of the webcases). The only important (client waiting) issue, I really hope that will be cleared - to my understanding it would be quite good thing for Xilinx too - because to my understanding this issue prevents any and all 3rd parties to program the XCFxxP parts with other tools than impact, that is the XCFxxP can not be programmed on the factory floor at all, as impact doesnt qualify for production programmer. Antti PS I actually think it would be the best of all of us if I would withhold ALL my public comments on Xilinx products and services and work more closely with Xilinx in order to fix them to the benefit of all of us. But that work should in that case be compensated to me. It doesnt make sense to pay premium support deal just to be able to help Xilinx to fix their problems better.Article: 88211
Can't be true. One can easily design a 16ish bit processor in under a week's time. But it will have to be embedded. You are right if you mean a "competitive general purpose uP". It is awfully hard to compete single-handedly against the likes of Intel.Article: 88212
This was in response to the following claim in parent message: "The story I hear is that Frederico Faggin was the last guy to single-handedly design a uP (Z-80). "Article: 88213
If FPGA/CPLDs don't meet your power requirement, you need to first think about the kind of process you want to use. With your tiny gate count on an up-to-date process your chip will be mostly blank and dominated by pads. You cost will be in testing and packaging. Best bet is to find an off-the-shelf solution or one of those "structured" ASICs. dave94024 wrote: > We're about to move an existing design to an ASIC. The prototype was > built using a small PIC and some discretes, so the ASIC will look > nothing like the prototype. > > I'm looking for some suggestions for ASIC design house people have used > and been happy with as well as ASIC design services (someone able to > take a project successfully from concept through production), should we > decide to use outside services. > > There are too many issues to detail here, but here are a few: > - Super-low power, we're looking for aggressive sleep mode, low power > while running, some kind of built-in RC oscillator if that's possible > (4MHz and 32KHz and off). > - Low voltage would be ideal 1.5 - 1.8 volts or thereabouts. > - Need some beefy I/O lines if possible 15-25ma > - The application itself is reasonably straight-forward, we need a > UART, a state machine, some switch debouncing, jelly-bean stuff like > that, as well as some kind of ROM space a few K and some RAM a hundred > bytes or so. > > The more I think about the problem, the more it seems like a custom > micro-controller. Any thoughts? > > Thanks, > Dave.Article: 88214
Hi Eric You can download the .exe file fom the following link: http://rapidshare.de/files/3899362/EquationSolve.exe.html I have limited the iterations to 1000 , so that it can solve equations like 13x + 4 = 615. It does it successfully. Once agains thanks AnkitArticle: 88215
ravindra28d@rediffmail-dot-com.no-spam.invalid (ravindra kalla) writes: > hi, > > i made a architecture,in which i want to run 18 proccessing elements > parrallely.Each processing element is connect with one memory > module.every memory module should store 256 bytes.Is it possible to > implement it in XILINX.If yes , how can i do so.Please help. > > > What is the maximum size i can store in memory of XILINX. > You'd be better off on comp.arch.fpga - I've corssposted there and set the followup there. The answer to your questions depends on whch of Xilinx's many chips you are going to use. You can do what you want with 9 Virtex-II architecture BlockRAMs (assuming each element only needs a single port access). There's plenty of space in each BRAM (each can hold 2048 bytes), and there are two ports on each BRAM. This will fit in even a smallish Spartan-3 device. Check the data sheets for precise numbers of BRAMs. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 88216
On 10 Aug 2005 23:36:00 -0700, "Gerr"
<gertvierman@hotmail.com> wrote:
>I'm a bit confused by the do's and dont's of delay's (#) in verilog,
>like the following snippet :
>
>always @(posedge clk)
> load_r <= #1 load;
In the jargon, this is intra-assignment delay on a
nonblocking assignment. It works very nicely to model
the clock-to-output delay of a flip-flop. Synthesis
tools will happily ignore it. It can make your simulation
waveforms look much prettier. Lots of people like to do it.
Please, whatever you do, DON'T do it.
I know that I'll get into trouble with some Verilog
experts by saying that, but it's just a crazy thing
to do. Here's why....
Consider the following rather useful synthesis idiom:
always @(posedge clk) begin
out_reg <= 2'd0; // Default value
if (condition_1)
out_reg <= 2'd1;
if (condition_2)
out_reg <= 2'd2;
end
Especially if there are complicated nested conditions,
this can be a very neat way of describing default
conditions - there's no need to check that you have
written the right "else" clauses to mop up all the
default possibilities. However, let's now suppose
that you added delays to the assignments - but you
missed one:
out_reg <= #1 2'd0;
if (condition_1)
out_reg <= #1 2'd1;
if (condition_2)
out_reg <= 2'd2; // oops, forgot the delay
Now imagine that we execute the code, and condition_1
is false but condition_2 is true. The first assignment
schedules an update on out_reg one time unit into the future.
The second assignment is not executed at all, because
its "if" conditional is false. The third assignment
schedules an update in the immediate future.
"<= #T" delay in Verilog is a transport delay, so both
updates remain active. So the assignment that we
wanted to happen,
out_reg <= 2'd2 ,
will take place immediately but, one time unit later, it
will be superseded by the default assignment. The design
is broken in a way that's very hard to diagnose, and
what's worse, simulation and synthesis will disagree
(synthesis will give the answer that you wanted, because
it ignores the delays).
The only way to get this right is to ensure that all
assignments have exactly the same delay. This is
completely absurd, and impossible to maintain across
a large always block - especially if it calls tasks.
DON'T DO IT. No delays, please.
If you really want to delay the output, then make your
clocked assignments to an internal variable, and copy
that on to the output port using a continuous assign
with a delay. In that way the delay is centralised in
one place and is not subject to the kind of error I
described.
Note that VHDL does not suffer this problem, because
assignment delays are (by default) inertial and so
the intuitive "most recent assignment wins" rule
works as you'd expect, even if the delays are different.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 88217"austin" <austin@xilinx.com> schrieb im Newsbeitrag news:1123801073.519240.126420@g44g2000cwa.googlegroups.com... > Antti Lukats wrote: > > Hi > > > > I wonder if Xilinx does any testing of their releases at all - creating Hard > > Macros seems to be impossible in 7.1 as the FPGAeditor self terminates > > itself on any attemp to add extpin. Well it seems to be that 6.3 made hard > > macros are compatible and useable in 7.1 but its very awkward to keep a copy > > of 6.3 only for that purpose. > > > > Antti > > PS to Xilinx, yes I did open a WebCase. I have plenty of webcases open. So > > far NO HELP. > > Antti, > > I had all your open webacases reviewed. > > Since you have only the most basic service level, the webcase goal is > to respond in less than two days. > > So far we are keeping within that goal. Except the time you went on > vacation, and we couldn't get to you for a week. > > A couple of your cases have been escalated further, as you are doing > things yourself, instead of using Impact tools (eg the flash > programming), and we have to find out what other things are > happening...and we will to help find out if you are doing something > wrong, or if we just didn't document all the steps that our software > performs. > > If you are dissatisfied with this level of service, you may always sign > up for something other than webcase support, and get less than 2 day > max turnaround. > > I accept you have issues, and get frustrated, but it looks like our > support folks here are doing a great job supporting you at the most > basic (ie free) level of service, and well within our service goals. > > So, I know you are not happy right now, but, we are on your side, and > we are providing the support you require, in a timely fashion. > > Austin > Hi Austin, I did review my webcases as well - there was one case where it was flagged as waiting files from me, but on that case the files are actually sent and I have received notification that the case has been duplicated by the Xilinx engineer. So in that case the WebCase status was wrong. On the other case there was status waiting customer call, this is something I dont understand at all, I have never selected phone as contact method or promised to call back. On this case I have not only sent all info TWICE to Xilinx I also sent to xilinx a snapshot of our internal ipcores developed to test Xilinx software. If Xilinx is not interested fix their tools then its not my problem. I have done more then enough already. I closed this case on my behalf as I feel that I can not longer spend my time in thise case to help Xilinx to finally fix S3e support in Impact. So there are no WebCases on hold because of my delayed responses. Just to clarify. Antti P.S. You did take time to comment my attitude, but did not comment the actual issue at all - is it possible to use 7.1 for Hard Macro development or not? If not then its very strange, it basically means that there are no advanced users of Xilinx tools at all? someone should have trapped that issue?Article: 88218
Stefan wrote: > Hello, > > does anybody know about clock accuracy - I need a very stable clock to > synchronize 2 devices via a RF connection. They must exactly have the same > clock, at this time I'm using a 100 MHz clock generator and a Spartan-3 > fpga. But for my intended purpose it's not accurate enough. That means, on a > scope my generated data bursts of each device with a interval of 3 us are > "running away" (that ones those aren't triggered). The 3 us intervals differ > perhaps in half a ns or something. > Is there a practicable solution for such a problem? Does a DLL with clock > mirroring eliminate the problem? I'm aware this is not an analog forum... Squaring the signal would give 200MHz. You could phaselock your squared oscillator to the incoming stream. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 88219
hi all, Im in the need of capturing images at about 500 Frames per second and sending all raw data to PC through some port. The sensor i'll be using will be one from Kodak ( KAC-9630, KAC-9638 ) and the communication channel im thinking of is USB 2. I need to do this with minimal effort, as the real work is writing some processing algorithems to this raw image data. The ideal solution for me is to buy a development board which support this Image sensor and USB2 interface. The ones i checked, which are from http://www.framos.de are too expensive. ( about $ 5500 ). So if some one knows a kit with those features for low cost, please let me know. The next alternative is to buy a FPGA development kit with USB2 support. i know some details about spartan 3 starter kit, which supports digilent Inc's Accessory module for USB2. Can some one explain the steps involved in using these two modules to communicate with the PC? Third alternative is to implement the logic for USB2 high speed communication in the FPGA it self. Is this possible? And how complicate will this be?Article: 88220
"CMOS" <manusha@millenniumit.com> schrieb im Newsbeitrag news:1123843120.103759.167000@o13g2000cwo.googlegroups.com... > hi all, > Im in the need of capturing images at about 500 Frames per second and 500 !?? KAC 9630 does 18 frames are you sure that you need 500 frame per second? > sending all raw data to PC through some port. The sensor i'll be using > will be one from Kodak ( KAC-9630, KAC-9638 ) and the communication > channel im thinking of is USB 2. I need to do this with minimal effort, > as the real work is writing some processing algorithems to this raw > image data. forget about minimal effort, you are facing pretty much major efforts, if you need image processing at 500 frames per second then if those cameras exist at all, then you should forget PC and USB alltogether and do all processing in FPGA. > The ideal solution for me is to buy a development board which support > this Image sensor and USB2 interface. The ones i checked, which are > from > http://www.framos.de are too expensive. ( about $ 5500 ). So if some > one knows a kit with those features for low cost, please let me know. > Micron offer complete kits with camera and USB module the usb adapter has Virtex-2 250 on board + Cypress USB HS interface > The next alternative is to buy a FPGA development kit with USB2 > support. i know some details about spartan 3 starter kit, which > supports digilent Inc's Accessory module for USB2. Can some one explain > the steps involved in using these two modules to communicate with the > PC? > I think digilent accessory module is unusable for your app > Third alternative is to implement the logic for USB2 high speed > communication in the FPGA it self. Is this possible? And how complicate > will this be? > pretty complicated AnttiArticle: 88221
Ask in USB Developers Forum Rgds Andr=E9Article: 88222
"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com>
schrieb im Newsbeitrag
news:1123808503.796652.203850@o13g2000cwo.googlegroups.com...
> Thanks. Yes, I'm back although via Google (which has it's own
> advantages).
>
> XC3S100E and XC3S500E samples are generally available today. If you
> are having a problem obtaining them after placing an order, please let
> me know.
>
> Samples of the rest of the family are through September and October.
>
> ---------------------------------
> Steven K. Knapp
> Applications Manager, Xilinx Inc.
> General Products Division
> Spartan-3/-3E FPGAs
> http://www.xilinx.com/spartan3e
> ---------------------------------
> The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.
>
Hi Steven
I just checked Xilinx web store, Spartan-3e is not there.
When it is to be expected to be available ??
What disties say I do know, they will quote standard leadtimes,
and that means that even though you can place order today the
actual parts will not arrive until september.
And september was what I have forecasted all the time for availability.
Nuhorizons, S3-100e, lead time 5 weeks, end of september!
Digikey: no S3 at all
Xilinx Online: no S3E
Avnet: s3-100e, ENGINEERING SAMPLE ONLY , no stock or call, that means NO
AVAIL, no leadtime known
s3-500e, ENGINEERING SAMPLE ONLY , no stock, that means NO
AVAIL, no leadtime known
Memec has been purchased by Avnet so no sense to check.
So where is the general availabiluty ??
Antti
Article: 88223The only purpose of these delays (at least in most OpenCores designs) is to allow a better view of the signals in the waveform viewer. If the signals of a clocked process change at the same time of the clock it could be confusing. Regards Javier On 10 Aug 2005 23:36:00 -0700, "Gerr" <gertvierman@hotmail.com> wrote: > >Hi, > >I'm a bit confused by the do's and dont's of delay's (#) in verilog, >like the following snippet : > >always @(posedge clk) > load_r <= #1 load; > >I'm trying to learn some tricks by reading other peoples code >(opencores.org, mostly), and a lot of projects are using delays like >this. All the books tell you not to use delays in verilog, though, >because it's not synthesizable. > >So what's the use of those delays in code that's ment to be synthesized >? > >Thanks,Article: 88224
CMOS wrote: > hi all, > Im in the need of capturing images at about 500 Frames per second and > sending all raw data to PC through some port. The sensor i'll be using > will be one from Kodak ( KAC-9630, KAC-9638 ) and the communication > channel im thinking of is USB 2. I need to do this with minimal effort, > as the real work is writing some processing algorithems to this raw > image data. > Hmm, 500 frames over USB 2.0 ?! USB 2.0 can do a peek of 56MBytes/sec, which would mean 56*1024/500 = 114 bytes per image ?! Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ****** > The ideal solution for me is to buy a development board which support > this Image sensor and USB2 interface. The ones i checked, which are > from > http://www.framos.de are too expensive. ( about $ 5500 ). So if some > one knows a kit with those features for low cost, please let me know. > > The next alternative is to buy a FPGA development kit with USB2 > support. i know some details about spartan 3 starter kit, which > supports digilent Inc's Accessory module for USB2. Can some one explain > the steps involved in using these two modules to communicate with the > PC? > > Third alternative is to implement the logic for USB2 high speed > communication in the FPGA it self. Is this possible? And how complicate > will this be?
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