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Hallo all, I am Monica from Germany working on data transmission over DVB.I must implement a MPEG-2 frame generator in the VHDL.But to my surprise I couldnt find anything realted to MPEG-2 frame structure and low level MPEG-2 signalling details.Every site says MPEG-2 is 188 byte frame and nothing more. Is MPEG-2 a poprietary standard?If anybody already worked on MPEG-2 related projects,kidnly give me some pointers/links reagrding MPEG-2 frame structure and low level signalling details. Thanks in advance. Monica, Germany.Article: 88101
"Monica" <monica_dsz@yahoo.com> writes:
>Hallo all,
>
>I am Monica from Germany working on data transmission over DVB.I
>must implement a MPEG-2 frame generator in the VHDL.But to my surprise
>I couldnt find anything realted to MPEG-2 frame structure and low level
>MPEG-2 signalling details.Every site says MPEG-2 is 188 byte frame and
>nothing more.
That's the transport stream level... There are other packaging methods...
>Is MPEG-2 a poprietary standard?If anybody already worked on MPEG-2
>related projects,kidnly give me some pointers/links reagrding MPEG-2
>frame structure and low level signalling details.
Look for the ISO13818-1 specification, everything is explained in it.
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 88102c d saunter schrieb am 08/08/05 22:24: > Probably a silly/redundant question, but the parallel port is set to ECP > mode in the BIOS of the PCs where the IV cable falls back to a III? As I said earlier, "no matter what parallel port settings you use". Believe me, I've spent days and tried *EVERYTHING*. ECP, EPP, ECP+EPP, different I/O-adresses, different DMA-channels, different power-sources for the cable (like a lab power supply instead of using the PS/2-adapter that comes with the cable), different fly leads/ribbon cables, different parallel cables, different versions of windows, Linux, different versions of ISE and the driver, different target boards, no chance. If the driver doesn't like your parallel port, there's nothing you can do, that's what it boils down to. cu, SeanArticle: 88103
> Antti Lukatswrote: "fahadislam2002" <fahadislam2002@hotmail-dot-com.no-spam.invalid> schrieb im > Newsbeitrag news:-tqdnXj1L7ewa2rfRVn_vQ@giganews.com... > hi........... > in sparton-2 ......for disply(VGA) controller ...i wanna > use bram...........can??????how????????? > > there is no sparton-2 to my knowledge. in spartan-2 you can use BRAM for any purpose, including VGA. Antti[/quote:b747d214ff] sorry for miss spell :) ... I know we can use BRAM for any purpose ... But i wanna ask is it possible tyo accomodate Bram for VGA as minimum resolution is 640*480 and minimum 8 colors needed ... so need 307200 pixel data to store and each pixel data of 3 bits ... while BRAM is of 32 kb ... can u guide if possible ... 8)Article: 88104
> Mark McDougallwrote:
fahadislam2002 wrote:
>
> i m using spartan-2 ......... and have designed a very simple
> vga controller on it ...... now i wanna interface an external ram
> with it .......... i m available only a sram of 32 kbit * 8 = 256
kb
> memory which is not dual port........
> i wanna store 640*480 pixels data on it ... as i need
> only 8 colors ...so 3 bits for each pixel ...
> is it possilble to reduce memory to make according to
> desired requiremeents ........ and to use it although it is not
dual
> port ...
>
You have two choices:
1. Timeslice access between whatever is writing to your video memory,
and the vga controller. You'll need some pretty fast SRAM to do this -
I
suspect your dot-clock is around 30MHz (33ns)? So you'll need SRAM
twice
as fast as this.
2. Use some sort if FIFO and write to the SRAM only during the
blanking
intervals on the vga controller. This will of course limit your
bandwidth writing to the video memory.
As for memory size, my calculations give 115.2KB required for the
display, though it's horribly aligned. Storing 2 pixels/byte requires
153.6KB. Not sure where you got 256KB from?
Regards,
Mark[/quote:43f0423306]
Hi...
first thanks for responding........
1- From time slicing u mean slicing between rows and colums or
between
a fixed no of pixels ?
2- I m using HM62256ALP-8 ... and its speed is 80ns :( ...
Article: 88105
> Peter Alfkewrote:
fahadislam,
> it is about time you grew up and stopped using these insane
> punctutions.
> It would also help if you learned how to spell.
> Perhaps you might even learn to think, if that is not asking for
too
> much..
> This is not a childrens' playground.
> If you want to mix with adults, behave like an adult.
>
> Peter Alfke
Hi ...
Sorry for miss spell and any other fault if u felt on my side
.. 8)
after that i will simply say that i feel we r engineers and so not
here to pick sentex errors .... try to be logical .... 8)
thats true that i m week in my spell ....... but i will not
change my style of writing for any one... we r here to discuss ideas
.. so be clear and focus on concept instead of sentex ... 8)
thats also true that ...i m new in that field ... so if u on
seniour or on adult side ... be clear to proof ur concepts and to help
others... 8)
anyways thanks for responding ... as u r my seniour ... so again i m
sorry if any fault done by me ... 8) ........
Waiting for ur logical response ....... 8)
Article: 88106Check out Gigabit System Reference Design (GSRD): http://www.xilinx.com/gsrd/ It uses the Virtex4 embedded TEMAC, is delievered as an EDK project, and runs PowerPC Linux. Paul Fridolin wrote: > > Hello, > I am trying to run the embedded TEMAC in the Virtex4 under Linux. > A design with the EMAC IP Core from the EDK is running with the > Montavista Preview Kit. > Now I am trying to change the adapter.c file from the Previewkit to the > Xilinx TEMAC source files. > Has anyone experiences with one of these parts? > ThanksArticle: 88107
The "Create and Import Peripheral Wizard" is the place to start. It generates an example user pcore and the device drivers to interface to it. http://www.xilinx.com/ise/embe dded/est_rm.pdf FIFO, DMA, and interrupt support are all available. Paul el_boricua wrote: > > Does anyone possess an example of a core incorporated to the PLB of > Virtex2Pro especially if the design is using FIFOs. I am trying to > incorporate my DES core to the PLB bus of the Virtex2Pro for a Single > PPC design. > > Thanks, > NoelArticle: 88108
Austin, Any help appreciated. Thanks, JDArticle: 88109
Peter Alfke wrote: > fahadislam, > it is about time you grew up and stopped using these insane > punctutions. > It would also help if you learned how to spell. > Perhaps you might even learn to think, if that is not asking for too > much.. > This is not a childrens' playground. > If you want to mix with adults, behave like an adult. > > Peter Alfke Wow Peter, why don't you just come out and say what you think? Thanks for giving me a chuckle this morning. :-) Paul.Article: 88110
fahadislam2002 wrote: > Hi... > i wanna use sram instead of Vram in my project ... according to > my knowledge vram is same as sram but its dual port...........as for > display its needed to read and write at same time fastly ...so uses > dual port sram...... but > problem is ... i m available only sram which is not > dual port.............is it possible to use it for display????????? > and how??????????? Run the SRAM interface twice as fast and interleave access between what's writing to it and what's reading from it. DDR SRAM interfaces are quite fast these days. -aArticle: 88111
fahadislam2002 wrote: > sorry for miss spell :) ... I know we can use BRAM for any purpose ... > But i wanna ask is it possible tyo accomodate Bram for VGA as minimum > resolution is 640*480 and minimum 8 colors needed ... so need 307200 > pixel data to store and each pixel data of 3 bits ... while BRAM is > of 32 kb ... can u guide if possible ... 8) After you learn to spell, you could learn to do some simple arithmetic. How much BRAM is available in your device? Call this "A." How much memory is needed for your frame store? Call this "B." If B > A, then you're hosed. -aArticle: 88112
Hallo Paul, thank you for your mail. A few days/weeks ago I tried this design. But it didn't run. Today I started again but there are errors during translation. My aim is to get the PLB_TEMAC and the HARD_TEMAC getting running under Linux. I have a design with the EDK EMAC core which is running under Linux. And now I tried to change the adapter.c file from the Xilinx xemac*.* to the xtemac*.* files. But this is much more difficult than I expacted. FridolinArticle: 88113
I have read it but an example is more helpful to clear out the details of what is not in the document.Article: 88114
When you run the IP Import Wizard, it does generate a very nice example design. It was very helpful for me. Make sure you have the latest EDK service pack installed since Xilinx is continually adding features to this area of the tools. Paul el_boricua wrote: > > I have read it but an example is more helpful to clear out the details > of what is not in the document.Article: 88115
Hello All: I am new to embedded development and fpgas in general so please bear with me. I am working with EDK 6.3 on a Virtex II board. In my system I have a user defined peripherals(IPIF) to interface with a DAC connected externally. So while working on my project I often need to make changes in the VHDL code of this peripheral. Everytime a minor change is made, the entire system (including all peripherals and the microblaze) have to be compiled again for the bitstream generation. This takes a long time and is proving cumbersome for me as I often need to play around with the VHDL codes. So Is there a way around this? Can we somehow save the rest of the bitstream generated and recompile only the parts that are modified? I have seen that a lot of people export the XPS project to ISE and work on it there. I am not familiar with ISE much, so could someone tell me what are the advantages of doing that? Does that speed up work in general? Thanks! Cheers, SuhridArticle: 88116
Search this newsgroup for the CORE_STATE option. You should find something from a few months ago.Article: 88117
Thanks, Philip. This seems to be just what I need. I already tried it. However, I definitely need to speed this up somewhat. It looks like I first have to re-convert the XDL-File to NCD using xdl.exe, and only then use bitgen. Or do you mean that I can somehow configure bitgen to accept XDL-Files? I just have to go from XDL-code to bitstream real fast. Preferably on-chip. Have you heard of ways to use Xilinx tools like "xdl" and "bitgen" on the FPGA itself? Thank you very much! TobyArticle: 88118
> Javier Castillowrote: Hello, > > I am working on cryptographic application over VirtexII FPGAs. I > need to store a simmetric key inside a reg of the FPGA, but I dont > want that someboy could read it analizyng the bitstream. The bitstream > could not be encrypted. Has anybody experience about hide data inside > a FPGA?. Anyone knows some papers about this topic? > > Regards > > Javier Javier, If you use the new Lattice XP devices, the need for an external PROM is eliminated and read back can be disabled. They do this by having the Flash internal. Just offering another way to "skin the cat". Regards, Jeff Holley Lattice FAE (yes, I work for Lattice)Article: 88119
Unless you specify otherwise, ISE sets the I/O standard to ... * LVCMOS25 * 12 mA output drive * SLOW slew rate. The output will follow whatever voltage level you have connected to the respective VCCO input. In other words, even if ISE sets the I/O to LVCMOS25 and you have VCCO = 3.3V, the output will drive 3.3V levels. However, it's best to always set the I/O level appropriately so the software can make sure that all your I/O assignments end up in the proper I/O banks.Article: 88120
On 9 Aug 2005 13:57:02 -0700, "Tobias Weihmann" <listen@fomalhaut.de> wrote: >Thanks, Philip. > >This seems to be just what I need. I already tried it. However, I >definitely need to speed this up somewhat. Faster computer >It looks like I first have to re-convert the XDL-File to NCD using >xdl.exe, and only then use bitgen. Right. >Or do you mean that I can somehow configure bitgen to accept >XDL-Files? Sorry I wasn't clear. You need to run XDL. >I just have to go from XDL-code to bitstream real fast. Preferably >on-chip. Have you heard of ways to use Xilinx tools like "xdl" and >"bitgen" on the FPGA itself? No. These are large programs that depend on complex database files that are part of your sw instalation. >Thank you very much! >Toby Sorry for the less than clear answer I gave. I wrote >From ascii you go through bitgen to get to a bitstream. What I should have written is this: 1) create a test design with maybe the stuff you know wont change and also some example stuff that uses all the I/Os you plan to use. Do this using the normal tool flow, such as VHDL/Verilog -> synthesis -> P&R -> Timing analysis -> bitgen. Make sure this works, and the I/Os you care about wiggle. 2) Take the NCD from the previous step, and run through XDL. Read the result very carefully, maybe comparing what you read with the view of the same design in fpgaeditor. Keep reading until you think you understand XDL syntax and all the many flavors of how it describes your design. There is no customer documentation that explains this. All XDL users end up going through this reverse engineering step. 3) Once you think you know what is going on, make a trivial change to the ascii from XDL, and convert it back to NCD, and load it into fpgaeditor. See if you got it right. If you did, try something more adventurous. Repeat till you feel confident. 4) Take the ascii of your test design as your baseline. Make the changes you want. Convert to NCD with XDL, and convert NCD to a bitstream with bitgen. 5) Repeat step 4 as you pursue your research of algorithms. Have fun. =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 88121
JD, 1. No you will not damage the FPGA with the core unpowered. However, remember that there are intrinsic diodes from IO pins to Vcco, and to ground. So if you connect Vcco to ground, and then connect all the IOs to another operating chip, you will have a diode to ground forward biased on every IO pin, probably blowing out the driving device, unless it is tough enough to handle it, Often the FPGA is accused of damaging the driver, as the FGPA will tolerate up to 200 mA sink or source for weeks without damage (same as shorting one of our pins to ground or Vcco, and leaving it there). 2. If the Vcco is just coming from a regulator or power supply, 99.99% of all such supplies are open, until powered. Thus the diodes will power ON the Vcco. That is harmless. The IOs power ON tristate, and then wait for the core and aux supplies to come up before configuring. Before, during, and immediately after configuring, all IO is tristate. Right up until DONE goes high, and then your design decides what to do with the IOs (they can stay tristate until your design sees a command on a bus, etc.). AustinArticle: 88122
Hey! Got it!... Thanks a lot; Appreciate it!Article: 88123
Hi Eric
Thanks for the code. It is quite complicated as compared to the psuedo
code. I tried making my own application in C#.It works sometimes but
sometimes it just enters an idefinite loop.This is when my population
values go beyond the right hand side constant value(ax + b = c
'value of constant c').I have a few questions for you:
1. What if you get the answer in the first population, the
corresponding normalised value would be infinite?
2.Are there any special conditions you need to check before populating
the list?
Here is my code which is based on your psuedo code.see if it makes
sense to you.
I really appreciate your help.
private void ImplementGA()
{
Random rnd = new Random();
int popsize=6;
int[] population = new int[popsize];
int i;
bool Found=false;
DateTime dt= new DateTime();
double a,b,c;
a=double.Parse(CoefficientTextBox.Text);
b=double.Parse(Constant1TextBox.Text);
c=double.Parse(Constant2TextBox.Text);
//Step 1
//Generate a random population
listBox1.Items.Add("Initial Population");
for(i=0;i<popsize;i++)
{
population.SetValue((int)(rnd.NextDouble()*10),i);
listBox1.Items.Add(population[i]);
}
listBox1.Items.Add("");
listBox1.Items.Add("");
//Step 2
//Fitness Function
listBox1.Items.Add("Corresponding Fitness Values");
double[] fitness = new double[popsize];
//(ax + b = c)
int x;
for(i=0;i<popsize;i++)
{
//fitness = ABS(1 - ((ax + b)/c))
x=population[i];
fitness[i] = Math.Abs(1 - ((a*x + b)/c));
listBox1.Items.Add(fitness[i]);
}
listBox1.Items.Add("");
listBox1.Items.Add("");
//My idea to check before repopulating
//Check for the end condition
for(i=0;i<popsize;i++)
{
if(fitness[i] == 0)
{
Result=population[i];
Found=true;
}
//else
//Found=false;
}
while(Found == false)
{
//Step 3
//Repopulate the population based on the fitness function
double ErrorTotal=0, NormalisedError=0;
double[] normalised = new double[popsize];
int[] RepopulationPercentage = new int[popsize];
for(i=0;i<popsize;i++)
{
ErrorTotal = ErrorTotal + fitness[i];
}
listBox1.Items.Add("Total Error = "+ErrorTotal);
//normlization
listBox1.Items.Add("");
listBox1.Items.Add("");
listBox1.Items.Add("");
listBox1.Items.Add("Normalisation values");
for(i=0;i<popsize;i++)
{
normalised[i] = ErrorTotal / fitness[i];
listBox1.Items.Add(normalised[i]);
}
//total of normalised error
for(i=0;i<popsize;i++)
{
NormalisedError = NormalisedError + normalised[i];
}
if(NormalisedError > 99999999)
Flag = true;
listBox1.Items.Add("");
listBox1.Items.Add("");
listBox1.Items.Add("Normalised Error = "+NormalisedError);
//Repopulation percentage
listBox1.Items.Add("");
listBox1.Items.Add("");
listBox1.Items.Add("Repopulation percentage");
for(i=0;i<popsize;i++)
{
RepopulationPercentage[i] = (int)((normalised[i] /
NormalisedError) * 100);
listBox1.Items.Add(RepopulationPercentage[i]);
}
//Elitism - copy the best solution to the next generation
int Best=100;
for(i=0;i<popsize;i++)
{
if(Flag==false)
{
if(Best>=RepopulationPercentage[i])
{
Best=population[i];
}
}
else if(fitness[i] == 0)
{
Best=population[i];
}
}
listBox1.Items.Add("Best = "+Best);
//Step 4
//Repopulate - Only mutation is being used
population[0]=Best;
//Crossover
listBox1.Items.Add("After Crossover");
listBox1.Items.Add(population[0]);
for(i=1;i<popsize-1;i++) //elements
{
population.SetValue((int)((population[i]+population[i+1])/2),i);
listBox1.Items.Add(population[i]);
}
population[popsize-1]=Best + 1;
listBox1.Items.Add(population[popsize-1]);
//Mutation
listBox1.Items.Add("After Mutation");
listBox1.Items.Add(population[0]);
for(i=1;i<popsize;i=i+2) //elements
{
if(dt.Second%2 == 0)
population.SetValue((int)(population[i]+1),i);
else
population.SetValue((int)(population[i]-1),i);
listBox1.Items.Add(population[i]);
}
listBox1.Items.Add("Above list is the final population");
//Calculate the fitness of the new population
listBox1.Items.Add("New population fitness");
for(i=0;i<popsize;i++)
{
//fitness = ABS(1 - ((ax + b)/c))
x=population[i];
fitness[i] = Math.Abs(1 - ((a*x + b)/c));
listBox1.Items.Add(fitness[i]);
}
//Check for the end condition
for(i=0;i<popsize;i++)
{
if(fitness[i] == 0)
{
Result=population[i];
Found=true;
}
//else
// Found=false;
}
}
//Display the answer
AnswerTextBox.Text = Result.ToString();
}
Article: 88124> Andy Peterswrote: fahadislam2002 wrote: > sorry for miss spell :) ... I know we can use BRAM for any purpose ... > But i wanna ask is it possible tyo accomodate Bram for VGA as minimum > resolution is 640*480 and minimum 8 colors needed ... so need 307200 > pixel data to store and each pixel data of 3 bits ... while BRAM is > of 32 kb ... can u guide if possible ... 8) > After you learn to spell, you could learn to do some simple arithmetic. How much BRAM is available in your device? Call this "A." How much memory is needed for your frame store? Call this "B." If B > A, then you're hosed. -a[/quote:4de8ef679f] today i feel my mathamatics is also weak 8) ... Actually my question was just that is it possible by using some kind of techniques like compression etc /// and if possible then how and by using which techniques 8) ... thanks 8)
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z