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Have you simulated the design? A full system simulation will not take more than a minute or two to execute. Another option is to use Chipscope to monitor the FSL signals between the two Microblazes and to ensure they are behaving as you and the protocol specification expects. Paul mvetromille wrote: > > Hello! > I'm trying on connecting two microblaze processors in EDK but I'm having > problems. I used microblaze_bread_datafsl and microblaze_bwrite_datafsl > macros to communicate them. The processors are working, they show a > message on the terminal, but when they call the macros, they stop working. > Does anyone know how to solve this problem? Does anyone have an example of > two microblazes communicating? > > Thank you! > > MelissaArticle: 88451
Hello,
I'm synthesizing a design in XST and I'm having a hard time figuring
out what's consuming all of the devices resources.
I wrote mostly structural VHDL, so I decided to synthesize each
component separately to get a better idea of the low level utilization.
I haven't seen any option in XST to see a hierarchal analysis of
area... Anyway, I estimated the resource consumption of my design,
excluding routing, the FSM, and some other small amounts of logic and
multiplexing:
Slice Count Slice FFs 4-input LUTs
----------- --------- ------------
used: 10936 29048 12406
total: 23616 47232 47232
----------- --------- ------------
46.31% 61.50% 26.27%
Here is the actual:
Number of Slices: 45523 out of 23616 192% (*)
Number of Slice Flip Flops: 22611 out of 47232 47%
Number of 4 input LUTs: 78378 out of 47232 165% (*)
When looking in the synthesis report, I noticed some warnings
indicating that duplicate FFs were removed, so that explains the
reduction in FF count. However, I cannot explain the HUGE increase in
LUT and Slice usage. What can I infer from this?
The report also tells me that some of my 6-bit counter signals are
being replicated (once or twice). What is the cause of this? High
fan-out?
<SNIP>
FlipFlop cnt_dout_ins_cnt_v_0 has been replicated 2 time(s)
FlipFlop cnt_dout_ins_cnt_v_1 has been replicated 1 time(s)
FlipFlop cnt_hreg_ins0_cnt_v_0 has been replicated 2 time(s)
FlipFlop cnt_hreg_ins0_cnt_v_1 has been replicated 1 time(s)
FlipFlop cnt_hreg_ins10_cnt_v_0 has been replicated 2 time(s)
FlipFlop cnt_hreg_ins10_cnt_v_1 has been replicated 1 time(s)
FlipFlop cnt_hreg_ins11_cnt_v_0 has been replicated 2 time(s)
</SNIP>
Is there anyway to decipher the cell usage count perhaps? Does anyone
have a URL that includes an explanation of all the cell names? I also
checked the macro statistics and everything is accounted for in that
table.
Thanks.
-Brandon
Article: 88452Pasacco wrote: > Yes, it is correct. > > In ILA, we can see the transition of the signal in a cycle accurate > manner. > > BTW, What I want to see in ILA , in the example above, is > > 'counter' signal change (0 -> 1 -> 2 -> 3 -> 4 ) part. > > Those transitions occur during the first 4 clock cycles, after (rst='0' > and en='1'). > > In my exercise, I do not see them. I only see the value '4', whih is > the last value. > > Is it possible to see, in ILA, those signal transition behaviors in the > example above? > I don't understand what you are looking for or what problem you are having. You will need to explain it better for me to be able to help you. Also after reviewing your VHDL code again it is not written in the standard way to define a registered counter and I am not sure what would actually be synthesized in the design. Specifically, you have any asynchronous comparison function (counter <= "0001") before the clock edge definition (clk'event and clk='1'). I'm not sure what would synthesized with this code, probably a gated clock, but it likely won't be what you intended. EdArticle: 88453
"Kolja Sulimma" <news@sulimma.de> wrote in message
news:430492a6$0$25879$9b4e6d93@newsread2.arcor-online.net...
> ADC_MUX is a transparent latch controlled by seq_daq_state. Therefore
> synthesis treats seq_daq_state as a clock signal.
>
> You need to either assign a value to ADC_MUX in all branches (including
> the case that seq_daq_state=seq_daq_state_4 and mux_channel(1)='1') or
> you to add an edge triggered DFF for ADC_MUX.
>
> Kolja Sulimma
>
> Marco schrieb:
>
>> when seq_daq_state_4 =>
>> if ( mux_channel(1) = '1' ) then
>> Adc_Mux <= "001";
>> end if;
>>
>> when seq_daq_state_5 =>
>>
I have modified every state where I verify if mux_channel is '0' or '1' into
the following:
when seq_daq_state_4 =>
Adc_Mux <= "001";
In this way Adc_Mux has a value set into all states, but XST adds BUFG to
signals in any case.
What could I do?
Marco
Article: 88454
Marco wrote:
> I need to use modelsim with a remote desktop, when someone is using the
> remote computer.
> With XP SP2 is possible applying a patch found on the web.
> But in this way Modelsim doesn't accept license and closes itself.
Either the other user has the license tied up
or you need a new license file tied to the other computer.
-- Mike Treseler
Article: 88455Hi Brandon, The floorplanner tool might help you track down where most of your usage is. HTH, Syms.Article: 88456
mvetromille <mvetromille@gmail.com> wrote: > Hello! Hi! > I'm trying on connecting two microblaze processors in EDK but I'm having Not talking about your problems, but mine ;) I also have two microblazes which should use a shared OPB. I just defined both as masters for this bus, but route&place fails (it works when one of the two microblazes is not connected to the OPB) Is the Spartan3-StarterKit too small for this or did I forget something? -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Sein oder DesignArticle: 88457
Since you didn't list the errors, it is hard to tell. However, if you didn't connect both Microblazes to the opb then its entirely possible one was optimized out since it had no connected outputs. My sense is two Microblazes in the S3 Starter Kit will be a real tight squeeze. Paul Adrian Knoth wrote: > > mvetromille <mvetromille@gmail.com> wrote: > > > Hello! > > Hi! > > > I'm trying on connecting two microblaze processors in EDK but I'm having > > Not talking about your problems, but mine ;) I also have two > microblazes which should use a shared OPB. I just defined > both as masters for this bus, but route&place fails (it works > when one of the two microblazes is not connected to the OPB) > > Is the Spartan3-StarterKit too small for this or did I forget > something? > > -- > mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver > > Sein oder DesignArticle: 88458
Jim, Answers in the thread below, Austin > Peter Alfke wrote: > >> I have been told that Virtex ( II to 4) the DCMs can divide down from a >> GHz, if you use the divide-by-two prescle option in the DCM. That means >> the DCM really runs on 500 MHz, which it is specified to do. > > > Interesting - is that DIV 2 in the IO area, or in the DCM itself - in > which case, are there pin restrictions to drive at 1GHz ? In the DCM. Turns out the IOB is pretty good at receiving signals: V2 stops at 1.15 GHz typically. This is not well characterized, and you are pretty much on your own here. > >> Division ( even combined multiply/divide) with numbers up to 32 is no >> problem. You can multiply 500 MHz by 7 and divide by 27 (if those are >> your numbers). The virtual 3.5 GHz are not really being generated, it's >> all mathematical trickery. :-) > > > What jitter spec, would the DCM give ? > assume sub 100MHz out, and 1GHz sub ps jitter IP . For simple divide by 10, the jitter will be entirely from the tap changes, which is ~50 ps tap in VII. Since +/- one tap is the theoretical best one can do, and in practice, you may decide the change the tap incorrectly, that makes three taps the minimum possible, and also the maximum if there is no other jitter. That is 150 ps P-P period jitter out of any output of the DCM, best case. As a percentage of the period, 150 ps is not so bad at 100 MHz (10 ns, or 10,000 ps). That is 150/10,000 of a unit interval jitter, or 1.5% UI jitter. > >> For finer granularity, you can use DDS phase accumulators which, >> however, generate som jitter (+ or - half a clock period). >> Peter Alfke, Xilinx Applications > > > -jg > >Article: 88459
I am modifying the Xilinx DDR controller core that comes with the EDK,
changing it interface from IPIF to another interface
I just completed some simulation runs and some things just don't seem
right:
I created a PPC program that has a int pointer pointing at the DDR base
address. Then a simple loop writes the same data to every address:
int* testfieldi = XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR;
int x;
print("0");
// LOOP 1
for (x = 0; x < 20; x+=2)
{
testfieldi[x] = 0xDEADBAAF;
}
But when I simulate this, the DDR controller always writes two
neighbouring data's to the same address... I cannot check if there is
any data actual corruption when I run it, I do not hava a physical
board at hand.
Also the IPIF addressing looks kind of odd:
The bus2IP addr gives a byte-aligned address, but there is also a
byte-wise mask that is set as if the address given is 64 bit aligned.
:
a byte write at address 1:
bus2IP_addr: 0x1
bus2IP_be: 0x000000f0
a byte write at address 12:
bus2IP_addr: 0x13
bus2IP_be: 0x00f00000
Anyone any thoughts about this one?
Article: 88460Marco wrote: > "Kolja Sulimma" <news@sulimma.de> wrote in message > news:430492a6$0$25879$9b4e6d93@newsread2.arcor-online.net... > > ADC_MUX is a transparent latch controlled by seq_daq_state. Therefore > > synthesis treats seq_daq_state as a clock signal. > > > > You need to either assign a value to ADC_MUX in all branches (including > > the case that seq_daq_state=seq_daq_state_4 and mux_channel(1)='1') or > > you to add an edge triggered DFF for ADC_MUX. > > > > Kolja Sulimma > > > > Marco schrieb: > > > >> when seq_daq_state_4 => > >> if ( mux_channel(1) = '1' ) then > >> Adc_Mux <= "001"; > >> end if; > >> > >> when seq_daq_state_5 => > >> > > I have modified every state where I verify if mux_channel is '0' or '1' into > the following: > > when seq_daq_state_4 => > Adc_Mux <= "001"; > > In this way Adc_Mux has a value set into all states, but XST adds BUFG to > signals in any case. > > What could I do? Get rid of the silly three-process state machine and make it all one or two clocked (synchronous) processes? --aArticle: 88461
Pasacco wrote: > When rst = 0, en = 1, the signal change "0 1 2 3 4 " should be seen in > ILA waveform. > But actually so signal change can be seen. > > What is the problem? > By the way, Is this problem? > > Thankyou. > > ------------------------------------------------------------------------ > -- Expected signal 'counter' behavior : 0 1 2 3 4 4 4 4 ..... > ------------------------------------------------------------------------ > entity top is > port > ( clk : in std_logic; > cnt : out std_logic_vector(3 downto 0) ); > end top; > > architecture behave of top is > signal counter : std_logic_vector(3 downto 0):=(others=>'0'); > > signal rst, en: std_logic; -- In VIO, reset=0, enable=1 > > begin > process(en,rst,clk,counter) > begin > if en='0' then > counter <= (others => '0'); > elsif rst='1' then > counter <= (others => '0'); > elsif counter <= "0011" then > if ( clk'event and clk = '1') then > counter <= counter + 1; > end if; > end if; > end process; > cnt <= counter(3 downto 0); > end behave; Yikes ... I don't know what the synthesis tool will do, but I suspect it won't do what you want! Did you get any synthesis warnings? Did you read the synthesis manual? -aArticle: 88462
Brandon, I would suggest taking a look at the synthesis warnings. Maybe you instantiated the same component twice, maybe you took wrong device size... But if you did everything ok, then the only thing that could happen here is that the estimation you get is not close (sometimes) to the actual placement results. Any details on this? Vladislav "Brandon" <killerhertz@gmail.com> wrote in message news:1124375215.587610.307000@g43g2000cwa.googlegroups.com... > Hello, > > I'm synthesizing a design in XST and I'm having a hard time figuring > out what's consuming all of the devices resources. > > I wrote mostly structural VHDL, so I decided to synthesize each > component separately to get a better idea of the low level utilization. > I haven't seen any option in XST to see a hierarchal analysis of > area... Anyway, I estimated the resource consumption of my design, > excluding routing, the FSM, and some other small amounts of logic and > multiplexing: > > Slice Count Slice FFs 4-input LUTs > ----------- --------- ------------ > used: 10936 29048 12406 > total: 23616 47232 47232 > ----------- --------- ------------ > 46.31% 61.50% 26.27% > > Here is the actual: > Number of Slices: 45523 out of 23616 192% (*) > Number of Slice Flip Flops: 22611 out of 47232 47% > Number of 4 input LUTs: 78378 out of 47232 165% (*) > > > When looking in the synthesis report, I noticed some warnings > indicating that duplicate FFs were removed, so that explains the > reduction in FF count. However, I cannot explain the HUGE increase in > LUT and Slice usage. What can I infer from this? > > The report also tells me that some of my 6-bit counter signals are > being replicated (once or twice). What is the cause of this? High > fan-out? > <SNIP> > FlipFlop cnt_dout_ins_cnt_v_0 has been replicated 2 time(s) > FlipFlop cnt_dout_ins_cnt_v_1 has been replicated 1 time(s) > FlipFlop cnt_hreg_ins0_cnt_v_0 has been replicated 2 time(s) > FlipFlop cnt_hreg_ins0_cnt_v_1 has been replicated 1 time(s) > FlipFlop cnt_hreg_ins10_cnt_v_0 has been replicated 2 time(s) > FlipFlop cnt_hreg_ins10_cnt_v_1 has been replicated 1 time(s) > FlipFlop cnt_hreg_ins11_cnt_v_0 has been replicated 2 time(s) > </SNIP> > > Is there anyway to decipher the cell usage count perhaps? Does anyone > have a URL that includes an explanation of all the cell names? I also > checked the macro statistics and everything is accounted for in that > table. > > Thanks. > -Brandon >Article: 88463
Hello, I am using Xilinx EDK 7.1 and ml310 development board from Xilinx. I have fedora core 2 OS on my PC. I have problem downloading design onto the fpga.I use minicom to connect to the ml310 board. It does connect at 9600 8N1 parameters . I get the following prompt in the minicom window : Enter Desired System ACE CF Configuration <0-7>. 0: ACE-loader. 1: Linux w/PCI. 2: VxWorks w/PCI. 3: QNX Demo. 4: Linux EDK Base Build. 5: VxWorks EDK Base Build. 6: User Configuration A. 7: User Configuration B. select : But when I try to download the design from my XPS window it gives me error saying cable connection failed .It does not connect ot the board from the xps window? What could be the problem? Thanks, NiteshArticle: 88464
Marco, I did not read the entire post, but I can tell you that: (*) You have some latches in the design. (**) The instantiation you are looking is called BUFGP, but it includes IBUFG (clock pad) + BUFG (the actual clock buffer). using a general purpose I/O as clock is not good, since you will ge an error during the placement. Vladislav "Marco" <marcotoschi@nospam.it> wrote in message news:de215m$18n$1@news.ngi.it... > Hallo, > I have made a state machine. When I synthetize it, XST adds lots of BUFG > to states. > > My code: > > type state_type is ( seq_daq_state_1, seq_daq_state_2, seq_daq_state_3, > seq_daq_state_4, seq_daq_state_5, seq_daq_state_6, seq_daq_state_7, > seq_daq_state_8, seq_daq_state_9, seq_daq_state_10, seq_daq_state_11, > seq_daq_state_12, seq_daq_state_13, seq_daq_state_14, seq_daq_state_15, > seq_daq_state_16, seq_daq_state_17 ); > > signal seq_daq_state, seq_daq_next_state : state_type; > > > > Here the log: > > ---------------------------------------------+---------------------------------------+-------+ > > Clock Signal | Clock buffer(FF name) | Load | > > ---------------------------------------------+---------------------------------------+-------+ > > USER_LOGIC_I__n0065(USER_LOGIC_I__n00651:O) | > NONE(*)(USER_LOGIC_I_rx_data_received)| 1 | > > USER_LOGIC_I__n0064(USER_LOGIC_I__n00641:O) | > NONE(*)(USER_LOGIC_I_interrupt_0) | 1 | > > OPB_Clk | BUFGP | 237 | > > USER_LOGIC_I_Clk_Spi_I_prescaler_out:Q | BUFG | 7 | > > USER_LOGIC_I_tx_state_FFd2:Q | NONE | 1 | > > USER_LOGIC_I__n0062(USER_LOGIC_I__n00621:O) | > NONE(*)(USER_LOGIC_I_interrupt_1) | 1 | > > USER_LOGIC_I__n0221(USER_LOGIC_I__n0221183:O)| > NONE(*)(USER_LOGIC_I_Adc_Mux_0) | 3 | > > USER_LOGIC_I__n0060(USER_LOGIC_I__n00601:O) | > NONE(*)(USER_LOGIC_I_Spi_Ss_0) | 1 | > > USER_LOGIC_I__n0059(USER_LOGIC_I__n00591:O) | > NONE(*)(USER_LOGIC_I_interrupt_2) | 1 | > > USER_LOGIC_I__n0058(USER_LOGIC_I__n00581:O) | > NONE(*)(USER_LOGIC_I_Spi_Ss_1) | 2 | > > USER_LOGIC_I__n0057(USER_LOGIC_I__n00571:O) | > NONE(*)(USER_LOGIC_I_interrupt_3) | 1 | > > USER_LOGIC_I__n0056(USER_LOGIC_I__n00561:O) | > NONE(*)(USER_LOGIC_I_interrupt_4) | 1 | > > USER_LOGIC_I__n0055(USER_LOGIC_I__n00551:O) | > NONE(*)(USER_LOGIC_I_interrupt_5) | 1 | > > USER_LOGIC_I__n0054(USER_LOGIC_I__n00541:O) | > NONE(*)(USER_LOGIC_I_interrupt_6) | 1 | > > USER_LOGIC_I__n0053(USER_LOGIC_I__n00531:O) | > NONE(*)(USER_LOGIC_I_interrupt_7) | 1 | > > USER_LOGIC_I__n0052(USER_LOGIC_I__n00521:O) | > NONE(*)(USER_LOGIC_I_tx_shift_enable) | 1 | > > USER_LOGIC_I__n0051(USER_LOGIC_I__n00511:O) | > NONE(*)(USER_LOGIC_I_rx_shift_enable) | 1 | > > USER_LOGIC_I_seq_daq_state_FFd17:Q | BUFG | 16 | > > USER_LOGIC_I_seq_daq_state_FFd15:Q | BUFG | 16 | > > USER_LOGIC_I_seq_daq_state_FFd13:Q | BUFG | 16 | > > USER_LOGIC_I_seq_daq_state_FFd11:Q | NONE | 16 | > > USER_LOGIC_I_seq_daq_state_FFd9:Q | BUFG | 16 | > > USER_LOGIC_I_seq_daq_state_FFd7:Q | BUFG | 16 | > > USER_LOGIC_I_seq_daq_state_FFd5:Q | BUFG | 16 | > > USER_LOGIC_I_seq_daq_state_FFd3:Q | NONE | 16 | > > ---------------------------------------------+---------------------------------------+-------+ > > (*) These 14 clock signal(s) are generated by combinatorial logic, > > and XST is not able to identify which are the primary clock signals. > > Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) > generated by combinatorial logic. > > INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically > buffered by XST with BUFG/BUFR resources. Please use the buffer_type > constraint in order to insert these buffers to the clock signals to help > prevent skew problems. > > > > In this way my project is overmapped, because it uses 10 GCLK. > > In what way could I resolve this trouble? > > There is a way to substitute BUFG with IBUF, in example? > >Article: 88465
This is a very interesting statement. Other than www.opencores.org, try thinking about FPGA implementation of: (*) H.264 codec (**) Multi-Protocol Encalsulation of any data traffic + ATM SAR (***) Ethernet switch (data processing path) (****) Turbo Encoder / Decoder for Comm (*****) LDPC codes for Comm (******) Fast Filtering of Ethernet traffic (*******) !!!!!! TDM Over IP (Packet) Circuit Emulation Data Processing Engine (********) T1/E1/T3/E3/T4/E4/Packet over SONET mapper :):):) If you are really interested.... those are only samples of what could actually done. Vladislav "easystep2" <chanhanmate260@yahoo-dot-com.no-spam.invalid> wrote in message news:-fydnVSBw5z4b5_eRVn_vQ@giganews.com... > Hi friends, > > I am new to this forum...and found that you guys are really helpful to > each other with strong knowledge on FPGAs. So i thought to get your > help. So i would really appreciate you guys if you can help me.. > > I am a graduate student and going to start my MS final project in this > fall semester. My interest lies in FPGA-based designs. These can be > either in cosumer, broadcast, medical, automotive etc. > industries.... > > So i need your help to find an interesting, new project topic (for > FPGA-based design) for me on whicd i can do some research and make > some thing new... > > So i hope you guys would share your opinions.... > > thanks much >Article: 88466
Antti, Two things: (*) What's the story with 5 bucks? (**) I could not find this reply && so can someone explain what the hell is going here. This "someone" should be (Antti || Xilinx). Thanks Vladislav "Antti Lukats" <antti@openchip.org> wrote in message news:ddt6pp$rjq$01$1@news.t-online.com... > Hi all > > I am regret to inform you all that this the last time I either post or > reply to comp.arch.fpga newsgroup. This decision was triggered by an reply > from an Xilinx employee to one of my postings. If someone wants to look up > that posting then its around the sentence: "This may have been a > mistake" - I do understand that I may have understand the original > intentions of that posting and that sentence and the context wrong, but > that doesnt make any difference to my decision which is final. I will not > discuss this matter in public or make any comments on it. A small > explanation about the reasoning and background of my decision is available > but not for free and not for quoting or republishing by any media. > > http://shop.openchip.org/shop/product_info.php?cPath=28_29&products_id=36 > > Antti Lukats, posted to comp.arch.fpga at 1900PM on 16 August 2005 > > my final smile :) to all of you. > > >Article: 88467
"Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:zW3Ne.12509$7R.712644@news20.bellglobal.com... > Antti, > > Two things: > > (*) What's the story with 5 bucks? Antti has given a lot of good information to this group in the past, so I was tempted to spend the five bucks to find out. However, I decided to get a couple of tacos for lunch instead. > (**) I could not find this reply && so can someone explain what the hell > is going here. This "someone" should be (Antti || Xilinx). http://groups-beta.google.com/group/comp.arch.fpga/browse_frm/thread/ce4294513319e0a3/1f1c2f77eaefea10?lnk=st&q=%22this+may+have+been+a+mistake%22+group:comp.arch.fpga&rnum=1&hl=en#1f1c2f77eaefea10Article: 88468
I would not give him 5 bucks, I think he does not need it. But I would gladly invite him for a lunch with other FPGA people, on one condition, which is "no talk about FPGA design" :):):):) Vlladislav "Pete Fraser" <pfraser@covad.net> wrote in message news:11g9k40c899ia83@news.supernews.com... > > "Vladislav Muravin" <muravinv@advantech.ca> wrote in message > news:zW3Ne.12509$7R.712644@news20.bellglobal.com... >> Antti, >> >> Two things: >> >> (*) What's the story with 5 bucks? > > Antti has given a lot of good information to this group > in the past, so I was tempted to spend the five bucks > to find out. However, I decided to get a couple of tacos > for lunch instead. > >> (**) I could not find this reply && so can someone explain what the hell >> is going here. This "someone" should be (Antti || Xilinx). > > http://groups-beta.google.com/group/comp.arch.fpga/browse_frm/thread/ce4294513319e0a3/1f1c2f77eaefea10?lnk=st&q=%22this+may+have+been+a+mistake%22+group:comp.arch.fpga&rnum=1&hl=en#1f1c2f77eaefea10 >Article: 88469
You will need a JTAG cable such as the Parallel-IV or Platform USB cable to download the bit file from within EDK/XPS. In general, the uart cannot be used to download a bitstream. Paul Nitesh wrote: > > Hello, > I am using Xilinx EDK 7.1 and ml310 development board from Xilinx. I > have fedora core 2 OS on my PC. > > I have problem downloading design onto the fpga.I use minicom to > connect to the ml310 board. It does connect at 9600 8N1 parameters . I > get the following prompt in the minicom window : > > Enter Desired System ACE CF Configuration <0-7>. > 0: ACE-loader. > 1: Linux w/PCI. > 2: VxWorks w/PCI. > 3: QNX Demo. > 4: Linux EDK Base Build. > 5: VxWorks EDK Base Build. > 6: User Configuration A. > 7: User Configuration B. > > select : > > But when I try to download the design from my XPS window it gives me > error saying > cable connection failed .It does not connect ot the board from the xps > window? > What could be the problem? > > Thanks, > NiteshArticle: 88470
"Marco" <marcotoschi@nospam.it> wrote in message news:de27h9$39n$1@news.ngi.it... > > "Kolja Sulimma" <news@sulimma.de> wrote in message > news:430492a6$0$25879$9b4e6d93@newsread2.arcor-online.net... >> ADC_MUX is a transparent latch controlled by seq_daq_state. Therefore >> synthesis treats seq_daq_state as a clock signal. >> >> You need to either assign a value to ADC_MUX in all branches (including >> the case that seq_daq_state=seq_daq_state_4 and mux_channel(1)='1') or >> you to add an edge triggered DFF for ADC_MUX. >> >> Kolja Sulimma >> >> Marco schrieb: >> >>> when seq_daq_state_4 => >>> if ( mux_channel(1) = '1' ) then >>> Adc_Mux <= "001"; >>> end if; >>> >>> when seq_daq_state_5 => >>> > > I have modified every state where I verify if mux_channel is '0' or '1' > into the following: > > when seq_daq_state_4 => > Adc_Mux <= "001"; > > In this way Adc_Mux has a value set into all states, but XST adds BUFG to > signals in any case. > > What could I do? > > Marco > > I have found the trouble, not Adc_Mux, but the assignment of the registers: slv_reg1, slv_reg2, ... They are 8 registers of 16 bit datas. I should realize a demultiplexer, but in a better way than the actual. Any idea?Article: 88471
Hi Paul , I was able to correct the problem.I downloaded the windrv6 drivers from jungo.com and it worked. Thanks, NiteshArticle: 88472
Vlad, No secret, it was I who offended Antti. I have apologized to him personnally. I did not intend to slight him in any way. In fact, his comments have been, and continue to be, very valuable to Xilinx. I respect Antti, if and when he feels comfortable with posting again, or when he feels it may be useful to post, it will be up to him to decide. I can live with that. Everyone here has the right to post, or not to post, and if they post, to post what they will. It takes time and energy to post here, and some people get things done without the bother. For example, the largest source of email addresses for spam are harvested from newsgroups (unfortunately). I reserve my right to reply to postings as well. I also have the best email filtering imaginable (three levels), and our internet service provider is daily driven crazy by the number of spam emails they have to block for Peter and me. I never intended to insult or offend anyone. Austin Vladislav Muravin wrote: > Antti, > > Two things: > > (*) What's the story with 5 bucks? > (**) I could not find this reply && so can someone explain what the hell is > going here. This "someone" should be (Antti || Xilinx). > > Thanks > > Vladislav > > "Antti Lukats" <antti@openchip.org> wrote in message > news:ddt6pp$rjq$01$1@news.t-online.com... > >>Hi all >> >>I am regret to inform you all that this the last time I either post or >>reply to comp.arch.fpga newsgroup. This decision was triggered by an reply >>from an Xilinx employee to one of my postings. If someone wants to look up >>that posting then its around the sentence: "This may have been a >>mistake" - I do understand that I may have understand the original >>intentions of that posting and that sentence and the context wrong, but >>that doesnt make any difference to my decision which is final. I will not >>discuss this matter in public or make any comments on it. A small >>explanation about the reasoning and background of my decision is available >>but not for free and not for quoting or republishing by any media. >> >>http://shop.openchip.org/shop/product_info.php?cPath=28_29&products_id=36 >> >>Antti Lukats, posted to comp.arch.fpga at 1900PM on 16 August 2005 >> >>my final smile :) to all of you. >> >> >> > > >Article: 88473
On 17 Aug 2005 18:24:20 -0700, ScreamingFPGA@yahoo.com wrote: > The old Volvo 240's had a 'Bulb Failure Warning Light' on the >dashboard. But what about the case where that bulb failed? Oh no! >Infinite recursion... Obviously, for a logical design, if the BFWL fails, all the other lights come on. JohnArticle: 88474
fahadislam2002 wrote: > Hi... first thanks for responding........ 1- From time slicing u > mean slicing between rows and colums or between a fixed no of pixels > ? 2- I m using HM62256ALP-8 ... and its speed is 80ns :( ... For 640x480, scanline time is 31.77us. At 4 bits/pixel, you need to fetch 320 bytes in that time, which gives you ~100ns per byte. You'd also need to pre-fetch a scanline on-chip since the actual dot clock is around 25.175MHz (2 pixels = 79ns). But then your SRAM bandwidth utilisation is approaching 100%, which leaves no time for the CPU to update the video memory. I suppose it would be possible to output interleaved VGA, and use every other scanline to allow the CPU to update video RAM, but that has other design implications. Not ideal... :( Regards, Mark
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