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>yes, if you buy it from xilinx, you will get all of it. but if you buy >it from digilent, you will not get the evaluation software. im not sure >whether im getting the other parts like JTAG cable and power adaptor if >i buy it from digilent. I prefer to buy it from digilent, because i >want to have a better device with atleast 400K gates. Im not sure >whether the starter kit is available with a better device. I got my starter kit from Digilent because I wanted one of their other boards too. It came with wall wart and programming cable. I pulled the software of the net and didn't pay any attention to whatever they shipped. It's a great little board, especially at the price. One thing to keep in mind. There aren't many ground pins on the expansion connectors. Don't expect them to work if you need to flap lots of pins at high speed. Earlier you asked aboue the USB card. Usually, Digilent has lots of info for their boards available on their web. Not much available for this one. Or maybe I just didn't look in the right place. I'd call/email before depending on it. The blurb that is available has the Cypress chip number. Have you looked up the specs on that chip? Can it do what you want? Are you prepared to write code for it and/or will their code do what you need? I'd guess that the USB chip is programmed and/or wired so that it can download the FPGA over the USB cable if you plug it into the right connector, but it doesn't say that so maybe that's not what they did. (Seems like a neat thing to brag about so I'm assuming they would say so if they had it working.) Ah.. Here is the info I was expecting: http://www.digilentinc.com/products/Documentation.cfm Looks like they forgot the wrapper page from the page full of I/O cards. Yup, says you can download and talk to a PC. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 88626
Hello Guys,
I am working on some verfication of the SoC IP. To verify these IP we
are implementing it on FPGA.
I am facing an strange problem.
One of the IP which i have implemented as Master and slave AHB
interface. Since the AMBA interface
i am having is a multiplexed bus i need to multiplex the master and
slave interface signal. So to do that
i am using grant signal of AHB to multiplex common signal (of master
and slave). But the problem is in
slave mode (grant signal is zero), external HBURST[2:0]=000 (seen
through logic analyzer), i have tapped
the internal HBURST to test point, i observed that the tapped internal
signal value is different from the external HBURST.
Internally i am connecting the HBURST to slave HBURST port and to
multiplex HBURST i am using the below assign for master mode
assign SGNTi = HGRANT[2];
always @(posedge iHCLKBUF or negedge nSYSRST)
begin : p_MasterEnable
if (nSYSRST == 1'b0)
AHBMasterEnable <= 1'b0;
else
if (HREADY == 1'b1)
AHBMasterEnable <= SGNTi;
end
assign HBURST = (AHBMasterEnable == 1'b1) ? iHBURSTOut : 3'bzzz;
iHburstOut is signal which is driven by the Master interface of the IP.
I am not able to understand how does the HBURST signal tapped (test
point) changed to something other then the external HBURST (HGRANT=0)?
One more doubt:
Is there any problem in assign the incoming HBURST directly to test
point?
waiting for ur reply,
Thanks and regards
williams
Article: 88627Hello, I would to use a simple/easy way to send, in multicast address, some IP packets fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I don't want to use the PowerPC and its EMAC controller. I read that the PHY interface can be set in hardware register but I don't know if I can use the PHY interface as a simple FIFO. Is there someone who uses that way to send IP packets to a network. I know it is strange ... but I just want to read some IP paquets define into my FPGA. Best regards PhilippeArticle: 88628
I'll try that, thanks. It's really annoying, it's the final simulation for my thesis and now I get these problems, with only a week to go :)Article: 88629
In Xilinx application Note XAPP501, there are two phrase --- "configuring Xilinx FPGAs" and "programming CPLDs and PROMs" i am not a english-speaker, and cann't fully understand the difference of the two words "configuring" and "programming", anybody can explain that for me? thanks a lot!Article: 88630
On Wed, 24 Aug 2005 01:05:16 +0200, Sylvain Munaut <com.246tNt@tnt> wrote: >Mike Harrison wrote: > >> Footprint for a Panel Link LVDS transmitter to drive TFT LCD panels. >> These are available cheaply surplus, and great fun to play with, but the easy-to-drive >> ttl-interface ones are much harder to find than the now near-universal LVDS panels. >> (Data rate is probably too high to drive the LVDS directly from the FPGA) > >I'm not so sure it's too high. At least for medium sized panels. >Even if it's too high for "direct" implementation of the serializer, >I think I saw an application note at Xilinx where they used the DDR >registers in the IOB so that the internal serializer logic only runned >at half the serial clock speed. > >I wish I had some hw to test that ;) > ..but for a dev/prototyping system, the interfaces need to be not unduly hard to use. From a starting point of never having done anything on an FPGA, and never having written a line of VHDL, I got a TTL-input TFT panel displaying stuff in a day. I doubt I could have got an LVDS interface going anything like that quickly! A Panel link chip means you just need to provide a clock at a sensible rate (40-70MHz), 3 sync signals and parallel RGB data. It's also much more portable than doing low-level fiddling with IOBs. It also means you don't need to have a scope that can see the LVDS high-frequency signals as you can talk to the panel link chip as if it was a ttl-style panel.Article: 88631
On 23 Aug 2005 21:27:35 -0700, "CMOS" <manusha@millenniumit.com> wrote: >is there a difference in buying spartan 3 starter board through >digilent or xilinx? Xilinx are bundling a trial version of EDK - doesn't say anything about software on the Digilent page.Article: 88632
Mike Harrison wrote: > On Wed, 24 Aug 2005 01:05:16 +0200, Sylvain Munaut <com.246tNt@tnt> wrote: > > >>Mike Harrison wrote: >> >> >>>Footprint for a Panel Link LVDS transmitter to drive TFT LCD panels. >>>These are available cheaply surplus, and great fun to play with, but the easy-to-drive >>>ttl-interface ones are much harder to find than the now near-universal LVDS panels. >>>(Data rate is probably too high to drive the LVDS directly from the FPGA) >> >>I'm not so sure it's too high. At least for medium sized panels. >>Even if it's too high for "direct" implementation of the serializer, >>I think I saw an application note at Xilinx where they used the DDR >>registers in the IOB so that the internal serializer logic only runned >>at half the serial clock speed. >> >>I wish I had some hw to test that ;) >> > > > ..but for a dev/prototyping system, the interfaces need to be not unduly hard to use. > From a starting point of never having done anything on an FPGA, and never having written a line of > VHDL, I got a TTL-input TFT panel displaying stuff in a day. I doubt I could have got an LVDS > interface going anything like that quickly! > > A Panel link chip means you just need to provide a clock at a sensible rate (40-70MHz), 3 sync > signals and parallel RGB data. It's also much more portable than doing low-level fiddling with IOBs. > > It also means you don't need to have a scope that can see the LVDS high-frequency signals as you can > talk to the panel link chip as if it was a ttl-style panel. > Sure, for a dev board that might not be the easiest way, but if you're trying to do something compact, that may save some board estate. Plus it's not _that_ harder if in the board package comes the serializer VHDL code. Then as input you have the exact same input as your ttl panel and as output, the iobs ;). The disavantage is that one of your bank has to be 2.5V. and you only use a few signal from that bank. SylvainArticle: 88633
Hello, I am working with a spartan 2 and a PROM XCF01S. Impact software does not recognized the chain of this two components, whereas I have the same schematic than in the datasheet. Could somebody help me ?Article: 88634
I can't believe it, but it actually works! yay! Thank you all very much for your help!Article: 88635
Perhaps "configuring" means after "configuring" data can be lost after power down, programming means NOT.Article: 88636
For analog video input ADV7402A is the best choice with it's RGB digital output ports..Article: 88637
"echoisme" <ghy@eyou.com> wrote in message news:1124873209.675446.63180@g44g2000cwa.googlegroups.com... > In Xilinx application Note XAPP501, there are two phrase --- > "configuring Xilinx FPGAs" and "programming CPLDs and PROMs" > i am not a english-speaker, and cann't fully understand the difference > of the two words "configuring" and "programming", > anybody can explain that for me? thanks a lot! > The main difference between the words is the spelling! In this context they mean the same thing, i.e. loading a bitstream into a device. The writer may be trying to convey some difference between a volatile configuration memory device and a non-volatile one. I would suggest "configuring" is the better choice for both sets of devices. To most engineers, "Programming" can also mean the act of writing code that is subsequently to be compiled into a bitstream, cf. "Computer programming". The problem with English is that it has too many words. Inevitably some of them have to mean nearly the same thing. Good for English poetry, bad for English students! Cheers, Syms. p.s. Rather than "echoisme" I would choose "iamecho". ;-)Article: 88638
pho wrote: > Hello, > I would to use a simple/easy way to send, in multicast address, some IP > packets > fprm a FPGA Xilinx VIRTEX4 to a Ethernet network. But I don't want to > use the > PowerPC and its EMAC controller. I read that the PHY interface can be > set in hardware register but I don't know if I can use the PHY > interface as a simple > FIFO. > Is there someone who uses that way to send IP packets to a network. > I know it is strange ... but I just want to read some IP paquets define > into my FPGA. Howdy Philippe, Yes, it is pretty simple to compose a packet of your choice and have the FPGA feed it to a phy (either an internal phy to the FPGA or an external xMII-type phy). phy's have simple FIFO interfaces with a small amount of extra signalling to indicate SOP, EOP, and idle times. A V2Pro works as well as a V4 for this type of thing. The easiest way would be to have a BRAM initialized with the packet that you want to send. When given a go signal by software, a counter can be kicked off to automaticly read the contents of the BRAM, feeding each byte to the phy. And since BRAM's are dual-port, the next step would be to allow read/write access to that packet in real time - allowing the destination address (or any other byte in the packet) to be modified on the fly. Be sure your counter stops reading at the end of the BRAM and doesn't wrap around to zero, continously flooding your local network with packets (hopefully that isn't your goal to begin with). MarcArticle: 88639
When DCM gets proper input clock, LOCKED signal is asserted and it works fine. It behaves correctly when the input clock changes are too wide to maintain the lock: in this situation LOCKED signal gets de-asserted. BUT in the situation when the input clock stops LOCKED signal is not de-asserted and stay asserted. My question is: does LOCKED signal in Spartan3 DCM require any clock at the input to be de-asserted? All comments are welcome, Regards WojtekArticle: 88640
apsolar@rediffmail.com wrote:
> Hi Guys
> I was able to implement Genetic algorithms on software.
> Now I am taking my project to the next level by simulating hardware
> like logic gates (AND,OR,NOT) as classes in software.
> Then I can create objects of these classes and evolve a circuit with
> the help of these gates. Maybe evolve a NAND gate. I think it is
> feasible but I would like your suggestions on this idea.
> Your suggestions did help me completing the previous software to solve
> an equation genetically.
> I was just wondering how should I represent a circuit in the form of a
> chromosome('010011010' or 'A!B&|C').Mutation is the next process and
> what could possibly be a fitness function.
>
> Ankit Parikh
> Manukau Institute of Technology
Expressing gates AND OR NOT is the easy part. You need to decide
whether you want the interconnect to be defined such that an
arbitrary sequence results in a single function of inputs or
if it can express multiple disjoint functions. For the second
case what if you add a fourth "gate" type of BUF or unary pass-
through. Then in a sequence where you have unary NOT and BUF
and two-input AND and OR, each instance of NOT or BUF indicates
an input to the function. Each AND or OR would take its inputs
from the two nearest preceding function outputs. If more than
two instances occur without AND or OR, there would be a "break"
and a new function would start. For example:
NOT BUF AND NOT NOT OR BUF AND
would encode in1 & !in2 .break. (!in3 | !in4) & in5
however adding another AND or OR at the end of this sequence
would then combine the two functions:
NOT BUF AND NOT NOT OR BUF AND AND
would encode (in1 & !in2) & ((!in3 | !in4) & in5)
This seems simple enough, except that as your sequence grows
you build functions of more and more inputs, and you need a
way to encode re-use of existing inputs (e.g. mapping in4
of the above equation to in2). Perhaps someone can come up
with an interesting way to do this...
Regards,
Gabor
Article: 88641Hi, i'm trying to start Xilinx fpga_editor on my Debian/Sarge machine. It shows the program window for some milliseconds. After that, the windows disappears and nothing happens any more. Until now, i found out that this problem exists in fvwm (my default window-manger) but not in KDE (same machine, same login-manager). Do you have any suggestions what i could do, to run fpga_editor with fvwm? Currently I use ISE 7.1.02i but ISE 6.3 did have the same problems. best regards Felix -- "Let's face it. The FPGA companies are really software companies that happen to have very expensive dongles" Ray Andraka in comp.arch.fpgaArticle: 88642
John, I need those multiplexers to multiplex the coefficients h[0] through h[63] to each MAC b input. There are 64 complex MACs, so I need 64x2=128, 64 to 1 multiplexers for the complex 'b' input. There are two 64 to 1 multiplexers to multiplex the complex accumulator outputs s[0] through s[63] to the output y. Here is how the timing goes for first two samples: __@ t = 0__ b[0] <= h[0] y[0] = x[0]h[0] b[1] <= h[1] x[0]h[1] . . . b[63] <= h[63] x[0]h[63] __@ t = 1__ b[0] <= h[63] x[1]h[63] b[1] <= h[0] y[1] = x[1]h[0]+x[0]h[1] . . . b[63] <= h[62] x[1]h[62] So, I have a counter for each multiplexer that controls which MAC gets which filter coefficient. Is there another way I can do this with less hardware, but 100% throughput? Andrew, Originally I had looked at DA FIRs, but we can't really use a multi-cycle approach. The sample rate for this real time system is 215 MSPS in the front end. We'll also end up interpolating later... We have FIFOs, but I'm worried that they will fill up quickly, especially since I'm not sure we'll be able to clock the FPGAs at 215 MHz. Thanks, -BrandonArticle: 88643
"Wojtek2U" <wojtek2u@wp.pl> wrote in message news:dehrgo$2nl$1@nemesis.news.tpi.pl... > When DCM gets proper input clock, LOCKED signal is asserted and it works > fine. It behaves correctly when the input clock changes are too wide to > maintain the lock: in this situation LOCKED signal gets de-asserted. BUT > in the situation when the input clock stops LOCKED signal is not > de-asserted and stay asserted. > My question is: does LOCKED signal in Spartan3 DCM require any clock at > the input to be de-asserted? > Hi Wojtek, If you read the user guide, you'll find that the LOCKED signal does need a clock. Maybe signal STATUS(1) is what you need, 'CLKIN stopped'. Again, you'll need to read the user guide to find this out! Cheers, Syms. p.s. Have you read the user guide? ;-)Article: 88644
Andrew Greensted wrote: > I'm trying to persuade xilinx ISE to display on a remote machine. > I've got X11 forwarding over SSH working fine. but for some reason the > project navigator just will not display. After installing the latest Solaris Patch Cluster, I've been able to resolve this. Be warned though, one of the Solaris Patches breaks X11 Forwarding. You need to disable the IPv6 stuff to get it to work again. There's some info here: http://supportforum.sun.com/salerts/index.php?t=msg&th=864&start=0&rid=0 Hope this helps someone. Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 88645
"Wojtek2U" <wojtek2u@wp.pl> wrote in message news:dehrgo$2nl$1@nemesis.news.tpi.pl... > When DCM gets proper input clock, LOCKED signal is asserted and it works > fine. It behaves correctly when the input clock changes are too wide to > maintain the lock: in this situation LOCKED signal gets de-asserted. BUT in > the situation when the input clock stops LOCKED signal is not de-asserted > and stay asserted. > My question is: does LOCKED signal in Spartan3 DCM require any clock at the > input to be de-asserted? > > All comments are welcome, > Regards > Wojtek Hi, Assuming that the DCM is basically the same as the one in a Virtex-2, it does need a clock signal. It's logic if you think about it: the DCM is clocked by it's input clock to make it work, so to change an output flipflop, you will need clock transitions. If you have another clock in your design, you can easily build a small circuit that will monitor the presence of your input clock to reset the DCM when it stops. If you don't have another clock, you might build a self oscilating circuit in your fpga (see other threads in this group). Of course, you may have other options, depending on your environment (software, cable inserted signal, an external clock monitoring device, ...). Regards, Alvin Andries.Article: 88646
John, I had a look at the Broaddown2 module, and one item I couldn't see was a user Flash device - although the platform flash can be used for user data it's sometimes convenient to have a physically seperate flash, and these days you can get some large storage, physically tiny SPI devices. Also as an asside, I was interested to see your note on the US & UK export regulations - can you expand any details on that? Top Secret pinout on the edge connectors :-) or regulations on the FPGA? Regards, Chris John Adair (removethisthenleavejea@replacewithcompanyname.co.uk) wrote: : Representing a manufacturer of development boards I am going offer you all : the chance to have your say on what is goes into our new product : Raggedstone1 and it's supporting modules. : What I can tell is that the board is very cheap and takes what we think are : some of the best attributes of the our existing Broaddown2 and MINI-CAN : products. Like them it is also a Spartan-3 board (why another! - well you : just have to wait and see when we start revealing features in about 4 weeks : time). We have also included ideas based on existing customer feedback on : the Broaddown2 and MINI-CAN products. : We are now in the last week of layout and have found some small areas of : board space that we might stick something on. So do your worst and suggest : (politely please) what we might give you in features. Even if your idea is : too big, or expensive, for Raggedstone1 itself then it may make our add-on : module list or even the next higher end Broaddown3/4 product launches. : John Adair : Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development : Board. : http://www.enterpoint.co.uk :Article: 88647
I'm working on an fpga program to write to hard drives and so far I've been pretty successful with the exception of a drive in the class I want to use. The project involves high speed data storage upwards of 30-40 MB/s per drive. Currently I have PIO transfer working on 3 out of 4 drives. An old 730mb (ata2 compatible I think), a 4.3gb (ata 3 compatible), a 6.4gb (ata 5 compatible), and a newer WD 80gb (ata 6 compatible). Problem is all the drives will recieve the data when I check sectors except the 80gb drive. Does anyone know if this is because the drive might be starting up in a udma mode and not accepting PIO commands? Only the DIOR, DIOW, CS, DA, and lower 8 bits are connected to the fpga - so could the 80gb be looking for another single or something? Any ideas? Thank you, KeithArticle: 88648
Think of the cost table as simply a random seed for the placement algorithm. I am not sure if this is still the case, but as of 2-3 years ago, placement was not timing driven, and was a somewhat stochastic process. Routing has always been timing driven. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado Based Xilinx Consultant email : jretta@rtc-inc.com web : www.rtc-inc.com <huangjielg@gmail.com> wrote in message news:1124793870.960302.79760@g14g2000cwa.googlegroups.com... > What about Xilinx place and route cost table mean ? > Or someone can give any information not just a number ? > Thank you! >Article: 88649
zoinks@mytrashmail.com wrote: > I just generated a design with XPS, using edk 6.3i. > It had a DDR controller, and a bus speed 4x lower than the 100Mhz CPU. > > The problem is, when I try to simulate this design, nothing happens, > since the second DCM in the chain does not generate ANY output signals. > I cannot find any cause of this. I didn't modify any of the settings, I > just generated and then went straigt to simulation in modelsim. > > The chain is as follows: > > DCM1 : clk divider, from 100 to 25 mhz > DCM2 : clk shifter, generates shifted signals <= DOES NOT WORK > DCM3 : DDR feedback shifter (uses external feedback loop) > Assuming that the clk shifter is getting clkin from the divider (which would be normal), then you should take the locked signal from the clock divider, invert it, and use that to reset the clk shifter. The result is that the clock shifter is held in reset until the divider has locked.
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