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Antti Lukats wrote:
> "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
> news:d8jrvf$7nv$00$1@news.t-online.com...
>
>>A small Quiz, for C programmers
>>
>>****** c code starts here *****
>> temp = docrc(temp2);
>> xil_printf("CRC: %08X\r",temp);
>> temp = docrc(temp2+1);
>> xil_printf("CRC: %08X\r",temp);
>>
>>xil_printf("\r\n-- 1");
>> temp = docrc(temp2);
>> xil_printf("CRC: %08X\r",temp);
>>xil_printf("\r\n-- 2");
>> temp = docrc(temp2+1);
>> xil_printf("CRC: %08X\r",temp);
>>xil_printf("\r\n-- 3");
>>
>>****** c code ends here *****
>>
>>the above c program should print "CRC: " how many times?
>>did you guess 4?
>>
>>wrong! Correct answer is 3 if the code is compiled with microblaze GCC
>>provided by Xilinx, here is the terminal log:
It prints 4 but you see 3 ;)
\r on the serial line acts are "return to begin of line", without
starting a new line. The other 4 works because there is a \n in the
intermediate printf with the numbers.
Sylvain
Article: 85651"Antti Lukats" <antti@openchip.org> wrote in message news:d8e4o5$hnc$03$1@news.t-online.com... > "MK" <nospam.please@here.ever> schrieb im Newsbeitrag > news:d8ccr7$hg9$1$8300dec7@news.demon.co.uk... >> >> "Mike Harrison" <mike@whitewing.co.uk> wrote in message >> news:cenia1pc7q3ptsc4rrhts8phl8085g2smh@4ax.com... >> > Wondering if anyone else has experienced this.... >> > After the recent X-Fest seminar in Cambridge UK, I ordered the Memex > FPGA >> Design Starter kit on the >> > x-fest special offer, as it was a cheap way to get the BaseX software. >> > I'm now told that the kit won't be shipped til mid-August. I have no >> problem with that as I don't >> > need the hardware immediately & already have the S3 starter kit.. >> > >> > However when I contacted Memec to ask if they could ship the software >> immediately (which >> > Incidentally they charged my card for 2 weeks ago), they claimed that > this >> wasn't possible, and when >> > I pressed them they said they'd ask Xilinx but were fairly sure they >> wouldn't do it. >> > >> > I'm sure I'm not the only one who ordered this offer as it was a very > good >> deal compared to the >> > normal price - has anyone else had any joy getting the software out of >> them ahead of the hardware ? >> > >> > Seems like a pretty daft situation..... >> >> >> Hi Mike, >> >> I haven't ordered mine yet (still in shock at the 8-10 weeks delivery). > I'm >> fairly horrified that they charged your card before they had the stuff to >> send. >> >> I'm going to copy this to the Xilinx Apps manager and see what happens. >> >> On past experience (are you there Xilinx !!) it won't be much - I'm still >> waiting for price and delivery from Memec re S3E parts from an enquiry I >> made on 20th May. >> >> Michael Kellett >> > > It was VERY surprising to see Memect to offer S3E kits, but all their > leaflets with pictures of the S3E kits where made with 'blurred' image of > the Xilinx S3E chips so it was quite clear the photos where FAKED, eg they > did use dummy packages for photo shooting. So for me it was also clear > that > there is no hope to expect actual deliveries before late august/september. > business as usual (for Memec) announce, charge and let customer to wait > for > 6+ months. > > If I would have any trust that Memec can deliver (orderdable products from > their web shop) I would have ordered the S3E kit rigth away, but knowing > the > past I did not bother. > > Antti It'll be interesting to see when xilinx/digilentinc start shipping the S3e starter kit, supposedly july . A place holder has been added for it in the xilinx online store <http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=PURCHASE&sSecondaryNavPick=Services&category=-1211456&iLanguageID=1&category=/Xilinx+Products/Design+Resources/Design+Starter+Kits/Spartan+3E+Starter+Kit> Has anyone else seen the announcement that avnet have bought memec from about a month ago ? http://circuitsassembly.com/cms/content/view/1442/94/ AlexArticle: 85652
"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42ad76f8$0$24317$ba620e4c@news.skynet.be...
> Antti Lukats wrote:
> > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
> > news:d8jrvf$7nv$00$1@news.t-online.com...
> >
> >>A small Quiz, for C programmers
> >>
> >>****** c code starts here *****
> >> temp = docrc(temp2);
> >> xil_printf("CRC: %08X\r",temp);
> >> temp = docrc(temp2+1);
> >> xil_printf("CRC: %08X\r",temp);
> >>
> >>xil_printf("\r\n-- 1");
> >> temp = docrc(temp2);
> >> xil_printf("CRC: %08X\r",temp);
> >>xil_printf("\r\n-- 2");
> >> temp = docrc(temp2+1);
> >> xil_printf("CRC: %08X\r",temp);
> >>xil_printf("\r\n-- 3");
> >>
> >>****** c code ends here *****
> >>
> >>the above c program should print "CRC: " how many times?
> >>did you guess 4?
> >>
> >>wrong! Correct answer is 3 if the code is compiled with microblaze GCC
> >>provided by Xilinx, here is the terminal log:
>
> It prints 4 but you see 3 ;)
> \r on the serial line acts are "return to begin of line", without
> starting a new line. The other 4 works because there is a \n in the
> intermediate printf with the numbers.
>
>
> Sylvain
gosh thanks!
this time you are right silly me, but the other case was true well it was
with EDK 3.2 back looong time ago.
ah possible I need some rest being working too hard
antti
Article: 85653"Alex Gibson" <news@alxx.net> schrieb im Newsbeitrag news:3h5bu3FfaeqvU1@individual.net... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:d8e4o5$hnc$03$1@news.t-online.com... > > "MK" <nospam.please@here.ever> schrieb im Newsbeitrag > > news:d8ccr7$hg9$1$8300dec7@news.demon.co.uk... > >> > >> "Mike Harrison" <mike@whitewing.co.uk> wrote in message > >> news:cenia1pc7q3ptsc4rrhts8phl8085g2smh@4ax.com... > >> > Wondering if anyone else has experienced this.... > >> > After the recent X-Fest seminar in Cambridge UK, I ordered the Memex > > FPGA > >> Design Starter kit on the > >> > x-fest special offer, as it was a cheap way to get the BaseX software. > >> > I'm now told that the kit won't be shipped til mid-August. I have no > >> problem with that as I don't > >> > need the hardware immediately & already have the S3 starter kit.. > >> > > >> > However when I contacted Memec to ask if they could ship the software > >> immediately (which > >> > Incidentally they charged my card for 2 weeks ago), they claimed that > > this > >> wasn't possible, and when > >> > I pressed them they said they'd ask Xilinx but were fairly sure they > >> wouldn't do it. > >> > > >> > I'm sure I'm not the only one who ordered this offer as it was a very > > good > >> deal compared to the > >> > normal price - has anyone else had any joy getting the software out of > >> them ahead of the hardware ? > >> > > >> > Seems like a pretty daft situation..... > >> > >> > >> Hi Mike, > >> > >> I haven't ordered mine yet (still in shock at the 8-10 weeks delivery). > > I'm > >> fairly horrified that they charged your card before they had the stuff to > >> send. > >> > >> I'm going to copy this to the Xilinx Apps manager and see what happens. > >> > >> On past experience (are you there Xilinx !!) it won't be much - I'm still > >> waiting for price and delivery from Memec re S3E parts from an enquiry I > >> made on 20th May. > >> > >> Michael Kellett > >> > > > > It was VERY surprising to see Memect to offer S3E kits, but all their > > leaflets with pictures of the S3E kits where made with 'blurred' image of > > the Xilinx S3E chips so it was quite clear the photos where FAKED, eg they > > did use dummy packages for photo shooting. So for me it was also clear > > that > > there is no hope to expect actual deliveries before late august/september. > > business as usual (for Memec) announce, charge and let customer to wait > > for > > 6+ months. > > > > If I would have any trust that Memec can deliver (orderdable products from > > their web shop) I would have ordered the S3E kit rigth away, but knowing > > the > > past I did not bother. > > > > Antti > > It'll be interesting to see when xilinx/digilentinc start shipping > the S3e starter kit, supposedly july . > > A place holder has been added for it in the xilinx online store > <http://www.xilinx.com/xlnx/xebiz/productview.jsp?sGlobalNavPick=PURCHASE&sS econdaryNavPick=Services&category=-1211456&iLanguageID=1&category=/Xilinx+Pr oducts/Design+Resources/Design+Starter+Kits/Spartan+3E+Starter+Kit> > > Has anyone else seen the announcement that avnet have bought memec > from about a month ago ? > http://circuitsassembly.com/cms/content/view/1442/94/ > WAUUUU THATS NEWS !!!! AnttiArticle: 85654
rod.beresford@gmail.com wrote:
>Hi,
>
>We're considering using the Xilinx Spartan FPGA series. We plan to use
>the free Web ISE tools for doing our verilog synthesis, place and route
>and simulation. I have several questions about this. I'm assuming that
>synthesis and pnr are well taken care off by the Web ISE. However, I
>noticed simulation might have to be done using ModelSim and rather than
>being free it is provided only with time limited licensing. Are there
>alternatives to ModelSim? We used to use Cadence's ncsim but we will
>not have funding to use it anymore. We were using verilog and C
>testbenches through PLI to get coverage in our simulations. I'd like to
>hear about what other people and teams have experienced in this area.
>This work is not-for-profit.
>
>Thanks,
>R. Beresford
>
>
>
I use Aldec's Active HDL, I find it more ergonomic than modelsim, and it
has a very nice design entry suite as well. The editor is emacs-like,
but also has the ability to copy and paste VHDL declarations and both
VHDL and Verilog instantiations of any of the library components as well
as any of your own components that have been compiled. It also has a
block diagram viewer/editor, matlab co-simulation and combined
verilog/vhdl/edif simulation. I highly recommend this product if you
are looking for an alternative to modelsim. I think you'll be very
happy with what you see if you check it out.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85655
Marco wrote:
> There is someone who could tell me about a state machine to read/write into
> ram with chip enable and write enable in VHDL?
Drive the ram address bus with a counter.
Some MSBs to the ram address bus
and some LSBs to the enables.
-- Mike Treseler
Article: 85656You first have to decide how many differnt states you need, how many outputs you need, and how many control inputs that cause conditional jumps. Here is a very simple design that folds everything into one BlockRAM The BlockRAM (really a ROM) is configured as 1k addresses and 18 output bits. Connect 6 of the outputs back to the address inputs. They perform the counting=stepping function for 64 states.. That leaves you 4 control inputs, and gives you 12 freely assignable outputs. So you have a 64-state state machine with four control inputs and 12 outputs beyond the 6 counter outputs. And it runs at BlockRAM speed, up to 500 MHz. Many variation are possible, like more states with fewer control inputs, or vice versa. Peter Alfke, Xilinx ApplicationsArticle: 85657
AFAIK, the device in the FPGAFLASH APP was a 9572 or thereabouts. It was not specific. I've some doubts about that, since it didn't seem to have enough data to ensure there were sufficient pins available with which to parallel-program the FLASH in question. The use of SPI flash raises some question as to wherether (a) there are any SPI devices large enough to be of use for programming medium-sized FPGA's, e.g. Spartan3's in the range up to 1Mgates, and (2) whether there's a really convenient way to program the SPI flash. I've not yet studied out the details, but I do like the fact that this approach doesn't require the serial port levels. Goodness knows that current generation FPGA's already require enough power supplies. thanks for your comment. DickArticle: 85658
"Austin Franklin" <austin@dark99room.com> schrieb im Newsbeitrag news:nn3re.2140$eL5.1905@fe04.lga... > Hi Falk, > > > Recently, I had a design, not really a big deal. Running at 36 and 72 MHz. > > XST was not able to squeeze it into a XC2S50E, but Synplify was. (~1600 > LUTs > > to ~ 1200 LUTs). Speed was not the problem, both implementation where fast > > enough. But Synplify was more area efficient. > > Interesting. What versions of the tools were you running? I'll check the > area use on the current designs I have and see how they compare. XST 6.2 (Service Pack 3 AFAIK) SynplifyPRO (Demo licence) 7.1 AFAIK. Regards FalkArticle: 85659
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:oibka1p30g1hs69add4jamu01mi9pc8de2@4ax.com... > On Fri, 10 Jun 2005 22:04:01 +0200, "Falk Brunner" > <Falk.Brunner@gmx.de> wrote: > > I do stuff with jitters in the > low single digits of ps, and use microstrip traces referenced to power > planes all the time. > Single ended? Cheers, Syms.Article: 85660
what about this error? --------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please consult the Answers Database and other online resources at <http://support.xilinx.com> ERROR: XST failed Process "Synthesize" did not complete. xilinx.support and google gave nothing... what step should I follow to solve this one???? thanks for help!Article: 85661
"john wo" <john.wo.71@gmail.com> schrieb im Newsbeitrag news:ee8ef27.-1@webx.sUN8CHnE... > what about this error? > > --------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please consult the Answers Database and other online resources at <http://support.xilinx.com> ERROR: XST failed Process "Synthesize" did not complete. > > xilinx.support and google gave nothing... what step should I follow to solve this one???? > > thanks for help! you need to open a WebCase, and wait for their response. nothing more you can do, its a fatal error. AnttiArticle: 85662
xilinx internal software error. nothing you can do, just call Xilinx and hope for the best... but sometimes you can have a temporary "work-around", like disabling flattening hierarchy or timing-driven packing, etc... until a new SP comes out Vladislav "john wo" <john.wo.71@gmail.com> wrote in message news:ee8ef27.-1@webx.sUN8CHnE... > what about this error? > > --------------------------------- > INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please > consult the Answers Database and other online resources at > <http://support.xilinx.com> ERROR: XST failed Process "Synthesize" did not > complete. > > xilinx.support and google gave nothing... what step should I follow to > solve this one???? > > thanks for help!Article: 85663
Paul Hartke <phartke@Stanford.EDU> writes: > http://www.menie.org/georges/embedded/#xmodem Thanks, seems like exactly what I'm looking for. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 85664
I would also like to recommend the following application note. It covers many of these details. Although it's written for Spartan-3-3E, it applies equally well to Virtex-II and Virtex-II Pro. XAPP463: Using Block RAM in Spartan-3 Generation FPGAs http://www.xilinx.com/bvdocs/appnotes/xapp463.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3h2emnFems79U1@individual.net... > > > And if I want two 8k ram in one 18k ram, how to declear this situation? > > 8k and 18k isnt a clean statement. How wide shall the RAMs be? 1 bit? 32 > Bit? > You can use CoreGen to get a full configured macro, fit to your settings. Or > you can use the templates from the VHDL template wizard and wire them up on > your own. > > > And can nine 2k or four 4k ram in one 18k ram be access at the same > > time? > > ??? > There are multiple RAM block inside the FPGA. every block can be accessed > individually. Even more, since they are true dual ported, you can access > each port on every BlockRAM individually. > > Regards > Falk > > >Article: 85665
"Michael Dreschmann" <michaeldre@gmx.de> wrote in message news:42acde49.49762154@news.rhein-zeitung.de... > Hello, > > I came in contact with FPGAs at the university and have done some > designs. Now I decided to start with FPGAs in private because I'm > really fascinated by their capabilities. > I think designing a PCB for an FPGA is not simple so I decided to buy > a board for my first (home) steps, but I've some requirement to that > board, because flashing LEDs isn't really interesting... :) > > It should be a Spartan3 1000 or above with a bootflash for a stand > alone powerup and maaaany free pins to connect a lot of things. > Things like clock oscillator and power supply are included on any > board I think. > The next point is external RAM. I'd like testing microblaze with uC > linux but I never worked with linux, especially not with the uC > version so I don't know how much external RAM is neccessary. > Any suggestions? > I've searched the web and only found a single board that has most of > my requirements and can be paid by a student: > http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_27&products_id=63 > Sorry, can't find the page in english. It has a Spartan3 1000 with > Xilinx Plattform-Flash XCF04 and USB 2.0 transceiver. The only point > I'm missing is the external RAM. > So my question is, do you have any alterntive boards in mind that fits > my requirements and can be paid? What do you think by the board above? > Is it ok? > > Thanks, > Michael The XESS XSA-3S1000 board might be another alternative. It has 32Mbytes of external SDRAM. http://www.xess.com/prod035.php3 --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs E-mail: steve.knapp@xilinx.com --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 85666
Austin Franklin (austin@dark99room.com) wrote: : I have not use XST, but it is becoming more attractive. I have been using : Synplify for many years now, and it works pretty well. XST has come a long : way, especially now that it appears to have an RTL viewer as well as a : "implementation" (gate level) viewer, which are two features I liked about <snip> Austin, The only area where I have any experience of Symplify is looking at autogenerated RTL schematics, and unlike my experience with ISE 6.1.xi they are correct - ISE 6.1 often misses out entire busses etc that actually exist (First time I found that I wasted half an hour thinking that synthesis was optimisng the bus away for some reason.) when displaying RTL schematics. Also the visual presentation of the Symplify RTL schematics far suparsed that of the Xilinx tools, but then ECS (The schemtic capture/viewer tool in the Xilins ISE package(s)) is pretty grotty. (I'm being polite here) Maybe things have got better with ISE 7.1.xi? hth, cdsArticle: 85667
praveen.kantharajapura@gmail.com wrote:
> Hi Gabor ,
>
> Thanks for the reply. My EEPROM is write protected i will only be
> reading the first 128 bytes, is this flow diagram all right.
>
>
> 1-bit 8-bits 1-bit
>
> Start from master --->> EEPROM Slave address("10100001") -->> ACK
> from eeprom --->>
Actually you need to start with write address "10100000" in order
to write the address register (you don't need to write the EEPROM
array so write protect doesn't matter).
>
>
> 8-bits 1-bit
> Write register address "00000000" --->> ACk from EEPROM
Right here you need to switch to read mode. There are two
ways to do this. Either master sends Stop followed by Start
or master sends repeated start. If you intend to reuse this
code for other peripherals besides EEPROM, you'll find the
repeated start is compatible with more chips.
Then you need to provide slave address "10100001" for read
and get ack from slave then:
> 8-bits 1-bit
> --->> Data[0]
> from EEPROM --->> ACK from master
>
> 8-bits 1-bit
>
> ................. --->>Data[127] from EEPROM --->> STOP from master
>
> I will generate the STOP condition after receiving 128 bytes.
>
> Any comments on this.
>
>
> Regards,
> Praveen
>
>
Also you talk about "bits" when you send start and stop. These
conditions
do not toggle the SCL line so they are not usually counted as "bits"
as would be data or Ack cycles.
Regards,
Gabor
Article: 85668Hi, I have a Verilog processing core. I want to implement it on Vertex2Pro device as a separate core , adding it to current bus architecture. I know that VHDL cores can be added. Is it possible to add Verilog cores? Thanks for the reply. Regards SPSArticle: 85669
Another point, if you haven't read the I2C specification yet it is available at: http://www.standardics.philips.com/products/collateral/i2c/pdf/spec-i2cbus21.pdf It contains some good figures to illustrate the bus protocol. Also this ap note: http://www.standardics.philips.com/support/appnotes/i2c/pdf/an168.pdf has a useful table of assigned addresses and some more timing diagrams. Links to more literature appear on this page: http://www.standardics.philips.com/products/collateral/i2c/ Gabor wrote: > > Regards, > GaborArticle: 85670
I am also looking for a cpld (at least 128 macrocell with 100 user i\o) board with two seperated 128kx8 srams. (min) seperated address and data buses. If you have seen this please reply the entry cheers,Article: 85671
New version of Xilinx ISE Foundation (7.1i) supports mixed design architectectures. So If you have one part of design in VHDL and other parts in Verilog you can it compile. Regards, AmirArticle: 85672
Hi C.D., I have Synplify 8.1, and have been using Synplify for many years. I just loaded the latest 7.1 ISE tools last night (w/ updates), and ran some tests. I found the RTL/technology viewers in ISE to be pretty decent, though I hardly tested it out much. But, from what I saw it is decent enough to strongly consider not paying $5800 for renewal of my Synplify maintenance. I'll take a closer look and compare the two side by side. The RTL and Technology viewers of Synplify were the biggest festures I liked about the tool. Regards, Austin "c d saunter" <christopher.saunter@durham.ac.uk> wrote in message news:d8kk7d$vp8$1@heffalump.dur.ac.uk... > Austin Franklin (austin@dark99room.com) wrote: > : I have not use XST, but it is becoming more attractive. I have been using > : Synplify for many years now, and it works pretty well. XST has come a long > : way, especially now that it appears to have an RTL viewer as well as a > : "implementation" (gate level) viewer, which are two features I liked about > > <snip> > > Austin, > The only area where I have any experience of Symplify is looking > at autogenerated RTL schematics, and unlike my experience with ISE 6.1.xi > they are correct - ISE 6.1 often misses out entire busses etc that > actually exist (First time I found that I wasted half an hour thinking > that synthesis was optimisng the bus away for some reason.) when > displaying RTL schematics. > > Also the visual presentation of the Symplify RTL schematics far suparsed > that of the Xilinx tools, but then ECS (The schemtic capture/viewer tool > in the Xilins ISE package(s)) is pretty grotty. (I'm being polite here) > > Maybe things have got better with ISE 7.1.xi? > > hth, > cds > >Article: 85673
In article <3h3o19Ff6phbU1@individual.net>,
Falk Brunner <Falk.Brunner@gmx.de> wrote:
>"Austin Franklin" <austin@dark99room.com> schrieb im Newsbeitrag
>news:911re.4452$Ub4.3176@fe06.lga...
>> > I used Synplify for many years but I haven't used it recently. I
>> > switched to XST about a year ago when it got to the good enough level.
>> > XST improves with each release, my gut says that it's pretty close to
>> > Synplify's level at this point.
>Recently, I had a design, not really a big deal. Running at 36 and 72 MHz.
>XST was not able to squeeze it into a XC2S50E, but Synplify was. (~1600 LUTs
>to ~ 1200 LUTs). Speed was not the problem, both implementation where fast
>enough. But Synplify was more area efficient.
>We are using XST only, this was just a test with a real case.
I'm having the same experience: Synplify_pro 8.1 uses 97% (map with -tx on)
of an XC2V6000 (which "map" with "-tx on -timing" actually can close timing
on), whereas XST 5.2 uses 102% (no -tx on). I think Synplify's CSE (or
"resource sharing") is better. The difference in price between an XC2V8000
and an XC2V6000 more than covers Synplicity's fee. On the other hand, XST
and Synplicity seem to be on par as far as the resulting design's speed.
One big annoyance: attributes use a completely different concept between the
two tools: Synplicity, following verilog tradition, associates attributes by
position within a comment before the ; of an instantiation. XST follow VHDL
and associates them by name: the comment can be anywhere in the file. But
now that I have my conversion script, this is no big deal. XST uses
data_bus<1> and Synplicity uses data_bus[1]. XST flattens the hierarchy,
Synplicity doesn't (earlier versions used to). All of this makes the .ucf
file fun.
We are not using later versions of XST due to answer record #16808 (casex
doesn't always make correct code)- I'd like to try 7.1i, but it wont work on
RedHat 7.3. Synplify 8.1 (their latest) does work in RedHat 7.3. Also code
errors which XST 5.2 allows cause XST 6.1 - 6.3 to core dump- which makes it
difficult to find the error. Note that we have to run XST 5.2i in wine (but
we then run place & route with 6.2isp3).
Other issues: synplicity runs about 33% faster, but sometimes for larger
designs it is much faster. I think we are hitting some exponential time
algorithm in XST.
The error reporting from Synplify is much better than XST:
// XST gives no error
output [5:0] foo;
reg [4:0] foo;
// XST gives no error: two always blocks writing to the same signal when the
// signal gets optimized out because nobody is readying it.
reg x;
always @(posedge clk or negedge reset_l)
if (!reset_l)
x <= 0;
always @(posedge clk or negedge reset_l)
if (!reset_l)
x <= 0;
else
x <= y;
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 85674Chapter 4: Create and Import Peripheral Wizard of "Embedded System Tools Reference Manual" (http://www.xilinx.com/ise/embedded/est_rm.pdf): "The OPB/PLB peripheral (top design entity) template is in VHDL only. This is because the underlying library elements are implemented in VHDL. The stub user-logic module template, however, can be in either VHDL or Verilog to support a mixed-language development mode." Additional verilog files can be used by adding them to the *.pao file of the generated pcore. Paul sps wrote: > > Hi, > > I have a Verilog processing core. I want to implement it on Vertex2Pro > device as a separate core , adding it to current bus architecture. I > know that VHDL cores can be added. > > Is it possible to add Verilog cores? > > Thanks for the reply. > > Regards > > SPS
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