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The current through pullup resistors for dedicated pins at Vcco of 3.3V is up to 2.35 mA per device according to the Spartan-3 FPGA Family: DC and Switching Characteristics (v1.6) datasheet, Table 6. These signals are probably only pulled high when the HSWAP_EN pin indicates pullups should be used in the unconfigured state. The Spartan-3 is - as far as I know - the only family with these strong pullups; the Spartan-3E devices are back to the weaker pullups typical of other Xilinx devices. "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:2h8eh1hhhv17o804mvpcpg1fukq4e3csvv@4ax.com... > We have a 3.3 volt uP that's programming two Spartan 3 FPGAs in slave > serial mode. A CPU port pin drives a 180 ohm series resistor to the > line that CCLKs both FPGAs, with a 330 ohm resistor to ground at the > last one, making a nice voltage divider for the 2.5 volt dedicated > config logic. It works fine and both chips configure nicely. > > But if we probe the resistor junction before we configure either chip, > which is both chip's CCLK pins, we get about +0.6 volts with the CPU > port pin at ground. Clearly one or both of the CCLK pins is sourcing > current... about 5 mA total! > > All FPGA ground pins seem to be properly grounded. Anybody have ideas? > > John >Article: 88976
I opened a case with this issue just a couple days ago. I'll post here if I get results. The bottom line: we have two solid designs (one shipping, the other ready to go) that have XC3S400-5PQG208C devices using PCI-66 without performance issues. I inherited the PQ208 package when the board designer insisted this was *the* part to use rather than the more SI-friendly FG256 since the price is based on multiple, existing projects. While trying to track down what I thought might be a bug, I found the SSO guidelines you found. Bottom line: I think those numbers are conservative to the point of laughter. We have the two designs I know of working beautifully and the bug in my own design may not be a hardware issue at all, providing solid performance for the testing I've done there as well. PCI should work but the SSO recommendations say there's not a chance in San Jose. - John_H "huangjie" <huangjielg@gmail.com> wrote in message news:1125588866.017556.180590@g47g2000cwa.googlegroups.com... > Hi All! > I have a project which will use spartan3 xc3s200-pq208 as an pci bridge > chip. > And there's the problem: > In spartan3 datasheet (ds-099,version:August 19 2005) part 3(DC and > Switching Characteristics) section called "Simultaneously Switching > Output Guidelines" table 23 page I noticed the SSO number for PCI33_3 > package pq208 is "1". Sine PCI use 49 signals , I think I can't use the > package. The SSO number for xc2s200-pq208 is "4".But why this > is so diffence between xc2s200-pq208 and xc3s200-pq208? > I make two ISE projects one target to xc2s200-pq208,another xc3s200, > and use ibiswriter generete to ibis file. Below is the result: > For 3S : > [Component] Spartan-3 > [Manufacturer] Xilinx, Inc. > | > [Package] > | For Package Type pq208 > | variable typ min max > R_pkg 0.2 0.199 0.2 > L_pkg 14.5nH 12.8nH 16.2nH > C_pkg 1.8pF 1.6pF 2.0pF > [Model] PCI33_3 > Model_type I/O > Polarity Non-Inverting > Enable Active-Low > Vinl = 0.99V > Vinh = 1.65V > Vmeas = 2.03V > Cref = 0.000F > Rref = 25.00 > |Vref = 0.00V > Vref = 3.30V > C_comp 6.38pF 4.60pF 8.23pF > [Ramp] > dV/dt_r 0.98/0.98n 0.75/1.56n 1.16/0.62n > dV/dt_f 0.98/1.87n 0.70/2.33n 1.24/1.28n > R_load = 25.00 > FOR 2S: > [Component] Spartan2 > [Manufacturer] Xilinx Inc. > [Package] > | For Package Type pq208 > | variable typ min max > R_pkg 182.50m 180.00m 185.00m > L_pkg 13.350nH 11.700nH 15.000nH > C_pkg 1.5500pF 1.3000pF 1.8000pF > > [Model] PCI33M5V > Model_type I/O > Polarity Non-Inverting > Enable Active-Low > Vinl = 0.800V > Vinh = 2.000V > Vmeas = 1.500V > Cref = 50.00pF > Rref = 1.0M > Vref = 0.0V > C_comp 6.5000pF 5.0000pF 8.0000pF > > [Ramp] > | variable typ min max > dV/dt_r 1.4790/1.4894n 1.1430/2.5760n 1.7178/1.0217n > dV/dt_f 1.7469/1.1800n 1.4917/2.0700n 1.9432/0.7937n > R_load = 50.0000 > > Since almost all values are almost equal(except the > R_load,S3:25,S2:50), > Why the SSO numbers are significant differ ? Or this just > representation > (When they driver same load , the SSO number are same )? > > Thank you for any words! >Article: 88977
Look closely at the datasheet for the A/D converter. How do they say you should acquire a reading and how are you trying to acquire it? "Marco" <marcotoschi@nospam.it> wrote in message news:df7380$h6e$2@news.ngi.it... > Hallo, > I have made a small microcontroller based on microblaze. > I have connected a differential 16 bit adc to my system. > The adc takes input from a opamp for testing. > > The system works well only if I measure voltage between chipselect of adc > and gnd. In this way it shows every hex number in range: 0 to 7FFF (it is > two complementer). > > If not, I can see only 4-5 numbers of the acquisition range: FB, 1F1F, 3E3E, > 7C7C. > > Which trouble could produce a so strange behavior? > > Many Thanks > Marco > >Article: 88978
Vladislav: Vladislav Muravin wrote: > First, I understand your situation and solidate with you. Thank you. > > Second, despite that DigiKey list those FPGAs for such high price, which > may be a bit old (?), the same devices from Virtex-II family are much > cheaper than the ones you have been screwed up with, if you check with the > distributor. Check out also the prices for similar devices, so that you > would not be screwed up with the offer... I understand. Two or three other people also wrote me and told me that these parts are out of date and that there are newer parts which are cheaper, therefore I would probably not get very much per device. As I said, I simply wish to recover what I can. Therefore, as long as the offer isn't insulting (such as 50 cents per chip), I would still entertain it. Thank you all for your kindness. Ram.Article: 88979
Hi, I'm currently designing a disc drive controller to interface with a 6502-based system. To ease the design a little, I've split it up into a few different modules which are all used by a module called "fdd_top". Now, if I simulate any of the child modules that fdd_top uses, I can simulate the module perfectly with Modelsim XE. That, of course, is what is supposed to happen. The problems start when I try and simulate fdd_top: nothing works! All the outputs are shown as "X". Is there some setting in Modelsim or ISE7.1 that I need to tweak to get MXE to simulate the children as well as the fdd_top module? Sorry if this question sounds a bit silly, but I only started learning howw to use CPLDs last week (using XC9500XL CPLDs, but I want some Coolrunner XPLA3s to play with - shame no-one seems to want to sell me any - same goes for the >72 macrocell XC9500XLs). I've worked out most of the basics of Verilog from studying other people's code (and reading some of the guides on fpga4fun) but still need to work out how the "<=" and "=" assignment operators differ, plus other stuff like that. Not too bad for a week's work I guess :) Thanks, -- Phil. philpem@despammed.com <<-- valid address http://www.philpem.me.uk/Article: 88980
Does anyone have experience running tools from Xilinx (ISE, XST) and Lattice (ispLever) on the same Windows computer? I've had problems in the past trying to install Xilinx and Altera (Quartus) on the same machine. In the end I uninstalled the Quartus software and still had to purge my registry of any remnants of it before the Xilinx (Foundation) tools worked again. Right now on one machine I'm running two versions of Xilinx, 4.1i Foundation (Aldec-based) and 6.1i ISE (XST). I can switch between them by changing only the Xilinx environment variable. I'm a bit reluctant to install the ispLever on the same machine (although it would be convenient) after what I went through to repair the Xilinx tools after installing Quartus. Regards, GaborArticle: 88981
> Where would the 35 MHz noise burst in the middle of the data come from, > and why? What do you think it would look like? It's a six layer board, I don't know where the noise would come from. Like I said, I'm looking for a low-end solution here. > Brad, you didn't mention exactly how the clocks are fed to/between the > two FPGA's, nor how far apart the devices are. I guess it's a synchonous source type clock, although, know that this is the first that I am using these terms. So the 30MHz is routed to a pin, travels about an inch, to the global clock input of the destination Spartan. I put a DCM there, with a fixed delay now at about 4ns, to allow some setup time for the parallel data that I have now. > Considering you are > talking about 9 bits x 30 MHz, it sounds like you're needing to > transfer at max, 270 Mbits/sec. That's right. > As long as your traces are nice and > short, you should be able to cut this down to a single LVCMOS25 net (or > single LVDS diff pair if you want some added security and if you have a > diff pair set up between the two devices). I did pair up the lines, in case I wanted to do just that. So what performance increase could I expect there, ballpark? Do I need to add termination resistor to do this? > You may want to compare the effort and complexity of a bit aligner in > the receiver as opposed to chewing up one more pin for a bit alignment > sync pulse. Seems to me that the source clock should be an adequate sync pulse. No? > Have fun, Yeah thanks and thanks for your advice. Brad SmallridgeArticle: 88982
Ram wrote:
>Vladislav:
>
>Vladislav Muravin wrote:
>
>
>
>>First, I understand your situation and solidate with you.
>>
>>
>
>Thank you.
>
>
>
>>Second, despite that DigiKey list those FPGAs for such high price, which
>>may be a bit old (?), the same devices from Virtex-II family are much
>>cheaper than the ones you have been screwed up with, if you check with the
>>distributor. Check out also the prices for similar devices, so that you
>>would not be screwed up with the offer...
>>
>>
>
>I understand.
>
>Two or three other people also wrote me and told me that these parts are out
>of date and that there are newer parts which are cheaper, therefore I would
>probably not get very much per device.
>
>As I said, I simply wish to recover what I can. Therefore, as long as the
>offer isn't insulting (such as 50 cents per chip), I would still entertain
>it.
>
>Thank you all for your kindness.
>
>Ram.
>
>
Your best bet may be to ebay the lot. The XCV1000-4's are the oldest of
the virtex line. The price you quoted is close to the price Xilinx
asked when these were the latest and greatest (btw, the 1000's were the
biggest in that family). That family has been superceded several times
over (virtexE, then virtex2 then virtex2pro and now virtex4), and even
the low cost Spartan3 line now reaches this 1M gate density, and will
significantly outperform it at a greatly reduced cost. BTW,, Digi-key's
chip prices for Xilinx have historically been way higher than you can
get the chips from just about any place else.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 88983
Ben Jones wrote:
>Hi Martin,
>
>
>
>>I am using the Xilinx ISE 7.1 with ModelSim 6.0a and I have a problem
>>when I use the "Perform Timing-Driven Packing and Placement" option for
>>the mapping process.
>><snip>
>>
>>
ISE 7.1 has been a nightmare of bugs. You might try using ISE6.3sp3
instead.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 88984I am facing the same problem.....looking forward to advice from the experienced members in the group ! thanks, TD Philip Pemberton wrote: > Hi, > I'm currently designing a disc drive controller to interface with a > 6502-based system. To ease the design a little, I've split it up into a few > different modules which are all used by a module called "fdd_top". Now, if I > simulate any of the child modules that fdd_top uses, I can simulate the module > perfectly with Modelsim XE. That, of course, is what is supposed to happen. > The problems start when I try and simulate fdd_top: nothing works! All the > outputs are shown as "X". > Is there some setting in Modelsim or ISE7.1 that I need to tweak to get MXE > to simulate the children as well as the fdd_top module? > > Sorry if this question sounds a bit silly, but I only started learning howw > to use CPLDs last week (using XC9500XL CPLDs, but I want some Coolrunner > XPLA3s to play with - shame no-one seems to want to sell me any - same goes > for the >72 macrocell XC9500XLs). > I've worked out most of the basics of Verilog from studying other people's > code (and reading some of the guides on fpga4fun) but still need to work out > how the "<=" and "=" assignment operators differ, plus other stuff like that. > Not too bad for a week's work I guess :) > > Thanks, > -- > Phil. > philpem@despammed.com <<-- valid address > http://www.philpem.me.uk/Article: 88985
On Thu, 01 Sep 2005 18:09:55 GMT, "John_H" <johnhandwork@mail.com> wrote: >The current through pullup resistors for dedicated pins at Vcco of 3.3V is >up to 2.35 mA per device according to the Spartan-3 FPGA Family: DC and >Switching Characteristics (v1.6) datasheet, Table 6. > >These signals are probably only pulled high when the HSWAP_EN pin indicates >pullups should be used in the unconfigured state. > >The Spartan-3 is - as far as I know - the only family with these strong >pullups; the Spartan-3E devices are back to the weaker pullups typical of >other Xilinx devices. > > OK, thanks a lot. I never would have suspected a dedicated CMOS clock input of having/needing a pullup! At least nothing's broke. JohnArticle: 88986
You can get them from Actel.Article: 88987
Hi all, I faced the following problem with my I2C slave code(VHDL). I was incrementing a counter on the negative edge of SCL(this clock is coming from the processor's I2C port , 100 KHz frequency). But what i observed on the CRO was that my bit counter which was running on the "negative edge" of SCL , was incrementing on "positive edge" also and this was not happening always. The solution to this problem was i inverted the incomimg clock "SCL" and used the rising edge to increment my counter now it was fine. Can any I2C experts clarify what is the problem with working on "negative edge of "SCL" clock. Regards, PravArticle: 88988
On Thu, 01 Sep 2005 08:26:47 +0000, Mike Harrison wrote: > > What frequency/display format are you aiming for ? 800x600 10.4" 18-bit color. Right now I'm using a pixel clock of 28 MHz with an eye to around 40MHz after resolving some other issues in the design that we copied from old stuff.Article: 88989
"John_H" <johnhandwork@mail.com> wrote in message news:bDHRe.27$tN4.242@news-west.eli.net... > Look closely at the datasheet for the A/D converter. How do they say you > should acquire a reading and how are you trying to acquire it? > To start acquiring chipselect must go high for 1 clock cycle. At the falling edge the adc starts conversion. (it's falling edge sensitive). After 5 clock cycles the serial data out goes from Hi-Z state to 0. After 1 clock cycle it starts sending data through serial data out for 16 clock cycles. Then it goes into power down state and waits for a chipselect. I have made a state machine which follows that. Into post-place simulation works well. MarcoArticle: 88990
Hi All. First off - Apologies if anyone considers this not the place to post such information - but I am getting desperate. I am self-studying the book "Advance Digital Design with the Verilog HDL" by Michael D. Ciletti. Unfortunately the original CD supplied with the book was blank. So I went back to the local book distributor and after waiting some weeks got a replacement. The replacement CD has several sector errors and refuses to load at about half way through installation. The local distributor now doesn't want to know me or about my problem, Even after I paid ~15% of my weekly wage on his product. I would like to ask anyone who has the same CD, if they would kindly supply me with a copy PLEASE (either they can ftp it to my home server or cut the CD and mail it to me via snail mail) whatever means of getting it to me would let me get further into my studies without more holdups. I have checked with the s/w originator - www.simucad.com unfortunately they no longer distribute this s/w for free so I have hit the "wall". So, is their anyone out in web-world willing & able to assist me. I'd be most appreciative of a working replacement CD. Much thanks. -- Cheers Grahame. at wildpossum dot comArticle: 88991
Thanks for John_H 's replay !
I will continue use spartan3 since your boards can run well.
Any one know how Xilinx calclate the SSO number ?
Use the following formula ?
Vgnd = L * 1.52* deltaV *C / (( T(10%-90%))^2) ?
I found this in book <<High Speed Digital Design>> (Section 2.4.1.4 ).
Xilinx may be use it because this formula is linear for L and C that
mentioned in xapp689 by xilinx.
When I read xapp689, I thought Xilinx maybe make some mistake in
calclating SSO number for PCI
because PCI has no capacitance load while they use capacitance.
There perhaps some other mistake in calculate the SSO number . Because
the higher package inductance
the slower ouput. So package inductance is not the most significant
factor .
Though I write these and post it , I am not know if it is right .
Thanks to anyone for any words!
Article: 88992
I have been working off and on trying to use the Xilinx XUP board on
Linux Fedora Core 3 with EDK 7.1 and ISE 7.1. I have been fairly
succesful with the software, but downloading the bitstream over the USB
cable has got me baffled. It has worked a few times, but most of the
time there seem to be errors in transmission and this makes the board
trying to do this:
WARNING:iMPACT:2301 - Platform Cable USB firmware must be updated.
This
operation may take up to 10 minutes on a USB 2.0 port
or up to 30 minutes on a USB 1.1 port. Please do not stop the
process or
disconnect the cable prior to compeletion. The cable
STATUS LED will be RED for the duration of the update process.
In the process, I then get:
Doing update for waitTime.
Doing update for waitTime.
Doing update for waitTime.
and after a while:
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
write cmdbuffer failed 20000015.
When it works correctly, it is like this (downloading the Basic System
Build):
Downloading Bitstream onto the target board
*********************************************
impact -batch etc/download.cmd
Release 7.1.03i - iMPACT H.41
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setCable -port auto
AutoDetecting cable. Please wait.
Connecting to cable (Parallel Port - parport0).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:57.
parport0: baseAddress=0x378, ecpAddress=0x778
LPT base address = 0378h.
ECP base address = 0778h.
Cable connection failed.
Connecting to cable (Parallel Port - parport1).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:57.
Cable connection failed.
Connecting to cable (Parallel Port - parport2).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:57.
Cable connection failed.
Connecting to cable (Parallel Port - parport3).
WinDriver v7.00 Jungo (c) 1997 - 2005 Build Date: Apr 26 2005 X86
21:13:57.
Cable connection failed.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /home/krish/binaries/Xilinx/bin/lin/xusbdfwu.hex =
1018(dec),
03FA.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec),
03FA.
Calling setinterface num=0, alternate=0.
DeviceAttach: received and accepted attach for:
vendor id 0x3fd, product id 0x8, device handle 0x92d9af0
Max current requested during enumeration is 150 mA.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1018.
CPLD file version = 0006h.
CPLD version = 0006h.
// *** BATCH CMD : identify
Identifying chain contents ....Version is 0001
'1': : Manufacturer's ID =Xilinx xc2vp30, Version : 1
INFO:iMPACT:1777 -
Reading /home/krish/binaries/Xilinx/virtex2p/data/xc2vp30.bsd...
INFO:iMPACT:501 - '1': Added Device xc2vp30 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Version is 0000
'2': : Manufacturer's ID =Xilinx xccace, Version : 0
INFO:iMPACT:1777 -
Reading /home/krish/binaries/Xilinx/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Version is 1111
'3': : Manufacturer's ID =Xilinx xcf32p, Version : 15
INFO:iMPACT:1777 -
Reading /home/krish/binaries/Xilinx/xcfp/data/xcf32p.bsd...
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
Validating chain...
Boundary-scan chain validated successfully.
Elapsed time = 2 sec.
// *** BATCH CMD : identifyMPMElapsed time = 0 sec.
// *** BATCH CMD : setAttribute -position 3 -attr configFileName -value
"implementation/download.bit"
'3': Loading file 'implementation/download.bit' ...
done.
INFO:iMPACT:501 - '3': Added Device xc2vp30 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
// *** BATCH CMD : program -p 3
Validating chain...
Boundary-scan chain validated successfully.
'3':Programming device...
done.
'3': Reading status register contents...
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
legacy input error : 0
status of GTS_CFG_B : 1
status of GWE : 1
status of GHIGH : 1
value of MODE pin M0 : 1
value of MODE pin M1 : 1
value of MODE pin M2 : 0
value of CFG_RDY (INIT_B) : 1
DONEIN input from DONE pin : 1
IDCODE not validated while trying to write FDRI : 0
write FDRI issued before or after decrypt operation: 0
Decryptor keys not used in proper sequence : 0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 0111 1101 1000 0000 0000 0000 0000
INFO:iMPACT:579 - '3': Completed downloading bit file to device.
INFO:iMPACT:580 - '3':Checking done pin ....done.
'3': Programmed successfully.
Elapsed time = 5 sec.
// *** BATCH CMD : quit
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
I am using a fully patched Fedora Core 3 system, with a locally
compiled kernel 2.6.12-local (basically identical to
2.6.12-1.1372_FC3), have observed FPGA-FAQ 0044, Xilinx Answer #21650,
and am using Jungo System's WinDriver v7.00 Jungo (c) 1997 - 2005 Build
Date: Apr 26 2005. Xilinx patches for ISE and EDK have been applied.
Is there a good way to determine what is causing this unreliability?
Are there any tests I can perform? I would be very grateful for any
suggestions.
Kind regards,
Kris Heyrman
Asst. Prof. in Electronics
Hogeschool Gent
(you can also respond to kris.heyrman@geenspam.hogent.be if you delete
'geenspam.')
Article: 88993"Eric" <ericjohnholland@hotmail.com> writes: > "...Altera continues to sell Excalibur devices, this product family Excalibur does not have a 3Gbps serdes. But what about the NIOS-II in a Stratix GX? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 88994
Thank you. The service pack didn't help, but setting the environment variable did. So now I can get a working design by: 1) disabling "Perform Timing-Driven Packing and Placement" and leaving XIL_MAP_NO_DSP_AUTOREG unset. 2) enabling "Perform Timing-Driven Packing and Placement" and setting XIL_MAP_NO_DSP_AUTOREG. However, option 1 results in the circuit with the highest maximum clock frequency so option 2 does not seem to be the better solution. So, for now, I will stick to my original solution (option 1). I am willing to submit part of the design to Xilinx for analysis. The performance difference between option 1 and 2 is not very significant in that part, but it is visible. So, where can I submit it?Article: 88995
I2C is an open-collector bus with a resistor pullup. So the falling edge is sharp and the rising edge is exponential. I would guess that the rising edge is too slow and is causing problems for your input buffer at the input threshold. Alan Nishioka praveen.kantharajapura@gmail.com wrote: > Hi all, > > I faced the following problem with my I2C slave code(VHDL). > > I was incrementing a counter on the negative edge of SCL(this clock is > coming from the processor's I2C port , 100 KHz frequency). > But what i observed on the CRO was that my bit counter which was > running on the "negative edge" of SCL , was incrementing on "positive > edge" also and this was not happening always. > > The solution to this problem was i inverted the incomimg clock "SCL" > and used the rising edge to increment my counter now it was fine. > > Can any I2C experts clarify what is the problem with working on > "negative edge of "SCL" clock.Article: 88996
Thank you, I will try to find an older version of the ISE Webpack on the Xilinx website. (No luck so far, if anybody has a link I would like to hear about it.) [Barely resisting the urge to rant about bad quality software]Article: 88997
Hello all Is it possible to instantiate multi dimensional input/output port in verilog2001. I tried the following code. module A(in,out); input [7:0]in[7:0]; output [7:0]out[7:0]; but it did gave an error in the Xilinx ISE 6.2.... SumeshArticle: 88998
Thank you for your reply. I guess I have no choice but to upgrade to the newest EDK/ISE. I wanted to avoid this since I do not have time to reconfigure eveything, and to iron out all the bugs created by the conversion :)Article: 88999
Brad Smallridge wrote: > > Where would the 35 MHz noise burst in the middle of the data come from, > > and why? What do you think it would look like? > > It's a six layer board, I don't know where the noise would come from. > Like I said, I'm looking for a low-end solution here. Howdy Brad, That question was actually for Mark. > > Brad, you didn't mention exactly how the clocks are fed to/between the > > two FPGA's, nor how far apart the devices are. > > I guess it's a synchonous source type clock, although, know that > this is the first that I am using these terms. So the 30MHz is routed > to a pin, travels about an inch, to the global clock input of the > destination Spartan. I put a DCM there, with a fixed delay now > at about 4ns, to allow some setup time for the parallel data that I > have now. Sorry, I'm still not clear. Do I understand you that you have a single 30 MHz clock feeding both FPGA's, routed in a daisy-chain fashion, with the second leg of the daisy-chain being only 1" long (those devices must be really close together)? On both devices does the clock go into the GCLK input? > > Considering you are > > talking about 9 bits x 30 MHz, it sounds like you're needing to > > transfer at max, 270 Mbits/sec. > > That's right. > > > As long as your traces are nice and > > short, you should be able to cut this down to a single LVCMOS25 net (or > > single LVDS diff pair if you want some added security and if you have a > > diff pair set up between the two devices). > > I did pair up the lines, in case I wanted to do just that. So what > performance increase could I expect there, ballpark? If you do a Google search on something like "lvds advantages cmos OR lvcmos", you'll get a number of hits, including an appnote from one of my more favorite companies: http://www.pericom.com/pdf/applications/AN041.pdf Note that they list CMOS (including LVCMOS) as having a max speed of "less than 100 Mbps". This is really, really conservative. We have a few LVCMOS25 busses on some of our boards running at over 300 MHz. It's all dependant on distance and slew rate. > Do I need to add termination resistor to do this? LVDS requires a 100 ohm termination at the receiver. If memory serves, the S3 doesn't have 100 ohm on-chip termination, so yes, you'd need to put one as close to the pins as possible. > > You may want to compare the effort and complexity of a bit aligner in > > the receiver as opposed to chewing up one more pin for a bit alignment > > sync pulse. > > Seems to me that the source clock should be an adequate sync pulse. No? When you take a byte (or 9 bits, in your case) and send it one after another in a serial fashion, how are you going to know where the first byte ends and the second byte begins? There are a VERY large number of ways to do this. Regards, Marc
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