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Threads Starting Feb 2007
115149: 07/02/01: John Williams: plb_gemac SerDes mode on V4-FX?
115151: 07/02/01: DC: Altera DSP Builder
115158: 07/02/01: Pablo: Condition Variable in pthread.h
115162: 07/02/01: Jecel: Webpack 9.1 problems with Impact on parallel cable
115163: 07/02/01: Quesito: Re: Webpack 9.1 problems with Impact on parallel cable
115164: 07/02/01: Sean Durkin: Re: Webpack 9.1 problems with Impact on parallel cable
115168: 07/02/01: Jecel: Re: Webpack 9.1 problems with Impact on parallel cable
115175: 07/02/01: Andy Peters: Re: Webpack 9.1 problems with Impact on parallel cable
115186: 07/02/02: Francesco: Re: Webpack 9.1 problems with Impact on parallel cable
115169: 07/02/01: <LT1Z07@yahoo.com>: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115170: 07/02/01: John_H: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115180: 07/02/01: John_H: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115195: 07/02/02: John_H: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115190: 07/02/02: Symon: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115171: 07/02/01: <LT1Z07@yahoo.com>: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115176: 07/02/01: Gabor: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115194: 07/02/02: <LT1Z07@yahoo.com>: Re: Spartan-3E differential outputs (LVPECL_33) with VCCO = 3.3V ?
115173: 07/02/01: idp2: Xilinx (without init value) has a constant value of 0?
115174: 07/02/01: Gabor: Re: Xilinx (without init value) has a constant value of 0?
115177: 07/02/01: idp2: Re: Xilinx (without init value) has a constant value of 0?
115198: 07/02/02: Gabor: Re: Xilinx (without init value) has a constant value of 0?
115228: 07/02/03: Duth: Re: Xilinx (without init value) has a constant value of 0?
115178: 07/02/01: radarman: EDK tri-state control
115441: 07/02/11: Newman: Re: EDK tri-state control
115181: 07/02/02: TC: Re: PCI Express user group
115193: 07/02/02: Fred: Re: PCI Express user group
115183: 07/02/01: nana: read fpga
115189: 07/02/02: Symon: Re: read fpga
115201: 07/02/02: davide: Re: read fpga
115184: 07/02/01: ralstef: DDR SDRAM controller for virtex 2 pro
115185: 07/02/02: Niv (KP): ProAsic-plus PLL
115210: 07/02/02: <mikeandmax@aol.com>: Re: ProAsic-plus PLL
115188: 07/02/02: Andreas Ehliar: XST broken for XC9536?
115192: 07/02/02: Klaus Falser: Re: XST broken for XC9536?
115205: 07/02/02: Mike Treseler: Re: XST broken for XC9536?
115247: 07/02/05: Andreas Ehliar: Re: XST broken for XC9536?
115207: 07/02/02: <cs_posting@hotmail.com>: Re: XST broken for XC9536?
115212: 07/02/02: David R Brooks: Re: XST broken for XC9536?
115209: 07/02/02: <mikeandmax@aol.com>: Re: XST broken for XC9536?
115925: 07/02/26: Andreas Ehliar: Re: XST broken for XC9536?
115196: 07/02/02: Francesco: ISE 9.1 SAY YOURS OPINION
115199: 07/02/02: John_H: Re: ISE 9.1 SAY YOURS OPINION
115208: 07/02/02: John_H: Re: ISE 9.1 SAY YOURS OPINION
115204: 07/02/02: <kicdonc@tiscali.fr>: Re: ISE 9.1 SAY YOURS OPINION
115206: 07/02/02: johnp: Re: ISE 9.1 SAY YOURS OPINION
115214: 07/02/02: Joseph Samson: Re: ISE 9.1 SAY YOURS OPINION
115296: 07/02/06: Joseph Samson: Re: ISE 9.1 SAY YOURS OPINION
115221: 07/02/03: mmihai: Re: ISE 9.1 SAY YOURS OPINION
115231: 07/02/04: Joseph Samson: Re: ISE 9.1 SAY YOURS OPINION
115232: 07/02/04: John_H: Re: ISE 9.1 SAY YOURS OPINION
115259: 07/02/05: Helmut: Re: ISE 9.1 SAY YOURS OPINION
115264: 07/02/05: Francesco: Re: ISE 9.1 SAY YOURS OPINION
115271: 07/02/05: yttrium: Re: ISE 9.1 SAY YOURS OPINION
115272: 07/02/05: Joseph Samson: Re: ISE 9.1 SAY YOURS OPINION
115292: 07/02/06: yttrium: Re: ISE 9.1 SAY YOURS OPINION
115276: 07/02/05: Andy Peters: Re: ISE 9.1 SAY YOURS OPINION
115197: 07/02/02: bharat_in: circle generation algorithm
115200: 07/02/02: Gabor: Re: circle generation algorithm
115203: 07/02/02: devices: Re: circle generation algorithm
115217: 07/02/03: Ben Popoola: Re: circle generation algorithm
115218: 07/02/03: spartan3wiz: Re: circle generation algorithm
115222: 07/02/03: <tdillon@dilloneng.com>: Re: circle generation algorithm
115223: 07/02/03: Ray Andraka: Re: circle generation algorithm
115286: 07/02/05: comp.arch.fpga: Re: circle generation algorithm
115342: 07/02/07: bharat_in: Re: circle generation algorithm
115202: 07/02/02: Colin Hankins: Re: PCI Express user group
115211: 07/02/02: <bharadwaj.sr@gmail.com>: Xilinx Interconnects/Routing
115215: 07/02/02: 2mao: Re: Xilinx Interconnects/Routing
115216: 07/02/02: Peter Alfke: Re: Xilinx Interconnects/Routing
115224: 07/02/03: Mr B: Re: Xilinx Interconnects/Routing
115226: 07/02/03: Mr B: Re: Xilinx Interconnects/Routing
115227: 07/02/03: Peter Alfke: Re: Xilinx Interconnects/Routing
115235: 07/02/04: jbnote: Re: Xilinx Interconnects/Routing
115236: 07/02/04: Mr B: Re: Xilinx Interconnects/Routing
115237: 07/02/04: Peter Alfke: Re: Xilinx Interconnects/Routing
115238: 07/02/04: Peter Alfke: Re: Xilinx Interconnects/Routing
115240: 07/02/04: jbnote: Re: Xilinx Interconnects/Routing
115241: 07/02/04: Mr B: Re: Xilinx Interconnects/Routing
115213: 07/02/02: Nju Njoroge: data OCM BRAM Issues
115220: 07/02/03: Jeff Shafer: Re: data OCM BRAM Issues
115432: 07/02/10: Nju Njoroge: Re: data OCM BRAM Issues
115234: 07/02/04: Mr B: Reconfiguration
115239: 07/02/04: Peter Alfke: Re: Reconfiguration
115242: 07/02/04: ram: query in P&R of FPGA
115243: 07/02/04: ram: Re: query in P&R of FPGA
115244: 07/02/05: Mark McDougall: Re: query in P&R of FPGA
115278: 07/02/05: Ben Twijnstra: Re: query in P&R of FPGA
115446: 07/02/11: phil: Re: query in P&R of FPGA
115246: 07/02/04: <kunals.spam.account@gmail.com>: BFM and Verilog custom IP
115248: 07/02/04: Guy_Sweden: SystemC hangs abruptly
115258: 07/02/05: Colin Paul Gloster: Re: SystemC hangs abruptly
115249: 07/02/05: Srini: DFT Details....
115251: 07/02/05: tomrohit: Re: PCI Express user group
115254: 07/02/05: <manuel-lozano@mixmail.com>: problem with microblaze gcc toolchain
115256: 07/02/05: S.T.: xilinx x2pro ppc custom crt0
115267: 07/02/05: S.T.: Re: xilinx x2pro ppc custom crt0
115260: 07/02/05: CMOS: or1k on spartan 3, 400K gate version
115261: 07/02/05: Andreas Ehliar: Re: or1k on spartan 3, 400K gate version
115263: 07/02/05: Andreas Ehliar: Re: or1k on spartan 3, 400K gate version
115265: 07/02/05: Symon: Re: or1k on spartan 3, 400K gate version
115268: 07/02/05: <joerg@zilium.de>: Re: or1k on spartan 3, 400K gate version
115288: 07/02/05: CMOS: Re: or1k on spartan 3, 400K gate version
115316: 07/02/07: Sandro: Re: or1k on spartan 3, 400K gate version
115262: 07/02/05: xingzhi: 9.1i in Red Hat Enterprise Linux AS 64-bit
115293: 07/02/06: priitr: Re: 9.1i in Red Hat Enterprise Linux AS 64-bit
115304: 07/02/06: Edoardo Causarano: Re: 9.1i in Red Hat Enterprise Linux AS 64-bit
115266: 07/02/05: vlsi_learner: moving data from slower to faster clock domain
115269: 07/02/05: Peter Alfke: Re: moving data from slower to faster clock domain
115274: 07/02/05: Manny: Re: moving data from slower to faster clock domain
115275: 07/02/05: John_H: Re: moving data from slower to faster clock domain
115277: 07/02/05: Kosta Xonis: [Q]: Is Digilent still in business ???
115279: 07/02/05: John_H: Re: Is Digilent still in business ???
115280: 07/02/05: Kosta Xonis: Re: Is Digilent still in business ???
115281: 07/02/05: John_H: Re: Is Digilent still in business ???
115290: 07/02/06: Squirrel: Re: Is Digilent still in business ???
115282: 07/02/05: Peter Alfke: Re: Is Digilent still in business ???
115317: 07/02/07: Sandro: Re: : Is Digilent still in business ???
115287: 07/02/05: <angeloaj@gmail.com>: HI guys...about EDK
115291: 07/02/05: vssumesh: Xilinx Virtex5 board
115303: 07/02/06: mike_la_jolla: Re: Xilinx Virtex5 board
115311: 07/02/07: bijoy: Re: Xilinx Virtex5 board
115356: 07/02/08: <vssumesh@gmail.com>: Re: Xilinx Virtex5 board
115299: 07/02/06: EEngineer: generating VHDL code from Matlab code for DSP - wavelet image compression
115323: 07/02/07: Martin Thompson: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115351: 07/02/08: HT-Lab: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115352: 07/02/08: Martin Thompson: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115459: 07/02/12: Martin Thompson: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115343: 07/02/07: EEngineer: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115436: 07/02/10: EEngineer: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115481: 07/02/12: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115546: 07/02/13: DSP_MADE_EASY: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115302: 07/02/06: bachimanchi@gmail.com: regarding the usage of embedded ethernet MAC on Virtex4
115305: 07/02/06: tony.uniquify@gmail.com: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
115310: 07/02/07: Colin Paul Gloster: Re: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
115313: 07/02/07: Sean Durkin: Re: Question about programming a FPGA using Modelsim Designer instead
115322: 07/02/07: Sean Durkin: Re: Question about programming a FPGA using Modelsim Designer instead
115319: 07/02/07: tony.uniquify@gmail.com: Re: Question about programming a FPGA using Modelsim Designer instead of ISE?? can it be done?
115306: 07/02/06: Shant: Multiple MicroBlaze based Multiprocessor system
115307: 07/02/07: John Williams: Re: Multiple MicroBlaze based Multiprocessor system
115314: 07/02/07: Philip Herzog: Re: Multiple MicroBlaze based Multiprocessor system
115308: 07/02/06: Saqib: Spartan-3E starter kit : trouble with configuration from NOR Flash
115309: 07/02/07: Pablo: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
115315: 07/02/07: Saqib: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
115851: 07/02/22: ziggy: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
116132: 07/03/01: Saqib: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
115312: 07/02/07: Geronimo Stempovski: question about power dissipation
115318: 07/02/07: operator jay: Re: question about power dissipation
115320: 07/02/07: Geronimo Stempovski: Re: question about power dissipation
115336: 07/02/08: Jim Granville: Re: question about power dissipation
115337: 07/02/08: Terry Given: Re: question about power dissipation
115321: 07/02/07: Tony Thai: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
115358: 07/02/08: Brian Drummond: Re: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
115398: 07/02/09: Tony T: Re: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
115431: 07/02/10: Tony T: Re: Modelsim SE 6.2c trying to use Xilinx ISE 9.1i simulation libraries... not working.
115324: 07/02/07: Pablo: Compile uCLinux for Spartan 3e
115326: 07/02/07: Francesco: Re: Compile uCLinux for Spartan 3e
115341: 07/02/08: John Williams: Re: Compile uCLinux for Spartan 3e
115379: 07/02/09: John Williams: Re: Compile uCLinux for Spartan 3e
115353: 07/02/08: Pablo: Re: Compile uCLinux for Spartan 3e
115354: 07/02/08: Pablo: Re: Compile uCLinux for Spartan 3e
115325: 07/02/07: Perry: Questions about pci transactions in my core
115327: 07/02/07: comp.arch.fpga: Re: Questions about pci transactions in my core
115328: 07/02/07: John Adair: Re: Questions about pci transactions in my core
115329: 07/02/07: ZHI: test UART
115330: 07/02/07: <gadav111@hotmail.com>: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
115378: 07/02/08: phil: Re: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
115396: 07/02/09: <gadav111@hotmail.com>: Re: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
115444: 07/02/11: phil: Re: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
115331: 07/02/07: cpope: Impact of only one bank powered?
115334: 07/02/07: Austin Lesea: Re: Impact of only one bank powered?
115332: 07/02/07: ALuPin@web.de: Parameter File in Mixed Mode Designs
115333: 07/02/07: General Schvantzkoph: Altera ByteBlaster and SignalTap on Fedora Core
115338: 07/02/07: <rekha.arun@gmail.com>: Re: Altera ByteBlaster and SignalTap on Fedora Core
115339: 07/02/07: General Schvantzkoph: Re: Altera ByteBlaster and SignalTap on Fedora Core
115349: 07/02/07: Subroto Datta: Re: Altera ByteBlaster and SignalTap on Fedora Core
115369: 07/02/08: General Schvantzkoph: Re: Altera ByteBlaster and SignalTap on Fedora Core
115340: 07/02/07: <angeloaj@gmail.com>: EDK and multipleprocessors - Virtex2p
115344: 07/02/07: Shant: Multiple Micorblaze instantion problem solved, Facing debugging related problem.
115348: 07/02/08: Göran Bilski: Re: Multiple Micorblaze instantion problem solved, Facing debugging related problem.
115345: 07/02/07: Srinu: Parallelism in HDL
115350: 07/02/08: backhus: Re: Parallelism in HDL
115346: 07/02/08: Daniel O'Connor: Replacing/emulating an asynchronous FIFO
115360: 07/02/08: Tim: Re: Replacing/emulating an asynchronous FIFO
115392: 07/02/09: Daniel O'Connor: Re: Replacing/emulating an asynchronous FIFO
115403: 07/02/10: Daniel O'Connor: Re: Replacing/emulating an asynchronous FIFO
115371: 07/02/08: Peter Alfke: Re: Replacing/emulating an asynchronous FIFO
115414: 07/02/09: Peter Alfke: Re: Replacing/emulating an asynchronous FIFO
115347: 07/02/08: Andreas Gauckler: ISE 9.1 Installation crash SuSE 10.2
115361: 07/02/08: Charles, NG: Re: ISE 9.1 Installation crash SuSE 10.2
115399: 07/02/09: gauckler: Re: ISE 9.1 Installation crash SuSE 10.2
115401: 07/02/09: Jan Panteltje: Re: ISE 9.1 Installation crash SuSE 10.2
115424: 07/02/09: Uwe Bonnes: Re: ISE 9.1 Installation crash SuSE 10.2
115355: 07/02/08: vlsi_learner: question abt DPRAM
115357: 07/02/08: vlsi_learner: Re: question abt DPRAM
115359: 07/02/08: Ben Jones: Re: question abt DPRAM
115362: 07/02/08: Symon: Re: question abt DPRAM
115367: 07/02/08: Joseph Samson: Re: question abt DPRAM
115391: 07/02/08: Eric Smith: Re: question abt DPRAM
115368: 07/02/08: pomerado@hotmail.com: Re: question abt DPRAM
115375: 07/02/08: Marlboro: Re: question abt DPRAM
115363: 07/02/08: Stefan Tillich: Floorplanning with Altera APEX20KE device
115364: 07/02/08: <santner@gmail.com>: Interrupts and PPC/opb_intc
115373: 07/02/08: Ben Jackson: Re: Interrupts and PPC/opb_intc
115415: 07/02/09: <santner@gmail.com>: Re: Interrupts and PPC/opb_intc
115416: 07/02/09: <santner@gmail.com>: Re: Interrupts and PPC/opb_intc
115419: 07/02/09: JD Newcomb: Re: Interrupts and PPC/opb_intc
115365: 07/02/08: Dolphin: ISE 9.1 sp1 and EDK 8.2 sp2
115372: 07/02/08: John McCaskill: Re: ISE 9.1 sp1 and EDK 8.2 sp2
115374: 07/02/08: davide: Re: ISE 9.1 sp1 and EDK 8.2 sp2
115366: 07/02/08: <me_2003@walla.co.il>: Radar pulse detection
115386: 07/02/08: <zwsdotcom@gmail.com>: Re: Radar pulse detection
115370: 07/02/08: sam@catalpatechnology.com: Virtex 4 SATA redux
115430: 07/02/10: Antti: Re: Virtex 4 SATA redux
116166: 07/03/02: Simon Tam: Re: Virtex 4 SATA redux
115376: 07/02/08: prakash: DCT/IDCT on FPGA
115425: 07/02/09: Doug Jones: Re: DCT/IDCT on FPGA
115380: 07/02/08: <yuchiwai@gmail.com>: Read CLB information from NCD file
115381: 07/02/09: John Williams: Re: Read CLB information from NCD file
115383: 07/02/08: Kevin Neilson: Re: Read CLB information from NCD file
115384: 07/02/08: <steve.lass@xilinx.com>: Re: Read CLB information from NCD file
115385: 07/02/08: <yuchiwai@gmail.com>: Re: Read CLB information from NCD file
115382: 07/02/08: Brandon Jasionowski: Need advice to help improve timing on V4 FX
115397: 07/02/09: <jetmarc@hotmail.com>: Re: Need advice to help improve timing on V4 FX
115410: 07/02/09: Joseph Samson: Re: Need advice to help improve timing on V4 FX
115404: 07/02/09: Brandon Jasionowski: Re: Need advice to help improve timing on V4 FX
115405: 07/02/09: Brandon Jasionowski: Re: Need advice to help improve timing on V4 FX
115409: 07/02/09: John McCaskill: Re: Need advice to help improve timing on V4 FX
115412: 07/02/09: Brandon Jasionowski: Re: Need advice to help improve timing on V4 FX
115413: 07/02/09: John McCaskill: Re: Need advice to help improve timing on V4 FX
115387: 07/02/08: motty: FSL Questions
115394: 07/02/09: Göran Bilski: Re: FSL Questions
115389: 07/02/08: AdamE: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115393: 07/02/08: Peter Alfke: Re: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115402: 07/02/09: AdamE: Re: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115411: 07/02/09: Peter Alfke: Re: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115390: 07/02/08: morpheus: Digital AM/FM Receiver
115395: 07/02/09: Johan Bernspang: Re: Digital AM/FM Receiver
116213: 07/03/04: Eric Smith: Re: Digital AM/FM Receiver
115647: 07/02/15: Ray Andraka: Re: Digital AM/FM Receiver
116203: 07/03/04: morpheus: Re: Digital AM/FM Receiver
115400: 07/02/09: Pablo: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115407: 07/02/09: Benjamin Todd: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115418: 07/02/09: Eric Smith: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115850: 07/02/22: ziggy: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115856: 07/02/22: Ben Jones: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115858: 07/02/22: John_H: Re: Xilinx Platform Studio Evaluation Trial Expired (included in
115406: 07/02/09: wojt: Setting VHDL standard in Xilinx ISE
115422: 07/02/09: davide: Re: Setting VHDL standard in Xilinx ISE
115434: 07/02/10: Jim Lewis: Re: Setting VHDL standard in Xilinx ISE
115498: 07/02/12: davide: Re: Setting VHDL standard in Xilinx ISE
115511: 07/02/12: <ghelbig@lycos.com>: Re: Setting VHDL standard in Xilinx ISE
115533: 07/02/13: Colin Paul Gloster: Re: Setting VHDL standard in Xilinx ISE
115408: 07/02/09: JD Newcomb: Applications under MontaVista Linux on ML310
115417: 07/02/09: cathy: uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING )
115420: 07/02/09: Joseph Samson: Re: uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING
115421: 07/02/09: cathy: Re: uestion about "clock signal" in Xilinx EDK design. (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING )
115423: 07/02/09: bachimanchi@gmail.com: regarding the usage of tri mode EMAC on virtex 4
115426: 07/02/09: Brad Smallridge: Xilinx ML40x SRAM to/from Flash
115427: 07/02/09: Ed: Disabling Interrupts/Context switching in Xilkernel
115553: 07/02/13: Vasanth Asokan: Re: Disabling Interrupts/Context switching in Xilkernel
115428: 07/02/10: quad: NGDBuild error
115464: 07/02/12: Sean Durkin: Re: NGDBuild error
115429: 07/02/10: Guy_FPGA: Xilinx Ethernet MAC - working with DMA (EDK)
115433: 07/02/10: pete o.: ModelSim - Do Files
115435: 07/02/10: Mike Treseler: Re: ModelSim - Do Files
115438: 07/02/11: Arnaud: Re: ModelSim - Do Files
115440: 07/02/11: Brian Drummond: Re: ModelSim - Do Files
115457: 07/02/12: backhus: Re: ModelSim - Do Files
115501: 07/02/12: Marlboro: Re: ModelSim - Do Files
115437: 07/02/11: <me_2003@walla.co.il>: chipscope + mdm with microblaze ..
115452: 07/02/11: motty: Re: chipscope + mdm with microblaze ..
115458: 07/02/12: <me_2003@walla.co.il>: Re: chipscope + mdm with microblaze ..
115491: 07/02/12: motty: Re: chipscope + mdm with microblaze ..
115439: 07/02/11: CMOS: substracting a whole array of values at once
115442: 07/02/11: CMOS: Re: substracting a whole array of values at once
115447: 07/02/11: John_H: Re: substracting a whole array of values at once
115466: 07/02/12: backhus: Re: substracting a whole array of values at once
115488: 07/02/12: Pete Fraser: Re: substracting a whole array of values at once
115497: 07/02/12: John_H: Re: substracting a whole array of values at once
115523: 07/02/13: backhus: Re: substracting a whole array of values at once
115528: 07/02/13: Jonathan Bromley: Re: substracting a whole array of values at once
115535: 07/02/13: Jonathan Bromley: Re: substracting a whole array of values at once
115540: 07/02/13: Pete Fraser: Re: substracting a whole array of values at once
115580: 07/02/14: backhus: Re: substracting a whole array of values at once
115589: 07/02/14: backhus: Re: substracting a whole array of values at once
115594: 07/02/14: Pete Fraser: Re: substracting a whole array of values at once
115482: 07/02/12: fpgabuilder: Re: substracting a whole array of values at once
115484: 07/02/12: Peter Alfke: Re: substracting a whole array of values at once
115495: 07/02/12: Marlboro: Re: substracting a whole array of values at once
115496: 07/02/12: Marlboro: Re: substracting a whole array of values at once
115527: 07/02/13: CMOS: Re: substracting a whole array of values at once
115529: 07/02/13: CMOS: Re: substracting a whole array of values at once
115545: 07/02/13: fpgabuilder: Re: substracting a whole array of values at once
115582: 07/02/14: CMOS: Re: substracting a whole array of values at once
115443: 07/02/11: mahdi: CLOCK GENERATOR
115448: 07/02/11: Peter Alfke: Re: CLOCK GENERATOR
115451: 07/02/12: Jim Granville: Re: CLOCK GENERATOR
115445: 07/02/11: cathy: question about DCM in virtex5: fails the maximum period check
115450: 07/02/11: Peter Alfke: Re: question about DCM in virtex5: fails the maximum period check
115480: 07/02/12: cathy: Re: question about DCM in virtex5: fails the maximum period check
115449: 07/02/11: jim2345: FPGA configuration direct from PLX
115453: 07/02/11: Peter Wallace: Re: FPGA configuration direct from PLX
115454: 07/02/12: Gavin Melville: Weird problem with WP 9.1sp1 and XC95144XL
115456: 07/02/12: Jim Granville: Re: Weird problem with WP 9.1sp1 and XC95144XL
115463: 07/02/12: Benjamin Todd: Re: Weird problem with WP 9.1sp1 and XC95144XL
115471: 07/02/12: Andreas Ehliar: Re: Weird problem with WP 9.1sp1 and XC95144XL
115467: 07/02/12: <gavin.melville@acclipse.co.nz>: Re: Weird problem with WP 9.1sp1 and XC95144XL
115460: 07/02/12: Magne Munkejord: Problem with floating inputs on LVDS ports
115465: 07/02/12: Sean Durkin: Re: Problem with floating inputs on LVDS ports
115490: 07/02/12: Magne Munkejord: Re: Problem with floating inputs on LVDS ports
115551: 07/02/13: Magne Munkejord: Re: Problem with floating inputs on LVDS ports
115510: 07/02/12: Jon Elson: Re: Problem with floating inputs on LVDS ports
115461: 07/02/12: Himlam8484: Picobalze in the FPGA
115486: 07/02/12: Nico Coesel: Re: Picobalze in the FPGA
115502: 07/02/12: Georg Acher: Re: Picobalze in the FPGA
115505: 07/02/12: Ben Jackson: Re: Picobalze in the FPGA
115524: 07/02/13: backhus: Re: Picobalze in the FPGA
115579: 07/02/14: backhus: Re: Picobalze in the FPGA
115975: 07/02/27: backhus: Re: Picobalze in the FPGA
115515: 07/02/12: Himlam8484: Picobalze in the FPGA
115530: 07/02/13: Himlam8484: Re: Picobalze in the FPGA
115928: 07/02/26: Himlam8484: Picobalze in the FPGA
116019: 07/02/27: Himlam8484: Re: Picobalze in the FPGA
115462: 07/02/12: Geronimo Stempovski: Building Coaxial transmission line on PCB?
115469: 07/02/12: John Fields: Re: Building Coaxial transmission line on PCB?
115472: 07/02/12: Geronimo Stempovski: Re: Building Coaxial transmission line on PCB?
115473: 07/02/12: Meindert Sprang: Re: Building Coaxial transmission line on PCB?
115475: 07/02/12: Henning Paul: Re: Building Coaxial transmission line on PCB?
115492: 07/02/12: John Fields: Re: Building Coaxial transmission line on PCB?
115521: 07/02/12: Bob: Re: Building Coaxial transmission line on PCB?
115494: 07/02/12: Grant Edwards: Re: Building Coaxial transmission line on PCB?
115517: 07/02/13: Robert Baer: Re: Building Coaxial transmission line on PCB?
115519: 07/02/13: CBFalconer: Re: Building Coaxial transmission line on PCB?
115532: 07/02/13: John Fields: Re: Building Coaxial transmission line on PCB?
115474: 07/02/12: Fred Bloggs: Re: Building Coaxial transmission line on PCB?
115518: 07/02/13: Robert Baer: Re: Building Coaxial transmission line on PCB?
115478: 07/02/12: <a7yvm109gf5d1@netzero.com>: Re: Building Coaxial transmission line on PCB?
115479: 07/02/12: Fred Bloggs: Re: Building Coaxial transmission line on PCB?
115483: 07/02/12: MassiveProng: Re: Building Coaxial transmission line on PCB?
115485: 07/02/12: John Larkin: Re: Building Coaxial transmission line on PCB?
115499: 07/02/12: Joel Kolstad: Re: Building Coaxial transmission line on PCB?
115500: 07/02/12: Austin Lesea: Re: Building Coaxial transmission line on PCB?
115504: 07/02/12: john jardine: Re: Building Coaxial transmission line on PCB?
115526: 07/02/13: Jim Granville: Re: Building Coaxial transmission line on PCB?
115544: 07/02/13: John Larkin: Re: Building Coaxial transmission line on PCB?
115659: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115671: 07/02/16: John Larkin: Re: Building Coaxial transmission line on PCB?
115675: 07/02/16: Michael A. Terrell: Re: Building Coaxial transmission line on PCB?
115676: 07/02/16: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115679: 07/02/16: John Larkin: Re: Building Coaxial transmission line on PCB?
115680: 07/02/16: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115701: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115703: 07/02/17: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115704: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115709: 07/02/17: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115713: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115705: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115706: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115712: 07/02/16: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115716: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115707: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115710: 07/02/17: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115715: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115719: 07/02/17: CBFalconer: Re: Building Coaxial transmission line on PCB?
115733: 07/02/18: MassiveProng: Re: Building Coaxial transmission line on PCB?
115720: 07/02/17: John Larkin: Re: Building Coaxial transmission line on PCB?
115725: 07/02/17: MassiveProng: Re: Building Coaxial transmission line on PCB?
115726: 07/02/17: John Larkin: Re: Building Coaxial transmission line on PCB?
115708: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115711: 07/02/17: Vladimir Vassilevsky: Re: Building Coaxial transmission line on PCB?
115714: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115699: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115718: 07/02/17: Michael A. Terrell: Re: Building Coaxial transmission line on PCB?
115678: 07/02/16: CBFalconer: Re: Building Coaxial transmission line on PCB?
115681: 07/02/16: John Larkin: Re: Building Coaxial transmission line on PCB?
115683: 07/02/16: msg: Re: Building Coaxial transmission line on PCB?
115700: 07/02/16: MassiveProng: Re: Building Coaxial transmission line on PCB?
115537: 07/02/13: Uwe Hercksen: Re: Building Coaxial transmission line on PCB?
115559: 07/02/13: john jardine: Re: Building Coaxial transmission line on PCB?
115561: 07/02/14: Jim Granville: Re: Building Coaxial transmission line on PCB?
115542: 07/02/13: John Larkin: Re: Building Coaxial transmission line on PCB?
115563: 07/02/13: john jardine: Re: Building Coaxial transmission line on PCB?
115663: 07/02/16: Grant Edwards: Re: Building Coaxial transmission line on PCB?
115666: 07/02/16: John Devereux: Re: Building Coaxial transmission line on PCB?
115668: 07/02/16: Grant Edwards: Re: Building Coaxial transmission line on PCB?
115670: 07/02/16: John Larkin: Re: Building Coaxial transmission line on PCB?
115516: 07/02/13: Robert Baer: Re: Building Coaxial transmission line on PCB?
115520: 07/02/12: werty: Re: Building Coaxial transmission line on PCB?
115525: 07/02/12: Tom Bruhns: Re: Building Coaxial transmission line on PCB?
115536: 07/02/13: Uwe Hercksen: Re: Building Coaxial transmission line on PCB?
115550: 07/02/13: Geronimo Stempovski: Re: Building Coaxial transmission line on PCB?
115591: 07/02/14: Uwe Hercksen: Re: Building Coaxial transmission line on PCB?
115593: 07/02/14: John Larkin: Re: Building Coaxial transmission line on PCB?
115615: 07/02/15: Geronimo Stempovski: Loss Diagram
115625: 07/02/15: John Larkin: Re: Loss Diagram
115653: 07/02/16: Geronimo Stempovski: Re: Loss Diagram
115667: 07/02/16: John Larkin: Re: Loss Diagram
115673: 07/02/16: Geronimo Stempovski: Re: Loss Diagram
115674: 07/02/16: John Larkin: Re: Loss Diagram
115724: 07/02/17: John Larkin: Re: Loss Diagram
115923: 07/02/25: glen herrmannsfeldt: Re: Loss Diagram
115627: 07/02/15: Uwe Hercksen: Re: Loss Diagram
115626: 07/02/15: Uwe Hercksen: Re: Building Coaxial transmission line on PCB?
115628: 07/02/15: John Larkin: Re: Building Coaxial transmission line on PCB?
115651: 07/02/15: werty: Re: Building Coaxial transmission line on PCB?
115652: 07/02/15: werty: Re: Building Coaxial transmission line on PCB?
115468: 07/02/12: Pablo: PETALINUX-COPY-AUTOCONFIG ERROR
115509: 07/02/13: John Williams: Re: PETALINUX-COPY-AUTOCONFIG ERROR
115470: 07/02/12: <vimes_ankh@yahoo.de>: Master IPIF interface
115476: 07/02/12: Antti: MPMC2 for Virtex-5 when?
115477: 07/02/12: Didi: Understanding something in a bsdl file
115487: 07/02/12: Say Joe: Which is your favorite FPGA language?
115507: 07/02/12: Tommy Thorn: Re: Which is your favorite FPGA language?
115514: 07/02/13: Jim Granville: Re: Which is your favorite FPGA language?
115538: 07/02/13: HT-Lab: Re: Which is your favorite FPGA language?
115539: 07/02/13: Colin Paul Gloster: Re: Which is your favorite FPGA language?
115554: 07/02/13: Jonathan Bromley: Re: Which is your favorite FPGA language?
115556: 07/02/14: Jim Granville: Re: Which is your favorite FPGA language?
115587: 07/02/14: Colin Paul Gloster: Re: Which is your favorite FPGA language?
115508: 07/02/12: Jon Beniston: Re: Which is your favorite FPGA language?
115513: 07/02/12: Say Joe: Re: Which is your favorite FPGA language?
115531: 07/02/13: Jon Beniston: Re: Which is your favorite FPGA language?
115534: 07/02/13: Say Joe: Re: Which is your favorite FPGA language?
115547: 07/02/13: Gabor: Re: Which is your favorite FPGA language?
115549: 07/02/13: Say Joe: Re: Which is your favorite FPGA language?
115489: 07/02/12: Thuy Pham: How to develop STM-16 framer in FPGA
115493: 07/02/12: John_H: Re: How to develop STM-16 framer in FPGA
115522: 07/02/13: Kim Enkovaara: Re: How to develop STM-16 framer in FPGA
115503: 07/02/12: Gabor: Re: Problem with floating inputs on LVDS ports
115506: 07/02/12: <kjasapara@yahoo.com>: Unable to load FPGA image from the prom
116908: 07/03/20: <brian.magnusen@gmail.com>: Re: Unable to load FPGA image from the prom
115541: 07/02/13: Andreas Ehliar: Typical clock frequencies of FPGA designs
115548: 07/02/13: Austin Lesea: Re: Typical clock frequencies of FPGA designs
115552: 07/02/13: Ben Jones: Re: Typical clock frequencies of FPGA designs
115557: 07/02/14: Jim Granville: Re: Typical clock frequencies of FPGA designs
115565: 07/02/13: Peter Alfke: Re: Typical clock frequencies of FPGA designs
115568: 07/02/13: mmihai: Re: Typical clock frequencies of FPGA designs
115569: 07/02/14: Jim Granville: Re: Typical clock frequencies of FPGA designs
115570: 07/02/14: Tim: Re: Typical clock frequencies of FPGA designs
115610: 07/02/14: Ray Andraka: Re: Typical clock frequencies of FPGA designs
115543: 07/02/13: Peter Mendham: SelectMAP Configuration and Readback
115555: 07/02/13: MikeJ: audio low pass filtering in FPGA
115560: 07/02/13: glen herrmannsfeldt: Re: audio low pass filtering in FPGA
115562: 07/02/13: MikeJ: Re: audio low pass filtering in FPGA
115804: 07/02/21: glen herrmannsfeldt: Re: audio low pass filtering in FPGA
115829: 07/02/21: Satoru Uzawa: Re: audio low pass filtering in FPGA
115577: 07/02/13: John Larkin: Re: audio low pass filtering in FPGA
115639: 07/02/15: MikeJ: Re: audio low pass filtering in FPGA
115558: 07/02/13: Gabor: Re: Typical clock frequencies of FPGA designs
115564: 07/02/14: Jim Granville: Re: Typical clock frequencies of FPGA designs
115574: 07/02/14: nospam: Re: Typical clock frequencies of FPGA designs
115566: 07/02/13: Gabor: Re: Problem with floating inputs on LVDS ports
115567: 07/02/13: Will: Need FPGA recommendation
115571: 07/02/14: Massoud: Is there any version of Aurora protocol which works with LVDS instead of MGTs?
115572: 07/02/13: motty: IP to OPB FIFO
115573: 07/02/14: John Williams: Re: IP to OPB FIFO
115576: 07/02/14: Zara: Re: IP to OPB FIFO
115575: 07/02/13: motty: Re: IP to OPB FIFO
115578: 07/02/13: ekavirsrikanth@gmail.com: regarding VREF and VCCO and GCLK in virtex 2 pro fpga
115592: 07/02/14: Joseph Samson: Re: regarding VREF and VCCO and GCLK in virtex 2 pro fpga
115581: 07/02/14: simon.stockton@baesystems.com: MGT RXRECCLK using 3 Global Clocks!
115583: 07/02/14: llandre: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115588: 07/02/14: B. Joshua Rosen: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115599: 07/02/14: llandre: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115600: 07/02/14: Nico Coesel: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115605: 07/02/14: Ray Andraka: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115620: 07/02/15: David Brown: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115642: 07/02/16: Thomas Womack: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
117109: 07/03/23: Fred: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
117115: 07/03/23: David Brown: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115656: 07/02/16: David Brown: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115664: 07/02/16: Andreas Ehliar: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115601: 07/02/14: B. Joshua Rosen: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115602: 07/02/14: B. Joshua Rosen: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115637: 07/02/15: spartan3wiz: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115660: 07/02/16: llandre: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115661: 07/02/16: General Schvantzkoph: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
116926: 07/03/20: Marc Randolph: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115584: 07/02/14: Vince: CoreABC on M7A3PE600
115585: 07/02/14: <rponsard@gmail.com>: picoblaze assembler : kcpsm3.exe and wine/linux
115590: 07/02/14: backhus: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115617: 07/02/15: Uwe Bonnes: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115623: 07/02/15: backhus: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115614: 07/02/14: dank: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115586: 07/02/14: Venu: OPB BRAM not bein detected
115595: 07/02/14: Kevin Neilson: Minimum Speed of DDR / DDR2 SDRAM w/o DLL
115619: 07/02/15: asicbaba: Re: Minimum Speed of DDR / DDR2 SDRAM w/o DLL
115596: 07/02/14: <pixelsmart@gmail.com>: wintel CPU reads across the PCI Express bus
115811: 07/02/21: Jules: Re: wintel CPU reads across the PCI Express bus
115815: 07/02/21: Andreas Ehliar: Re: wintel CPU reads across the PCI Express bus
115597: 07/02/14: jetq88: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
115616: 07/02/14: <ghelbig@lycos.com>: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
115618: 07/02/15: Mike Treseler: Re: Need fair opinions on choosing either Altera or Xilinx as main
115621: 07/02/15: Kim Enkovaara: Re: Need fair opinions on choosing either Altera or Xilinx as main
115630: 07/02/15: Peter Alfke: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
115640: 07/02/16: Jim Granville: Re: Need fair opinions on choosing either Altera or Xilinx as main
115654: 07/02/15: <rickystickyrick@hotmail.com>: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
115682: 07/02/16: <kayrock66@yahoo.com>: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
117022: 07/03/21: <lnds@hotmail.com>: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
115598: 07/02/14: Symon: MGT free design papers.
115603: 07/02/14: <stephenmck@gmail.com>: Xilinx Platform Studio adding Xilinx coreGen IP
115611: 07/02/14: John McCaskill: Re: Xilinx Platform Studio adding Xilinx coreGen IP
115631: 07/02/15: Matt B: Re: Xilinx Platform Studio adding Xilinx coreGen IP
115821: 07/02/21: <stephenmck@gmail.com>: Re: Xilinx Platform Studio adding Xilinx coreGen IP
115606: 07/02/14: bengineerd: Spartan 3 Output Driver Issue
115608: 07/02/14: John_H: Re: Spartan 3 Output Driver Issue
115633: 07/02/15: John_H: Re: Spartan 3 Output Driver Issue
115635: 07/02/15: John_H: Re: Spartan 3 Output Driver Issue
115632: 07/02/15: bengineerd: Re: Spartan 3 Output Driver Issue
115634: 07/02/15: bengineerd: Re: Spartan 3 Output Driver Issue
115607: 07/02/14: <angeloaj@gmail.com>: ppc405_1 and LED in EDK
115609: 07/02/14: Dave H: Can't get the ACE to run software apps on the ML403
115612: 07/02/15: John Williams: Re: Can't get the ACE to run software apps on the ML403
115613: 07/02/15: Marco T.: ML403 FPGA and CPLD
115622: 07/02/15: Tim: Can't be too thin or too rich or have too many ground pads
115624: 07/02/15: motty: EDK Simulation on NCSIM
115638: 07/02/15: motty: Re: EDK Simulation on NCSIM
115629: 07/02/15: <patrick.melet@dmradiocom.fr>: FFT IP ALTERA FORMAT
115636: 07/02/15: Frank van Eijkelenburg: using shared vhdl code in customer ipif block
115752: 07/02/19: Harry Stello: Re: using shared vhdl code in customer ipif block
115641: 07/02/15: Peter Alfke: Do you like Virtex-5 ?
115643: 07/02/16: Jim Granville: Re: Do you like Virtex-5 ?
115672: 07/02/16: Colin Paul Gloster: Re: Do you like Virtex-5 ?
115731: 07/02/18: Nico Coesel: Re: Do you like Virtex-5 ?
115732: 07/02/19: Jim Granville: Re: Do you like Virtex-5 ?
115644: 07/02/16: Tim: Re: Do you like Virtex-5 ?
115646: 07/02/15: Austin: Re: Do you like Virtex-5 ?
115648: 07/02/16: Tim: Re: Do you like Virtex-5 ?
115649: 07/02/16: Tim: Re: Do you like Virtex-5 ?
115658: 07/02/16: Uwe Bonnes: Re: Do you like Virtex-5 ?
115662: 07/02/16: Georg Acher: Re: Do you like Virtex-5 ?
115669: 07/02/16: Colin Paul Gloster: Re: Do you like Virtex-5 ?
115698: 07/02/17: Tim: Re: Do you like Virtex-5 ?
115721: 07/02/17: Austin: Re: Do you like Virtex-5 ?
115729: 07/02/18: Brian Drummond: Re: Do you like Virtex-5 ?
115784: 07/02/20: Austin Lesea: Business is not "as usual"
115798: 07/02/21: S Matthews: Re: Business is not "as usual"
115814: 07/02/21: Austin Lesea: Re: Business is not "as usual"
115785: 07/02/20: Pete Fraser: Re: Do you like Virtex-5 ?
115865: 07/02/22: Colin Paul Gloster: Re: Do you like Virtex-5 ?
115695: 07/02/16: Jon Elson: Re: Do you like Virtex-5 ?
115702: 07/02/17: Jim Granville: Re: Do you like Virtex-5 ?
115748: 07/02/19: Sean Durkin: Re: Do you like Virtex-5 ?
115756: 07/02/19: Jon Elson: Re: Do you like Virtex-5 ?
115691: 07/02/16: Jon Elson: Re: Do you like Virtex-5 ?
115693: 07/02/16: Jon Elson: Re: Do you like Virtex-5 ?
115645: 07/02/15: Peter Alfke: Re: Do you like Virtex-5 ?
115655: 07/02/15: <rickystickyrick@hotmail.com>: Re: Do you like Virtex-5 ?
115717: 07/02/16: <rickystickyrick@hotmail.com>: Re: Do you like Virtex-5 ?
115782: 07/02/20: kunil: Re: Do you like Virtex-5 ?
115835: 07/02/21: kunil: Re: Do you like Virtex-5 ?
115650: 07/02/15: motty: ModelSim EDK Sim Problem
115677: 07/02/16: motty: Re: ModelSim EDK Sim Problem
115657: 07/02/16: Metin: Lattice / M-LVDS
115685: 07/02/16: Gabor: Re: Lattice / M-LVDS
115665: 07/02/16: Dave H: Has anyone gotten the GSRD to run from Ace CF?
115684: 07/02/16: Kevin Neilson: Verilog: Simulating Transport Delays on Bidirectional Tristate Lines
115686: 07/02/16: jasonL: Does Xilinx XST synthesize combinational divider?
115689: 07/02/16: John_H: Re: Does Xilinx XST synthesize combinational divider?
115734: 07/02/18: comp.arch.fpga: Re: Does Xilinx XST synthesize combinational divider?
115687: 07/02/16: <bitsbytesandbugs@googlemail.com>: Where to start???
115692: 07/02/16: Austin Lesea: Re: Where to start???
115694: 07/02/16: Austin Lesea: Re: Where to start???
115697: 07/02/17: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Re: Where to start???
115727: 07/02/17: <pbFJKD@ludd.invalid>: Re: Where to start???
115730: 07/02/18: John Adair: Re: Where to start???
115735: 07/02/18: <bitsbytesandbugs@googlemail.com>: Re: Where to start???
115688: 07/02/16: evilkidder@googlemail.com: LUT based virtex multiplier
115690: 07/02/16: John_H: Re: LUT based virtex multiplier
115696: 07/02/16: evilkidder@googlemail.com: Re: LUT based virtex multiplier
115722: 07/02/17: ScottNortman: Xilinx ISE WebPack Simulation Problem
115723: 07/02/17: KJ: Re: Xilinx ISE WebPack Simulation Problem
115728: 07/02/17: <cs_posting@hotmail.com>: Nexys from Digilent... aka, binge hacking
115769: 07/02/20: RedskullDC: Re: Nexys from Digilent... aka, binge hacking
115796: 07/02/21: S Matthews: Re: Nexys from Digilent... aka, binge hacking
115799: 07/02/20: <cs_posting@hotmail.com>: Re: Nexys from Digilent... aka, binge hacking
115736: 07/02/18: <rits11@gmail.com>: need help on our thesis proposal in our school.
115740: 07/02/18: Tim Wescott: Re: need help on our thesis proposal in our school.
115745: 07/02/19: <rits11@gmail.com>: Re: need help on our thesis proposal in our school.
115737: 07/02/18: JK: best way to get 4xclk
115738: 07/02/18: JK: Re: best way to get 4xclk
115739: 07/02/18: JK: Re: best way to get 4xclk
115743: 07/02/18: Peter Alfke: Re: best way to get 4xclk
115746: 07/02/19: JK: Re: best way to get 4xclk
115741: 07/02/18: subint: Testing FPGA
115744: 07/02/18: Peter Alfke: Re: Testing FPGA
115755: 07/02/19: Nicolas Matringe: Re: Testing FPGA
115742: 07/02/18: subint: System Requirement to run V4Lx200,v5lx330
115747: 07/02/19: dang_hut@yahoo.com: Need help with VHDL simulation with SPW in Linux
115749: 07/02/19: Charles: ACTEL ProAsic Plus
115754: 07/02/19: HT-Lab: Re: ACTEL ProAsic Plus
115757: 07/02/19: <cs_posting@hotmail.com>: Re: ACTEL ProAsic Plus
115758: 07/02/20: Jim Granville: Re: ACTEL ProAsic Plus
115765: 07/02/19: <cs_posting@hotmail.com>: Re: ACTEL ProAsic Plus
115772: 07/02/20: Thomas Stanka: Re: ACTEL ProAsic Plus
115777: 07/02/20: dscolson@rcn.com: Re: ACTEL ProAsic Plus
115780: 07/02/20: HT-Lab: Re: ACTEL ProAsic Plus
115750: 07/02/19: cpope: low cost xilinx prom burner?
115764: 07/02/19: <cs_posting@hotmail.com>: Re: low cost xilinx prom burner?
115774: 07/02/20: cpope: Re: low cost xilinx prom burner?
115805: 07/02/21: cpope: Re: low cost xilinx prom burner?
115825: 07/02/21: cpope: Re: low cost xilinx prom burner?
115794: 07/02/20: <cs_posting@hotmail.com>: Re: low cost xilinx prom burner?
115812: 07/02/21: <cs_posting@hotmail.com>: Re: low cost xilinx prom burner?
115813: 07/02/21: <cs_posting@hotmail.com>: Re: low cost xilinx prom burner?
115751: 07/02/19: Harry Stello: MPD Files
115759: 07/02/20: John Williams: Re: MPD Files
116507: 07/03/11: Amit Kasat: Re: MPD Files
115753: 07/02/19: mahdi: ROC PORT
115857: 07/02/22: <simon.charles@bloomsbury-dsp.co.uk>: Re: ROC PORT
115870: 07/02/22: Ben Twijnstra: Re: ROC PORT
115867: 07/02/22: mahdi: Re: ROC PORT
115760: 07/02/20: El-Mehdi Taileb: MIG 1.6 on ISE-9.1i-SP1
115761: 07/02/19: Erik Widding: Xilinx MIG DDR2 Documentation
115763: 07/02/19: Erik Widding: Re: Xilinx MIG DDR2 Documentation
115773: 07/02/20: Joseph Samson: Re: Xilinx MIG DDR2 Documentation
115797: 07/02/20: rao: Re: Xilinx MIG DDR2 Documentation
115762: 07/02/19: Aaron: How to get the area/time results without IO mapping
115771: 07/02/20: Martin Thompson: Re: How to get the area/time results without IO mapping
115792: 07/02/20: Jim Wu: Re: How to get the area/time results without IO mapping
116169: 07/03/03: jtw: Re: How to get the area/time results without IO mapping
116178: 07/03/03: John McCaskill: Re: How to get the area/time results without IO mapping
115766: 07/02/19: ekavirsrikanth@gmail.com: configuring in slave serial mode with serial platform PROM
115786: 07/02/20: Matthew Hicks: Re: configuring in slave serial mode with serial platform PROM
115767: 07/02/19: mh: Managing input clock of 20MHz at input of DCM
115768: 07/02/20: Zara: Re: Managing input clock of 20MHz at input of DCM
115783: 07/02/20: Austin Lesea: Re: Managing input clock of 20MHz at input of DCM
115770: 07/02/20: <m.afgani@gmail.com>: Xilinx ML402 Virtex-4 Eval kit - I2C Bus
115789: 07/02/20: Brad Smallridge: Re: Xilinx ML402 Virtex-4 Eval kit - I2C Bus
115775: 07/02/20: vlsi_learner: can I convert DPRAM to SPRAM?
115776: 07/02/20: John_H: Re: can I convert DPRAM to SPRAM?
115787: 07/02/20: John_H: Re: can I convert DPRAM to SPRAM?
115810: 07/02/21: John_H: Re: can I convert DPRAM to SPRAM?
115781: 07/02/20: vlsifresher: Re: can I convert DPRAM to SPRAM?
115801: 07/02/21: vlsifresher: Re: can I convert DPRAM to SPRAM?
115778: 07/02/20: Vladimir Orlic: Selecting device in Project Properties : no XC2V1000?
115779: 07/02/20: Dave Pollum: Re: Selecting device in Project Properties : no XC2V1000?
115793: 07/02/20: <frank_logic@yahoo.com>: Re: Selecting device in Project Properties : no XC2V1000?
115795: 07/02/20: Peter Alfke: Re: Selecting device in Project Properties : no XC2V1000?
115800: 07/02/20: <cs_posting@hotmail.com>: Re: Selecting device in Project Properties : no XC2V1000?
115788: 07/02/20: Pablo: PETALINUX AUTO-BOOT
115790: 07/02/20: Patrick: Looking for a superscalar simulator
115791: 07/02/20: ziggy: Spartan-3E Sample Packs
115802: 07/02/21: Surya: RTOS?
115808: 07/02/21: Jules: Re: RTOS?
115803: 07/02/21: vlsi_learner: newbie question
115806: 07/02/21: KJ: Re: newbie question
115807: 07/02/21: Jules: Cyclone II "altsyncram" timing constraints?
115842: 07/02/22: Rob: Re: Cyclone II "altsyncram" timing constraints?
115848: 07/02/22: ALuPin@web.de: Re: Cyclone II "altsyncram" timing constraints?
115849: 07/02/22: RedskullDC: Re: Cyclone II "altsyncram" timing constraints?
115809: 07/02/21: Jules: Re: Theora vs. M-JPEG2000
115816: 07/02/21: vu_5421: nets vs. pads ; constraints question
115828: 07/02/21: John_H: Re: nets vs. pads ; constraints question
115818: 07/02/21: jams: up down lfsr
115819: 07/02/21: motty: Re: up down lfsr
115820: 07/02/21: Austin Lesea: Re: up down lfsr
115822: 07/02/21: Pasacco: how to use STD_LOGIC_VECTOR2
115830: 07/02/21: KJ: Re: how to use STD_LOGIC_VECTOR2
115823: 07/02/21: Neil Steiner: OPB IPIF: write to DIER causing bus timeout
117151: 07/03/23: Neil Steiner: Re: OPB IPIF: write to DIER causing bus timeout
115824: 07/02/21: Teece: Can someone give me some pointers on using ibis models?
115826: 07/02/21: Austin Lesea: Re: Can someone give me some pointers on using ibis models?
115827: 07/02/21: Austin Lesea: Re: Can someone give me some pointers on using ibis models?
115833: 07/02/21: Andrew FPGA: Re: Can someone give me some pointers on using ibis models?
115831: 07/02/21: axr0284: Determine error in asynchronous signal
115832: 07/02/22: Jim Granville: Re: Determine error in asynchronous signal
115834: 07/02/21: Peter Alfke: Re: Determine error in asynchronous signal
115836: 07/02/22: John_H: Re: Determine error in asynchronous signal
115837: 07/02/22: Jim Granville: Re: Determine error in asynchronous signal
115839: 07/02/22: John_H: Re: Determine error in asynchronous signal
115838: 07/02/22: John_H: Re: Determine error in asynchronous signal
115844: 07/02/22: Jim Granville: Re: Determine error in asynchronous signal
115845: 07/02/22: John_H: Re: Determine error in asynchronous signal
115847: 07/02/22: Jim Granville: Re: Determine error in asynchronous signal
115863: 07/02/22: John_H: Re: Determine error in asynchronous signal
115840: 07/02/21: Tim Wescott: Re: Determine error in asynchronous signal
115854: 07/02/22: axr0284: Re: Determine error in asynchronous signal
115859: 07/02/22: Peter Alfke: Re: Determine error in asynchronous signal
115876: 07/02/22: axr0284: Re: Determine error in asynchronous signal
115841: 07/02/21: <dipumisc@hotmail.com>: Using Xilinx DCM FX output without DLL
115843: 07/02/21: Austin: Re: Using Xilinx DCM FX output without DLL
115862: 07/02/22: johnp: Re: Using Xilinx DCM FX output without DLL
115846: 07/02/21: Sandip: VHDL code for Generating registers
115852: 07/02/22: KJ: Re: VHDL code for Generating registers
115864: 07/02/22: Dave Pollum: Re: VHDL code for Generating registers
115853: 07/02/22: <lkjrsy@gmail.com>: porting virtex2-pro into virtex4. Performance!!
115855: 07/02/22: Sean Durkin: Re: porting virtex2-pro into virtex4. Performance!!
115875: 07/02/22: Sean Durkin: Re: porting virtex2-pro into virtex4. Performance!!
115887: 07/02/23: Ralf Hildebrandt: Re: porting virtex2-pro into virtex4. Performance!!
115866: 07/02/22: JK: Re: porting virtex2-pro into virtex4. Performance!!
115860: 07/02/22: David: MicroBlaze and OPB block ram interface controller run at different frequency
115861: 07/02/22: David: MicroBlaze and OPB block ram interface controller run at different frequency
115882: 07/02/23: Göran Bilski: Re: MicroBlaze and OPB block ram interface controller run at different frequency
115891: 07/02/23: cathy: Re: MicroBlaze and OPB block ram interface controller run at different frequency
115868: 07/02/22: mahdi: 2x technique
115871: 07/02/22: Ben Twijnstra: Re: 2x technique
115888: 07/02/23: Ralf Hildebrandt: Re: 2x technique
115884: 07/02/22: mahdi: Re: 2x technique
115869: 07/02/22: mahdi: internal DCM
115872: 07/02/22: Ben Twijnstra: Re: internal DCM
115873: 07/02/22: davide: Re: internal DCM
115874: 07/02/22: Brad Smallridge: Re: internal DCM
115897: 07/02/23: Brad Smallridge: Re: internal DCM
115883: 07/02/22: mahdi: Re: internal DCM
115877: 07/02/22: John_H: Structured ASIC players
115878: 07/02/23: Jim Granville: Re: Structured ASIC players
115879: 07/02/22: Austin: Re: Structured ASIC players
115881: 07/02/23: Jim Granville: Re: Structured ASIC players
115880: 07/02/22: dang_hut@yahoo.com: Need help to buy first FPGA board!
115885: 07/02/23: Dominik Domanski: Chipscope with Spartan 3E Starter Kit
115886: 07/02/23: Andrea05: Not power of two BRAM size problem
115892: 07/02/23: Paulo Dutra: Re: Not power of two BRAM size problem
115895: 07/02/23: Andrea05: Re: Not power of two BRAM size problem
115954: 07/02/26: <jetmarc@hotmail.com>: Re: Not power of two BRAM size problem
115889: 07/02/23: VHDL_HELP: help for video compression
115890: 07/02/23: Andreas Ehliar: SystemVerilog?
115894: 07/02/23: John_H: Re: SystemVerilog?
115898: 07/02/23: HT-Lab: Re: SystemVerilog?
115899: 07/02/24: Andreas Ehliar: Re: SystemVerilog?
115982: 07/02/27: HT-Lab: Re: SystemVerilog?
115893: 07/02/23: Chris Murphy: Small FPGA Dev Board with Ethernet
115896: 07/02/23: John_H: Re: Small FPGA Dev Board with Ethernet
115900: 07/02/24: Thorsten Trenz: Re: Small FPGA Dev Board with Ethernet
115901: 07/02/24: Marc Kelly: Interfacing to 10Gig ethernet with Xilinx FPGAs
115902: 07/02/24: Austin: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115905: 07/02/24: Marc Kelly: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115963: 07/02/26: Jeff Cunningham: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115907: 07/02/24: Marc Kelly: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115904: 07/02/24: Alain: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115906: 07/02/24: Alain: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115989: 07/02/27: Torsten Landschoff: High throughput TCP/IP on Xilinx FPGA
115903: 07/02/24: Brandon Jasionowski: How to specify ISE INST constraint with GENERATE statements?
115909: 07/02/24: Jim Wu: Re: How to specify ISE INST constraint with GENERATE statements?
115911: 07/02/24: Brandon Jasionowski: Re: How to specify ISE INST constraint with GENERATE statements?
115912: 07/02/25: Brian Drummond: Re: How to specify ISE INST constraint with GENERATE statements?
115908: 07/02/24: El-Mehdi Taileb: MIG 1.6 on ISE9.1i
115910: 07/02/25: Michael Gernoth: Xilinx Platform cable USB and impact on linux without windrvr
115913: 07/02/25: Andreas Ehliar: Re: Xilinx Platform cable USB and impact on linux without windrvr
115933: 07/02/26: Andreas Ehliar: Re: Xilinx Platform cable USB and impact on linux without windrvr
115929: 07/02/26: Guenter: Re: Xilinx Platform cable USB and impact on linux without windrvr
115988: 07/02/27: Torsten Landschoff: Re: Xilinx Platform cable USB and impact on linux without windrvr
116476: 07/03/09: Grant Likely: Re: Xilinx Platform cable USB and impact on linux without windrvr
116586: 07/03/13: Sylvain Munaut: Re: Xilinx Platform cable USB and impact on linux without windrvr
116638: 07/03/14: Michael Gernoth: Re: Xilinx Platform cable USB and impact on linux without windrvr
117116: 07/03/23: Sean Durkin: Re: Xilinx Platform cable USB and impact on linux without windrvr
116770: 07/03/17: Luzerne: Re: Xilinx Platform cable USB and impact on linux without windrvr
117080: 07/03/22: Uwe Bonnes: Re: Xilinx Platform cable USB and impact on linux without windrvr
117108: 07/03/23: Michael Gernoth: Re: Xilinx Platform cable USB and impact on linux without windrvr
117101: 07/03/22: <carlos.asmat@gmail.com>: Re: Xilinx Platform cable USB and impact on linux without windrvr
117107: 07/03/23: Michael Gernoth: Re: Xilinx Platform cable USB and impact on linux without windrvr
117103: 07/03/23: Luzerne: Re: Xilinx Platform cable USB and impact on linux without windrvr
117169: 07/03/25: <carlos.asmat@gmail.com>: Re: Xilinx Platform cable USB and impact on linux without windrvr
117179: 07/03/25: Luzerne: Re: Xilinx Platform cable USB and impact on linux without windrvr
117305: 07/03/27: Luzerne: Re: Xilinx Platform cable USB and impact on linux without windrvr
159073: 16/07/25: <adityaishwar1994@gmail.com>: Re: Xilinx Platform cable USB and impact on linux without windrvr
159078: 16/07/26: Johann Klammer: Re: Xilinx Platform cable USB and impact on linux without windrvr
160268: 17/10/01: <roman.eberle@arcor.de>: Re: Xilinx Platform cable USB and impact on linux without windrvr
160269: 17/10/01: Jon Elson: Re: Xilinx Platform cable USB and impact on linux without windrvr
160271: 17/10/06: rndhro: Re: Xilinx Platform cable USB and impact on linux without windrvr
160272: 17/10/06: Jan Coombs: Re: Xilinx Platform cable USB and impact on linux without windrvr
115914: 07/02/25: Bhanu Chandra: Making a 32KB BRAM block, virtex-4
115916: 07/02/25: KJ: Re: Making a 32KB BRAM block, virtex-4
115918: 07/02/26: MikeJ: Re: Making a 32KB BRAM block, virtex-4
115919: 07/02/25: Ray Andraka: Re: Making a 32KB BRAM block, virtex-4
115930: 07/02/26: KJ: Re: Making a 32KB BRAM block, virtex-4
115961: 07/02/26: Tim: Re: Making a 32KB BRAM block, virtex-4
116004: 07/02/27: Ray Andraka: Re: Making a 32KB BRAM block, virtex-4
116007: 07/02/27: Tim: Re: Making a 32KB BRAM block, virtex-4
116010: 07/02/27: Ray Andraka: Re: Making a 32KB BRAM block, virtex-4
116012: 07/02/27: John_H: Re: Making a 32KB BRAM block, virtex-4
116015: 07/02/28: Tim: Re: Making a 32KB BRAM block, virtex-4
116059: 07/02/28: Daniel S.: Re: Making a 32KB BRAM block, virtex-4
116067: 07/03/01: Tim: Re: Making a 32KB BRAM block, virtex-4
116158: 07/03/02: Daniel S.: Re: Making a 32KB BRAM block, virtex-4
116159: 07/03/02: Peter Alfke: Re: Making a 32KB BRAM block, virtex-4
115915: 07/02/25: Bhanu Chandra: Making a 32KB BRAM block, virtex-4
115917: 07/02/25: Mohamed Bakr: Bluetooth standard in software defined radio
115920: 07/02/25: Venu: OPB BRAM not detected in EDK
115921: 07/02/25: <mahenreddy@gmail.com>: Edge vs Level triggering
115922: 07/02/25: Peter Alfke: Re: Edge vs Level triggering
115924: 07/02/25: Steve Battazzo: Xilinx ISE webpack in Ubuntu?
115926: 07/02/26: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
115935: 07/02/26: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
116021: 07/02/27: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
115932: 07/02/26: <jonas@mit.edu>: Re: Xilinx ISE webpack in Ubuntu?
115977: 07/02/27: Luzerne: Re: Xilinx ISE webpack in Ubuntu?
116020: 07/02/27: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
115992: 07/02/27: <jonas@mit.edu>: Re: Xilinx ISE webpack in Ubuntu?
115996: 07/02/27: <joerg@zilium.de>: Re: Xilinx ISE webpack in Ubuntu?
116136: 07/03/02: Andreas Ehliar: Re: Xilinx ISE webpack in Ubuntu?
116138: 07/03/02: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
116155: 07/03/02: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
116183: 07/03/03: Steve Battazzo: Re: Xilinx ISE webpack in Ubuntu?
116140: 07/03/02: Luzerne: Re: Xilinx ISE webpack in Ubuntu?
116156: 07/03/02: <aholtzma@gmail.com>: Re: Xilinx ISE webpack in Ubuntu?
117631: 07/04/05: <zelixor@gmail.com>: Re: Xilinx ISE webpack in Ubuntu?
117824: 07/04/11: <zelixor@gmail.com>: Re: Xilinx ISE webpack in Ubuntu?
115927: 07/02/26: Uwe Bonnes: XC3S400 and XC3S500E in PQ208
115942: 07/02/26: Josep Duran: Re: XC3S400 and XC3S500E in PQ208
116003: 07/02/27: Nico Coesel: Re: XC3S400 and XC3S500E in PQ208
115972: 07/02/26: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: XC3S400 and XC3S500E in PQ208
115980: 07/02/27: Uwe Bonnes: Re: XC3S400 and XC3S500E in PQ208
116036: 07/02/28: Symon: Re: XC3S400 and XC3S500E in PQ208
116039: 07/02/28: Tim: Re: XC3S400 and XC3S500E in PQ208
116060: 07/03/01: Symon: Re: XC3S400 and XC3S500E in PQ208
116065: 07/03/01: Tim: Re: XC3S400 and XC3S500E in PQ208
116153: 07/03/02: Symon: Re: XC3S400 and XC3S500E in PQ208
116120: 07/03/01: Uwe Bonnes: Re: XC3S400 and XC3S500E in PQ208
116122: 07/03/02: Jim Granville: Re: XC3S400 and XC3S500E in PQ208
116125: 07/03/01: Uwe Bonnes: Re: XC3S400 and XC3S500E in PQ208
116075: 07/02/28: Josep Duran: Re: XC3S400 and XC3S500E in PQ208
115931: 07/02/26: MotM: Xilinx platform cable USB API?
115934: 07/02/26: Andreas Ehliar: Re: Xilinx platform cable USB API?
116023: 07/02/27: Eric Smith: Re: Xilinx platform cable USB API?
116026: 07/02/27: Eric Smith: Re: Xilinx platform cable USB API?
116027: 07/02/28: Andreas Ehliar: Re: Xilinx platform cable USB API?
116033: 07/02/28: Sylvain Munaut: Re: Xilinx platform cable USB API?
116024: 07/02/27: <cs_posting@hotmail.com>: Re: Xilinx platform cable USB API?
116028: 07/02/28: Torsten Landschoff: Re: Xilinx platform cable USB API?
115936: 07/02/26: jim: Virtex 4, how do I generate 100khz clock
115937: 07/02/26: Peter Alfke: Re: Virtex 4, how do I generate 100khz clock
115938: 07/02/26: Austin Lesea: Re: Virtex 4, how do I generate 100khz clock
115948: 07/02/26: Symon: Re: Virtex 4, how do I generate 100khz clock
115939: 07/02/26: self: ML501 Platform Flash Configuration
115969: 07/02/26: Ed McGettigan: Re: ML501 Platform Flash Configuration
116037: 07/02/28: self: Re: ML501 Platform Flash Configuration
115940: 07/02/26: Antti: Spartan-3AN
115943: 07/02/26: Antti: Re: Spartan-3AN
115947: 07/02/26: Austin Lesea: Re: Spartan-3AN
115951: 07/02/26: Austin Lesea: Re: Spartan-3AN
115953: 07/02/26: nospam: Re: Spartan-3AN
115944: 07/02/26: Antti: Re: Spartan-3AN
115945: 07/02/26: -jg: Re: Spartan-3AN
115949: 07/02/26: Antti: Re: Spartan-3AN
115950: 07/02/26: Antti: Re: Spartan-3AN
115955: 07/02/26: Antti: Re: Spartan-3AN
115956: 07/02/26: Austin Lesea: Re: Spartan-3AN
115957: 07/02/26: Peter Alfke: Re: Spartan-3AN
115962: 07/02/26: Eli Hughes: Re: Spartan-3AN
115964: 07/02/26: Nico Coesel: Re: Spartan-3AN
115983: 07/02/27: <lb.edc@telenet.be>: Re: Spartan-3AN
115985: 07/02/27: Tim: Re: Spartan-3AN
115990: 07/02/27: Sean Durkin: Re: Spartan-3AN
115994: 07/02/27: <lb.edc@telenet.be>: Re: Spartan-3AN
116001: 07/02/28: Jim Granville: Re: Spartan-3AN
116061: 07/03/01: <lb.edc@telenet.be>: Re: Spartan-3AN
116063: 07/03/01: Jim Granville: Re: Spartan-3AN
115959: 07/02/26: Antti: Re: Spartan-3AN
115965: 07/02/26: -jg: Re: Spartan-3AN
115966: 07/02/26: Antti: Re: Spartan-3AN
115970: 07/02/26: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3AN
115978: 07/02/27: Uwe Bonnes: Re: Spartan-3AN
116005: 07/02/27: Nico Coesel: Re: Spartan-3AN
116006: 07/02/27: Tim: Re: Spartan-3AN
116008: 07/02/27: Austin Lesea: Re: Spartan-3AN
116009: 07/02/27: Uwe Bonnes: Re: Spartan-3AN
116011: 07/02/28: Tim: Re: Spartan-3AN
116013: 07/02/27: John_H: Re: Spartan-3AN
116017: 07/02/28: Tim: Re: Spartan-3AN
116058: 07/02/28: Ray Andraka: Re: Spartan-3AN
116014: 07/02/27: Austin Lesea: Re: Spartan-3AN
116076: 07/03/01: doug: Re: Spartan-3AN
115971: 07/02/26: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3AN
115999: 07/02/27: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3AN
116002: 07/02/27: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3AN
116073: 07/02/28: Steve Knapp (Xilinx Spartan-3 Generation FPGAs): Re: Spartan-3AN
115941: 07/02/26: <prasad.anirudh@gmail.com>: Virtex 4
115946: 07/02/26: Austin Lesea: Re: Virtex 4
115968: 07/02/27: John Williams: Re: Virtex 4
117499: 07/04/02: <prasad.anirudh@gmail.com>: Re: Virtex 4
115952: 07/02/26: self: Spartan-3AN
115958: 07/02/26: Brandon Jasionowski: OFFSET and Data Clock Skew?
116943: 07/03/21: kislo: Re: OFFSET and Data Clock Skew?
115960: 07/02/26: Mr B: Redundancy
115967: 07/02/26: John_H: Re: Redundancy
115973: 07/02/26: <aiiadict@gmail.com>: spartan 3E USB port... use for i/o instead of programming
115979: 07/02/27: Uwe Bonnes: Re: spartan 3E USB port... use for i/o instead of programming
115998: 07/02/27: Matthew Hicks: Re: spartan 3E USB port... use for i/o instead of programming
115974: 07/02/26: skyworld: $recovery
115976: 07/02/27: Benjamin Todd: Re: $recovery
116100: 07/03/01: Benjamin Todd: Re: $recovery
116069: 07/02/28: skyworld: Re: $recovery
116134: 07/03/01: skyworld: Re: $recovery
115981: 07/02/27: <robquigley@gmail.com>: Modelsim (errno = ENOSPC) error
115984: 07/02/27: HT-Lab: Re: Modelsim (errno = ENOSPC) error
116040: 07/02/28: Weng Tianxiang: Re: Modelsim (errno = ENOSPC) error
115986: 07/02/27: Pawel Piotr Czapski, SP5EPD: Xilinx and archive of Teaching Materials
115987: 07/02/27: Pawel Piotr Czapski, SP5EPD: Handel-C, multiple clock domains, and PAL library
115991: 07/02/27: <lkjrsy@gmail.com>: How can we know how many BRAM are used?
115995: 07/02/27: Jeff Cunningham: Re: How can we know how many BRAM are used?
115993: 07/02/27: ANIL CELEBI: ISE:Simulation
115997: 07/02/27: Joseph Samson: Re: ISE:Simulation
116000: 07/02/27: AG: Altera PowerPlay Power estimation
116475: 07/03/09: <mvaria@gmail.com>: Re: Altera PowerPlay Power estimation
116016: 07/02/27: <heliboy2003@yahoo.com.tw>: [Q] Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
116018: 07/02/27: <heliboy2003@yahoo.com.tw>: Re: Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
116022: 07/02/28: Rob: Spartan MicroBlaze
116025: 07/02/28: Zara: Re: Spartan MicroBlaze
116032: 07/02/28: Andreas Hofmann: Re: Spartan MicroBlaze
116070: 07/03/01: John Williams: Re: Spartan MicroBlaze
116038: 07/02/28: Rob: Re: Spartan MicroBlaze
116029: 07/02/28: <lkjrsy@gmail.com>: How to implement pipeline in this case?
116064: 07/02/28: Derek Simmons: Re: How to implement pipeline in this case?
116030: 07/02/28: <lkjrsy@gmail.com>: How to implement pipeline in this case?
116031: 07/02/28: Martin Thompson: Re: How to implement pipeline in this case?
116068: 07/02/28: Daniel S.: Re: How to implement pipeline in this case?
116085: 07/03/01: Mike Treseler: Re: How to implement pipeline in this case?
116160: 07/03/02: Daniel S.: Re: How to implement pipeline in this case?
116161: 07/03/02: Mike Treseler: Re: How to implement pipeline in this case?
116250: 07/03/05: Daniel S.: Re: How to implement pipeline in this case?
116299: 07/03/06: Tim: Re: How to implement pipeline in this case?
116302: 07/03/06: Daniel S.: Re: How to implement pipeline in this case?
116312: 07/03/07: Daniel S.: Re: How to implement pipeline in this case?
116295: 07/03/06: Attila Kinali: Re: How to implement pipeline in this case?
116297: 07/03/06: Daniel S.: Re: How to implement pipeline in this case?
116402: 07/03/08: Jim Lewis: Re: How to implement pipeline in this case?
116298: 07/03/06: Patrick Dubois: Re: How to implement pipeline in this case?
116303: 07/03/06: Patrick Dubois: Re: How to implement pipeline in this case?
116305: 07/03/06: Patrick Dubois: Re: How to implement pipeline in this case?
116356: 07/03/07: Attila Kinali: Re: How to implement pipeline in this case?
116360: 07/03/07: Patrick Dubois: Re: How to implement pipeline in this case?
116034: 07/02/28: comp.arch.fpga: Virtex 4 FX Sonet Alignment
116043: 07/02/28: Ed McGettigan: Re: Virtex 4 FX Sonet Alignment
116062: 07/03/01: <lb.edc@telenet.be>: Re: Virtex 4 FX Sonet Alignment
116044: 07/02/28: comp.arch.fpga: Re: Virtex 4 FX Sonet Alignment
116090: 07/03/01: comp.arch.fpga: Re: Virtex 4 FX Sonet Alignment
116094: 07/03/01: comp.arch.fpga: Re: Virtex 4 FX Sonet Alignment
116104: 07/03/01: comp.arch.fpga: Re: Virtex 4 FX Sonet Alignment
116035: 07/02/28: Patrick Dubois: SCons build tool as an alternative to makefiles
116081: 07/03/01: Martin Thompson: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
116146: 07/03/02: Martin Thompson: Re: Potential problem in batch files for Xilinx
116218: 07/03/05: Martin Thompson: Re: Potential problem in batch files for Xilinx
116219: 07/03/05: Martin Thompson: Re: Potential problem in batch files for Xilinx
116316: 07/03/07: Martin Thompson: Re: Potential problem in batch files for Xilinx
116086: 07/03/01: Patrick Dubois: Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
116152: 07/03/02: <aholtzma@gmail.com>: Re: Potential problem in batch files for Xilinx
116157: 07/03/02: Jim Wu: Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
116226: 07/03/05: Patrick Dubois: Re: SCons build tool as an alternative to makefiles
116286: 07/03/06: Martin Thompson: Re: SCons build tool as an alternative to makefiles
116317: 07/03/07: Martin Thompson: Re: SCons build tool as an alternative to makefiles
116389: 07/03/08: Martin Thompson: Re: SCons build tool as an alternative to makefiles
116293: 07/03/06: Jim Wu: Re: Potential problem in batch files for Xilinx
116296: 07/03/06: Patrick Dubois: Re: SCons build tool as an alternative to makefiles
116331: 07/03/07: Patrick Dubois: Re: SCons build tool as an alternative to makefiles
116041: 07/02/28: radarman: Can write, can't read with OPB_SPI 1.00e
116050: 07/02/28: radarman: Re: Can write, can't read with OPB_SPI 1.00e
116042: 07/02/28: Marlboro: Xilinx USB flatform cable length mistery ?
116045: 07/02/28: <cs_posting@hotmail.com>: Re: Xilinx USB flatform cable length mistery ?
116047: 07/02/28: davide: Re: Xilinx USB flatform cable length mistery ?
116053: 07/02/28: davide: Re: Xilinx USB flatform cable length mistery ?
116056: 07/02/28: Austin Lesea: Re: Xilinx USB flatform cable length mistery ?
116048: 07/02/28: Marlboro: Re: Xilinx USB flatform cable length mistery ?
116046: 07/02/28: B. Joshua Rosen: Altera Byte Blaster Cable on Linux
116049: 07/02/28: <cs_posting@hotmail.com>: Re: Altera Byte Blaster Cable on Linux
116051: 07/02/28: General Schvantzkoph: Re: Altera Byte Blaster Cable on Linux
116052: 07/02/28: <mtsukanov@gmail.com>: what does a 'blank check' do exactly
116054: 07/02/28: John_H: Re: what does a 'blank check' do exactly
116057: 07/03/01: Jim Granville: Re: what does a 'blank check' do exactly
116066: 07/03/01: Tim: Re: what does a 'blank check' do exactly
116087: 07/03/01: John_H: Re: what does a 'blank check' do exactly
116101: 07/03/01: Tim: Re: what does a 'blank check' do exactly
116105: 07/03/01: John_H: Re: what does a 'blank check' do exactly
116118: 07/03/01: John_H: Re: what does a 'blank check' do exactly
116121: 07/03/02: Jim Granville: Re: what does a 'blank check' do exactly
116084: 07/03/01: <mtsukanov@gmail.com>: Re: what does a 'blank check' do exactly
116093: 07/03/01: <mtsukanov@gmail.com>: Re: what does a 'blank check' do exactly
116095: 07/03/01: <cs_posting@hotmail.com>: Re: what does a 'blank check' do exactly
116098: 07/03/01: <mtsukanov@gmail.com>: Re: what does a 'blank check' do exactly
116116: 07/03/01: <mtsukanov@gmail.com>: Re: what does a 'blank check' do exactly
116119: 07/03/01: <mtsukanov@gmail.com>: Re: what does a 'blank check' do exactly
116055: 07/02/28: TC: Re: PCI-E TS1s
116091: 07/03/01: Fred: Re: PCI-E TS1s
116130: 07/03/02: TC: Re: PCI-E TS1s
116071: 07/02/28: <raju.penum@gmail.com>: Where can i get free CAN VHDL core
116078: 07/03/01: <rponsard@gmail.com>: Re: Where can i get free CAN VHDL core
116079: 07/03/01: Colin Paul Gloster: Re: Where can i get free CAN VHDL core
116128: 07/03/01: Tom: Re: Where can i get free CAN VHDL core
116139: 07/03/02: raju: Re: Where can i get free CAN VHDL core
116072: 07/02/28: Brandon Jasionowski: Regional Clock Network and Large Designs
116082: 07/03/01: John McCaskill: Re: Regional Clock Network and Large Designs
116106: 07/03/01: Brandon Jasionowski: Re: Regional Clock Network and Large Designs
116127: 07/03/01: Jim Wu: Re: Regional Clock Network and Large Designs
116074: 07/02/28: huangjie: what about dma scatter /gather support in xilinx edk ipif ?
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