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Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1 Evaluation Software. Now it has expired and I cannot design for hardware arquitecture. Does anybody resolve it?? That is, is some method or crack for this?? Another possibility: Is there another platform (free) for designing with this FPGA?? Thanks.Article: 115401
On a sunny day (9 Feb 2007 03:55:10 -0800) it happened "gauckler" <gauckler@fh-furtwangen.de> wrote in <1171022110.232002.251470@a75g2000cwd.googlegroups.com>: > >Solved !! Installation succeeded !! > >I doubled ram to 1GB, I increased swap partition to 5G and I changed >openSuSE 10.2 Distribution >from easyLinux to Novel Distribution. > > Andreas Did you also change your shoes? If so, then that was it.Article: 115402
Peter, I don't want to build the LUT out of 4 and 5 input LUTs :) I would agree about using the BlockRAM, I guess I was looking for a more generic statement of the form "if you have a 2^n x m LUT (in my case 2^8 x 8), you can expect the access time to be f(n,m) levels of logic" regardless of technology/use of BlockRAM. The real question becomes what is f(n,m), ie can I say something like for a 2^8 x 8 LUT it will be log_2_(2^8) = 8 levels of logic or something like that? Thanks again! Adam On Feb 9, 1:20 am, "Peter Alfke" <a...@sbcglobal.net> wrote: > Your example is a 256 x 8 = 2048 bit LUT, which is best implemented in > a Xilinx BlockRAM. > The BlockRAM is a synchronous device, so it has a specified address > set-up time and a specified clock-to-out time. There is only one level > of such delays. The multi-level decoding delay is hidden in the > BlockRAM access time. > If you want to implement such a LUT in 4-input LUTs, you need more > than 128 LUTs and probably 5 layers of LUT delays, but a clock is not > necessary > Virtex-5 has 6-input LUTs,and you need only 40 LUTs total, with a two- > LUT combinatorial delay, and no clock. > Your choice. > Peter Alfke, Xilinx > ================== > > AdamE wrote: > > Is there a standard used for look-up table access time in terms of > > levels of logic? As an example, if I have a 2^8 x 8 look-up table (8- > > bit to 8-bit), how many levels of logic are required to perform the > > look-up operation or is the table considered to be just one level of > > SRAM? > > > Thanks! > > > AdamArticle: 115403
Peter Alfke wrote: >> Yep. That's the what you have to do. All other routes lead to madness. >> Synchronize the incoming signals and as much of the rest as possible. I >> would look hard at making the FIFO synchronous. > > Since you have to synchronize to a new clock anyhow, make the whole > FIFO synchronous (same clock for write and read, but with separate > Enables). That makes the FIFO design very simple, and avoids all the > tricky circuitry requires for asynchronous operation. OK, I am using the Xilinx core so the complexity of it's internal design doesn't bother me much :) I'll do as you suggest though as it makes sense to avoid the potential testing pitfalls :) Thanks for the input. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 115404
On Feb 9, 5:22 am, jetm...@hotmail.com wrote: > > fifo_full -> [combinational logic] -> usr_tx_ack -> next_st > > (combinational logic) -> curr_st (register) > > > Any ideas why it's reporting the path this way? > > Maybe you're looking at the wrong path. To me it looks as if the > report is about doing a FIFO write from one of your states. > > Regards > Marc That's what it looks like, but no path like that exists. The signal usr_tx_ack is connected to the read enable of the FIFO: fifo_rd_en <= usr_tx_ack; Makes no sense to me. The write condition of the fifo is completely unrelated to my FSM. Could this be some sort of false path?Article: 115405
On Feb 9, 5:22 am, jetm...@hotmail.com wrote: > > fifo_full -> [combinational logic] -> usr_tx_ack -> next_st > > (combinational logic) -> curr_st (register) > > > Any ideas why it's reporting the path this way? > > Maybe you're looking at the wrong path. To me it looks as if the > report is about doing a FIFO write from one of your states. > > Regards > Marc No, it's definitely a fifo read. The fifo write path is completely unrelated to the FSM. I'm not sure why the delays are so large on this read enable path to the FIFO. Seems odd... 0.195+1.052+0.194+1.641+0.518 = 3.6 ns Clues? Possible optimization options?Article: 115406
Hi Does anyone here know, how to explicitly set which VHDL standard should be used by Xilinx ISE (actually, by XST I think)? Cheers WojtekArticle: 115407
you don't need the XPS/EDK to get going, just download Webpack http://www.xilinx.com/ise/logic_design_prod/webpack.htm Dig out the examples from the xilinx web-site and use them as a framework for whatever you're building. http://www.xilinx.com/s3estarter Unless you're using some fancy stuff that needs the EDK/XPS. Ben "Pablo" <pbantunez@gmail.com> wrote in message news:1171023946.472850.59840@v33g2000cwv.googlegroups.com... > Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1 > Evaluation Software. Now it has expired and I cannot design for > hardware arquitecture. Does anybody resolve it?? That is, is some > method or crack for this?? > > Another possibility: Is there another platform (free) for designing > with this FPGA?? > > Thanks. >Article: 115408
Greetings! I have a question regarding applications running on embedded Linux on an ML310. Getting things to work under standalone has been fairly easy with my custom hardware (just a little pulse counter generating interrupts on each pulse, in Verilog). I want to make a jump to running this same application (that really just handles the interrupts and reads the register that holds the counter value) to MontaVista Linux on one of the PPCs in the V2Pro. The thing is that the BSP is pretty different for Linux as the OS than standalone, so all the header files are in different places or not even there. I've been instructed to cross-compile the application on the host machine (which I know I can do), but do I have to know how to handle interrupts under Linux (like, by reading O'Reilly's Linux Device Drivers) to be able to run this application properly? For example, xexception_l.h wasn't copied to my project directory, which I needed for standalone, but I don't know what to replace it with for interrupt handling under Linux. It seems like doing things for embedded Linux is a completely different monster. And I'm pretty clueless when it comes to the inner workings of Linux. Thanks a ton! ----JD----Article: 115409
On Feb 8, 5:53 pm, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > Hello, > > I can't meet the following constraint after playing around w/ some > synthesis and implementation settings. Any specific advice as it > relates to this delay path? > > I'm also a bit unsure how it's calculating this path. The signals are > connected as follows: > > fifo_full -> [combinational logic] -> usr_tx_ack -> next_st > (combinational logic) -> curr_st (register) > > Any ideas why it's reporting the path this way? > > Thanks, > -Brandon > > ================================================================================ > Timing constraint: TS_clkgen_ifclk200 = PERIOD TIMEGRP > "TG_clkgen_ifclk200" 5 ns HIGH 50%; > > 9757 items analyzed, 50 timing errors detected. (50 setup errors, 0 > hold errors) > Minimum period is 5.630ns. > -------------------------------------------------------------------------------- > Slack: -0.630ns (requirement - (data path - clock > path skew + uncertainty)) > Source: ctrl_inst/curr_st_FFd4 (FF) > Destination: ctrl_inst/fifo_inst/BU2/U0/gen_as.fgas/ > normgen.memblk/mem1nc.coreinst/BU1023 (RAM) > Requirement: 5.000ns > Data Path Delay: 5.435ns (Levels of Logic = 3) > Clock Path Skew: -0.135ns > Source Clock: clkgen_ifclk200 rising at 0.000ns > Destination Clock: clkgen_ifclk200 rising at 5.000ns > Clock Uncertainty: 0.060ns > Timing Improvement Wizard > Data Path: ctrl_inst/curr_st_FFd4 to ctrl_inst/fifo_inst/BU2/U0/ > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023 > Delay type Delay(ns) Logical Resource(s) > ---------------------------- ------------------- > Tcko 0.360 ctrl_inst/curr_st_FFd4 > net (fanout=23) 0.677 ctrl_inst/curr_st_FFd4 > Tilo 0.194 ctrl_inst/curr_st_Out391 > net (fanout=3) 0.604 ctrl_inst/usr_tx_ack > Tilo 0.195 ctrl_inst/fifo_inst/BU2/U0/ > gen_as.fgas/normgen.memblk/tmp_ram_rd_en1 > net (fanout=18) 1.052 ctrl_inst/fifo_inst/BU2/U0/ > gen_as.fgas/normgen.memblk/tmp_ram_rd_en > Tilo 0.194 ctrl_inst/fifo_inst/BU2/U0/ > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU163 > net (fanout=14) 1.641 ctrl_inst/fifo_inst/BU2/U0/ > gen_as.fgas/normgen.memblk/mem1nc.coreinst/N1881 > Trcck_ENB 0.518 ctrl_inst/fifo_inst/BU2/U0/ > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023 > ---------------------------- --------------------------- > Total 5.435ns (1.461ns logic, 3.974ns route) > (26.9% logic, 73.1% route) With 73% of the delay coming from the routing, try constraining the placement. The area group constraint is easy to apply, and has helped me many times. Also, the clock uncertainty looks low, did you add the jitter of your clock source to the period constraint? Are you running your clock through any DCMs? Regards, John McCaskill www.fastertechnology.comArticle: 115410
Brandon Jasionowski wrote: > > No, it's definitely a fifo read The problem here is the long routing delay. > Total 5.435ns (1.461ns logic, 3.974ns route) I'm running 8.1i, and I have been getting good results by using the timing-driven mapping, optimized for speed (optimized for area is the default). I like 'Allow Logic Optimization Across Hierarchy', too. --- Joe Samson Pixel VelocityArticle: 115411
This newsgroup is about FPGAs, and in FPGAs you build your solution out of existing subfunctions, in your case out of RAMs. Such pre-built RAMs have a specified guaranteed worst-case access time, irrespective of the number of address bits (as long as it fits in one RAM). That's why your question has this very simple answer. Peter Alfke =================== On Feb 9, 5:46 am, "AdamE" <aelb...@cs.uml.edu> wrote: > Peter, > > I don't want to build the LUT out of 4 and 5 input LUTs :) I would > agree about using the BlockRAM, I guess I was looking for a more > generic statement of the form "if you have a 2^n x m LUT (in my case > 2^8 x 8), you can expect the access time to be f(n,m) levels of logic" > regardless of technology/use of BlockRAM. The real question becomes > what is f(n,m), ie can I say something like for a 2^8 x 8 LUT it will > be log_2_(2^8) = 8 levels of logic or something like that? > > Thanks again! > > Adam > > On Feb 9, 1:20 am, "Peter Alfke" <a...@sbcglobal.net> wrote: > > > Your example is a 256 x 8 = 2048 bit LUT, which is best implemented in > > a Xilinx BlockRAM. > > The BlockRAM is a synchronous device, so it has a specified address > > set-up time and a specified clock-to-out time. There is only one level > > of such delays. The multi-level decoding delay is hidden in the > > BlockRAM access time. > > If you want to implement such a LUT in 4-input LUTs, you need more > > than 128 LUTs and probably 5 layers of LUT delays, but a clock is not > > necessary > > Virtex-5 has 6-input LUTs,and you need only 40 LUTs total, with a two- > > LUT combinatorial delay, and no clock. > > Your choice. > > Peter Alfke, Xilinx > > ================== > > > AdamE wrote: > > > Is there a standard used for look-up table access time in terms of > > > levels of logic? As an example, if I have a 2^8 x 8 look-up table (8- > > > bit to 8-bit), how many levels of logic are required to perform the > > > look-up operation or is the table considered to be just one level of > > > SRAM? > > > > Thanks! > > > > AdamArticle: 115412
On Feb 9, 10:20 am, "John McCaskill" <junkm...@fastertechnology.com> wrote: > On Feb 8, 5:53 pm, "Brandon Jasionowski" <killerhe...@gmail.com> > wrote: > > > > > Hello, > > > I can't meet the following constraint after playing around w/ some > > synthesis and implementation settings. Any specific advice as it > > relates to this delay path? > > > I'm also a bit unsure how it's calculating this path. The signals are > > connected as follows: > > > fifo_full -> [combinational logic] -> usr_tx_ack -> next_st > > (combinational logic) -> curr_st (register) > > > Any ideas why it's reporting the path this way? > > > Thanks, > > -Brandon > > > ================================================================================ > > Timing constraint: TS_clkgen_ifclk200 = PERIOD TIMEGRP > > "TG_clkgen_ifclk200" 5 ns HIGH 50%; > > > 9757 items analyzed, 50 timing errors detected. (50 setup errors, 0 > > hold errors) > > Minimum period is 5.630ns. > > -------------------------------------------------------------------------------- > > Slack: -0.630ns (requirement - (data path - clock > > path skew + uncertainty)) > > Source: ctrl_inst/curr_st_FFd4 (FF) > > Destination: ctrl_inst/fifo_inst/BU2/U0/gen_as.fgas/ > > normgen.memblk/mem1nc.coreinst/BU1023 (RAM) > > Requirement: 5.000ns > > Data Path Delay: 5.435ns (Levels of Logic = 3) > > Clock Path Skew: -0.135ns > > Source Clock: clkgen_ifclk200 rising at 0.000ns > > Destination Clock: clkgen_ifclk200 rising at 5.000ns > > Clock Uncertainty: 0.060ns > > Timing Improvement Wizard > > Data Path: ctrl_inst/curr_st_FFd4 to ctrl_inst/fifo_inst/BU2/U0/ > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023 > > Delay type Delay(ns) Logical Resource(s) > > ---------------------------- ------------------- > > Tcko 0.360 ctrl_inst/curr_st_FFd4 > > net (fanout=23) 0.677 ctrl_inst/curr_st_FFd4 > > Tilo 0.194 ctrl_inst/curr_st_Out391 > > net (fanout=3) 0.604 ctrl_inst/usr_tx_ack > > Tilo 0.195 ctrl_inst/fifo_inst/BU2/U0/ > > gen_as.fgas/normgen.memblk/tmp_ram_rd_en1 > > net (fanout=18) 1.052 ctrl_inst/fifo_inst/BU2/U0/ > > gen_as.fgas/normgen.memblk/tmp_ram_rd_en > > Tilo 0.194 ctrl_inst/fifo_inst/BU2/U0/ > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU163 > > net (fanout=14) 1.641 ctrl_inst/fifo_inst/BU2/U0/ > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/N1881 > > Trcck_ENB 0.518 ctrl_inst/fifo_inst/BU2/U0/ > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023 > > ---------------------------- --------------------------- > > Total 5.435ns (1.461ns logic, 3.974ns route) > > (26.9% logic, 73.1% route) > > With 73% of the delay coming from the routing, try constraining the > placement. The area group constraint is easy to apply, and has helped > me many times. > > Also, the clock uncertainty looks low, did you add the jitter of your > clock source to the period constraint? Are you running your clock > through any DCMs? > > Regards, > > John McCaskillwww.fastertechnology.com The clock is sourced from a DCM. Do I need to modify the constraint? I thought ISE takes care of this for me...Article: 115413
On Feb 9, 9:42 am, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > On Feb 9, 10:20 am, "John McCaskill" <junkm...@fastertechnology.com> > wrote: > > > > > On Feb 8, 5:53 pm, "Brandon Jasionowski" <killerhe...@gmail.com> > > wrote: > > > > Hello, > > > > I can't meet the following constraint after playing around w/ some > > > synthesis and implementation settings. Any specific advice as it > > > relates to this delay path? > > > > I'm also a bit unsure how it's calculating this path. The signals are > > > connected as follows: > > > > fifo_full -> [combinational logic] -> usr_tx_ack -> next_st > > > (combinational logic) -> curr_st (register) > > > > Any ideas why it's reporting the path this way? > > > > Thanks, > > > -Brandon > > > > ================================================================================ > > > Timing constraint: TS_clkgen_ifclk200 = PERIOD TIMEGRP > > > "TG_clkgen_ifclk200" 5 ns HIGH 50%; > > > > 9757 items analyzed, 50 timing errors detected. (50 setup errors, 0 > > > hold errors) > > > Minimum period is 5.630ns. > > > -------------------------------------------------------------------------------- > > > Slack: -0.630ns (requirement - (data path - clock > > > path skew + uncertainty)) > > > Source: ctrl_inst/curr_st_FFd4 (FF) > > > Destination: ctrl_inst/fifo_inst/BU2/U0/gen_as.fgas/ > > > normgen.memblk/mem1nc.coreinst/BU1023 (RAM) > > > Requirement: 5.000ns > > > Data Path Delay: 5.435ns (Levels of Logic = 3) > > > Clock Path Skew: -0.135ns > > > Source Clock: clkgen_ifclk200 rising at 0.000ns > > > Destination Clock: clkgen_ifclk200 rising at 5.000ns > > > Clock Uncertainty: 0.060ns > > > Timing Improvement Wizard > > > Data Path: ctrl_inst/curr_st_FFd4 to ctrl_inst/fifo_inst/BU2/U0/ > > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023 > > > Delay type Delay(ns) Logical Resource(s) > > > ---------------------------- ------------------- > > > Tcko 0.360 ctrl_inst/curr_st_FFd4 > > > net (fanout=23) 0.677 ctrl_inst/curr_st_FFd4 > > > Tilo 0.194 ctrl_inst/curr_st_Out391 > > > net (fanout=3) 0.604 ctrl_inst/usr_tx_ack > > > Tilo 0.195 ctrl_inst/fifo_inst/BU2/U0/ > > > gen_as.fgas/normgen.memblk/tmp_ram_rd_en1 > > > net (fanout=18) 1.052 ctrl_inst/fifo_inst/BU2/U0/ > > > gen_as.fgas/normgen.memblk/tmp_ram_rd_en > > > Tilo 0.194 ctrl_inst/fifo_inst/BU2/U0/ > > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU163 > > > net (fanout=14) 1.641 ctrl_inst/fifo_inst/BU2/U0/ > > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/N1881 > > > Trcck_ENB 0.518 ctrl_inst/fifo_inst/BU2/U0/ > > > gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023 > > > ---------------------------- --------------------------- > > > Total 5.435ns (1.461ns logic, 3.974ns route) > > > (26.9% logic, 73.1% route) > > > With 73% of the delay coming from the routing, try constraining the > > placement. The area group constraint is easy to apply, and has helped > > me many times. > > > Also, the clock uncertainty looks low, did you add the jitter of your > > clock source to the period constraint? Are you running your clock > > through any DCMs? > > > Regards, > > > John McCaskillwww.fastertechnology.com > > The clock is sourced from a DCM. Do I need to modify the constraint? I > thought ISE takes care of this for me... I am still using EDK/ISE 8.1, so I do not know if this has changed for more recent releases. With 8.1, the timing analyzer does not take the DCMs jitter contributions into account. If you are using the FX mode of a DCM to generate a clock, the jitter can be 100s of ps. If you have specified the jitter of your clock input to to the DCM in your period constraint, that jitter will be modified and propagated to the constraints that are created for the output of the DCM, but the jitter that is added by the DCM is not added to the constraint. I found this out the hard way, and it was a nasty problem. I think that the jitter of the DCMs depends on full the FPGA is and/or how much power it is using. All of my smaller unit test designs would work just fine, and only when I had a very full design would I have problems, and then the only symptom was that Linux would crash with a TLB exception after a while. I was able to work around the issue by over specifying the amount of jitter on the source clock to the DCMs to cause the output DCM clock to be properly specified. Make sure that you have a proper jitter spec on your input clock to the DCM, at 200 MHz the jitter on your oscillator is starting to take a noticeable bite out of you clock period, and so does the DCM. Either Peter or Austin has written several articles about dealing with jitter that are available on the Xilinx web site if you search for them. Regards, John McCaskill www.fastertechnology.comArticle: 115414
To quote Albert Einstein: "Make everything as simple as possible, but not simpler". Good advice! Peter Alfke On Feb 8, 10:03 pm, Daniel O'Connor <dar...@dons.net.au> wrote: > Tim wrote: > > Daniel O'Connor wrote: > >> I am also considering taking the 50MHz clock on my board and multiplying > >> it up to, say, 150MHz and sychronising/one-shotting all of the signals > >> from the other board to that. > > > Yep. That's the what you have to do. All other routes lead to madness. > > Synchronize the incoming signals and as much of the rest as possible. I > > would look hard at making the FIFO synchronous. > > I guess that explains the pounding headaches then ;) > > -- > Daniel O'Connor software and network engineer > for Genesis Software -http://www.gsoft.com.au > "The nice thing about standards is that there > are so many of them to choose from." > -- Andrew Tanenbaum > GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 115415
On Feb 8, 12:29 pm, Ben Jackson <b...@ben.com> wrote: > On 2007-02-08, sant...@gmail.com <sant...@gmail.com> wrote: > > > The problem is that the PORT Intr sees premt_intr > > Is there a way to do this? I would like to keep it very general as it > > is now. Can I do something like: > > PORT Preemption_Interrupt(0) = premt_intr_0 > > PORT Preemption_Interrupt(1) = premt_intr_1 > > Well, you could send all the interrupts to all processors and have > them each ignore the lines they don't care about. > > You could use one of those util_bus_split things (probably more than > one) and whittle off bits. The existance of this Xilinx block makes > me think that generic bus indexing does not work in a MHS file. > > You could make a custom module to split up the bits. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/ Couldn't use util_bus_split because I couldn't specify the output signals (out1 and out2 I think) as interrupt signals. Instead just developed simple custom core. Thanks for the suggestions.Article: 115416
On Feb 8, 12:29 pm, Ben Jackson <b...@ben.com> wrote: > On 2007-02-08, sant...@gmail.com <sant...@gmail.com> wrote: > > > The problem is that the PORT Intr sees premt_intr > > Is there a way to do this? I would like to keep it very general as it > > is now. Can I do something like: > > PORT Preemption_Interrupt(0) = premt_intr_0 > > PORT Preemption_Interrupt(1) = premt_intr_1 > > Well, you could send all the interrupts to all processors and have > them each ignore the lines they don't care about. > > You could use one of those util_bus_split things (probably more than > one) and whittle off bits. The existance of this Xilinx block makes > me think that generic bus indexing does not work in a MHS file. > > You could make a custom module to split up the bits. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/ Couldn't use util_bus_split because I couldn't specify the output signals (out1 and out2 I think) as interrupt signals. Instead just developed simple custom core. Thanks for the suggestions.Article: 115417
Hi, ALL: I have my own design connected with two MBs in the system evaluated on ML501. My design uses the "opb_rst" as its reset signal. I was given the error when tried to generate the .bit file: ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site. The clock IOB component <sys_rst_pin> is placed at site <T23>. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design, you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue. Phase 5.2 (Checksum:98a043) REAL time: 1 mins 44 secs It asked me to put the sys_rst_pin to an optimal clock IOB site. But T23 is the pin for the "cpu reset" button on the board and I need to use it. My question is: 1, why it took the reset signal as a clock signal? I uses if(rst='0') then...elsif(rising_edge(clk)) then... 2, where to set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING? Thanks a lot, CathyArticle: 115418
"Pablo" <pbantunez@gmail.com> writes: > Hello, I bought a Spartan 3E Starter kit which included a XPS 8.1 > Evaluation Software. Now it has expired and I cannot design for > hardware arquitecture. Does anybody resolve it?? That is, is some > method or crack for this?? Yes, a crack for it is available from your Xilinx distributor, for a fee.Article: 115419
On Feb 9, 12:21 pm, sant...@gmail.com wrote: > On Feb 8, 12:29 pm, Ben Jackson <b...@ben.com> wrote: > > > > > On 2007-02-08, sant...@gmail.com <sant...@gmail.com> wrote: > > > > The problem is that the PORT Intr sees premt_intr > > > Is there a way to do this? I would like to keep it very general as it > > > is now. Can I do something like: > > > PORT Preemption_Interrupt(0) = premt_intr_0 > > > PORT Preemption_Interrupt(1) = premt_intr_1 Hi. Are you using XPS? Using multiple interrupts from custom hardware (I'm assuming it's custom) is as simple as making each interrupt line a separate port output from the custom hardware. Import your IP to the project (specifying which ports are your interrupt ports), select your interrupt ports in your custom IP in the System Assembly View: Ports filter, and add each interrupt to each opb_intc instance per processor. It has worked for me using one PPC, adding each interrupt line to one opb_intc instance. I haven't tried combining all of the interrupts into one ports and breaking off each line of the port. I think the former way is simpler. Basically, break out your interrupt lines from the vector in your HDL to be separate ports (instead of Preemption_Interrupt : out std_logic_vector(0 to C_NUM_CPUS - 1), let them be Preemption_Interrupt_0 : out std_logic; ..._1, ..._2, ..._3, etc.), and then connect them separately to each opb_intc instance. Hopefully that works! If you could, please let me know if it does not. ----JD----Article: 115420
cathy wrote: > 2, where to set the environment variable > XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING? Assuming that you are using windows, try: Start -> Settings -> Control Panel -> System This gets you to the system control panel. Choose the 'Advanced' tab Click the 'Environmental Variables' button The Environmental Variables dialog shows two group boxes, one for user variables, and one for system variables. I put the XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING in both. click the New button put XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING as the variable name put 1 as the variable value --- Joe Samson Pixel VelocityArticle: 115421
On Feb 9, 2:09 pm, Joseph Samson <jsam...@the-company-name.com> wrote: > cathy wrote: > > 2, where to set the environment variable > > XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING? > > Assuming that you are using windows, try: > Start -> Settings -> Control Panel -> System > > This gets you to the system control panel. > > Choose the 'Advanced' tab > > Click the 'Environmental Variables' button > > The Environmental Variables dialog shows two group boxes, one for user > variables, and one for system variables. I put the > XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING in both. > > click the New button > put XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING as the variable name > > put 1 as the variable value > > --- > Joe Samson > Pixel Velocity Thank you very much.Article: 115422
Wojtek, The XST Users Guide gives specific details on which VHDL standard XST supports (and those that are conflicts). See the UG located here: http://toolbox.xilinx.com/docsan/xilinx9/books/docs/xst/xst.pdf I do not believe that there is a way to specify the exact standard that you may want to use. Verilog 2001 appears to be the only HDL standard that is selectable within the synthesis options. -David "wojt" <wojtek.bocer@gmail.com> wrote in message news:1171033608.993210.85410@a75g2000cwd.googlegroups.com... > Hi > > Does anyone here know, how to explicitly set which VHDL standard > should be used by Xilinx ISE (actually, by XST I think)? > > Cheers > Wojtek >Article: 115423
Hi, I am trying to establish communication between PC and Virtex4 FX 12 mini module from www.memec.com.As I am new to this task I am really not sure where to start.Can some one suggest me what is the starting point to this one. Things I would like to know are,Do I need any knowledge of networking(ethernet communication) protocols for understanding the operation of Tri mode EMAC core?Once I generate the core using Xilinx core generator it is generating an example design, What parts do I need to modify so that I can use it for my designs?It is generating lot of VHDL files and I don't know where my design will fit into this? Can somone kindly suggest and help me with this issue. Thanks for the response, Ramakrishna BachimachiArticle: 115424
gauckler <gauckler@fh-furtwangen.de> wrote: > On 8 Feb., 08:26, "Andreas Gauckler" <gauck...@fh-furtwangen.de> > wrote: > > Hello > > > > yesterday I ' ve tried to install ISE 9.1 on a openSuSE 10.2 system. > > Unfortunately the installation crashs after about 60% without messages. > > > > I tried a different installation source -- same result. > > > > Has someone any experience with openSuSE 10.2 and Xilinx ISE 9.1 > > installation ? > > > > Best regards > > > > Andreas > Solved !! Installation succeeded !! > I doubled ram to 1GB, I increased swap partition to 5G and I changed > openSuSE 10.2 Distribution > from easyLinux to Novel Distribution. Look for my message: " Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2) " ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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