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On 2007-03-28, Ace <yasirmm@gmail.com> wrote: > Hello everyone, > > Please help. What is the maximum clock frequency that can be used on a > Spartan-3 5000? I know it's a grade -4 speed but I couldn't find any > documentation regarding it. It depends on what you want to do with it. If all you are interested in is one long shift register you can run it extremely fast as an approximation. If you want to run a complex superscalar microprocessor in it with a three stage pipeline then you can run it extremely slow as an approximation... Most designs will fall somewhere in between. Remember that you are constructing a circuit here and depending on the circuit you build you will get different delays. It is totally possible to build a combinatorial path that will span every single LUT of the chip. Not a good idea, but possible :) (So I guess it would be possible to calculate a theoretical minimum frequency by doing a path which would go through every LUT and place the LUTs as badly as possible so the routing delays are maximized.) /AndreasArticle: 117301
On 2007-03-27, Pete Fraser <pfraser@covad.net> wrote: > > "Sean Durkin" <news_mar07@durkin.de> wrote in message > news:56t9c1F29u138U1@mid.individual.net... >> Pete Fraser wrote: >>> Any suggestions? >> Just one: get a Platform USB Cable. Much more reliable, simply works, >> under Windows and Linux. > > Thanks Sean. > I am going to borrow a USB cable, and if it works > I'll buy one. I had just hoped I could get the cable I > have already to work, but it seems like USB is the > way to go. I remember a few years ago folks were > complaining about the USB cable, but it seems like > it's solid now. Just a heads up if you are interested in Linux: If you want to use the cable in Linux you are going to have to mess around a bit if you don't use a supported kernel. Especially if it is a new development kernel which WinDriver don't support yet. There are ways to work around this such as the excellent WinDriver replacement library posted on this newsgroup some weeks ago. (I'm using this method lately and it seems to work ok for me.) With the parallel cable you can use XC3SProg in Linux, but it will only work in Cable III mode unfortunately. /AndreasArticle: 117302
On 2007-03-27, Daniel S. <digitalmastrmind_no_spam@hotmail.com> wrote:
> Since the picoblaze's license is self-enforced by design, my guess is that
> you would not have any problems using the picoblaze in a GPL'd project as
> long as you do not slap the GPL onto picoblaze sources or alter/remove the
> existing license.
It is quite trivial to write small wrappers for modules like FDCE, LUT4, and
SRL16E in portable VHDL or Verilog and then synthesize it with an ASIC flow.
Even if this wouldn't be possible you would still not be allowed to mix the
designs [1] since the Xilinx only limitation is not compatible with the GPL
requirement on no extra limitations on distribution.
/Andreas
[1] Well, it is not quite as clear cut as this. If you do this internally
without distributing it outside of your organisation in a product or
otherwise it should be ok. [2]
[2] IANAL applies to this one...
Article: 117303Hello everyone, Please help. What is the maximum clock frequency that can be used on a Spartan-3 5000? I know it's a grade -4 speed but I couldn't find any documentation regarding it. -Ace-Article: 117304
You can check here http://www.xilinx.com/ise/products/webpack_config.htm . -Ace-Article: 117305
I found some feedback on the microblaze-uclinux mailing list : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2007/03/msg00101.html This is a mail from Paul-Armand Verhaegen, and it explains the 16 steps he followed to use this usb lib with ISE 8.2 SP3 on Ubuntu, to download the Virtex2 of a XUPV2P board. Luzerne GANHIRArticle: 117306
> > emacs VHDL mode to the rescue. > My primary OS is WinXP... but for all my boring regexable copy-paste jobs, > I started using remote-X'd Nedit sessions about a year ago. That sounds very cumbersome. Are you aware that Emacs (and other FOSS editors) is available for WinXP? (Of course than you must to call it GNU/WinXP) Kolja SulimmaArticle: 117307
Rob, If I take a look in the timing analysis then I see that not all my LVDS pins have the same setup time. I am worried that this causes the problem. 0.120 ns TA1 0.113 ns TA1 0.335 ns TA2 0.328 ns TA2 5.061 ns TB1 5.054 ns TB1 5.151 ns TB2 5.144 ns TB2 5.067 ns TC1 5.060 ns TC1 5.143 ns TC2 5.136 ns TC2 5.079 ns TD1 5.075 ns TD1 5.158 ns TD2 5.151 ns TD2 5.090 ns TE1 5.083 ns TE1 5.128 ns TE2 5.121 ns TE2 Do you have an idea what causes this or should I ignore this tSU mismatch? thanks again and best regards, KarelArticle: 117308
"Jim Lewis" <jim@synthworks.com> wrote in message
news:130it10cdc7ocbf@corp.supernews.com...
> Please also read my paper on Accellera VHDL standard 3.0. Read up
> on the unary usage of operators such as XOR.
> Unfortunately due to overloading it will need a type qualifier, but
> you will be able to use it as:
>
> >> y_xor(0) <= XOR std_logic_vector'( x(1), x(2), x(3), x(5), x(8),
> >> x(9), x(11), x(14),
> >> x(17), x(18), x(19), x(21), x(24), x(25), x(27),
> >> x(30), x(32), x(36),
> >> x(38), x(39), x(42), x(44), x(45), x(47), x(48),
> >> x(52), x(54), x(55),
> >> x(58), x(60), x(61), x(63) );
Or I think I'd prefer:
y_xor(0) <= xor (x and X"B4D1B4D14B2E4B2E");
Because it's much less typing.
-Ben-
Article: 117309On Tue, 27 Mar 2007 10:12:40 -0700, "Pete Fraser" <pfraser@covad.net> wrote: >I've just started a new FPGA project, and am having trouble >getting the parallel cable IV to work at speed. > >I'm using a Win XP computer that's new since the last project, >and I removed the combination PCI parallel card from my >old computer, to use in the new one. > >I can't get the Xilinx parallel cable to work in anything >other than compatibility mode (where I either tell >the software that it's a PCIII, or a PCIV running at >200 kHz. > >I never had any problem with the same PCI card in my >old computer. > >Xilinx says to make sure the parallel port is configured >in the BIOS as ECP, but the parallel port doesn't >appear in the BIOS. The hardware properties page >allows me to select use of interrupts in the "Filter >Resource Method" pane, and to enable legacy plug >and play detection. None of this seems to make >a difference. > >Any suggestions? > Same problem. When upgradong from win2000 to winXP, pcIV stopped working. I filed a WebCase, and a Xilinx engineer tried to solve the problem. No way. Now I work wih pcIV as a PCIII and whenever I can, I borrow an USB cable Regards, zaraArticle: 117310
"Daniel S." <digitalmastrmind_no_spam@hotmail.com> writes: > Andy Peters wrote: >> On Mar 27, 12:06 am, "Daniel S." >> <digitalmastrmind_no_s...@hotmail.com> wrote: >> >>> Back then, I used schematics only to avoid having to code boring top-level >>> VHDL port maps... but the frequent crashes and other annoyances (like zero >>> portability) quickly convinced me that I would be better off wrapping >>> everything up in VHDL. >> >> emacs VHDL mode to the rescue. >> >> oh, yeah, it's open source. > > My primary OS is WinXP... but for all my boring regexable copy-paste > jobs, I started using remote-X'd Nedit sessions about a year > ago. Regex replace is definitely a godsend for portmaps and batch > portmap signal declaration. > vhdl-mode is even better, IMHO. NTEmacs works really well under XP (it feels a little bit unixy, as all the paths get / in them instead of \). There's even a win32 installer now I gather, which sets lots fo defaults to the way you expect them to work in Windows. The best bit is the "paste as testbench", which takes your entity and creates a testbench with all the signals wired up, a clock generator installed and a process ready for you to fill in. Now if only it would do the stimulus and error checking for me :-) >>> An extra semicolumn at the wrong place can crash XST but these are often >>> hard to spot since any other programming language would silently accept >>> them. >> >> I take it that you don't simulate much, if at all ... >> >> you should have used ModelSim FIRST ! > In emacs, you can have modelsim compile an individual file at the prod of a key. Then you can get a very quick syntax check. > It depends on what I am doing and why. > > Until my larger designs are sufficiently advanced to start producing > meaningful simulation results (I call this the approximation phase), I > am more interested in tracking resource utilization and static timing > evolution than correctness: achieving absolute correctness in the > first pass (the one most susceptible to typos and syntax errors) is > useless if the implementation fails to meet target timings or exceeds > the logic budget. It is during these passes that XST&all die on me the > most and Modelsim as a simulation tool is irrelevant - that's why it > took me so long to think of using it as a syntax checker. But if you make a trivial error in your design, won't the optimiser chuck lots of stuff out and make it look much better than it is? You'll never know until you simulate... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 117311
Hello everyone! I try to compile the EDK 8.1.02i simulation libraries with its wizard under Fedora Linux. My problem is that, although the compilation should take some time (almost 1 hour for P4@1GHz according to Xilinx), in my case it goes DIRECTLY to 100% and finishes. After I check the folders that should normally contain the compiled libraries, I see that they are empty! Does anyone have a solution to that? I should mention that I use a public PC and I do not have administrator rights. Thank you very much for your time! Regards, DimitrisArticle: 117312
On 27 Mar 2007 11:14:16 -0700, "radarman" <jshamlet@gmail.com> wrote: >Hi, >I'm working on a Microblaze system in a Spartan 3-2000. I am trying to >implement a watchdog timer using the opb_timebase_wdt IP core. I'm >currently using ISE/EDK 8.2.02i, and the WDT version is 1.00a. > >The watchdog timer otherwise works fine. I can start/stop/reset the >timer with no problem. The trouble is that when the watchdog timer >DOES cause a reset, it won't release the reset line, which was >effectively locking up the system. It did NOT respond like the >datasheet. > >To solve the immediate problem, I have inserted an edge detector into >the reset control logic, which allows the system to reboot, but I >can't get the WDT_Reset signal to go low at all. The end result is >that the WDT can only reset the system once. >What am I missing here? Ummm, the watchdog isn't clocked from the DCM, by any chance? I have seen a cunning synchronous reset block rendered completely inoperative by the fact that its own clock went away while it held the DCM in reset! - BrianArticle: 117313
> Even if this wouldn't be possible you would still not be allowed to mix the
> designs [1] since the Xilinx only limitation is not compatible with the GPL
> requirement on no extra limitations on distribution.
>
This is my understanding as well, and it's a real pain if you want to
incorporate other chunks of GPL'd code (of which there are many). This
frequently results in me having to, for example, reimplement xilinx
app notes from the pdf alone and not touch the code, just so I can
then use the result.
I understand why xilinx would want to prevent someone from turning
picoblaze into an asic, or being used by competing fpga vendors. But
if the design really is optimized for xilinx primitives, then that
shouldn't be that possible without a lot of work. :) And one of the
benefits of FPGAs as a platform is you can potentially switch vendors
(although with as often as I directly instantiate things like DCMs and
BlockRAMs, that's easier said than done).
...Eric
Article: 117314On 2007-03-28, Daniel O'Connor <darius@dons.net.au> wrote: > Andreas Ehliar wrote: >> There are ways to work around this such as the excellent >> WinDriver replacement library posted on this newsgroup some >> weeks ago. (I'm using this method lately and it seems to work >> ok for me.) > > Can you point to where? :) Sure, either search for LD_PRELOAD on comp.arch.fpga or look at http://groups.google.se/group/comp.arch.fpga/browse_thread/thread/f149e5b6028e2c70/7757eaae87bd9ac9?lnk=gst&q=ld_preload&rnum=1#7757eaae87bd9ac9 /AndreasArticle: 117315
Andreas Ehliar wrote: > There are ways to work around this such as the excellent > WinDriver replacement library posted on this newsgroup some > weeks ago. (I'm using this method lately and it seems to work > ok for me.) Can you point to where? :) -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 117316
Weng, I applaud your serious desire to improve the vhdl language, as evidenced by your many posts on suggested enhancements. However, improving it does not always mean "expanding it so that it will do this..." The strength of a good language lies in its consistency and simplicity, and ability to have user added functionality. VHDL already has the capability to do what you want, just not with the syntax the way you want it. The problem is, VHDL already has a consistent syntactical footprint, one that your suggestion would make significantly less consistent if added. Perhaps the strongest capability of VHDL is its ability to handle unconstrained array type parameters, so that most functions need only be written once (whether as part of a standard package, or by the user), but can operate on any size array. Jim and Ben have already shown efficient ways to implement the functionality you want, within the existing language, with no real disadvantage over what you suggested (Ben's solution is actually far superior!), other than it doesn't "feel" the same as what you asked for. However, what they suggested has a common feel that most practiced users of vhdl are already comfortable with. Andy On Mar 27, 1:48 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > On Mar 27, 8:48 am, Jim Lewis <j...@synthworks.com> wrote: > > > > > Andy > > > > I think Synopsys has problems with not knowing the type of the > > > expression (A'range => ASel). Other vendors seem to be able to figure > > > it out, but I've never tracked down whether it is legal per LRM. > > > Formally when you run into a situation where one tool accepts code > > and another does not, you enter a bug (interpretation) request to > > VHDL's Issues Screening and Analysis Committee (ISAC) via: > > http://www.eda-stds.org/vasg/#Enhancements > > > In this case select: Report a BUG on an IEEE VHDL revision > > > Then ISAC will issue a response. The following is the ISAC > > resolution to the above issue (recently ISAC Approved): > > http://www.eda.org/isac/IRs-VHDL-2002/IR2097.txt > > > > Weng, would you rather have to type all that garbage out, or just > > > write a function: > > > > ... > > > temp := '0'; > > > for i in x'range loop > > > temp := temp xor x(i); > > > end loop; > > > return temp; > > > Note that he is calculating several parity terms (such > > as in SECDED logic) and each incorporates different, not necessarily > > contiguous pieces of the array. I also note that in my final equation, > > I had ment to give the function call a different name than XOR as you > > would not want to use the operator name in this case: > > > y_xor(0) <= XOR_Reduce(( x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14), > > x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36), > > x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55), > > x(58), x(60), x(61), x(63) )); > > > You can either code your own XOR_reduce or use the one from synopsys' > > package, std_logic_misc (IIRC). > > > Cheers, > > Jim > > Hi Jim, > Thank you for your response. > > > Also note, in VHDL, "*" is multiply and "+" is add. Is that > > what you mean or are using it as a short hand for "and" and "or". > > Yes. > > > Y <= A(A'left - 1) ; > > OK, XOR_Recude(A'left - 1, A'left - 2); > > It doesn't change any original VHDL definitions or rules, but only add > a '...' as a unlimited input signal that means user can add any number > of input signals as required by the function to do the same operation > as designed with variable number of input signals. > > Which is better: > Introduction: > AndOR(a0, b0, ...); > > With this package, you can write your equations as: > R(63 downto 0) <= (a0 and b0) or (a1 and b1) or ... or > (an and bn); > > In my presentation, it will become: > > R(63 downto 0) <= AndOR(a0, b0, a1, b1, a2, b3, ..., an, bn); > > The best thing is the AndOR function will be optimized by compiler > companies, because its definition is clear to do AND, then OR > operations on pair of input signals one pair after another. > > > Write yourself a function that accepts std_logic_vector as an input and > > add an extra set of parentheses to the call: > > y_xor(0) <= XOR(( x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14), > > x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36), > > x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55), > > x(58), x(60), x(61), x(63) )); > > What I want to introduce a new type of input signal '...' is not to > write any type of this function any more, no matter how many signals > are there, a library function can be called. It should be much better > than several functions XOR(a0, b0) that are included in some library. > > If a compiler company provides a XOR_Reduce(a0, a1, ...) in its > library or VHDL standard library includes such functions, VHDL users > would never have to write it again and again. Because in this type of > function XOR_Reduce(a0, a1, ...), the number of input signals can be > varied without concerning to write an 8 input signals, 9 input signals > or others. The function XOR_Reduce(a0, a1, ...) is applied to all XOR > operators with any number of input signals. In current situations, for > function XOR(a0, a1), it has only 2 input signals, far leg behind the > real need such that I don't think XOR(a0, a1) is useful, even though > XOR operators are used widely in any projects. > > WengArticle: 117317
As stated here.... for ANY fpga, the specified Fmax is a theoretical max. Odds are you will never hit that if you are doing anything vaguely complex. That assumes your logic as pipelined to the maximum capabilities of the part - no more than one LUT of combinatorial logic before a DFF - so it makes maximum use of the CLB layout. It also assumes that routing delays are near negligible - i.e. assumes your design can be routed such that you flow from one CLB directly to the neiboring CLB. As soon as you go through more than one LUT of combinatorial logic before a flop or pack your part tight enough that your routes aren't all COMPLETELY ideal.... that is to say, as soon as you put a real design in the part, that Fmax goes down depending upon the details of your design. On Mar 28, 1:29 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-03-28, Ace <yasi...@gmail.com> wrote: > > > Hello everyone, > > > Please help. What is the maximum clock frequency that can be used on a > > Spartan-3 5000? I know it's a grade -4 speed but I couldn't find any > > documentation regarding it. > > It depends on what you want to do with it. If all you are interested in is > one long shift register you can run it extremely fast as an approximation. > If you want to run a complex superscalar microprocessor in it with a three > stage pipeline then you can run it extremely slow as an approximation... > Most designs will fall somewhere in between. > > Remember that you are constructing a circuit here and depending on the > circuit you build you will get different delays. It is totally possible > to build a combinatorial path that will span every single LUT of the chip. > Not a good idea, but possible :) (So I guess it would be possible to > calculate a theoretical minimum frequency by doing a path which would > go through every LUT and place the LUTs as badly as possible so the > routing delays are maximized.) > > /AndreasArticle: 117318
On 28 Mrz., 07:06, sheikh.m.far...@gmail.com wrote: > Hi, (this is my second attempt to get some help on the subject). > I am searching for an FPGA board having multiple gigabit ethernet > connectivity support on it. To be more precise, I need to have > multiple RJ45 connectors and associated logic (PHYs) on the FPGA board > so that I can process multiple ethernet streams on the FPGA. Can > anyone suggest any such board? or any add-on module which can be > hooked up on some particuar FPGA board providing multiple ethernet > connections ! If you can find an evaluation board for an SPI4.2 concentrator you should be able to hook that up to any FPGA development board via a flat band cable. One example: http://www.oiforum.com/public/documents/SPI4-report.doc Kolja SulimmaArticle: 117319
In my interleaver design for FPGA, I am using an external SDRAM for data storage. The clock cycles required to write a frame into the RAM and read a frame back to error correction unit ain't enough. The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of data. And one row of the RAM contains 256 data. The write/read pointers are increased by 200*i or decreased by 200*i (0<i<39) for each write/read operation. As a result, nearly everytime I write one data or read one data, I have to go through a "open a new row, write or read 1 data, close the row" cycle. To open a row and close it, the memory requires some 10 clock cycles. How is it possible to design it in such a way that memory write is in sequential order? That is, when a new frame arrives, I write into the RAM column by until current row is filled, then open the next row. I may have to read in a random access, but I can save a lot of clock cycles in the memory write. FYI, my resources is some RTL logic and an SDRAM. The design can be made with the FPGA's LUTs, but i don't own the resource.Article: 117320
On Mar 28, 4:56 am, "Andy" <jonesa...@comcast.net> wrote: > Weng, > > I applaud your serious desire to improve the vhdl language, as > evidenced by your many posts on suggested enhancements. > > However, improving it does not always mean "expanding it so that it > will do this..." > > The strength of a good language lies in its consistency and > simplicity, and ability to have user added functionality. > > VHDL already has the capability to do what you want, just not with the > syntax the way you want it. The problem is, VHDL already has a > consistent syntactical footprint, one that your suggestion would make > significantly less consistent if added. > > Perhaps the strongest capability of VHDL is its ability to handle > unconstrained array type parameters, so that most functions need only > be written once (whether as part of a standard package, or by the > user), but can operate on any size array. Jim and Ben have already > shown efficient ways to implement the functionality you want, within > the existing language, with no real disadvantage over what you > suggested (Ben's solution is actually far superior!), other than it > doesn't "feel" the same as what you asked for. However, what they > suggested has a common feel that most practiced users of vhdl are > already comfortable with. > > Andy > > On Mar 27, 1:48 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > On Mar 27, 8:48 am, Jim Lewis <j...@synthworks.com> wrote: > > > > Andy > > > > > I think Synopsys has problems with not knowing the type of the > > > > expression (A'range => ASel). Other vendors seem to be able to figure > > > > it out, but I've never tracked down whether it is legal per LRM. > > > > Formally when you run into a situation where one tool accepts code > > > and another does not, you enter a bug (interpretation) request to > > > VHDL's Issues Screening and Analysis Committee (ISAC) via: > > > http://www.eda-stds.org/vasg/#Enhancements > > > > In this case select: Report a BUG on an IEEE VHDL revision > > > > Then ISAC will issue a response. The following is the ISAC > > > resolution to the above issue (recently ISAC Approved): > > > http://www.eda.org/isac/IRs-VHDL-2002/IR2097.txt > > > > > Weng, would you rather have to type all that garbage out, or just > > > > write a function: > > > > > ... > > > > temp := '0'; > > > > for i in x'range loop > > > > temp := temp xor x(i); > > > > end loop; > > > > return temp; > > > > Note that he is calculating several parity terms (such > > > as in SECDED logic) and each incorporates different, not necessarily > > > contiguous pieces of the array. I also note that in my final equation, > > > I had ment to give the function call a different name than XOR as you > > > would not want to use the operator name in this case: > > > > y_xor(0) <= XOR_Reduce(( x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14), > > > x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36), > > > x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55), > > > x(58), x(60), x(61), x(63) )); > > > > You can either code your own XOR_reduce or use the one from synopsys' > > > package, std_logic_misc (IIRC). > > > > Cheers, > > > Jim > > > Hi Jim, > > Thank you for your response. > > > > Also note, in VHDL, "*" is multiply and "+" is add. Is that > > > what you mean or are using it as a short hand for "and" and "or". > > > Yes. > > > > Y <= A(A'left - 1) ; > > > OK, XOR_Recude(A'left - 1, A'left - 2); > > > It doesn't change any original VHDL definitions or rules, but only add > > a '...' as a unlimited input signal that means user can add any number > > of input signals as required by the function to do the same operation > > as designed with variable number of input signals. > > > Which is better: > > Introduction: > > AndOR(a0, b0, ...); > > > With this package, you can write your equations as: > > R(63 downto 0) <= (a0 and b0) or (a1 and b1) or ... or > > (an and bn); > > > In my presentation, it will become: > > > R(63 downto 0) <= AndOR(a0, b0, a1, b1, a2, b3, ..., an, bn); > > > The best thing is the AndOR function will be optimized by compiler > > companies, because its definition is clear to do AND, then OR > > operations on pair of input signals one pair after another. > > > > Write yourself a function that accepts std_logic_vector as an input and > > > add an extra set of parentheses to the call: > > > y_xor(0) <= XOR(( x(1), x(2), x(3), x(5), x(8), x(9), x(11), x(14), > > > x(17), x(18), x(19), x(21), x(24), x(25), x(27), x(30), x(32), x(36), > > > x(38), x(39), x(42), x(44), x(45), x(47), x(48), x(52), x(54), x(55), > > > x(58), x(60), x(61), x(63) )); > > > What I want to introduce a new type of input signal '...' is not to > > write any type of this function any more, no matter how many signals > > are there, a library function can be called. It should be much better > > than several functions XOR(a0, b0) that are included in some library. > > > If a compiler company provides a XOR_Reduce(a0, a1, ...) in its > > library or VHDL standard library includes such functions, VHDL users > > would never have to write it again and again. Because in this type of > > function XOR_Reduce(a0, a1, ...), the number of input signals can be > > varied without concerning to write an 8 input signals, 9 input signals > > or others. The function XOR_Reduce(a0, a1, ...) is applied to all XOR > > operators with any number of input signals. In current situations, for > > function XOR(a0, a1), it has only 2 input signals, far leg behind the > > real need such that I don't think XOR(a0, a1) is useful, even though > > XOR operators are used widely in any projects. > > > Weng- Hide quoted text - > > - Show quoted text - Hi Jim, Andy, Thank you for your inputs. WengArticle: 117321
On Mar 28, 3:36 pm, "news reader" <newsrea...@google.com> wrote: > In my interleaver design for FPGA, I am using an external SDRAM for data > storage. > > The clock cycles required to write a frame into the RAM and read a frame > back to error correction unit ain't enough. > > The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of data. > And one row of the RAM contains 256 data. The write/read pointers are > increased by 200*i or decreased by 200*i (0<i<39) for each write/read > operation. > > As a result, nearly everytime I write one data or read one data, I have to > go > through a "open a new row, write or read 1 data, close the row" cycle. To > open > a row and close it, the memory requires some 10 clock cycles. > > How is it possible to design it in such a way that memory write is in > sequential > order? That is, when a new frame arrives, I write into the RAM column by > until current row is filled, then open the next row. > > I may have to read in a random access, but I can save a lot of clock cycles > in > the memory write. > > FYI, my resources is some RTL logic and an SDRAM. The design can be made > with the FPGA's LUTs, but i don't own the resource. If you write out by hand the order in which data comes out of a depth- N interleaver, you should be able to spot the pattern (it's really not a very complicated pattern...). You can then just apply this pattern to the read pointer, letting you store your data in the original (sequential) order. In other words, the interleaving is done during the read operation. However, the read access pattern will be just as "random" as the write access pattern was in your original design. So unless your SDRAM's read cycle is shorter than its write cycle, this won't save you any time. -- OliArticle: 117322
Karel, These Tsu times are expected to be different, but slightly . Your TA1 and TA2 number jump out as suspicious to me. The reason these Tsu times are different is because the path delays (either pin to register or clock path) will be slightly (on the order of 10's of ps) different. A better representation of Tsu on this input register would be to subtract the pin to register delay from the reported Tsu. Depending on the transmitter (THline) output clock jitter, bit position variance, and board trace skew, you might have to tune the Tsu time by adjusting the phase delay of the PLL, which will change the time the latch edge triggers the input register. Rob On Mar 28, 4:01 am, "Dolphin" <Karel.Dep...@gemidis.be> wrote: > Rob, > > If I take a look in the timing analysis then I see that not all my > LVDS pins have the same setup time. I am worried that this causes the > problem. > 0.120 ns TA1 > 0.113 ns TA1 > 0.335 ns TA2 > 0.328 ns TA2 > 5.061 ns TB1 > 5.054 ns TB1 > 5.151 ns TB2 > 5.144 ns TB2 > 5.067 ns TC1 > 5.060 ns TC1 > 5.143 ns TC2 > 5.136 ns TC2 > 5.079 ns TD1 > 5.075 ns TD1 > 5.158 ns TD2 > 5.151 ns TD2 > 5.090 ns TE1 > 5.083 ns TE1 > 5.128 ns TE2 > 5.121 ns TE2 > > Do you have an idea what causes this or should I ignore this tSU > mismatch? > > thanks again and best regards, > KarelArticle: 117323
On Mar 27, 11:14 am, "radarman" <jsham...@gmail.com> wrote: > The watchdog timer otherwise works fine. I can start/stop/reset the > timer with no problem. The trouble is that when the watchdog timer > DOES cause a reset, it won't release the reset line, which was > effectively locking up the system. It did NOT respond like the > datasheet. The source in /cygdrive/c/EDK81/hw/XilinxProcessorIPLib/pcores/ opb_timebase_wdt_v1_00_a/hdl/vhdl/timebase_wdt_core.vhd says that the state machine will only leave the ExpiredTwice state on OPB_Rst. So you need an OPB_Rst to release the WDT_Reset line. Alan NishiokaArticle: 117324
Hi, To program my Atmel(ATmega128L) controller and Xilinx FPGA (sparta-3 XCS400) at the same time, I decided as a programmer to use the Xilinx Parallel Cable III. I implemented the programmer 100% the same as found in Xilinx's website ( http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html). The programmer worked, but not without problems. For programming the Atmel uC I used AVRdude, and for the FPGA, ISE9.1i. The ribbon-cable from the LPT port to Programmer was 20cm long and from the programmer to the uC/FPGA board was not more than 10 cm. The problem related with this programmer were verification errors, i.e the PC can't program or read properly from the board. The interesting thing is how these verification problem came up. In the morning when I turn the PC and Board on, these verification errors are a lot. When the code that I want to download is big, its impossible to program the FPGA/uC, for small codes it works but after many tries. After 10 tries or so, the programming works correct and no verification errors no matter how many times I try to download the code or how big the code is, and this without even touching a thing on the hardware!!! Since this problem applies to more than one board, I assume the problem must lay on the programmer itself. My explanation is that maybe the buffer IC's get hot or something...I really don't know. I want to know if there is anyone who has had problems with this programmer cable. Thank You, JJ
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