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Compare FPGA features and resources
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Threads Starting Dec 2001
37144: 01/12/01: VhdlCohen: New book: Real Chip DSGN and Verification, Verilog/VHDL
37150: 01/12/01: Theron Hicks: problem with manual floorplanner
37190: 01/12/03: Don Husby: Re: problem with manual floorplanner
37156: 01/12/01: Hippolyte Lizard: XNF file gets corrupted
37462: 01/12/11: Jason T. Wright: Re: XNF file gets corrupted
37163: 01/12/02: Alex Sherstuk: Phase noise (jitter) of XILINX logic elements - ?
37187: 01/12/03: Austin Lesea: Re: Phase noise (jitter) of XILINX logic elements - ?
37201: 01/12/03: Alex Sherstuk: Re: Phase noise (jitter) of XILINX logic elements - ?
37207: 01/12/04: John_H: Re: Phase noise (jitter) of XILINX logic elements - ?
37242: 01/12/04: Alex Sherstuk: Re: Phase noise (jitter) of XILINX logic elements - ?
37226: 01/12/04: Symon: Re: Phase noise (jitter) of XILINX logic elements - ?
37210: 01/12/04: glen herrmannsfeldt: Re: Phase noise (jitter) of XILINX logic elements - ?
37230: 01/12/04: Austin Lesea: Re: Phase noise (jitter) of XILINX logic elements - ?
37250: 01/12/04: Brian Davis: Re: Phase noise (jitter) of XILINX logic elements - ?
37258: 01/12/05: Austin Lesea: Re: Phase noise (jitter) of XILINX logic elements - ?
37265: 01/12/05: Brian Davis: Re: Phase noise (jitter) of XILINX logic elements - ?
37266: 01/12/05: Austin Lesea: Re: Phase noise (jitter) of XILINX logic elements - ?
37520: 01/12/13: Ian Dedic: Re: Phase noise (jitter) of XILINX logic elements - ?
37175: 01/12/03: VR: Crossing a clock domain
37177: 01/12/03: Philip Freidin: Re: Crossing a clock domain
37241: 01/12/04: Austin Franklin: Re: Crossing a clock domain
37251: 01/12/04: Chua Kah Hean: Re: Crossing a clock domain
37253: 01/12/05: Philip Freidin: Re: Crossing a clock domain
37271: 01/12/05: Assaf Sarfati: Re: Crossing a clock domain
37178: 01/12/02: Antonio: Synplify 7 and Xilinx 4.1 Pair
37211: 01/12/03: Modelsim/Synplify/VCS/LDV/FPGA Express/Xilinx/Quar: Re: Synplify 7 and Xilinx 4.1 Pair
37246: 01/12/04: Illan: Re: Synplify 7 and Xilinx 4.1 Pair
37179: 01/12/02: Antonio: Multicycle Synplify question
37182: 01/12/03: Sul Weh: Free PCI simulation model???
37185: 01/12/03: Utku Ozcan: XC17S00A programmable as XC17S00 for 2 XC2Ss?
37221: 01/12/04: Karl Olsen: Re: XC17S00A programmable as XC17S00 for 2 XC2Ss?
37186: 01/12/03: Hananiel Sarella: Benchmarking RC
37191: 01/12/03: Brady Gaughan: Xilinx Parallel FIR Implementations
37200: 01/12/03: D2fabrizio: Announce: TimingAnalyzer Program Update
37214: 01/12/03: Brinda: Webpack Version 3: Exit with error code 0002
37325: 01/12/06: Kevin Brace: Re: Webpack Version 3: Exit with error code 0002
37220: 01/12/03: Kevin Brace: How to increase clock skew for Spartan-II
37222: 01/12/04: <hamish@cloud.net.au>: Re: How to increase clock skew for Spartan-II
37329: 01/12/06: Kevin Brace: Re: How to increase clock skew for Spartan-II
37234: 01/12/04: Falk Brunner: Re: How to increase clock skew for Spartan-II
37328: 01/12/06: Kevin Brace: Re: How to increase clock skew for Spartan-II
37343: 01/12/07: Falk Brunner: Re: How to increase clock skew for Spartan-II
37347: 01/12/07: Eric Crabill: Re: How to increase clock skew for Spartan-II
37227: 01/12/04: Laurent SANDRIN: altera max++ baseline and jedec file
37256: 01/12/05: Wolfgang Loewer: Re: altera max++ baseline and jedec file
37228: 01/12/04: Nick: quartus post simulation setup problem
37261: 01/12/05: Mike Treseler: Re: quartus post simulation setup problem
37262: 01/12/05: Brian Philofsky: Re: quartus post simulation setup problem
37264: 01/12/05: Mike Treseler: Re: quartus post simulation setup problem
37287: 01/12/06: Nick: Re: quartus post simulation setup problem
37293: 01/12/06: Brian Philofsky: Re: quartus post simulation setup problem
37305: 01/12/06: Mike Treseler: Re: quartus post simulation setup problem
37340: 01/12/07: Nick: Re: quartus post simulation setup problem
37292: 01/12/06: Nick: Re: quartus post simulation setup problem
37330: 01/12/06: Asher C. Martin: Re: quartus post simulation setup problem
37229: 01/12/04: Boris: Triscend E5 vs Atmel FPSLIC
37280: 01/12/06: Ulf Samuelsson: Re: Triscend E5 vs Atmel FPSLIC
37231: 01/12/04: Bernd Scheuermann: Installing ISE 4.1i
37235: 01/12/04: Falk Brunner: Re: Installing ISE 4.1i
37239: 01/12/04: Andy Peters: Re: Installing ISE 4.1i
37283: 01/12/06: Falser Klaus: Re: Installing ISE 4.1i
37236: 01/12/04: Jens Frauenschlaeger: JTAG readback format
37244: 01/12/04: Kuan Zhou: Where to get JBit or Jroute
37255: 01/12/05: Stephen Melnikoff: Re: Where to get JBit or Jroute
37245: 01/12/05: Jas: Altera to Actel conversion
37248: 01/12/04: Eftychios Eftychiou: Xilinx ISE 4.1 md0 md2 and ipad symbols not found for xc4005xl
37252: 01/12/05: #BASUKI ENDAH PRIYANTO#: Multiple Drivers & illegal connection
37291: 01/12/06: VhdlCohen: Re: Multiple Drivers & illegal connection
37254: 01/12/05: Tom: Board Level Sim: Models And Pullup ?
37257: 01/12/05: Jose I Quinones: For Sale: Huge Xilinx FPGA lots
37259: 01/12/05: Jim Stewart: Re: For Sale: Huge Xilinx FPGA lots
37260: 01/12/05: Andy Holt: Re: For Sale: Huge Xilinx FPGA lots
37314: 01/12/06: Robert Posey: Re: For Sale: Huge Xilinx FPGA lots
37348: 01/12/07: Keith: Re: For Sale: Huge Xilinx FPGA lots
37319: 01/12/07: Eser Chamoglu: Re: For Sale: Huge Xilinx FPGA lots
37351: 01/12/07: Ray Andraka: Re: For Sale: Huge Xilinx FPGA lots
37349: 01/12/07: Arthur: Re: For Sale: Huge Xilinx FPGA lots
37387: 01/12/09: Rick Filipkiewicz: Re: For Sale: Huge Xilinx FPGA lots
37263: 01/12/05: Dave Lowry: Can WebPack and Student Edition Co-exist?
37350: 01/12/07: Arthur: Re: Can WebPack and Student Edition Co-exist?
37267: 01/12/06: Kiyoung SON: where is designed FPGA for apple II computer...?
37272: 01/12/05: Eric Smith: Re: where is designed FPGA for apple II computer...?
37274: 01/12/06: sdfjsd: Re: where is designed FPGA for apple II computer...?
37299: 01/12/06: glen herrmannsfeldt: Re: where is designed FPGA for apple II computer...?
37301: 01/12/06: Eric Smith: Re: where is designed FPGA for apple II computer...?
37315: 01/12/06: Rob Finch: Re: where is designed FPGA for apple II computer...?
37309: 01/12/06: Neil Franklin: Re: where is designed FPGA for apple II computer...?
37310: 01/12/06: Ray Andraka: Re: where is designed FPGA for apple II computer...?
37320: 01/12/07: Ray Andraka: Re: where is designed FPGA for apple II computer...?
37326: 01/12/07: Nicholas Weaver: Re: where is designed FPGA for apple II computer...?
37426: 01/12/10: glen herrmannsfeldt: Re: where is designed FPGA for apple II computer...?
37427: 01/12/10: Eric Smith: Re: where is designed FPGA for apple II computer...?
37428: 01/12/10: Jan Gray: Re: where is designed FPGA for apple II computer...?
37302: 01/12/06: Leon Heller: Re: where is designed FPGA for apple II computer...?
37304: 01/12/06: Andy Peters: Re: where is designed FPGA for apple II computer...?
37311: 01/12/06: Austin Lesea: Re: where is designed FPGA for apple II computer...?
37332: 01/12/07: olivier JEAN: Re: where is designed FPGA for apple II computer...?
37356: 01/12/07: Mike Butts: Re: where is designed FPGA for apple II computer...?
37268: 01/12/06: Kiyoung SON: where is designed FPGA for APPLE....?
37306: 01/12/06: James Horn: Re: where is designed FPGA for APPLE....?
37269: 01/12/05: Quigley: Newbie: FPGA or microcontroller for MPEG4 decoding?
37294: 01/12/06: Falk Brunner: Re: Newbie: FPGA or microcontroller for MPEG4 decoding?
37270: 01/12/06: deerlux: Where can I find the implemention of block float multiplier?
37285: 01/12/06: Ray Andraka: Re: Where can I find the implemention of block float multiplier?
37300: 01/12/06: glen herrmannsfeldt: Re: Where can I find the implemention of block float multiplier?
37316: 01/12/07: Ray Andraka: Re: Where can I find the implemention of block float multiplier?
37288: 01/12/06: Tom Dillon: Re: Where can I find the implemention of block float multiplier?
37275: 01/12/05: Miem Chan: ISA bus adr decoder with GAL16V8D
37276: 01/12/06: AH: IEEE 1149.1 boundary scan and HIGHZ opcode
37277: 01/12/06: AH: Re: IEEE 1149.1 boundary scan and HIGHZ opcode
37278: 01/12/06: AH: ISP via JTAG
37295: 01/12/06: Falk Brunner: Re: ISP via JTAG
37279: 01/12/06: enny: $EXPORT=NO(exp_EDIF) for CoreGen Component, schematic entry
37281: 01/12/06: Sul Weh: Has anyone successfully used opencores PCI?
37303: 01/12/06: Andy Peters: Re: Has anyone successfully used opencores PCI?
37324: 01/12/06: Kevin Brace: Re: Has anyone successfully used opencores PCI?
37331: 01/12/07: Petter Gustad: Re: Has anyone successfully used opencores PCI?
37282: 01/12/06: Tobias: Timing Constraints Spartan, divided Clk
37286: 01/12/06: Utku Ozcan: Re: Timing Constraints Spartan, divided Clk
37296: 01/12/06: Falk Brunner: Re: Timing Constraints Spartan, divided Clk
37284: 01/12/06: =?ISO-8859-1?Q?Jo=E3o_Ferreira?=: Call for papers on CCMs for high-performance computing
37289: 01/12/06: Srinivasan Venkataramanan: using UNIX Environment variables in "ncvlog -file option" - Help!
37322: 01/12/07: Petter Gustad: Re: using UNIX Environment variables in "ncvlog -file option" - Help!
37290: 01/12/06: Tony Nelson: Synplify to Actel clkbuf problems
37342: 01/12/07: Gerald Weile: Re: Synplify to Actel clkbuf problems
37297: 01/12/06: Jeremy Whatley: Xilinx CPLD pin mapping with Foundation F3.1i
37298: 01/12/06: Jason: XC6200
37308: 01/12/06: Peter Alfke: Re: XC6200
37334: 01/12/07: Reinoud: Re: XC6200
37307: 01/12/06: H.L: xilinx ise 4.1i
37338: 01/12/07: jacky Renaux: Re: xilinx ise 4.1i
37313: 01/12/06: Bernd Scheuermann: ISE 4.1i / FPGA Express network installation
37317: 01/12/06: H.L: xilinx ise 4
37450: 01/12/11: Tobias Stumber: Re: xilinx ise 4
37497: 01/12/12: H.L: Re: xilinx ise 4
37499: 01/12/12: Eric Smith: Re: xilinx ise 4
37507: 01/12/12: Jack Tai: Re: xilinx ise 4
37512: 01/12/13: H.L: Re: xilinx ise 4
37318: 01/12/07: AH: anyone in comp.arch.fpga in irc?
37775: 01/12/20: Domagoj: Re: anyone in comp.arch.fpga in irc?
37333: 01/12/07: Anand Kumar V: Parameters deciding Max. Clock Frequency supported in a Sequential Ckt
37344: 01/12/07: Falk Brunner: Re: Parameters deciding Max. Clock Frequency supported in a Sequential Ckt
37335: 01/12/07: Simon Deeley: IP Updates and Modelsim
37337: 01/12/07: #BASUKI ENDAH PRIYANTO#: RE: IP Updates and Modelsim
37410: 01/12/10: Brian Philofsky: Re: IP Updates and Modelsim
37336: 01/12/07: Giggio: Translating....
37345: 01/12/07: Falk Brunner: Re: Translating....
37404: 01/12/10: Giggio: Re: Translating....
37414: 01/12/10: Falk Brunner: Re: Translating....
37445: 01/12/11: Giggio: Re: Translating....
37420: 01/12/10: Mike Treseler: Re: Translating....
37432: 01/12/10: Chua Kah Hean: Re: Translating....
37341: 01/12/07: Andrea Sabatini: Altera pin drivers
37346: 01/12/07: Falk Brunner: Re: Altera pin drivers
37399: 01/12/09: George P. Kosmopoulos: Re: Altera pin drivers
37412: 01/12/10: Falk Brunner: Re: Altera pin drivers
37423: 01/12/10: Mike Treseler: Re: Altera pin drivers
37477: 01/12/12: Ray Andraka: Re: Altera pin drivers
37478: 01/12/12: Ray Andraka: Re: Altera pin drivers
37555: 01/12/14: Yury: Re: Altera pin drivers
37353: 01/12/07: vi: Orcad
37372: 01/12/08: Rotem Gazit: Re: Orcad
37354: 01/12/07: Speedy Zero Two: Webpack V4 SVF file generation
37355: 01/12/08: Alex Rast: Xilinx FPGA Editor 4.1- problems with manually routing high-fanout nets
37357: 01/12/07: Eric Crabill: Re: Xilinx FPGA Editor 4.1- problems with manually routing high-fanout
37358: 01/12/08: Alex Rast: Re: Xilinx FPGA Editor 4.1- problems with manually routing high-fanout
37440: 01/12/11: Alex Rast: Re: Xilinx FPGA Editor 4.1- problem...solved!
37359: 01/12/08: Markus Meng: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37360: 01/12/08: Falk Brunner: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37367: 01/12/08: Markus Meng: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37369: 01/12/08: Falk Brunner: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37378: 01/12/09: Peter Alfke: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37384: 01/12/09: Markus Meng: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37388: 01/12/09: Philip Freidin: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37361: 01/12/08: Ray Andraka: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37364: 01/12/08: Peter Alfke: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37453: 01/12/11: Markus Meng: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ? Update ...
37362: 01/12/08: Jason Berringer: ISA syncronization?
37390: 01/12/09: Peter Wallace: Re: ISA syncronization?
37395: 01/12/09: Jason Berringer: Re: ISA syncronization?
37394: 01/12/09: ikauranen: Re: ISA syncronization?
37429: 01/12/11: Miem Chan: Re: ISA syncronization?
37437: 01/12/10: rickman: Re: ISA syncronization?
37438: 01/12/11: Philip Freidin: Re: ISA syncronization?
37400: 01/12/10: rickman: Re: ISA syncronization?
37363: 01/12/08: Warren Wisnewski: aldec
37381: 01/12/09: Peter Alfke: Re: aldec
37368: 01/12/08: Sul Weh: Xilinx multiplier and block ram error
37371: 01/12/08: Ray Andraka: Re: Xilinx multiplier and block ram error
37379: 01/12/09: Peter Alfke: Re: Xilinx multiplier and block ram error
37396: 01/12/10: Deli Geng (David): DSP or FPGA for ODFM Demodulation?
37401: 01/12/09: Banana: Michelangelo's Counter
37411: 01/12/10: Peter Alfke: Re: Michelangelo's Counter
37416: 01/12/10: Falk Brunner: Re: Michelangelo's Counter
37424: 01/12/10: Peter Alfke: Re: Michelangelo's Counter
37441: 01/12/10: Banana: Re: Michelangelo's Counter
37452: 01/12/11: Peter Alfke: Re: Michelangelo's Counter
37482: 01/12/11: Banana: Re: Michelangelo's Counter
37494: 01/12/12: Peter Alfke: Re: Michelangelo's Counter
37844: 01/12/21: Carl Brannen: Re: Michelangelo's Counter
37849: 01/12/21: Antonio: Re: Michelangelo's Counter
37402: 01/12/10: VR: XESS XSV-800 Gripes
37568: 01/12/15: sdfjsd: Re: XESS XSV-800 Gripes
37405: 01/12/10: Dennis: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37442: 01/12/11: Dennis: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37451: 01/12/11: Noel Klonsky: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37484: 01/12/12: Dennis: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37963: 01/12/27: Stuart Moses: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37965: 01/12/28: Nicholas Weaver: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37994: 01/12/29: Victor Schutte: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
38037: 02/01/02: Goran Bilski: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37406: 01/12/10: =?ISO-8859-1?Q?Michael_Kr=E4mer?=: MaxplusII 9.6 under Win2k, any known problems?
37407: 01/12/10: Bernd Scheuermann: FPGA Advantage and Atmel Figaro
37408: 01/12/10: Michael Boehnel: Timing Simulation Model
37422: 01/12/10: Andy Peters: Re: Timing Simulation Model
37409: 01/12/10: Shi Zhong: JBits programming questions.
37419: 01/12/11: David Miller: SelectIO and Virtex II: PAR weirdness
37421: 01/12/10: Bernd Scheuermann: IP Core Update #1
37458: 01/12/11: Brian Philofsky: Re: IP Core Update #1
37425: 01/12/10: Tim: PC Cache size. Was: ModelSim performance on Solaris/sparc and Linux/x86
37537: 01/12/13: Gary Helbig: Re: PC Cache size. Was: ModelSim performance on Solaris/sparc and Linux/x86
37571: 01/12/15: sdfjsd: Re: PC Cache size. Was: ModelSim performance on Solaris/sparc and
37430: 01/12/11: David Miller: apologies.. and functional simulation of DCMs
37459: 01/12/11: Brian Philofsky: Re: apologies.. and functional simulation of DCMs
37431: 01/12/10: Kurt: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37435: 01/12/11: S. Ramirez: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37449: 01/12/11: Rick Filipkiewicz: Re: About special promotion of Synplicity's Synplify? FPGA synthesis
37456: 01/12/11: Kurt: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37443: 01/12/11: MH: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37455: 01/12/11: Kurt: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37457: 01/12/11: MH: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37466: 01/12/11: S. Ramirez: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37559: 01/12/14: S. Ramirez: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37581: 01/12/16: MH: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37439: 01/12/10: Rvsoln: how do i implement it?
37475: 01/12/12: Ray Andraka: Re: how do i implement it?
37505: 01/12/12: Rvsoln: Re: how do i implement it?
37444: 01/12/11: alco: ISP by JTAG using a microcontroller
37464: 01/12/12: Jim Granville: Re: ISP by JTAG using a microcontroller
37625: 01/12/17: Randal Kuramoto: Re: ISP by JTAG using a microcontroller
37651: 01/12/18: Greg Neff: Re: ISP by JTAG using a microcontroller
37653: 01/12/19: Jim Granville: Re: ISP by JTAG using a microcontroller
37663: 01/12/18: Greg Neff: Re: ISP by JTAG using a microcontroller
37665: 01/12/18: Greg Neff: Re: ISP by JTAG using a microcontroller
37446: 01/12/11: Gyunseog Yang: i want "RAMB4_S1_S16.VHD"
37448: 01/12/11: Utku Ozcan: Re: i want "RAMB4_S1_S16.VHD"
37460: 01/12/11: Brian Philofsky: Re: i want "RAMB4_S1_S16.VHD"
37447: 01/12/11: lennart: HDL editor ISE 4.1 : auto-keyboard switching
37454: 01/12/11: jakab tanko: DCM error
37470: 01/12/12: Philip Freidin: Re: DCM error
37473: 01/12/12: Ray Andraka: Re: DCM error
37493: 01/12/12: jakab tanko: Re: DCM error
37463: 01/12/11: Litvinov: Initialization of RAM
37471: 01/12/12: Rick Filipkiewicz: Re: Initialization of RAM
37476: 01/12/12: S. Ramirez: Re: Initialization of RAM
37479: 01/12/12: Ray Andraka: Re: Initialization of RAM
37492: 01/12/12: Peter Alfke: Re: Initialization of RAM
37498: 01/12/12: Eric Smith: Re: Initialization of RAM
37510: 01/12/13: Utku Ozcan: Re: Initialization of RAM
37502: 01/12/12: Rick Filipkiewicz: Re: Initialization of RAM
37503: 01/12/13: S. Ramirez: Re: Initialization of RAM
37504: 01/12/13: Jim Granville: Re: Initialization of RAM
37506: 01/12/13: Ray Andraka: Re: Initialization of RAM
37870: 01/12/22: Carl Brannen: Re: Initialization of RAM
37487: 01/12/12: Roberta Crescentini: Re: Initialization of RAM
37467: 01/12/11: Robert Abiad: Crosstalk on clocks
37468: 01/12/11: Peter Alfke: Re: Crosstalk on clocks
37469: 01/12/12: Philip Freidin: Re: Crosstalk on clocks
37500: 01/12/12: Robert Abiad: Re: Crosstalk on clocks
37508: 01/12/13: Ray Andraka: Re: Crosstalk on clocks
37472: 01/12/11: Robert Abiad: Re: Crosstalk on clocks
37486: 01/12/12: Russell Shaw: Re: Crosstalk on clocks
37495: 01/12/12: Peter Alfke: Re: Crosstalk on clocks
37490: 01/12/12: John_H: Re: Crosstalk on clocks
37496: 01/12/12: Speedy Zero Two: Re: Crosstalk on clocks
37527: 01/12/13: Falk Brunner: Re: Crosstalk on clocks
37521: 01/12/13: Philip Freidin: Re: Crosstalk on clocks
37474: 01/12/12: David Brown: chipscope "disable JTAG clock BUFG insertion"
37491: 01/12/12: David Hawke: Re: chipscope "disable JTAG clock BUFG insertion"
39259: 02/02/05: Sanket Bandyopadhyay: Re: chipscope "disable JTAG clock BUFG insertion"
39534: 02/02/12: Eirik Esp: Re: chipscope "disable JTAG clock BUFG insertion"
37483: 01/12/12: Ramnath: Constraints Some basics
37485: 01/12/12: Utku Ozcan: Re: Constraints Some basics
37488: 01/12/12: Sebastian: ROM prog problem Virtex2 eval board
37489: 01/12/12: Bryan: Re: ROM prog problem Virtex2 eval board
37501: 01/12/12: David Rogoff: Xilinx ISE4.1/FPGA express: specify pin loading
37526: 01/12/13: Falk Brunner: Re: Xilinx ISE4.1/FPGA express: specify pin loading
37509: 01/12/13: Guy-Armand: svf files in webpack 4.2
37515: 01/12/13: Petter Gustad: Re: svf files in webpack 4.2
37522: 01/12/13: Guy-Armand: Re: svf files in webpack 4.1
37531: 01/12/13: Petter Gustad: Re: svf files in webpack 4.1
37535: 01/12/13: Neil Glenn Jacobson: Re: svf files in webpack 4.1
37546: 01/12/14: Tom Dillon: Re: svf files in webpack 4.2
37533: 01/12/13: Speedy Zero Two: Re: svf files in webpack 4.2
37536: 01/12/13: Neil Glenn Jacobson: Re: svf files in webpack 4.2
37552: 01/12/14: Speedy Zero Two: Re: svf files in webpack 4.2
37511: 01/12/13: ddale: How to use the CoreGen hdl code within my source?
37514: 01/12/13: Alan Fitch: Re: How to use the CoreGen hdl code within my source?
37523: 01/12/13: Theron Hicks: Re: How to use the CoreGen hdl code within my source?
37541: 01/12/14: Alan Fitch: Re: How to use the CoreGen hdl code within my source?
37513: 01/12/13: AAP3: datapath schematic editor
37544: 01/12/14: Duncan Crowther: Re: datapath schematic editor
37549: 01/12/14: AAP3: Re: datapath schematic editor
37516: 01/12/13: JianYong Niu: FPGA development board
37518: 01/12/13: David Langmann: Re: FPGA development board
37519: 01/12/13: Jason Langkamer-Smith: FPGA introduction
37530: 01/12/13: Peter Alfke: Re: FPGA introduction
37532: 01/12/13: Marc Baker: Re: FPGA introduction
37534: 01/12/13: Peter Alfke: Re: FPGA introduction
37524: 01/12/13: Jeff Cunningham: referencing Spartan2 DLL to 24.576 Mhz?
37525: 01/12/13: Austin Lesea: Re: referencing Spartan2 DLL to 24.576 Mhz?
37528: 01/12/13: Falk Brunner: Fondation 4.1 and SpartanXL
37529: 01/12/13: Philip Freidin: Re: Fondation 4.1 and SpartanXL
37548: 01/12/14: Falk Brunner: Re: Fondation 4.1 and SpartanXL
37553: 01/12/14: Ray Andraka: Re: Fondation 4.1 and SpartanXL
37554: 01/12/14: Yury: Re: Fondation 4.1 and SpartanXL
37538: 01/12/13: 345678: Problem with PALASM 4 and 22V10 and GLOBAL.SETF
37539: 01/12/13: Ramnath: Relation between net delay & Period
37540: 01/12/13: Antonio: The speedest FPGA
37574: 01/12/15: ron: Re: The speedest FPGA
37799: 01/12/20: Ray Andraka: Re: The speedest FPGA
37786: 01/12/20: Falk Brunner: Re: The speedest FPGA
37962: 01/12/27: Stuart Moses: Re: The speedest FPGA
37978: 01/12/28: Falk Brunner: Re: The speedest FPGA
38294: 02/01/10: Jay: Re: The speedest FPGA
38299: 02/01/11: Ray Andraka: Re: The speedest FPGA
37542: 01/12/14: Russell Shaw: Dual-port ram templates
37545: 01/12/14: Peter Alfke: Re: Dual-port ram templates
37547: 01/12/14: Ray Andraka: Re: Dual-port ram templates
37556: 01/12/14: Ray Andraka: Re: Dual-port ram templates
37617: 01/12/17: David Dye: Re: Dual-port ram templates
37551: 01/12/14: adarsh: Re: Dual-port ram templates
37561: 01/12/15: Russell Shaw: Re: Dual-port ram templates
37562: 01/12/15: Russell Shaw: Re: Dual-port ram templates
37566: 01/12/15: Russell Shaw: Re: Dual-port ram templates
37564: 01/12/15: Ray Andraka: Re: Dual-port ram templates
37565: 01/12/15: Peter Alfke: Re: Dual-port ram templates
37557: 01/12/14: Mike Treseler: Re: Dual-port ram templates
37563: 01/12/15: Russell Shaw: Re: Dual-port ram templates
37584: 01/12/16: Mike Treseler: Re: Dual-port ram templates
37586: 01/12/17: Russell Shaw: Re: Dual-port ram templates
37836: 01/12/21: Russell Shaw: Re: Dual-port ram templates
37854: 01/12/21: Mike Treseler: Re: Dual-port ram templates
37871: 01/12/22: Russell Shaw: Re: Dual-port ram templates
37543: 01/12/14: rob: random number generator in Handel-C?
37642: 01/12/18: Noel Klonsky: Re: random number generator in Handel-C?
37796: 01/12/20: rob: Re: random number generator in Handel-C?
37558: 01/12/14: enny: Direct Digital Synthesizer, CoreGen
37560: 01/12/14: zg: Testing used xilinx components
37567: 01/12/15: Mohap: annoying problem
37569: 01/12/15: Falk Brunner: Re: annoying problem
37572: 01/12/16: Peter Alfke: Re: annoying problem
37583: 01/12/16: John Larkin: Re: annoying problem
37757: 01/12/19: Peter Alfke: Re: annoying problem and "simple and clever solution"
37768: 01/12/20: Rick Filipkiewicz: Re: annoying problem and "simple and clever solution"
37819: 01/12/20: Ray Andraka: Re: annoying problem and "simple and clever solution"
37820: 01/12/20: Peter Alfke: Re: annoying problem and "simple and clever solution"
37823: 01/12/21: Jim Granville: Re: annoying problem and "simple and clever solution"
37848: 01/12/21: Greg Neff: Re: annoying problem and "simple and clever solution"
37772: 01/12/20: Jonathan Bromley: Re: annoying problem and "simple and clever solution"
37570: 01/12/15: sdfjsd: newbie Xilinx Foundation ISE4.1 questions
37620: 01/12/17: Andy Peters: Re: newbie Xilinx Foundation ISE4.1 questions
37627: 01/12/18: Ukkdl: Re: newbie Xilinx Foundation ISE4.1 questions
37575: 01/12/15: ron: multi-cycle constraint
37747: 01/12/20: David Miller: Re: multi-cycle constraint
37755: 01/12/19: Brian Philofsky: Re: multi-cycle constraint
37576: 01/12/16: arlington: FPGA-Conversion. IP Cores
37589: 01/12/16: Kevin Brace: Re: FPGA-Conversion. IP Cores
37678: 01/12/18: Kevin Brace: Re: FPGA-Conversion. IP Cores
37577: 01/12/16: Rotem Gazit: Xilinx Modular Design tool
37578: 01/12/16: C.Schlehaus: Leonardo Spectrum Editor Configuration
37585: 01/12/17: Russell Shaw: Re: Leonardo Spectrum Editor Configuration
37579: 01/12/16: Carl Brannen: Efficient multiplication using block SRAM...
37580: 01/12/16: Carl Brannen: Multiplying by squaring using Block RAM.
37604: 01/12/17: Christopher Saunter: Re: Multiplying by squaring using Block RAM.
37582: 01/12/16: Jay Berg: Certicom challenge and FPGA based modular math
37590: 01/12/16: Eric Pearson: Re: Certicom challenge and FPGA based modular math
37591: 01/12/16: Jay Berg: Re: Certicom challenge and FPGA based modular math
37592: 01/12/17: Carl Brannen: Re: Certicom challenge and FPGA based modular math
37593: 01/12/16: Jay Berg: Re: Certicom challenge and FPGA based modular math
37597: 01/12/17: Carl Brannen: Re: Certicom challenge and FPGA based modular math
37598: 01/12/17: Carl Brannen: Re: Certicom challenge and FPGA based modular math
37605: 01/12/17: Philip Freidin: Re: Certicom challenge and FPGA based modular math
37613: 01/12/17: Jay Berg: Re: Certicom challenge and FPGA based modular math
37594: 01/12/16: Jay Berg: Re: Certicom challenge and FPGA based modular math
37595: 01/12/17: Steven Derrien: Re: Certicom challenge and FPGA based modular math
37609: 01/12/17: Jay Berg: Re: Certicom challenge and FPGA based modular math
37596: 01/12/17: Steven Derrien: Re: Certicom challenge and FPGA based modular math
37600: 01/12/17: Carl Brannen: Re: Certicom challenge and FPGA based modular math
37611: 01/12/17: Jay Berg: Re: Certicom challenge and FPGA based modular math
37610: 01/12/17: Christopher Saunter: Re: Certicom challenge and FPGA based modular math
37644: 01/12/18: Jay Berg: Re: Certicom challenge and FPGA based modular math
37587: 01/12/16: Jason Berringer: SPI interface in VHDL
37602: 01/12/17: AlexS.: Re: SPI interface in VHDL
37614: 01/12/17: Alexander Richter: Re: SPI interface in VHDL
37631: 01/12/18: Patrick Loschmidt: Re: SPI interface in VHDL
37646: 01/12/18: Don Husby: Re: SPI interface in VHDL
37637: 01/12/18: Wolfgang Loewer: Re: SPI interface in VHDL
37670: 01/12/19: Adam Hawes: Re: SPI interface in VHDL
37588: 01/12/16: Kevin Brace: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns?
37782: 01/12/20: Milos Becvar: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns?
37917: 01/12/24: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37599: 01/12/17: Steven Derrien: Configuring Xilinx FPGA through parallel port
37619: 01/12/17: Nick Macias: Re: Configuring Xilinx FPGA through parallel port
37601: 01/12/17: Mardin: division 64
37603: 01/12/17: next: Re: division 64
37608: 01/12/17: Pallek, Andrew [CAR:CN34:EXCH]: Re: division 64
37628: 01/12/18: Muzaffer Kal: Re: division 64
37638: 01/12/18: Russell Shaw: Re: division 64
37650: 01/12/18: Muzaffer Kal: Re: division 64
37607: 01/12/17: Peter Alfke: Re: division 64
37621: 01/12/17: Andy Peters: Re: division 64
37612: 01/12/17: Wolfgang Loewer: Re: division 64
37623: 01/12/17: next: Re: division 64
37624: 01/12/18: Philip Freidin: Re: division 64
37606: 01/12/17: deerlux: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37701: 01/12/19: Utku Ozcan: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37787: 01/12/20: kh05168: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37805: 01/12/20: Ray Andraka: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37933: 01/12/25: hrzic: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37615: 01/12/17: Rick Filipkiewicz: Xilinx ChipScope - experiences ?
37626: 01/12/18: Phil Hays: Re: Xilinx ChipScope - experiences ?
37635: 01/12/18: Rotem Gazit: Re: Xilinx ChipScope - experiences ?
37616: 01/12/17: supaman: research on fast carry chains for FPGA
37618: 01/12/17: Dave Lowry: Problems Installing Foundation 4.1 Under '98SE
37622: 01/12/17: shawn chen: Download byteblast circuit with byteblasterMV mode(Maxplus II baseline) :
37760: 01/12/20: Russell Shaw: Re: Download byteblast circuit with byteblasterMV mode(Maxplus II
37629: 01/12/17: Antonio: Hardware FPGA questions
37766: 01/12/20: Ray Andraka: Re: Hardware FPGA questions
37767: 01/12/19: Josh Pfrimmer: Re: Hardware FPGA questions
37778: 01/12/20: Keith R. Williams: Re: Hardware FPGA questions
37785: 01/12/20: Falk Brunner: Re: Hardware FPGA questions
37795: 01/12/20: Peter Alfke: Re: Hardware FPGA questions
37798: 01/12/20: Keith R. Williams: Re: Hardware FPGA questions
37829: 01/12/20: H.L: Re: Hardware FPGA questions
37792: 01/12/20: Peter Alfke: Re: Hardware FPGA questions
37821: 01/12/20: <Kevin>: Re: Hardware FPGA questions
37831: 01/12/21: Peter Alfke: Re: Hardware FPGA questions
37842: 01/12/21: Rick Filipkiewicz: Re: Hardware FPGA questions
40352: 02/03/05: Paul Taylor: Re: Hardware FPGA questions
37630: 01/12/18: arlington: Altera vs Xilinx
37632: 01/12/18: Kenily: is it OK?
37634: 01/12/18: chensw20hotmail.com: Re: is it OK?
37645: 01/12/18: Andy Peters: Re: is it OK?
37662: 01/12/18: Ray Andraka: Re: is it OK?
37676: 01/12/18: Kenily: Re: is it OK?
37633: 01/12/18: enny: Disadvantages of core creating_rpm and pipeline ?
37639: 01/12/18: Christian Plessl: Xilinx Foundation - Routing constraints/prohibit
37648: 01/12/18: Falk Brunner: Re: Xilinx Foundation - Routing constraints/prohibit
37695: 01/12/19: Ray Andraka: Re: Xilinx Foundation - Routing constraints/prohibit
37640: 01/12/18: Wilco Vahrmeijer: FGPA express bidir pins Xilinx, FPGA-pmap-18
37647: 01/12/18: Falk Brunner: Re: FGPA express bidir pins Xilinx, FPGA-pmap-18
37654: 01/12/18: Peter Alfke: Re: FGPA express bidir pins Xilinx, FPGA-pmap-18
37641: 01/12/18: Elmar Dukek: Atmel IDS 7.5 and also older Versions do not work with Windows XP
37643: 01/12/18: Stephen Byrne: Best-case Timing?
37649: 01/12/18: Aare Tali: WebPack blows up CPLDs?
37652: 01/12/18: Peter Alfke: Kindergarten Stuff
37655: 01/12/18: Muzaffer Kal: Re: Kindergarten Stuff
37667: 01/12/18: Austin Franklin: Re: Kindergarten Stuff
37669: 01/12/18: Bryan: Re: Kindergarten Stuff
37672: 01/12/18: Austin Franklin: Re: Kindergarten Stuff
37673: 01/12/18: Austin Lesea: You take the low road and I'll ......
37679: 01/12/19: Ray Andraka: Re: You take the low road and I'll ......
37682: 01/12/19: Kevin Neilson: Re: You take the low road and I'll ......
37688: 01/12/19: Ray Andraka: Re: You take the low road and I'll ......
37680: 01/12/18: Austin Franklin: Re: You take the low road and I'll ......
37715: 01/12/19: Austin Lesea: Re: You take the low road and I'll ......
37734: 01/12/19: Austin Franklin: Re: You take the low road and I'll ......
37741: 01/12/19: Ray Andraka: Re: You take the low road and I'll ......
37797: 01/12/20: Pete Dudley: Re: You take the low road and I'll ......
37804: 01/12/20: Austin Lesea: Re: You take the low road and I'll ......
37812: 01/12/20: Rick Filipkiewicz: Re: You take the low road and I'll ......
37814: 01/12/20: Austin Lesea: Re: You take the low road and I'll ......
37822: 01/12/21: Russell Shaw: Re: You take the low road and I'll ......
37815: 01/12/20: Bryan: Re: You take the low road and I'll ......
37818: 01/12/20: Ray Andraka: Re: You take the low road and I'll ......
37845: 01/12/21: Mikeandmax: Re: You take the low road and I'll ......
37851: 01/12/21: Austin Franklin: Re: You take the low road and I'll ......
37872: 01/12/22: kryten_droid: Re: You take the low road and I'll ......
37900: 01/12/23: ZhengLin: Re: You take the low road and I'll ......
37916: 01/12/24: John Jakson: Re: You take the low road and I'll ......
37674: 01/12/18: Bret Wade: Re: Kindergarten Stuff
37718: 01/12/19: Bryan: Re: Kindergarten Stuff
37720: 01/12/19: David Hawke: Re: Kindergarten Stuff
37726: 01/12/19: Bret Wade: Re: Kindergarten Stuff
37748: 01/12/19: Carl Brannen: How to route a segment at a time with FPGA Editor
37749: 01/12/19: Carl Brannen: Re: Kindergarten Stuff
37784: 01/12/20: Falk Brunner: Re: Kindergarten Stuff
37850: 01/12/21: Bryan: Re: Kindergarten Stuff
37869: 01/12/22: Carl Brannen: Re: Kindergarten Stuff
37878: 01/12/22: Falk Brunner: Re: Kindergarten Stuff
37684: 01/12/19: Carl Brannen: Re: Kindergarten Stuff
37719: 01/12/19: Bryan: Re: Kindergarten Stuff
37750: 01/12/19: Carl Brannen: Re: Kindergarten Stuff
37716: 01/12/19: David Hawke: Re: Kindergarten Stuff
37722: 01/12/19: Tim: Re: Kindergarten Stuff
37771: 01/12/20: David Hawke: Re: Kindergarten Stuff
37683: 01/12/19: Kevin Neilson: Re: Kindergarten Stuff
37693: 01/12/19: Steve Underwood: Re: Kindergarten Stuff
37769: 01/12/20: Rick Filipkiewicz: Re: Kindergarten Stuff
37891: 01/12/23: Ed Ngai: Re: Kindergarten Stuff
37896: 01/12/23: Ray Andraka: Re: Kindergarten Stuff
37897: 01/12/23: Ed Ngai: Re: Kindergarten Stuff
37905: 01/12/24: Peter Alfke: Re: Kindergarten Stuff
37910: 01/12/24: Rick Filipkiewicz: Re: Kindergarten Stuff
37915: 01/12/24: Ed Ngai: Re: Kindergarten Stuff
37940: 01/12/26: Rick Filipkiewicz: Re: Kindergarten Stuff
37912: 01/12/24: Carl Brannen: Re: Kindergarten Stuff
37656: 01/12/18: Carl Brannen: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37658: 01/12/18: Steven Derrien: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37659: 01/12/18: Peter Alfke: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37664: 01/12/18: Ray Andraka: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37681: 01/12/19: Carl Brannen: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37689: 01/12/19: Ray Andraka: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37697: 01/12/19: Carl Brannen: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37752: 01/12/19: glen herrmannsfeldt: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37802: 01/12/20: Frederic Rivoallon: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37816: 01/12/20: Carl Brannen: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37817: 01/12/20: Ray Andraka: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37710: 01/12/19: Stephen Melnikoff: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37866: 01/12/21: Carl Brannen: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37867: 01/12/22: Ray Andraka: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37657: 01/12/18: S. Ramirez: Defauolt Should Be "Inputs and Outputs" For IOBs
37661: 01/12/18: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37687: 01/12/19: David Miller: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37725: 01/12/19: S. Ramirez: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37727: 01/12/19: Bret Wade: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37733: 01/12/19: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37753: 01/12/19: Bret Wade: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37761: 01/12/19: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37783: 01/12/20: Ken McElvain: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37788: 01/12/20: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37808: 01/12/20: Alan Nishioka: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37813: 01/12/20: Rick Filipkiewicz: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37888: 01/12/23: <hamish@cloud.net.au>: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37894: 01/12/23: Rick Filipkiewicz: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37852: 01/12/21: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37875: 01/12/22: Bret Wade: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37880: 01/12/22: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37883: 01/12/22: Bret Wade: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37892: 01/12/23: Austin Franklin: Re: Default Should Be "Inputs and Outputs" For IOBs - please respond???
37895: 01/12/23: Ray Andraka: Re: Default Should Be "Inputs and Outputs" For IOBs - please respond???
37737: 01/12/19: S. Ramirez: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37740: 01/12/19: Ray Andraka: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37754: 01/12/19: Bret Wade: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37762: 01/12/19: Austin Franklin: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37774: 01/12/20: S. Ramirez: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37806: 01/12/20: Tim Hubberstey: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37724: 01/12/19: S. Ramirez: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37732: 01/12/19: Austin Franklin: Re: Default Should Be "Inputs and Outputs" For IOBs
37736: 01/12/19: S. Ramirez: Re: Default Should Be "Inputs and Outputs" For IOBs
37743: 01/12/19: Austin Franklin: Re: Default Should Be "Inputs and Outputs" For IOBs
37739: 01/12/20: David Miller: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37721: 01/12/19: Andy Peters: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37770: 01/12/20: Rick Filipkiewicz: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37826: 01/12/21: S. Ramirez: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37832: 01/12/21: Peter Alfke: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37660: 01/12/18: Peter Fenn: Spartan-IIE schematic symbol?
37666: 01/12/18: Austin Franklin: Re: Spartan-IIE schematic symbol?
37668: 01/12/18: Greg Neff: Re: Spartan-IIE schematic symbol?
37810: 01/12/20: Eric Smith: Re: Spartan-IIE schematic symbol?
37675: 01/12/18: Pete Dudley: Re: Spartan-IIE schematic symbol?
37758: 01/12/19: pete dudley: Re: Spartan-IIE schematic symbol?
37773: 01/12/20: Rick Filipkiewicz: Re: Spartan-IIE schematic symbol?
37671: 01/12/18: Carl Brannen: Divide by 3, with remainder, efficient and fast, for Altera or Xilinx
37686: 01/12/19: Carl Brannen: Re: Divide by 3, with remainder, efficient and fast, for Altera or Xilinx
37708: 01/12/19: Eric Pearson: Re: Divide by 3, with remainder, efficient and fast, for Altera or Xilinx
37677: 01/12/18: Kevin Brace: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37751: 01/12/19: Eric Crabill: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37923: 01/12/24: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
38041: 02/01/02: Milos Becvar: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37685: 01/12/19: David Miller: DCM stability in Virtex2 -ES
37704: 01/12/19: John Adair: Re: DCM stability in Virtex2 -ES
37717: 01/12/19: Austin Lesea: Re: DCM stability in Virtex2 -ES
37764: 01/12/20: David Miller: Re: DCM stability in Virtex2 -ES
37830: 01/12/21: David Miller: Re: DCM stability in Virtex2 -ES
37690: 01/12/18: Kevin Brace: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7
37700: 01/12/19: Carl Brannen: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37838: 01/12/21: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37728: 01/12/19: Eric Crabill: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37885: 01/12/23: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37735: 01/12/19: Falk Brunner: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37884: 01/12/23: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37745: 01/12/19: Austin Franklin: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37841: 01/12/21: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37868: 01/12/22: Carl Brannen: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37882: 01/12/22: Austin Franklin: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37922: 01/12/24: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37921: 01/12/24: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu <
37833: 01/12/21: Phil Hays: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37920: 01/12/24: <Kevin>: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu
37691: 01/12/18: Kevin Brace: Re: FPGA-Conversion. IP Cores
37746: 01/12/19: Austin Franklin: Re: FPGA-Conversion. IP Cores
37692: 01/12/18: Kevin Brace: Google Groups problems?
37709: 01/12/19: Harish Y S: Re: Google Groups problems?
37694: 01/12/18: ssy: the effect of syn_maxfan
37696: 01/12/19: AAP3: MIPS or MOPS?
37702: 01/12/19: Murali Jayapala: Re: MIPS or MOPS?
37705: 01/12/19: Sander Vesik: Re: MIPS or MOPS?
37707: 01/12/19: Murali Jayapala: Re: MIPS or MOPS?
37711: 01/12/19: Murali Jayapala: Re: MIPS or MOPS?
37738: 01/12/19: glen herrmannsfeldt: Re: MIPS or MOPS?
37731: 01/12/19: Rupert Pigott: Re: MIPS or MOPS?
37698: 01/12/19: Carl Brannen: Low area barrel shift puts 3 to 1 mux in a Xilinx LUT:
37699: 01/12/19: Carl Brannen: Re: Low area barrel shift puts 3 to 1 mux in a Xilinx LUT:
37730: 01/12/19: Mike Treseler: Re: Low area barrel shift puts 3 to 1 mux in a Xilinx LUT:
37703: 01/12/19: Martin Fischer: How can I check my PLD program ?
37706: 01/12/19: Stephen Byrne: Best-case timing?
37723: 01/12/19: Andy Peters: Re: Best-case timing?
37759: 01/12/20: Bob Perlman: Re: Best-case timing?
37791: 01/12/20: Andy Peters: Re: Best-case timing?
37800: 01/12/20: Bob Perlman: Re: Best-case timing?
37807: 01/12/21: Jim Granville: Re: Best-case timing?
37811: 01/12/20: Peter Alfke: Re: Best-case timing?
37827: 01/12/21: Bob Perlman: Re: Best-case timing?
37742: 01/12/19: Austin Lesea: Re: Best-case timing?
37712: 01/12/19: Martin Fischer: Boundary Scn, Bist
38293: 02/01/10: Neil Glenn Jacobson: Re: Boundary Scn, Bist
37713: 01/12/19: Antonio: clk_dll general question
37781: 01/12/20: Falk Brunner: Re: clk_dll general question
37714: 01/12/19: Antonio: Clocks and Synplify
37780: 01/12/20: Falk Brunner: Re: Clocks and Synplify
37729: 01/12/19: Carl Brannen: Efficient new multiplier for Spartan2, Virtex &c.
37744: 01/12/19: Alexei Lomakin: Re: Efficient new multiplier for Spartan2, Virtex &c.
37825: 01/12/21: Carl Brannen: An algorithm improvement...
37839: 01/12/21: Carl Brannen: 16x5 multiplier uses new multiply algorithm
37756: 01/12/20: Alex Rast: Virtex configuration problem: GTS being deasserted before DONE?
37763: 01/12/19: Quiet Desperation: Virtex 2 & Trace
37765: 01/12/20: Ray Andraka: Re: Virtex 2 & Trace
37779: 01/12/20: Quiet Desperation: Re: Virtex 2 & Trace
37776: 01/12/20: Tony Burch: Ann: FPGA board Super-Value-Pack released
37777: 01/12/20: none: Re: Clock pins in Virtex-E
37828: 01/12/20: H.L: Re: Clock pins in Virtex-E
37789: 01/12/20: Behrang: Array Divider
37790: 01/12/20: rob: Floating point numbers in Handel C
37793: 01/12/20: Peter Alfke: Re: Clock pins in Virtex-E
37801: 01/12/20: H.L: Re: Clock pins in Virtex-E
37834: 01/12/21: Carl Brannen: Re: Clock pins in Virtex-E
37837: 01/12/21: H.L: Re: Clock pins in Virtex-E
37803: 01/12/20: H.L: Clock pins in Virtex-E
37809: 01/12/20: none: Re: Clock pins in Virtex-E
37824: 01/12/20: ssy: how to group a critical path into a most small area
37835: 01/12/21: Rob Finch: A ram wish
37855: 01/12/21: Peter Alfke: Re: A ram wish
37856: 01/12/21: stefaan vanheesbeke: Re: A ram wish
37862: 01/12/21: Peter Alfke: Re: A ram wish
37863: 01/12/21: Rick Filipkiewicz: Re: A ram wish
37864: 01/12/21: Peter Alfke: Re: A ram wish
37893: 01/12/23: stefaan vanheesbeke: Re: A ram wish
37840: 01/12/21: Frank Papenfuss: CE on XILINX FFs and Metastability
37843: 01/12/21: Rick Filipkiewicz: Re: CE on XILINX FFs and Metastability
37859: 01/12/21: Peter Alfke: Re: CE on XILINX FFs and Metastability
37847: 01/12/21: none: Re: CE on XILINX FFs and Metastability
37857: 01/12/21: Peter Alfke: Re: CE on XILINX FFs and Metastability
37876: 01/12/22: Rob Finch: How do i get rid of "Signal xx has a multisource" warning in Xilinx webpack ?
37879: 01/12/22: Tim: Re: How do i get rid of "Signal xx has a multisource" warning in Xilinx webpack ?
37877: 01/12/22: Marc: Beginners question: several circuits in one chip
37881: 01/12/22: Ray Andraka: Re: Beginners question: several circuits in one chip
37886: 01/12/23: freny: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
37898: 01/12/23: ZhengLin: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
37911: 01/12/24: freny: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
37961: 01/12/27: Andy Peters: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
37887: 01/12/23: freny: no net attached to set reset cell
37903: 01/12/23: ZhengLin: Re: no net attached to set reset cell
37889: 01/12/23: deerlux: Does the core or Xilinx Core Generator support timing-simlulation?
37902: 01/12/23: ZhengLin: Re: Does the core or Xilinx Core Generator support timing-simlulation?
37906: 01/12/24: Peter Alfke: Re: Does the core or Xilinx Core Generator support timing-simlulation?
37907: 01/12/23: ZhengLin: Re: Does the core or Xilinx Core Generator support timing-simlulation?
37899: 01/12/23: ssy: where can I find a indepth manual about place and route in Quartus II
37901: 01/12/24: David Miller: availability of VirtexII production silicon
37904: 01/12/24: Peter Alfke: Re: availability of VirtexII production silicon
37908: 01/12/24: Muzaffer Kal: Re: availability of VirtexII production silicon
37937: 01/12/26: Jkkfjf: Re: availability of VirtexII production silicon
37909: 01/12/24: <Kevin>: Should clock skew be included for setup time analysis?
37913: 01/12/24: Hien Pham: What the many ways to meet FPGA timing ?
37918: 01/12/25: David G.: Look for FPGA Starterkit
37925: 01/12/25: newman: Re: Look for FPGA Starterkit
37939: 01/12/26: arlington: Re: Look for FPGA Starterkit
37946: 01/12/26: newman: Re: Look for FPGA Starterkit
37943: 01/12/27: Tony Burch: Re: Look for FPGA Starterkit
37953: 01/12/27: Roberto Waltman: Re: Look for FPGA Starterkit
37957: 01/12/27: Uday Hegde: Re: Look for FPGA Starterkit
37989: 01/12/28: Rashid Karimov: Re: Look for FPGA Starterkit
37995: 01/12/29: Martin Rice: Re: Look for FPGA Starterkit
37924: 01/12/25: <Kevin>: Where could I get a signal waveform editor?
37927: 01/12/25: freny: Re: Where could I get a signal waveform editor?
37929: 01/12/25: jrschenk: Re: Where could I get a signal waveform editor?
37930: 01/12/25: ZhengLin: Re: Where could I get a signal waveform editor?
37932: 01/12/25: Johnsonw10: Re: Where could I get a signal waveform editor?
37936: 01/12/25: Eric Pearson: Re: Where could I get a signal waveform editor?
37938: 01/12/26: Srinivasan Venkataramanan: Re: Where could I get a signal waveform editor?
37956: 01/12/27: Dan Fabrizio: Re: Where could I get a signal waveform editor?
37967: 01/12/27: SynaptiCAD Sales: Re: Where could I get a signal waveform editor?
37926: 01/12/25: Daniel Yap: Lattice Filter Schematic?
37960: 01/12/27: Andy Peters: Re: Lattice Filter Schematic?
37935: 01/12/25: Andy Hall: Innoveda Speedwave vs. Modelsim?
37941: 01/12/26: Rick Filipkiewicz: Re: Innoveda Speedwave vs. Modelsim?
37971: 01/12/27: Andy Hall: Re: Innoveda Speedwave vs. Modelsim?
37975: 01/12/28: Rick Filipkiewicz: Re: Innoveda Speedwave vs. Modelsim?
37979: 01/12/28: newman: Re: Innoveda Speedwave vs. Modelsim?
37991: 01/12/29: rickman: Re: Innoveda Speedwave vs. Modelsim?
38006: 01/12/30: <hamish@cloud.net.au>: Re: Innoveda Speedwave vs. Modelsim?
38007: 01/12/30: Patrick Muller: Re: Innoveda Speedwave vs. Modelsim?
38010: 01/12/30: Rick Filipkiewicz: Re: Innoveda Speedwave vs. Modelsim?
38013: 01/12/31: Rick Filipkiewicz: Re: Innoveda Speedwave vs. Modelsim?
38014: 01/12/30: Duane Clark: Re: Innoveda Speedwave vs. Modelsim?
37947: 01/12/26: newman: Re: Innoveda Speedwave vs. Modelsim?
37949: 01/12/27: Rick Filipkiewicz: Re: Innoveda Speedwave vs. Modelsim?
37990: 01/12/29: rickman: Re: Innoveda Speedwave vs. Modelsim?
37944: 01/12/26: Brad Eckert: ROM die area question
38295: 02/01/10: Jay: Re: ROM die area question
37945: 01/12/26: <ffa-list@chchpoly.ac.nz>: NEW: Subscribe To Newsletter
37948: 01/12/27: Utku Ozcan: vector reversed in netlist of XC9572XL
37950: 01/12/27: Rick Filipkiewicz: Re: vector reversed in netlist of XC9572XL
37951: 01/12/27: Allan Herriman: Re: vector reversed in netlist of XC9572XL
37959: 01/12/27: Andy Peters: Re: vector reversed in netlist of XC9572XL
37952: 01/12/27: Utku Ozcan: Re: vector reversed in netlist of XC9572XL
37954: 01/12/27: Srinivasan Venkataramanan: Signal Spy feature available for NC VHDL - Thanks to Martyn, Cadence
37955: 01/12/27: jetmarc: Atmel FPSLIC - Problem with concurrent statements
37958: 01/12/27: Andy Peters: Re: Atmel FPSLIC - Problem with concurrent statements
37976: 01/12/28: jetmarc: Re: Atmel FPSLIC - Problem with concurrent statements
37980: 01/12/28: Andy Peters: Re: Atmel FPSLIC - Problem with concurrent statements
38051: 02/01/03: Ulf Samuelsson: Re: Atmel FPSLIC - Problem with concurrent statements
38062: 02/01/03: Andy Peters: Re: Atmel FPSLIC - Problem with concurrent statements
37966: 01/12/27: Mardin: CRC-32 verilog source code
37970: 01/12/27: Mardin: Re: CRC-32 verilog source code
37974: 01/12/28: glen herrmannsfeldt: Re: CRC-32 verilog source code
37993: 01/12/28: Mardin: Re: CRC-32 verilog source code
38005: 01/12/30: Petter Gustad: Re: CRC-32 verilog source code
37968: 01/12/27: Rob Finch: How to generate .edn in Webpack ?
37982: 01/12/28: Ryan Laity: Re: How to generate .edn in Webpack ?
37987: 01/12/29: Rick Filipkiewicz: Re: How to generate .edn in Webpack ?
38008: 01/12/30: Tim Boescke: Re: How to generate .edn in Webpack ?
38009: 01/12/30: Rick Filipkiewicz: Re: How to generate .edn in Webpack ?
37969: 01/12/27: Rob Finch: How to set block ram contents ?
37981: 01/12/28: Ryan Laity: Re: How to set block ram contents ?
37984: 01/12/28: Rob Finch: Re: How to set block ram contents ?
37999: 01/12/29: Eric Smith: Re: How to set block ram contents ?
38001: 01/12/29: Rashid Karimov: Re: How to set block ram contents ?
38000: 01/12/29: Brian Davis: Re: How to set block ram contents ?
37972: 01/12/27: Sachin Garg: IPDS 2002 Deadline extended to January 10, 2002
37973: 01/12/28: H.L: memory arbiter
37983: 01/12/28: Brad Eckert: Spartan LUT question
37986: 01/12/29: S. Ramirez: Re: Spartan LUT question
37988: 01/12/29: Philip Freidin: Re: Spartan LUT question
37996: 01/12/29: S. Ramirez: Re: Spartan LUT question
37998: 01/12/29: Rick Filipkiewicz: Re: Spartan LUT question
37985: 01/12/28: M. Sachemo: instruction processor
38018: 01/12/31: Kevin Brace: Re: instruction processor
37992: 01/12/28: freny: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
38022: 01/12/31: Carl Brannen: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
37997: 01/12/29: Dimitry Yegorov 1598864168: How do I use Altera's PLL megafunction to multiply some frequency ?
38292: 02/01/10: Jay: Re: How do I use Altera's PLL megafunction to multiply some frequency ?
38348: 02/01/11: Vitaliy Tkachenko: Re: How do I use Altera's PLL megafunction to multiply some frequency ?
38003: 01/12/30: Kenily: CRC-32 48bit(width)
38004: 01/12/30: Petter Gustad: Re: CRC-32 48bit(width)
38019: 01/12/31: Kenily: Re: CRC-32 48bit(width)
38023: 01/12/31: Ray Andraka: Re: CRC-32 48bit(width)
38695: 02/01/22: Muthu: Re: CRC-32 48bit(width)
38698: 02/01/22: Ray Andraka: Re: CRC-32 48bit(width)
38709: 02/01/22: Allan Herriman: Re: CRC-32 48bit(width)
38720: 02/01/23: Muthu: Re: CRC-32 48bit(width)
38723: 02/01/23: Allan Herriman: Re: CRC-32 48bit(width)
38736: 02/01/23: Ray Andraka: Re: CRC-32 48bit(width)
38011: 01/12/31: Nicholas Weaver: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for you)
38015: 01/12/31: Ray Andraka: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for
38017: 01/12/31: Kevin Brace: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for
38021: 01/12/31: Carl Brannen: Re: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for you)
38043: 02/01/02: Nicholas Weaver: Thanks all....Re: Stupid Foundation Question
38012: 01/12/31: <khtsoi@cse.cuhk.edu.hk>: exclude a path in TRACE timing
38016: 01/12/31: <hamish@cloud.net.au>: Re: exclude a path in TRACE timing
38020: 01/12/31: <khtsoi@cse.cuhk.edu.hk>: Re: exclude a path in TRACE timing
38024: 01/12/31: gajju: Synplicity to Xilinx hierarchical net names
38030: 02/01/02: <hamish@cloud.net.au>: Re: Synplicity to Xilinx hierarchical net names
38025: 01/12/31: john: Actel 54sx series clock doubler
38026: 01/12/31: A. Karen Rowe: Re: Actel 54sx series clock doubler
38071: 02/01/03: rk: Re: Actel 54sx series clock doubler
38027: 01/12/31: Rvsoln: Study and Forward about ethernet
38028: 01/12/31: Rustam: Asic design issues .
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