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Threads Starting Aug 2001

33618: 01/08/01: Paul Campbell: Re: Spanning the heirarchy
33626: 01/08/01: Rotem Gazit: Vitex-II prototyping board
    33646: 01/08/01: John_H: Re: Vitex-II prototyping board
        33677: 01/08/02: Rotem Gazit: Re: Virtex-II prototyping board
            33785: 01/08/04: Foolish: Re: Virtex-II prototyping board
            33967: 01/08/09: jku: Re: Virtex-II prototyping board
    34107: 01/08/14: Robert White: Virtex-II prototyping board
33627: 01/08/01: Rick Collins: Spanning the heirarchy
    33630: 01/08/01: Muzaffer Kal: Re: Spanning the heirarchy
    33636: 01/08/01: Rotem Gazit: Re: Spanning the heirarchy
    33651: 01/08/01: Ken McElvain: Re: Spanning the heirarchy
    33696: 01/08/02: Dave Feustel: Re: Spanning the heirarchy
        33744: 01/08/03: Brian Dickinson: Re: Spanning the heirarchy
            33757: 01/08/03: Ken McElvain: Re: Spanning the heirarchy
33631: 01/08/01: Rajesh Kumar E.V: VIRTEX E FPGA Configuration through SelectMap
33633: 01/08/01: LUUTHANHTRUNG: Xilinx Foundation 2.1i Update
    33654: 01/08/01: Philip Freidin: Re: Xilinx Foundation 2.1i Update
33635: 01/08/01: Markus Meng: [ALTERA] EPC1 devices in DIP8 package for sell
33638: 01/08/01: Krishnakumar Rao: post synthesis simulation
    33972: 01/08/09: Brian Philofsky: Re: post synthesis simulation
33639: 01/08/01: Simon Webb: Foundation 2.1 Schematic in WebPack
    33653: 01/08/01: Stephan Neuhold: Re: Foundation 2.1 Schematic in WebPack
        33660: 01/08/01: Chris Arndt: Re: Foundation 2.1 Schematic in WebPack
33640: 01/08/01: Olaf Reichenbaecher: May I connect two pins to the same net?
    33648: 01/08/01: Peter Alfke: Re: May I connect two pins to the same net?
    33663: 01/08/01: Peter Ormsby: Re: May I connect two pins to the same net?
        33675: 01/08/02: Nial Stewart: Re: May I connect two pins to the same net?
    33671: 01/08/01: Falk: Re: May I connect two pins to the same net?
        33685: 01/08/02: <martin.j.thompson@trw.com>: Re: May I connect two pins to the same net?
            33722: 01/08/02: Peter Ormsby: Re: May I connect two pins to the same net?
                33741: 01/08/03: <martin.j.thompson@trw.com>: Re: May I connect two pins to the same net?
    33694: 01/08/02: Falk Brunner: Re: May I connect two pins to the same net?
    33733: 01/08/02: Falk: Re: May I connect two pins to the same net?
        33747: 01/08/03: Peter Ormsby: Re: May I connect two pins to the same net?
            33819: 01/08/06: <martin.j.thompson@trw.com>: Re: May I connect two pins to the same net?
        33786: 01/08/05: vr: Re: May I connect two pins to the same net?
            33787: 01/08/05: Paul Teagle: Re: May I connect two pins to the same net?
                33810: 01/08/06: Lasse Langwadt Christensen: Re: May I connect two pins to the same net?
                    33824: 01/08/06: Paul Teagle: Re: May I connect two pins to the same net?
                    33831: 01/08/06: Ray Andraka: Re: May I connect two pins to the same net?
            33817: 01/08/06: Falk Brunner: Re: May I connect two pins to the same net?
33642: 01/08/01: Abhimanyu Rastogi: Err with this AHDL code
    33645: 01/08/01: John_H: Re: Err with this AHDL code
        33647: 01/08/01: Abhimanyu Rastogi: Re: Err with this AHDL code
            33690: 01/08/02: John_H: Re: Err with this AHDL code
    33664: 01/08/02: Russell Shaw: Re: Err with this AHDL code
        33684: 01/08/02: Abhimanyu Rastogi: Re: Err with this AHDL code
            33717: 01/08/02: John_H: Re: Err with this AHDL code
33649: 01/08/01: Pascal Merkel: LUT as Buffer?
    33927: 01/08/08: Austin Franklin: Re: LUT as Buffer?
        33931: 01/08/08: Ray Andraka: Re: LUT as Buffer?
            33939: 01/08/09: Austin Franklin: Re: LUT as Buffer?
                33951: 01/08/09: Ray Andraka: Re: LUT as Buffer?
                    33964: 01/08/09: Austin Franklin: Re: LUT as Buffer?
                33953: 01/08/09: Pascal Merkel: Re: LUT as Buffer?
33661: 01/08/01: atif: a few xilinx fpga and hdl questions
    33707: 01/08/02: Andy Peters <andy [@] exponentmedia: Re: a few xilinx fpga and hdl questions
33662: 01/08/01: emanuel stiebler: spartan & atmel eeproms
    33673: 01/08/02: Felix Bertram: Re: spartan & atmel eeproms
    33706: 01/08/02: Andy Peters <andy [@] exponentmedia: Re: spartan & atmel eeproms
33667: 01/08/01: Manoj K Krishnan: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
    33670: 01/08/02: Ray Andraka: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
    33705: 01/08/02: Andy Peters <andy [@] exponentmedia: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
        33801: 01/08/06: Erik Widding: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
            33827: 01/08/06: Ray Andraka: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
33669: 01/08/01: Yoram Stern: deskewing PLL/DLL paper
33676: 01/08/02: LUUTHANHTRUNG: Core 2.1i
33678: 01/08/02: Sune G. Krohn: Duty cycle problem with Virtex-II
    33704: 01/08/02: Andy Peters <andy [@] exponentmedia: Re: Duty cycle problem with Virtex-II
        33734: 01/08/03: Sune G. Krohn: Re: Duty cycle problem with Virtex-II
            33773: 01/08/03: Andy Peters <andy [@] exponentmedia: Re: Duty cycle problem with Virtex-II
    33807: 01/08/05: Austin Lesea: Re: Duty cycle problem with Virtex-II
33680: 01/08/02: Tim Forcer: ANNOUNCE: Workshop on Computer based learning (etc) for electronics
33682: 01/08/02: stoneman: Altera EPM7064.............HELP
    33686: 01/08/02: <martin.j.thompson@trw.com>: Re: Altera EPM7064.............HELP
    33761: 01/08/03: Mike Treseler: Re: Altera EPM7064.............HELP
33687: 01/08/02: Robert Sefton: Alliance tools going away?
    33691: 01/08/02: Kamal Patel: Re: Alliance tools going away?
        33726: 01/08/03: Phil Hays: Re: Alliance tools going away?
            33767: 01/08/03: Petter Gustad: Re: Alliance tools going away?
                33779: 01/08/04: Rick Filipkiewicz: Re: Alliance tools going away?
                    33973: 01/08/09: Brian Philofsky: Re: Alliance tools going away?
        33950: 01/08/09: Marius Vollmer: Re: Alliance tools going away?
            33980: 01/08/09: Brian Philofsky: Re: Alliance tools going away?
            33984: 01/08/09: Petter Gustad: Re: Alliance tools going away?
                33994: 01/08/10: Kamal Patel: Re: Alliance tools going away?
                    34004: 01/08/10: Petter Gustad: Re: Alliance tools going away?
33692: 01/08/02: Steven Derrien: Spartan II and asynchronous memory interface
    33695: 01/08/02: david garnett: Re: Spartan II and asynchronous memory interface
        33697: 01/08/02: Steven Derrien: Re: Spartan II and asynchronous memory interface
            33710: 01/08/02: Peter Alfke: Re: Spartan II and asynchronous memory interface
            33712: 01/08/02: Ray Andraka: Re: Spartan II and asynchronous memory interface
                33736: 01/08/03: Steven Derrien: Re: Spartan II and asynchronous memory interface
                    33738: 01/08/03: Tim: Re: Spartan II and asynchronous memory interface
                    33742: 01/08/03: <martin.j.thompson@trw.com>: Re: Spartan II and asynchronous memory interface
            33714: 01/08/02: david garnett: Re: Spartan II and asynchronous memory interface
                33724: 01/08/03: Russell Shaw: Re: Spartan II and asynchronous memory interface
        33700: 01/08/02: Peter Alfke: Re: Spartan II and asynchronous memory interface
        33701: 01/08/02: Andy Peters <andy [@] exponentmedia: Re: Spartan II and asynchronous memory interface
            33740: 01/08/03: Steven Derrien: Re: Spartan II and asynchronous memory interface
                33750: 01/08/03: Ray Andraka: Re: Spartan II and asynchronous memory interface
                    33755: 01/08/03: Steven Derrien: Re: Spartan II and asynchronous memory interface
                        33765: 01/08/03: Ray Andraka: Re: Spartan II and asynchronous memory interface
    33702: 01/08/02: Andy Peters <andy [@] exponentmedia: Re: Spartan II and asynchronous memory interface
        33708: 01/08/02: Steven Derrien: Re: Spartan II and asynchronous memory interface
            33715: 01/08/02: Shane Tow: Re: Spartan II and asynchronous memory interface
    33746: 01/08/03: Martin Schoeberl: Re: Spartan II and asynchronous memory interface
    33798: 01/08/05: Rob Finch: Re: Spartan II and asynchronous memory interface
        33821: 01/08/06: Steven Derrien: Re: Spartan II and asynchronous memory interface
    33876: 01/08/07: Steven Derrien: Re: Spartan II and asynchronous memory interface
        33882: 01/08/07: Jan Gray: Re: Spartan II and asynchronous memory interface
33698: 01/08/02: Dave Feustel: Does Flexlm Licensing Work on Windows 2000 Pro?
    33718: 01/08/02: Mike Treseler: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
        33729: 01/08/02: ron: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
            33756: 01/08/03: Dave Feustel: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
    33725: 01/08/03: Russell Shaw: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
        33762: 01/08/03: Chris Arndt: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
33709: 01/08/02: szekit: newbie
    33974: 01/08/09: Brian Philofsky: Re: newbie
33713: 01/08/02: jdiaz_pr: Simple Division by Shift/Add (2nd try)
    33716: 01/08/02: John_H: Re: Simple Division by Shift/Add (2nd try)
33719: 01/08/02: Cary McCormick: Clock skew with Xilinx DLLs...
    33723: 01/08/03: John_H: Re: Clock skew with Xilinx DLLs...
        33739: 01/08/03: Falk: Re: Clock skew with Xilinx DLLs...
            33751: 01/08/03: Ray Andraka: Re: Clock skew with Xilinx DLLs...
                33780: 01/08/04: Falk Brunner: Re: Clock skew with Xilinx DLLs...
    33727: 01/08/03: Ray Andraka: Re: Clock skew with Xilinx DLLs...
    33759: 01/08/03: Kevin Neilson: Re: Clock skew with Xilinx DLLs...
        33766: 01/08/03: Ray Andraka: Re: Clock skew with Xilinx DLLs...
33732: 01/08/02: Jaime Andres Aranguren Cardona: 4 (8) bit Microporcessor Implementation
    33737: 01/08/03: CBFalconer: Re: 4 (8) bit Microporcessor Implementation
        33743: 01/08/03: Mike: Re: 4 (8) bit Microporcessor Implementation
    33745: 01/08/03: Falk: Re: 4 (8) bit Microporcessor Implementation
    33749: 01/08/03: Veronica Merryfield: Re: 4 (8) bit Microporcessor Implementation
    33752: 01/08/03: Jan Gray: Re: 4 (8) bit Microporcessor Implementation
    33758: 01/08/03: Kevin Neilson: Re: 4 (8) bit Microporcessor Implementation
        33760: 01/08/03: Phil James-Roxby: Re: 4 (8) bit Microporcessor Implementation
    33763: 01/08/03: Ben Franchuk: Re: 4 (8) bit Microporcessor Implementation
    33769: 01/08/03: Andy Peters <andy [@] exponentmedia: Re: 4 (8) bit Microporcessor Implementation
        33784: 01/08/04: Jaime Andres Aranguren Cardona: FPGA - VHDL Design Tools (Was: 4 (8) bit Microporcessor Implementation)
            33863: 01/08/07: Kevin Neilson: Re: FPGA - VHDL Design Tools (Was: 4 (8) bit Microporcessor Implementation)
33764: 01/08/03: David Rogoff: ISE 3.3 .npl files
    33768: 01/08/03: Kamal Patel: Re: ISE 3.3 .npl files
33770: 01/08/03: Alex Ivchenko: Looking for Verilog/FPGA engineer in Boston
33771: 01/08/03: Mark Borgerson: Newbie Question: LPT245 in CoolRunner?
    33893: 01/08/07: Martin Rice: Re: Newbie Question: LPT245 in CoolRunner?
33775: 01/08/04: Manjunathan: how to replicate the Logic through VHDL attribut ?
    33778: 01/08/04: Tim: Re: how to replicate the Logic through VHDL attribut ?
    33846: 01/08/06: Andy Peters <andy [@] exponentmedia: Re: how to replicate the Logic through VHDL attribut ?
33781: 01/08/04: Ben Franchuk: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
    33854: 01/08/06: Ray Andraka: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
33782: 01/08/04: Chris_S: Where's SpartanXL in WebPack?
    33796: 01/08/05: Leon Heller: Re: Where's SpartanXL in WebPack?
33790: 01/08/05: Jaime Andres Aranguren Cardona: Which is the best Design Toolchain?
    33792: 01/08/05: Victor Schutte: Re: Which is the best Design Toolchain?
        33800: 01/08/05: Jaime Andres Aranguren Cardona: Re: Which is the best Design Toolchain?
            33802: 01/08/05: chris: Re: Which is the best Design Toolchain?
    33812: 01/08/06: Tobias Russ: Re: Which is the best Design Toolchain?
    33816: 01/08/06: tb: Re: Which is the best Design Toolchain?
        33826: 01/08/06: Jaime Andres Aranguren Cardona: Re: Which is the best Design Toolchain?
        33841: 01/08/06: Andy Peters <andy [@] exponentmedia: Re: Which is the best Design Toolchain?
    33849: 01/08/06: Jerry: Re: Which is the best Design Toolchain?
    33873: 01/08/07: Russell Shaw: Re: Which is the best Design Toolchain?
    33887: 01/08/07: Andy Peters <andy [@] exponentmedia: Re: Which is the best Design Toolchain?
        33906: 01/08/08: Hal Murray: Re: Which is the best Design Toolchain?
            33922: 01/08/08: Andy Peters <andy [@] exponentmedia: Re: Which is the best Design Toolchain?
        33926: 01/08/08: Rick Filipkiewicz: Re: Which is the best Design Toolchain?
            33985: 01/08/09: Joe: Re: Which is the best Design Toolchain?
    34509: 01/08/28: Ian Smith: Re: Which is the best Design Toolchain?
33791: 01/08/05: Rick Collins: Slightly off topic - PCs for running FPGA tools
    33803: 01/08/05: chris: Re: Slightly off topic - PCs for running FPGA tools
        33808: 01/08/06: Rick Collins: Re: Slightly off topic - PCs for running FPGA tools
            33822: 01/08/06: Ulf Samuelsson: Re: Slightly off topic - PCs for running FPGA tools
                33860: 01/08/06: Rick Collins: Re: Slightly off topic - PCs for running FPGA tools
        33845: 01/08/06: Andy Peters <andy [@] exponentmedia: Re: Slightly off topic - PCs for running FPGA tools
        33847: 01/08/06: Eric: Re: Slightly off topic - PCs for running FPGA tools
            33848: 01/08/06: Nicholas Weaver: Re: Slightly off topic - PCs for running FPGA tools
    33920: 01/08/08: Keith R. Williams: Re: Slightly off topic - PCs for running FPGA tools
        34044: 01/08/12: Rick Collins: Re: Slightly off topic - PCs for running FPGA tools
            34045: 01/08/12: Dave Feustel: Re: Slightly off topic - PCs for running FPGA tools
                34083: 01/08/13: Dave Feustel: Re: Slightly off topic - PCs for running FPGA tools
            34061: 01/08/13: Keith R. Williams: Re: Slightly off topic - PCs for running FPGA tools
            34076: 01/08/13: Andy Peters <andy [@] exponentmedia: Re: Slightly off topic - PCs for running FPGA tools
33795: 01/08/05: Dave Feustel: Webpack Default Browser
33799: 01/08/05: Rob Finch: Webpack DOS shelling
33804: 01/08/06: Mike Damiano: Principal FPGA design/verification contractor available
33805: 01/08/05: LUUTHANHTRUNG: Core Generation 2.1i
33806: 01/08/05: LUUTHANHTRUNG: Core Generation 2.1i
33809: 01/08/05: Krishnakumar Rao: Urgent-Simulation with Leo. Spec
33814: 01/08/06: Antonio: Cordic NCO questions
    33828: 01/08/06: Ray Andraka: Re: Cordic NCO questions
        33875: 01/08/07: Antonio: Re: Cordic NCO questions
            33879: 01/08/07: Ray Andraka: Re: Cordic NCO questions
                33940: 01/08/08: Antonio: Re: Cordic NCO questions
                    33952: 01/08/09: Ray Andraka: Re: Cordic NCO questions
33815: 01/08/06: Antonio: General question on VHDL code
    33844: 01/08/06: Andy Peters <andy [@] exponentmedia: Re: General question on VHDL code
    33975: 01/08/09: Brian Philofsky: Re: General question on VHDL code
33820: 01/08/06: Antonio: Polyphase and VHDL questions
    33862: 01/08/07: Kevin Neilson: Re: Polyphase and VHDL questions
        33864: 01/08/07: Ray Andraka: Re: Polyphase and VHDL questions
            33872: 01/08/07: Antonio: Re: Polyphase and VHDL questions
                33878: 01/08/07: Ray Andraka: Re: Polyphase and VHDL questions
33823: 01/08/06: Manjunathan: how to give timing constraint in an hierarchy des
    33829: 01/08/06: Ray Andraka: Re: how to give timing constraint in an hierarchy des
33832: 01/08/06: Michael Boehnel: Bitgen persist option
    33833: 01/08/06: Tim: Re: Bitgen persist option
    33836: 01/08/06: Kamal Patel: Re: Bitgen persist option
        33842: 01/08/06: Kamal Patel: Re: Bitgen persist option
    33837: 01/08/06: Michael Boehnel: Re: Bitgen persist option
    33840: 01/08/06: Kamal Patel: Re: Bitgen persist option
33835: 01/08/06: Dave Feustel: Batch Install of Xilinx Webpack?
33838: 01/08/06: Paul Smart: Choosing a verilog synthesis tool (Altera/Xilinx)
    33843: 01/08/06: Andy Peters <andy [@] exponentmedia: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
33839: 01/08/06: Austin Lesea: revisting Claude Shannon
33850: 01/08/06: Yoram Rovner: I NEED TO BUY A FPGA BOARD
    33851: 01/08/06: Victor Schutte: Re: I NEED TO BUY A FPGA BOARD
    33852: 01/08/06: Dave Vanden Bout: Re: I NEED TO BUY A FPGA BOARD
    33877: 01/08/08: Tony Burch: Re: I NEED TO BUY A FPGA BOARD
    33917: 01/08/08: David Langmann: Re: I NEED TO BUY A FPGA BOARD
    33925: 01/08/08: Felix Bertram: Re: I NEED TO BUY A FPGA BOARD
    34108: 01/08/14: Robert White: FPGA Boards
33853: 01/08/06: Buckin: eine Frage
    33861: 01/08/07: Kevin Neilson: Re: eine Frage
        33889: 01/08/07: Nir Dahan: Re: eine Frage
33855: 01/08/06: Dave Feustel: Looking for a Particular Used Book
    33890: 01/08/07: Tim: Re: Looking for a Particular Used Book
        33898: 01/08/07: Dave Feustel: Re: Looking for a Particular Used Book
        33908: 01/08/08: Srinivasan Venkataramanan: Re: Looking for a Particular Used Book
    33900: 01/08/08: Clyde R. Shappee: Re: Looking for a Particular Used Book
        33901: 01/08/08: Dave Feustel: Re: Looking for a Particular Used Book
            34393: 01/08/23: Lorinc Antoni: XHWIF for XESS boards
    33905: 01/08/07: Colin Marquardt: Re: Looking for a Particular Used Book
        33919: 01/08/08: Dave Feustel: Re: Looking for a Particular Used Book
33859: 01/08/07: dragon: How to generate *.vfe from viewdraw
33866: 01/08/06: chris: working proto of something cool...whats the next step
33867: 01/08/06: Antonio: What to do if a constrain is not met ???
    33874: 01/08/07: Ray Andraka: Re: What to do if a constrain is not met ???
        33942: 01/08/08: Antonio: Re: What to do if a constrain is not met ???
            33954: 01/08/09: Ray Andraka: Re: What to do if a constrain is not met ???
33868: 01/08/07: L. Heijnen: 200MHz, 28 bit counter in Spartan ii
    33871: 01/08/07: Ray Andraka: Re: 200MHz, 28 bit counter in Spartan ii
33870: 01/08/07: Jason: Reconfigurable Computational Accelerator
    33885: 01/08/07: Ben Franchuk: Re: Reconfigurable Computational Accelerator
        33989: 01/08/09: Hjhke: Re: Reconfigurable Computational Accelerator
    33886: 01/08/07: Philip Freidin: Re: Reconfigurable Computational Accelerator
    34017: 01/08/11: Dave Feustel: Re: Reconfigurable Computational Accelerator
        34021: 01/08/11: Jan Gray: Re: Reconfigurable Computational Accelerator
        34023: 01/08/11: Mike Butts: Re: Reconfigurable Computational Accelerator
            34026: 01/08/11: Dave Feustel: Re: Reconfigurable Computational Accelerator
            34128: 01/08/15: Dave Feustel: Re: Reconfigurable Computational Accelerator
                34172: 01/08/16: Dave Feustel: Re: Reconfigurable Computational Accelerator
                    34210: 01/08/16: Dave Feustel: Re: Reconfigurable Computational Accelerator
    34152: 01/08/15: Luke Roth: Re: Reconfigurable Computational Accelerator
    34204: 01/08/16: Luke Roth: Re: Reconfigurable Computational Accelerator
33883: 01/08/07: Dave Feustel: URL for XILINX's free 314-page design and sythesis guide
    33894: 01/08/07: Tim Jaynes: Re: URL for XILINX's free 314-page design and sythesis guide
    33895: 01/08/07: Tim Jaynes: Re: URL for XILINX's free 314-page design and sythesis guide
    33896: 01/08/07: Peter Alfke: Re: URL for XILINX's free 314-page design and sythesis guide
        33899: 01/08/07: Dave Feustel: Re: URL for XILINX's free 314-page design and sythesis guide
            33923: 01/08/08: Andy Peters <andy [@] exponentmedia: Re: URL for XILINX's free 314-page design and sythesis guide
                33929: 01/08/08: Dave Feustel: Re: URL for XILINX's free 314-page design and sythesis guide
    33897: 01/08/07: Peter Alfke: Re: URL for XILINX's free 314-page design and sythesis guide
        33902: 01/08/07: nnnnnnnnnnnn: Re: URL for XILINX's free 314-page design and sythesis guide (and a question about the Quick Start Guide)
33884: 01/08/07: Daniel Nilsson: interfacing XILINX XC95 to PC parallell port
    33907: 01/08/08: Klaus Falser: Re: interfacing XILINX XC95 to PC parallell port
        33932: 01/08/09: Tony Burch: Re: interfacing XILINX XC95 to PC parallell port
            33934: 01/08/09: Daniel Nilsson: Re: interfacing XILINX XC95 to PC parallell port
33888: 01/08/07: Aare Tali: Spartan-2 and homemade parallel cable
    33909: 01/08/08: Nicolas Matringe: Re: Spartan-2 and homemade parallel cable
33891: 01/08/07: Speedy Zero Two: Xilinx + WebPack + Verilog + Pin designation + Help?
    33921: 01/08/08: Kamal Patel: Re: Xilinx + WebPack + Verilog + Pin designation + Help?
33910: 01/08/08: Entwicklung: PCI Postcode Display
    33928: 01/08/08: Austin Franklin: Re: PCI Postcode Display
    33936: 01/08/08: Kevin Brace: Re: PCI Postcode Display
        34041: 01/08/12: <czhou1949@home.com>: Re: PCI Postcode Display
            34054: 01/08/13: Klaus Falser: Re: PCI Postcode Display
            34238: 01/08/16: Austin Franklin: Re: PCI Postcode Display
                34284: 01/08/18: <czhou1949@home.com>: Re: PCI Postcode Display
            34263: 01/08/17: Kevin Brace: Re: PCI Postcode Display
                34296: 01/08/19: Austin Franklin: Re: PCI Postcode Display
                    34452: 01/08/24: Kevin Brace: Re: PCI Postcode Display
                        34453: 01/08/24: Eric Smith: Re: PCI Postcode Display
                            34521: 01/08/28: Kevin Brace: Re: PCI Postcode Display
    33962: 01/08/09: clevin1234: Re: PCI Postcode Display
        33965: 01/08/09: Austin Franklin: Re: PCI Postcode Display
            33966: 01/08/09: clevin1234: Re: PCI Postcode Display
                33968: 01/08/09: Austin Franklin: Re: PCI Postcode Display
33911: 01/08/08: Gary Cook: Q: Revision and Database Control for FPGA Designs
    33913: 01/08/08: Allan Herriman: Re: Q: Revision and Database Control for FPGA Designs
        34018: 01/08/11: Rick Collins: Re: Q: Revision and Database Control for FPGA Designs
            34019: 01/08/11: Hal Murray: Re: Q: Revision and Database Control for FPGA Designs
            34037: 01/08/12: Allan Herriman: Re: Q: Revision and Database Control for FPGA Designs
                34043: 01/08/12: Rick Collins: Re: Q: Revision and Database Control for FPGA Designs
                    34056: 01/08/13: Allan Herriman: Re: Q: Revision and Database Control for FPGA Designs
                        34062: 01/08/13: Rick Collins: Re: Q: Revision and Database Control for FPGA Designs
                            34063: 01/08/13: <hamish@cloud.net.au>: Re: Q: Revision and Database Control for FPGA Designs
                                34065: 01/08/13: Allan Herriman: Re: Q: Revision and Database Control for FPGA Designs
                                34087: 01/08/14: Thomas Stanka: Re: Q: Revision and Database Control for FPGA Designs
                                    34100: 01/08/14: <hamish@cloud.net.au>: Re: Q: Revision and Database Control for FPGA Designs
                                        34131: 01/08/15: Thomas Stanka: Re: Q: Revision and Database Control for FPGA Designs
                                34090: 01/08/14: Gary Cook: Re: Q: Revision and Database Control for FPGA Designs
                                    34091: 01/08/14: Allan Herriman: Re: Q: Revision and Database Control for FPGA Designs
                                        34093: 01/08/14: Gary Cook: Re: Q: Revision and Database Control for FPGA Designs
                                34129: 01/08/15: Rick Collins: Re: Q: Revision and Database Control for FPGA Designs
                                    34132: 01/08/15: Allan Herriman: Re: Q: Revision and Database Control for FPGA Designs
                                    34142: 01/08/15: <hamish@cloud.net.au>: Re: Q: Revision and Database Control for FPGA Designs
33914: 01/08/08: Abhimanyu Rastogi: Why doesn't DFF stroes the value from the previous clock
    33959: 01/08/09: bob elkind: Re: Why doesn't DFF stroes the value from the previous clock
33915: 01/08/09: James Brennan: Wildcard and Foundation tools
    33916: 01/08/08: Ray Andraka: Re: Wildcard and Foundation tools
        33918: 01/08/09: James Brennan: Re: Wildcard and Foundation tools
            33957: 01/08/09: Ray Andraka: Re: Wildcard and Foundation tools
33933: 01/08/08: Duane Clark: Generate constants with a function
    33938: 01/08/09: Ray Andraka: Re: Generate constants with a function
        33983: 01/08/09: Duane Clark: Re: Generate constants with a function
            33986: 01/08/09: Ray Andraka: Re: Generate constants with a function
    33941: 01/08/09: Renaud Pacalet: Re: Generate constants with a function
33937: 01/08/08: Dipl.-Ing. Andreas Schmidt: Digital Design/Systems/CAD engineer looking for a job in CA (Fremont
33943: 01/08/08: Antonio: Map report question
    33944: 01/08/09: Allan Herriman: Re: Map report question
    33978: 01/08/09: Brian Philofsky: Re: Map report question
    34057: 01/08/13: Arnaud Dion: Re: Map report question
33945: 01/08/09: Harry Chung: Install : Administrative privileges in Win2K
    33979: 01/08/09: Andy Peters <andy [@] exponentmedia: Re: Install : Administrative privileges in Win2K
33947: 01/08/09: Ali: Question on use of FPGA in a special Data Aquisition system
    33949: 01/08/09: Steven Derrien: Re: Question on use of FPGA in a special Data Aquisition system
    33961: 01/08/09: clevin1234: Re: Question on use of FPGA in a special Data Aquisition system
        34011: 01/08/10: Jay: Re: Question on use of FPGA in a special Data Aquisition system
33948: 01/08/09: Peter Rauschert: Problem with fft16 generated by Xilinx Core Gen 3.1i
    33955: 01/08/09: Ray Andraka: Re: Problem with fft16 generated by Xilinx Core Gen 3.1i
33958: 01/08/09: Abhimanyu Rastogi: this code doesn't work properly
    33963: 01/08/09: bob elkind: Re: this code doesn't work properly
        34058: 01/08/13: Harjo Otten: Re: this code doesn't work properly
            34110: 01/08/14: Falk Brunner: Re: this code doesn't work properly
    34066: 01/08/13: Wayne: Re: this code doesn't work properly
33969: 01/08/09: Markus Meng: Spartan-II serial configuration problem from ATMEL device
    33977: 01/08/09: Andy Peters <andy [@] exponentmedia: Re: Spartan-II serial configuration problem from ATMEL device
    33981: 01/08/09: Peter Alfke: Re: Spartan-II serial configuration problem from ATMEL device
        34001: 01/08/10: Andy Peters <andy [@] exponentmedia: Re: Spartan-II serial configuration problem from ATMEL device
            34002: 01/08/10: Peter Alfke: Re: Spartan-II serial configuration problem from ATMEL device
                34005: 01/08/10: Dave Colson: Re: Spartan-II serial configuration problem from ATMEL device
                    34007: 01/08/10: Peter Alfke: Re: Spartan-II serial configuration problem from ATMEL device
    33998: 01/08/10: Dave Colson: Re: Spartan-II serial configuration problem from ATMEL device
        34009: 01/08/10: Rick Filipkiewicz: Re: Spartan-II serial configuration problem from ATMEL device
33971: 01/08/09: Reinoud: Announcing MPGA: an open source meta-FPGA
33982: 01/08/09: K.O: multplier
    33987: 01/08/09: Ray Andraka: Re: multplier
33988: 01/08/09: skitz: how do i LOC Virtex-II BUFGMUX and DCM?
    34000: 01/08/10: Austin Lesea: Re: how do i LOC Virtex-II BUFGMUX and DCM?
33990: 01/08/10: =?ISO-8859-1?Q?Beno=EEt?=: Orcad symbol for a Virtex II
    33993: 01/08/10: bob elkind: Re: Orcad symbol for a Virtex II
    35287: 01/09/27: Tim Hart: Re: Orcad symbol for a Virtex II
        35340: 01/09/29: Rotem Gazit: Re: Orcad symbol for a Virtex II
33991: 01/08/10: Robert Myers: Anyone using Xilinx System Generator yet???
    33997: 01/08/10: Ray Andraka: Re: Anyone using Xilinx System Generator yet???
    34013: 01/08/10: pete dudley: Re: Anyone using Xilinx System Generator yet???
33995: 01/08/10: bob elkind: newbie help needed
    33996: 01/08/10: bob elkind: Re: newbie help needed
        33999: 01/08/10: Abhimanyu Rastogi: Re: newbie help needed
            34014: 01/08/11: Russell Shaw: Re: newbie help needed
34003: 01/08/11: Jim Granville: Re: Low Cost FPGA or PLD
    34010: 01/08/11: Rick Filipkiewicz: Re: Low Cost FPGA or PLD
34006: 01/08/10: Todd Brown: Low Cost FPGA or PLD
    34015: 01/08/11: Peter Ormsby: Re: Low Cost FPGA or PLD
34008: 01/08/10: Manjunathan: how to acheive high frquency in Xinlinx Virtex E
    34022: 01/08/11: John_H: Re: how to acheive high frquency in Xinlinx Virtex E
    34025: 01/08/11: Kevin Neilson: Re: how to acheive high frquency in Xinlinx Virtex E
        34064: 01/08/13: <hamish@cloud.net.au>: Re: how to acheive high frquency in Xinlinx Virtex E
34012: 01/08/10: pete dudley: Quicklogic and Actel floorplanning?
    34024: 01/08/11: Jonathan Bromley: Re: Quicklogic and Actel floorplanning?
    34088: 01/08/14: Thomas Stanka: Re: Quicklogic and Actel floorplanning?
34029: 01/08/12: Mark Borgerson: Xilinx WebPack .UCF file
    34202: 01/08/16: Martin Rice: Re: Xilinx WebPack .UCF file
        34222: 01/08/16: Mark Borgerson: Re: Xilinx WebPack .UCF file
34035: 01/08/12: Mark Walter: Use of lpm in Xilinx Foundation 2.1i
    34053: 01/08/13: Utku Ozcan: Re: Use of lpm in Xilinx Foundation 2.1i
        34084: 01/08/13: Mark: Re: Use of lpm in Xilinx Foundation 2.1i
            34085: 01/08/14: Mark: Re: Use of lpm in Xilinx Foundation 2.1i
                34111: 01/08/14: Mike Treseler: Re: Use of lpm in Xilinx Foundation 2.1i
34039: 01/08/12: Martin v. Weymarn: Keep Xilinx Webpack from removing unused NETs?
    34072: 01/08/13: Andy Peters <andy [@] exponentmedia: Re: Keep Xilinx Webpack from removing unused NETs?
        34079: 01/08/13: Rick Filipkiewicz: Re: Keep Xilinx Webpack from removing unused NETs?
34040: 01/08/12: kryten_droid: Xilinx webpack vs. Student edition software
    34060: 01/08/13: Leon Heller: Re: Xilinx webpack vs. Student edition software
34042: 01/08/12: Kuan Zhou: Fast Mux and low power voltage reference
    34073: 01/08/13: Andy Peters <andy [@] exponentmedia: Re: Fast Mux and low power voltage reference
34048: 01/08/12: Christopher J. Holland: Digilab 10K10 resources / samples?
    34052: 01/08/13: Russell Shaw: Re: Digilab 10K10 resources / samples?
    34059: 01/08/13: Leon Heller: Re: Digilab 10K10 resources / samples?
        34069: 01/08/13: Christopher J. Holland: Re: Digilab 10K10 resources / samples?
34050: 01/08/12: Hu Chen: FPGA or CPLD data compression
    34051: 01/08/13: Jim Granville: Re: FPGA or CPLD data compression
        34068: 01/08/13: Hu Chen: Re: FPGA or CPLD data compression
34055: 01/08/13: =?ISO-8859-1?Q?H=E5kon?=: Virtex-II and LVDS clocks.
    34067: 01/08/13: Austin Lesea: Re: Virtex-II and LVDS clocks.
    34077: 01/08/13: Austin Lesea: Re: virtex2 Block Ram: dual port ram with different da
        34080: 01/08/13: Rick Filipkiewicz: Re: virtex2 Block Ram: dual port ram with different da
            34082: 01/08/13: Austin Lesea: Re: virtex2 Block Ram: dual port ram with different da
                34089: 01/08/14: Rick Filipkiewicz: Re: virtex2 Block Ram: dual port ram with different da
                    34104: 01/08/14: Austin Lesea: Re: virtex2 Block Ram: dual port ram with different da
    34086: 01/08/14: BriMDavis: Re: virtex2 Block Ram: dual port ram with different da
        34098: 01/08/14: spyng: Re: virtex2 Block Ram: dual port ram with different da
            34106: 01/08/14: Peter Alfke: Re: virtex2 Block Ram: dual port ram with different da
            34119: 01/08/14: Philip Freidin: Re: virtex2 Block Ram: dual port ram with different da
34071: 01/08/13: spyng: virtex2 Block Ram: dual port ram with different da
    34074: 01/08/13: Andy Peters <andy [@] exponentmedia: Re: virtex2 Block Ram: dual port ram with different da
        34075: 01/08/13: spyng: Re: virtex2 Block Ram: dual port ram with different da
        34081: 01/08/13: Philip Freidin: Re: virtex2 Block Ram: dual port ram with different da
            34115: 01/08/14: Andy Peters <andy [@] exponentmedia: Re: virtex2 Block Ram: dual port ram with different da
    34078: 01/08/13: Duane Clark: Re: virtex2 Block Ram: dual port ram with different da
34092: 01/08/14: jimmy: WinMe installation
    34099: 01/08/14: Paul Teagle: Re: WinMe installation
        34101: 01/08/14: jimmy siu: Re: WinMe installation
        34598: 01/08/30: G E Geiger: Re: WinMe installation
            34616: 01/08/31: Russell Shaw: Re: WinMe installation
    34126: 01/08/15: jimmy: Re: WinMe installation
    34246: 01/08/17: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Re: WinMe installation
34094: 01/08/14: Ali: Development Boards for FPGA based Application
    34120: 01/08/14: Steven K. Knapp: Re: Development Boards for FPGA based Application
    34134: 01/08/15: Robert White: FPGA Development Boards
    34156: 01/08/15: Walt: Re: Development Boards for FPGA based Application
34095: 01/08/14: Matthias Fuchs: constaining dll stuff problem
    34103: 01/08/14: David Hawke: Re: constaining dll stuff problem
34096: 01/08/14: khoi ha: VHDL floating point arithmetic
    34102: 01/08/14: Steven Derrien: Re: VHDL floating point arithmetic
34097: 01/08/14: Felix Brack: Looking for MAXPLUS DOS Version
34105: 01/08/14: Reinoud: A parallel port - low voltage signal interface (for new FPGAs)
34109: 01/08/14: David Pariseau: Xilinx foundation multi-pad pin assignments
    34121: 01/08/14: Philip Freidin: Re: Xilinx foundation multi-pad pin assignments
        34151: 01/08/15: David Pariseau: Re: Xilinx foundation multi-pad pin assignments
34112: 01/08/14: Steven Derrien: Modeling delay on a bidirectionnal signal
34118: 01/08/14: Eric Inazaki: Building a clock out of a PLD
    34124: 01/08/15: Jim Granville: Re: Building a clock out of a PLD
        34125: 01/08/14: Eric Inazaki: Re: Building a clock out of a PLD
            34135: 01/08/15: Maki: Re: Building a clock out of a PLD
            34139: 01/08/15: Jim Granville: Re: Building a clock out of a PLD
    34147: 01/08/15: luigi funes: Re: Building a clock out of a PLD
    34155: 01/08/15: Ken Smith: Re: Building a clock out of a PLD
        34164: 01/08/15: Eric Inazaki: Re: Building a clock out of a PLD
            34173: 01/08/16: Ken Smith: Re: Building a clock out of a PLD
    34165: 01/08/15: Martin Rice: Re: Building a clock out of a PLD
        34166: 01/08/15: Ben Franchuk: Re: Building a clock out of a PLD
        34170: 01/08/16: Jim Granville: Re: Building a clock out of a PLD
            34225: 01/08/16: Andy Peters <andy [@] exponentmedia: Re: Building a clock out of a PLD
        34174: 01/08/16: Ken Smith: Re: Building a clock out of a PLD
34122: 01/08/14: Rick Filipkiewicz: Porno Junk cluttering up CAF
    34123: 01/08/14: Duane Clark: Re: Porno Junk cluttering up CAF
34127: 01/08/15: Allan Herriman: Xilinx pin lists in text format
    34133: 01/08/15: Philip Freidin: Re: Xilinx pin lists in text format
        34137: 01/08/15: Allan Herriman: Re: Xilinx pin lists in text format
            34138: 01/08/15: Allan Herriman: Re: Xilinx pin lists in text format
34130: 01/08/15: Rick Collins: Replication of FFs in Xilinx XC4000
    34175: 01/08/16: Phil Hays: Re: Replication of FFs in Xilinx XC4000
        34181: 01/08/16: Rick Filipkiewicz: Re: Replication of FFs in Xilinx XC4000
            34234: 01/08/17: Phil Hays: Re: Replication of FFs in Xilinx XC4000
                34267: 01/08/17: Bret Wade: Re: Replication of FFs in Xilinx XC4000
    34178: 01/08/16: Hal Murray: Re: Replication of FFs in Xilinx XC4000
        34183: 01/08/16: Allan Herriman: Re: Replication of FFs in Xilinx XC4000
            34185: 01/08/16: Hal Murray: Re: Replication of FFs in Xilinx XC4000
                34190: 01/08/16: Allan Herriman: Re: Replication of FFs in Xilinx XC4000
        34203: 01/08/16: Magnus Homann: Re: Replication of FFs in Xilinx XC4000
34136: 01/08/15: jfh: Hysteresis behavior of an fpga buffer
34140: 01/08/15: Jason: FPGA for Reconfigurable Computing
    34194: 01/08/16: Herbi: Re: FPGA for Reconfigurable Computing
        34259: 01/08/17: Jason: Re: FPGA for Reconfigurable Computing
34141: 01/08/15: Richard B. Katz: 2001 MAPLD Conference: Early Registration Closing, Last CFP
34143: 01/08/15: Jonathan Wilson: I need help disassembling a JEDEC .jed file from a PLHS18P8A
    34145: 01/08/15: Keith R. Williams: Re: I need help disassembling a JEDEC .jed file from a PLHS18P8A
    34237: 01/08/17: Peter Ormsby: Re: I need help disassembling a JEDEC .jed file from a PLHS18P8A
34144: 01/08/15: Opende2001: fpga dev
    34696: 01/09/04: olivier JEAN: Re: fpga dev
        34708: 01/09/04: kryten_droid: Re: fpga dev
34146: 01/08/15: Jamie Sanderson: Internal clock skew when using DLL
    34149: 01/08/15: Peter Alfke: Re: Internal clock skew when using DLL
        34198: 01/08/16: K.O: Re: Internal clock skew when using DLL
            34226: 01/08/16: Tim: Re: Internal clock skew when using DLL
                34231: 01/08/16: Peter Alfke: Re: Internal clock skew when using DLL
                    34236: 01/08/16: qlyus: Re: Internal clock skew when using DLL
                    34244: 01/08/17: What Order: Re: Internal clock skew when using DLL
                        34258: 01/08/17: Peter Alfke: Re: Internal clock skew when using DLL
                    34249: 01/08/17: Jamie Sanderson: Re: Internal clock skew when using DLL
                        34260: 01/08/17: Peter Alfke: Re: Internal clock skew when using DLL
                            34313: 01/08/20: Philip Freidin: Re: Internal clock skew when using DLL
        34201: 01/08/16: fred: Re: Internal clock skew when using DLL
    34153: 01/08/15: Jamie Sanderson: Re: Internal clock skew when using DLL
        34154: 01/08/15: Jamie Sanderson: Re: Internal clock skew when using DLL
            34182: 01/08/15: Philip Freidin: Re: Internal clock skew when using DLL
                34207: 01/08/16: Jamie Sanderson: Re: Internal clock skew when using DLL
                34215: 01/08/16: Austin Lesea: Re: Internal clock skew when using DLL
        34257: 01/08/17: Falk Brunner: Re: Internal clock skew when using DLL
            34280: 01/08/18: K.O: Re: Internal clock skew when using DLL
                34297: 01/08/20: Philip Freidin: Re: Internal clock skew when using DLL
                34303: 01/08/20: <hamish@cloud.net.au>: Re: Internal clock skew when using DLL
                34317: 01/08/20: Falk Brunner: Re: Internal clock skew when using DLL
    34213: 01/08/16: Falk Brunner: Re: Internal clock skew when using DLL
    34248: 01/08/17: Matthias Fuchs: Re: Internal clock skew when using DLL
        34261: 01/08/17: Jamie Sanderson: Re: Internal clock skew when using DLL
    34300: 01/08/20: Jonathan Bromley: Re: Internal clock skew when using DLL
34157: 01/08/15: Adrianus: fpga with the smallest i/o setup and hold requirement
    34167: 01/08/15: Austin Lesea: Re: fpga with the smallest i/o setup and hold requirement
        34171: 01/08/15: Dave Feustel: Re: fpga with the smallest i/o setup and hold requirement
            34208: 01/08/16: Austin Lesea: Re: fpga with the smallest i/o setup and hold requirement
                34230: 01/08/16: Tim: Re: fpga with the smallest i/o setup and hold requirement
                    34252: 01/08/17: Austin Lesea: Re: fpga with the smallest i/o setup and hold requirement
34158: 01/08/15: Pierre de Vos: DPLL frequency synthesis
    34212: 01/08/16: John_H: Re: DPLL frequency synthesis
    34254: 01/08/17: Falk Brunner: Re: DPLL frequency synthesis
34163: 01/08/15: Frederic Antonin: Major performance problem with Modelsim
    34177: 01/08/16: Allan Herriman: Re: Major performance problem with Modelsim
34168: 01/08/15: Joey Oravec: Slowing PCI for FPGA
    34179: 01/08/16: Hal Murray: Re: Slowing PCI for FPGA
    34180: 01/08/15: Kevin Brace: Re: Slowing PCI for FPGA
        34191: 01/08/16: Olaf Birkeland: Re: Slowing PCI for FPGA
            34218: 01/08/16: Austin Franklin: Re: Slowing PCI for FPGA
        34223: 01/08/16: Andy Peters <andy [@] exponentmedia: Re: Slowing PCI for FPGA
    34200: 01/08/16: clevin1234: Re: Slowing PCI for FPGA
        34216: 01/08/16: Austin Franklin: Re: Slowing PCI for FPGA
    34217: 01/08/16: Austin Franklin: Re: Slowing PCI for FPGA
        34319: 01/08/21: Joseph Oravec: Re: Slowing PCI for FPGA
            34323: 01/08/21: Rick Filipkiewicz: Re: Slowing PCI for FPGA
                34332: 01/08/21: Joey Oravec: Re: Slowing PCI for FPGA
                    34354: 01/08/22: <hamish@cloud.net.au>: Re: Slowing PCI for FPGA
                        34373: 01/08/22: Joey Oravec: Re: Slowing PCI for FPGA
                            34407: 01/08/23: Ken McElvain: Re: Slowing PCI for FPGA
                                34423: 01/08/24: Austin Franklin: Re: Slowing PCI for FPGA
                                    34425: 01/08/24: Phil Hays: Re: Slowing PCI for FPGA
                                        34436: 01/08/24: Austin Franklin: Re: Slowing PCI for FPGA
                                            34451: 01/08/25: Phil Hays: Re: Slowing PCI for FPGA
                                                34456: 01/08/25: Austin Franklin: Re: Slowing PCI for FPGA
                                                    34458: 01/08/25: Ben Franchuk: Re: Slowing PCI for FPGA
                                                    34459: 01/08/26: Russell Shaw: Re: Slowing PCI for FPGA
                                                        34460: 01/08/25: Austin Franklin: Re: Slowing PCI for FPGA
                                                        34537: 01/08/29: Ray Andraka: Re: Slowing PCI for FPGA
                                                    34461: 01/08/26: Phil Hays: Re: Slowing PCI for FPGA
                                                        34472: 01/08/27: Austin Franklin: Re: Slowing PCI for FPGA
                                                            34482: 01/08/27: Kolja Sulimma: Re: Slowing PCI for FPGA
                                                                34498: 01/08/27: Philip Freidin: Defending Austin Franklin
                                                                    34501: 01/08/27: Ivar: Re: Defending Austin Franklin
                                                                    34513: 01/08/28: Don Husby: Re: Defending Austin Franklin
                                                                        34529: 01/08/28: Rick Filipkiewicz: Re: Defending Austin Franklin
                                                                            34534: 01/08/28: Austin Franklin: Re: Defending Austin Franklin
                                                                                34541: 01/08/29: Rick Filipkiewicz: Re: Defending Austin Franklin
                                                                                    34547: 01/08/29: Jim Granville: Re: Version Control
                                                                                        34549: 01/08/29: Austin Franklin: Re: Version Control
                                                                                            34572: 01/08/30: Jim Granville: Re: Version Control
                                                                                                34573: 01/08/29: Austin Franklin: Re: Version Control
                                                                                            34575: 01/08/29: Tim: Re: Version Control
                                                                                                34588: 01/08/30: Hal Murray: Re: Version Control
                                                                                                    34590: 01/08/30: Rick Filipkiewicz: Re: Version Control
                                                                                                    34593: 01/08/30: Tim: Re: Version Control
                                                                                                    34596: 01/08/30: Austin Franklin: Re: Version Control
                                                                                    34548: 01/08/29: Austin Franklin: Re: Defending Austin Franklin
                                                                                        34569: 01/08/29: Rick Filipkiewicz: Re: Defending Austin Franklin
                                                                                            34609: 01/08/30: Andy Peters <andy [@] exponentmedia: Re: Defending Austin Franklin
                                                                                                34610: 01/08/30: Austin Franklin: Re: Defending Austin Franklin
                                                                                                    34613: 01/08/30: Eric Smith: Re: Defending Austin Franklin
                                                                                                    34633: 01/08/31: Mike Treseler: Re: Defending Austin Franklin
                                                                                                        34643: 01/08/31: Ben Franchuk: Re: Defending Austin Franklin
                                                                                                            34655: 01/09/01: Simon Gornall: Re: Defending Austin Franklin
                                                                                                        34647: 01/08/31: Austin Franklin: Re: Defending Austin Franklin
                                                                                                            34654: 01/09/01: Kolja Sulimma: Re: Defending Austin Franklin
                                                                    34554: 01/08/29: Ivar: Re: Defending Austin Franklin
                                                                        34564: 01/08/29: Richard Dungan: Re: Defending Austin Franklin
                                                                34535: 01/08/29: Phil Hays: Re: Slowing PCI for FPGA
                                                            34494: 01/08/28: Phil Hays: Re: Slowing PCI for FPGA
                    34372: 01/08/22: Richard Iachetta: Re: Slowing PCI for FPGA
                        34386: 01/08/23: Austin Franklin: Re: Slowing PCI for FPGA
                            34395: 01/08/23: Rick Filipkiewicz: Re: Slowing PCI for FPGA
                            34410: 01/08/23: Richard Iachetta: Re: Slowing PCI for FPGA
                34340: 01/08/21: Austin Franklin: Re: Slowing PCI for FPGA
                34366: 01/08/22: Falk Brunner: Re: Slowing PCI for FPGA
            34329: 01/08/21: Keith R. Williams: Re: Slowing PCI for FPGA
    34224: 01/08/16: Andy Peters <andy [@] exponentmedia: Re: Slowing PCI for FPGA
    34255: 01/08/17: Falk Brunner: Re: Slowing PCI for FPGA
34169: 01/08/15: Quiet Desperation: Multilinx problem
34176: 01/08/16: Russell Shaw: star-wars ascii-animation:)
    34184: 01/08/16: Peter Seed: Re: star-wars ascii-animation:)
        34577: 01/08/29: Ben Franchuk: Re: star-wars ascii-animation:)
        34615: 01/08/30: Ron Huizen: Re: star-wars ascii-animation:)
    34197: 01/08/16: Andrew: Re: star-wars ascii-animation:)
        34256: 01/08/17: Tom Del Rosso: Re: star-wars ascii-animation:)
            34274: 01/08/18: -:Install:-: Re: star-wars ascii-animation:)
                34292: 01/08/19: Tom Del Rosso: Re: star-wars ascii-animation:)
    34242: 01/08/17: David L. Jones: Re: star-wars ascii-animation:)
        34299: 01/08/20: Andrew: Re: star-wars ascii-animation:)
34186: 01/08/16: John: Development boards
    34188: 01/08/16: Lars Rzymianowicz: Re: Development boards
    34193: 01/08/16: Herbi: Re: Development boards
    34285: 01/08/18: Jiri Gaisler: Re: Development boards
34187: 01/08/16: Herbi: Readback Xilinx Vertex FPGA
34189: 01/08/16: Andrew Gray: Help with ACEX1K100 device
    34192: 01/08/16: Herbi: Re: Help with ACEX1K100 device
        34195: 01/08/16: Robert Staven: Re: Help with ACEX1K100 device
        34196: 01/08/16: Andrew Gray: Re: Help with ACEX1K100 device
    34206: 01/08/16: Gerald B: Re: Help with ACEX1K100 device
        34240: 01/08/17: Andrew Gray: Re: Help with ACEX1K100 device
    34233: 01/08/17: Leon: Re: Help with ACEX1K100 device
34199: 01/08/16: Marc Battyani: Virtex-II and 5V devices
    34209: 01/08/16: Austin Lesea: Re: Virtex-II and 5V devices
        34219: 01/08/16: Marc Battyani: Re: Virtex-II and 5V devices
            34227: 01/08/16: Austin Lesea: Re: Virtex-II and 5V devices
    34221: 01/08/16: Andy Peters <andy [@] exponentmedia: Re: Virtex-II and 5V devices
        34228: 01/08/16: Marc Battyani: Re: Virtex-II and 5V devices
            34312: 01/08/20: Kolja Sulimma: Re: Virtex-II and 5V devices
        34229: 01/08/16: Rick Filipkiewicz: Re: Virtex-II and 5V devices
            34241: 01/08/17: Marc Battyani: Re: Virtex-II and 5V devices
                34251: 01/08/17: Austin Lesea: Re: Virtex-II and 5V devices
                    34266: 01/08/17: Marc Battyani: Re: Virtex-II and 5V devices
                        34268: 01/08/17: Austin Lesea: Re: Virtex-II and 5V devices
                            34275: 01/08/18: Hal Murray: Re: Virtex-II and 5V devices
                                34307: 01/08/20: Austin Lesea: Re: Virtex-II and 5V devices
34205: 01/08/16: Dave Feustel: Virtex Pro Info
    34220: 01/08/16: Philip Freidin: Re: Virtex Pro Info
        34245: 01/08/17: Dave Feustel: Re: Virtex Pro Info
34211: 01/08/16: Olaf Reichenbaecher: Xilinx Floorplanner in batch mode?
    34214: 01/08/16: Steven Derrien: Re: Xilinx Floorplanner in batch mode?
34232: 01/08/16: Vitali: Foundation Series 3.1i ---> Foundation Series ISE 3.3i
34235: 01/08/16: Jonathan Wilson: does anyone have a datasheet for a 18P8 PAL
    34250: 01/08/17: Jonathan Bromley: Re: does anyone have a datasheet for a 18P8 PAL
        34276: 01/08/17: Jonathan Wilson: Re: does anyone have a datasheet for a 18P8 PAL
    34281: 01/08/18: David Gesswein: Re: does anyone have a datasheet for a 18P8 PAL
34239: 01/08/16: Eric Smith: hardware damage to a Virtex or Spartan-II?
    34243: 01/08/17: Reinoud: Re: hardware damage to a Virtex or Spartan-II?
        34270: 01/08/17: Eric Smith: Re: hardware damage to a Virtex or Spartan-II?
            34289: 01/08/19: Reinoud: Re: hardware damage to a Virtex or Spartan-II?
                34306: 01/08/20: Austin Lesea: Re: hardware damage to a Virtex or Spartan-II?
            34314: 01/08/20: Peter Alfke: Re: hardware damage to a Virtex or Spartan-II?
                34316: 01/08/20: Bryan: Re: hardware damage to a Virtex or Spartan-II?
                34342: 01/08/21: John Larkin: Re: hardware damage to a Virtex or Spartan-II?
                    34364: 01/08/22: Austin Lesea: Re: hardware damage to a Virtex or Spartan-II?
                        34422: 01/08/23: Dave Vanden Bout: Re: hardware damage to a Virtex or Spartan-II?
                            34440: 01/08/24: Austin Lesea: Re: hardware damage to a Virtex or Spartan-II?
        34318: 01/08/20: glen herrmannsfeldt: Re: hardware damage to a Virtex or Spartan-II?
            34333: 01/08/21: Bryan: Re: hardware damage to a Virtex or Spartan-II?
                34335: 01/08/21: glen herrmannsfeldt: Re: hardware damage to a Virtex or Spartan-II?
                    34341: 01/08/21: Peter Alfke: Re: hardware damage to a Virtex or Spartan-II?
                    34343: 01/08/21: Philip Freidin: Re: hardware damage to a Virtex or Spartan-II?
                        34351: 01/08/22: Tim: Re: hardware damage to a Virtex or Spartan-II?
                            34369: 01/08/22: glen herrmannsfeldt: Re: hardware damage to a Virtex or Spartan-II?
                                34378: 01/08/22: Philip Freidin: Re: hardware damage to a Virtex or Spartan-II?
                    34361: 01/08/22: Bryan: Re: hardware damage to a Virtex or Spartan-II?
34247: 01/08/17: M Pedley: Atmel CPLD - JEDEC to ABEL
    34253: 01/08/18: Jim Granville: Re: Atmel CPLD - JEDEC to ABEL
        34279: 01/08/18: M Pedley: Re: Atmel CPLD - JEDEC to ABEL
            34286: 01/08/19: Jim Granville: Re: Atmel CPLD - JEDEC to ABEL
34262: 01/08/17: Speedy Zero Two: Xilinx DLL in VirtexE
    34264: 01/08/17: Peter Alfke: Re: Xilinx DLL in VirtexE
34277: 01/08/18: Hayden So: connected "not connect" pins on Xilinx
    34282: 01/08/18: Leon Heller: Re: connected "not connect" pins on Xilinx
    34315: 01/08/20: Peter Alfke: Re: connected "not connect" pins on Xilinx
    34322: 01/08/21: Leon Heller: Re: connected "not connect" pins on Xilinx
34278: 01/08/18: Miha Dolenc: Spartan2 5V PCI IO
    34287: 01/08/18: Eric Crabill: Re: Spartan2 5V PCI IO
        34304: 01/08/20: <hamish@cloud.net.au>: Re: Spartan2 5V PCI IO
            34309: 01/08/20: Tim: Re: Spartan2 5V PCI IO
    34293: 01/08/19: Brian Drummond: Re: Spartan2 5V PCI IO
34283: 01/08/18: Markus Meng: [Spartan-II] JTAG configuration problem ...
    34290: 01/08/18: Jeff and Bev Neil: Re: [Spartan-II] JTAG configuration problem ...
34288: 01/08/18: John Morris: Asia-Pacific Computer Systems Architecture Conference - CFP
34294: 01/08/19: Dave Feustel: Principles of Verifiable RTL Design (2nd ed)
    34348: 01/08/22: James Lee: Re: Principles of Verifiable RTL Design (2nd ed)
        34360: 01/08/22: Ben Franchuk: Re: Principles of Verifiable RTL Design (2nd ed)
            34412: 01/08/23: Ben Franchuk: Re: Principles of Verifiable RTL Design (2nd ed)
                34414: 01/08/23: Ben Franchuk: Re: Principles of Verifiable RTL Design (2nd ed)
                    34601: 01/08/30: Nial Stewart: Re: Principles of Verifiable RTL Design (2nd ed)
                34441: 01/08/24: Andy Peters <andy [@] exponentmedia: Re: Principles of Verifiable RTL Design (2nd ed)
            34437: 01/08/24: Mike: Re: Principles of Verifiable RTL Design (2nd ed)
34298: 01/08/20: Hans: JTAG
    34311: 01/08/20: Philip Freidin: Re: JTAG
34301: 01/08/20: Mark Taylor: Some questions about Spartan2 (& a bug report for XST sp8)
    34305: 01/08/20: Mark Taylor: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34308: 01/08/20: Johnsonw10: Need help: CLKDLLE.v does not work in simulation.
    34326: 01/08/21: fred: Re: Need help: CLKDLLE.v does not work in simulation.
        34327: 01/08/21: lennart: Re: Need help: CLKDLLE.v does not work in simulation.
34310: 01/08/20: Nicolas Matringe: Xilinx XC18V PROM problem
34321: 01/08/20: tonyz: Set up!
34325: 01/08/21: federico: hardware(FPGA,DSP......) that it implements a function random or method of runge kutta?
34328: 01/08/21: Mark: FPGA MP3 decoder
    34330: 01/08/21: Wolfgang Loewer: Re: FPGA MP3 decoder
        34331: 01/08/21: Mark: Re: FPGA MP3 decoder
            34353: 01/08/22: Robin Kinge: Re: FPGA MP3 decoder
            34357: 01/08/22: Lewis: Re: FPGA MP3 decoder
    34367: 01/08/22: Andy Peters <andy [@] exponentmedia: Re: FPGA MP3 decoder
        34401: 01/08/23: Falk Brunner: Re: FPGA MP3 decoder
34334: 01/08/21: Mark Taylor: Re: Some questions about Spartan2 (& a bug report for XST sp8)
    34448: 01/08/25: Mark Taylor: Re: Some questions about Spartan2 (& a bug report for XST sp8)
        34450: 01/08/24: Austin Lesea: Re: Some questions about Spartan2 (& a bug report for XST sp8)
            34466: 01/08/26: Mark Taylor: Re: Some questions about Spartan2 (& a bug report for XST sp8)
                34476: 01/08/27: Austin Lesea: Re: Some questions about Spartan2 (& a bug report for XST sp8)
            34475: 01/08/27: Tim: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34336: 01/08/21: Abhimanyu Rastogi: How does For Loop works in AHDL
    34346: 01/08/22: Russell Shaw: Re: How does For Loop works in AHDL
        34362: 01/08/22: Abhimanyu Rastogi: Re: How does For Loop works in AHDL
            34365: 01/08/22: John_H: Re: How does For Loop works in AHDL
                34368: 01/08/22: Abhimanyu Rastogi: Re: How does For Loop works in AHDL
                    34377: 01/08/22: John_H: Re: How does For Loop works in AHDL
        34374: 01/08/22: Steve: Re: How does For Loop works in AHDL
34337: 01/08/21: M Smith: Help the clueless guy....
    34344: 01/08/21: Philip Freidin: Re: Help the clueless guy....
    34347: 01/08/22: Russell Shaw: Re: Help the clueless guy....
34338: 01/08/22: Jim Granville: Re: protecting pins on xilinx xc95 cpld
34339: 01/08/22: Daniel Nilsson: protecting pins on xilinx xc95 cpld
34345: 01/08/21: Justin Oo: JTAG issue again ...
    34376: 01/08/22: Justin Oo: Re: JTAG issue again ...
        34379: 01/08/22: Rick Filipkiewicz: Re: JTAG issue again ...
    34628: 01/09/01: Terrence Mak: Re: JTAG issue again ...
34349: 01/08/22: Michael Boehnel: Logic Emulation
    34352: 01/08/22: Tim: Re: Logic Emulation
        34370: 01/08/22: Muzaffer Kal: Re: Logic Emulation
            34371: 01/08/22: Tim: Re: Logic Emulation
            34375: 01/08/22: John Eaton: Re: Logic Emulation
        34384: 01/08/22: Ben Franchuk: Re: Logic Emulation
        34389: 01/08/23: Thomas Stanka: Re: Logic Emulation
        34396: 01/08/23: Falk Brunner: Re: Logic Emulation
            34408: 01/08/23: Ken McElvain: Re: Logic Emulation
            34565: 01/08/29: Ben Franchuk: Re: Logic Emulation
34350: 01/08/22: Hakon Lislebo: Confusion around BUS LVDS in Virtex-II
    34390: 01/08/23: Hakon Lislebo: Re: Confusion around BUS LVDS in Virtex-II
34355: 01/08/22: Sanjay Maniku: Re: I NEED TO BUY A FPGA BOARD
    34399: 01/08/23: Andy Peters <andy [@] exponentmedia: Re: Optical Bay Area Start-up! SW/HW Engs needed
        34405: 01/08/23: Rick Filipkiewicz: Re: Optical Bay Area Start-up! SW/HW Engs needed
        34416: 01/08/23: Philip Freidin: Re: Optical Bay Area Start-up! SW/HW Engs needed
            34442: 01/08/24: Andy Peters <andy [@] exponentmedia: Re: Optical Bay Area Start-up! SW/HW Engs needed
34381: 01/08/22: Completely Fazed: Virtex-II place and route : Design doesn't route
    34383: 01/08/23: Tim: Re: Virtex-II place and route : Design doesn't route
    34388: 01/08/22: Ivar: Re: Virtex-II place and route : Design doesn't route
34385: 01/08/23: A. I. Khan: Why this mismatches in simulation and sysnthesis results ?
    34387: 01/08/23: Kevin Neilson: Re: Why this mismatches in simulation and sysnthesis results ?
34391: 01/08/23: <khtsoi@pc90026.cse.cuhk.edu.hk>: xchecker under Linux
34392: 01/08/23: Andrew Gray: SmartMedia
    34428: 01/08/24: Martin Roenne: Re: SmartMedia
        34433: 01/08/24: Kolja Sulimma: Re: SmartMedia
        34434: 01/08/24: Bram van de Kerkhof: Re: SmartMedia
            34544: 01/08/29: Edwin Naroska: Re: SmartMedia
    34446: 01/08/24: darrell mcginnis: Re: SmartMedia
    35203: 01/09/25: Paul J. Menchini: Re: SmartMedia
34394: 01/08/23: Dave Feustel: Latest Maxim bit serializer-deserializer chip announcements
    34418: 01/08/23: John Larkin: Re: Latest Maxim bit serializer-deserializer chip announcements
        34424: 01/08/24: Dave Feustel: Re: Latest Maxim bit serializer-deserializer chip announcements
            34457: 01/08/25: John Larkin: Re: Latest Maxim bit serializer-deserializer chip announcements
34397: 01/08/23: Patrick Dano: Actel Pad locations
    34427: 01/08/24: Thomas Stanka: Re: Actel Pad locations
34398: 01/08/23: Speedy Zero Two: DRAM burst mode
    34403: 01/08/23: Jan Pech: Re: DRAM burst mode
        34445: 01/08/24: Speedy Zero Two: Re: DRAM burst mode
            34447: 01/08/25: Rick Filipkiewicz: Re: DRAM burst mode
                34455: 01/08/25: Speedy Zero Two: Re: DRAM burst mode
                    34481: 01/08/27: Andy Peters <andy [@] exponentmedia: Re: DRAM burst mode
34400: 01/08/23: Diedricher: Testbench book
    34402: 01/08/23: VhdlCohen: Re: Testbench book
    34404: 01/08/23: Tim: Re: Testbench book
34406: 01/08/23: Rick Filipkiewicz: Testing ... please ignore
    34697: 01/09/04: Kate Thompson: Re: Testing ... please ignore
34409: 01/08/23: Rick Filipkiewicz: Carry chain warnings from Xilinx MAP
    34432: 01/08/24: Rick Filipkiewicz: Re: Carry chain warnings from Xilinx MAP
34411: 01/08/23: Rick Filipkiewicz: Re: DRAM Burst Mode
    34413: 01/08/23: Speedy Zero Two: Re: DRAM Burst Mode
        34415: 01/08/23: Rick Filipkiewicz: Re: DRAM Burst Mode
34417: 01/08/24: Alex Rast: Xilinx FPGA Editor - how to route to an internal macro net?
    34449: 01/08/25: Mark Taylor: Re: Xilinx FPGA Editor - how to route to an internal macro net?
        34484: 01/08/27: Alex Rast: Re: Xilinx FPGA Editor - how to route to an internal macro net?
            34510: 01/08/28: Mark Taylor: Re: Xilinx FPGA Editor - how to route to an internal macro net?
                34580: 01/08/29: Alex Rast: Re: Xilinx FPGA Editor - how to route to an internal macro net?
                    34608: 01/08/30: Mark Taylor: Re: Xilinx FPGA Editor - how to route to an internal macro net?
                        34624: 01/08/31: Mark Taylor: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34419: 01/08/24: Kevin Neilson: Reading Text in Verilog
    34439: 01/08/24: Brian Philofsky: Re: Reading Text in Verilog
    34443: 01/08/24: Andy Peters <andy [@] exponentmedia: Re: Reading Text in Verilog
34426: 01/08/24: Jan Pech: Spartan-II & clock
    34429: 01/08/24: Stephan Neuhold: Re: Spartan-II & clock
    34430: 01/08/24: Falk: Re: Spartan-II & clock
        34431: 01/08/24: Jan Pech: Re: Spartan-II & clock
    34478: 01/08/27: John_H: Re: Spartan-II & clock
        34508: 01/08/28: Jan Pech: Re: Spartan-II & clock
34438: 01/08/24: Artur: Set associative mapping in VHDL
34444: 01/08/24: Aare Tali: Spartan II JTAG configuration
    34827: 01/09/10: Falk Brunner: Re: Spartan II JTAG configuration
        34858: 01/09/11: Aare Tali: Re: Spartan II JTAG configuration
34465: 01/08/26: Fred: Help needed: simulation OK, synthesis OK, but doesnt work :-<
    34468: 01/08/26: skitz: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
    34477: 01/08/27: John_H: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
    34496: 01/08/27: lingbo: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
        34504: 01/08/28: Rick Filipkiewicz: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
            34505: 01/08/28: Fred: Re: Help needed: simulation OK, synthesis OK, but doesnt work :-<
34467: 01/08/26: Mark Taylor: Some questions about Spartan2 (& a bug report for XST sp8)
34469: 01/08/27: Petter Gustad: PCI-X based hosts, availability?
34470: 01/08/27: H.L: System Requirements
    34480: 01/08/27: Leon Heller: Re: System Requirements
        34500: 01/08/28: Hakon Lislebo: Re: System Requirements
            34516: 01/08/28: Nial Stewart: Re: System Requirements
                34530: 01/08/28: Rick Filipkiewicz: Re: System Requirements
                    34550: 01/08/29: Nial Stewart: Re: System Requirements
                        34570: 01/08/29: Rick Filipkiewicz: Re: System Requirements
        34552: 01/08/29: H.L: Re: System Requirements
34471: 01/08/27: Antonio: Polyphase adjustment to keep it working
    34490: 01/08/28: Daniel Nilsson: Re: Polyphase adjustment to keep it working
34474: 01/08/27: Daniel Nilsson: new to fpga
    34503: 01/08/28: Felix Bertram: Re: new to fpga
        34533: 01/08/29: Ray Andraka: Re: new to fpga
34479: 01/08/27: Marco Castellon: DUART core synthesizable in Xilinx FPGA.
    34486: 01/08/27: Steven K. Knapp: Re: DUART core synthesizable in Xilinx FPGA.
34483: 01/08/27: KJ: Looking for a synthesizable JPEG coder core
    34725: 01/09/05: Vincenzo Liguori: Re: Looking for a synthesizable JPEG coder core
34485: 01/08/27: Moadl: FPGA : USB in an FPGA, has anyone done it before?
    34502: 01/08/28: Felix Bertram: Re: FPGA : USB in an FPGA, has anyone done it before?
        34507: 01/08/28: Dave Feustel: Re: FPGA : USB in an FPGA, has anyone done it before?
            34511: 01/08/28: Felix Bertram: Re: FPGA : USB in an FPGA, has anyone done it before?
                34512: 01/08/28: Dave Feustel: Re: FPGA : USB in an FPGA, has anyone done it before?
                    34514: 01/08/28: Glen Atkins: Re: FPGA : USB in an FPGA, has anyone done it before?
                        34528: 01/08/28: Dave Feustel: Re: FPGA : USB in an FPGA, has anyone done it before?
                            34539: 01/08/29: Felix Bertram: Re: FPGA : USB in an FPGA, has anyone done it before?
                    34524: 01/08/29: Jim Granville: Re: FPGA : USB in an FPGA, has anyone done it before?
                    34527: 01/08/28: Muzaffer Kal: Re: FPGA : USB in an FPGA, has anyone done it before?
                        34653: 01/09/01: David Feustel: Re: FPGA : USB in an FPGA, has anyone done it before?
                    34666: 01/09/02: <jum>: Re: FPGA : USB in an FPGA, has anyone done it before?
    34716: 01/09/05: Mark Pettigrew: Re: FPGA : USB in an FPGA, has anyone done it before?
34487: 01/08/27: Ken Morrow: FPGA to ASIC conversion?
    34488: 01/08/27: Muzaffer Kal: Re: FPGA to ASIC conversion?
    34491: 01/08/27: Eric Braeden: Re: FPGA to ASIC conversion?
    34492: 01/08/28: Kevin Neilson: Re: FPGA to ASIC conversion?
34495: 01/08/28: Daniel Nilsson: IEEE 1149.1-1990
34499: 01/08/28: <khtsoi@pc90026.cse.cuhk.edu.hk>: download bitstream to FPGA
    34506: 01/08/28: Fred: Re: download bitstream to FPGA
        34536: 01/08/29: <khtsoi@pc90026.cse.cuhk.edu.hk>: Re: download bitstream to FPGA
            34538: 01/08/29: Lasse Langwadt Christensen: Re: download bitstream to FPGA
            34546: 01/08/29: Philip Freidin: Re: download bitstream to FPGA
                34585: 01/08/30: <khtsoi@pc90026.cse.cuhk.edu.hk>: Re: download bitstream to FPGA
                    34589: 01/08/30: Philip Freidin: Re: download bitstream to FPGA
                        34592: 01/08/30: <khtsoi@pc90026.cse.cuhk.edu.hk>: Re: download bitstream to FPGA
                34586: 01/08/30: <khtsoi@pc90026.cse.cuhk.edu.hk>: Re: download bitstream to FPGA
    34560: 01/08/29: Alan Nishioka: Re: download bitstream to FPGA
        34574: 01/08/29: Neil Franklin: Re: download bitstream to FPGA
            34579: 01/08/29: Alan Nishioka: Re: download bitstream to FPGA
34515: 01/08/28: Rémi SEGLIE: Orcad Symbol
    34519: 01/08/28: Jan Pech: Re: Orcad Symbol
    34809: 01/09/08: remi-seglie: Re: Orcad Symbol
34517: 01/08/28: Dave Colson: test
34518: 01/08/28: Chris Softley: Level sensitive latches in Xilinx Virtex
    34520: 01/08/28: Mike Treseler: Re: Level sensitive latches in Xilinx Virtex
    34522: 01/08/28: Chris Softley: Re: Level sensitive latches in Xilinx Virtex
    34531: 01/08/28: Rick Filipkiewicz: Re: Level sensitive latches in Xilinx Virtex
        34532: 01/08/28: Muzaffer Kal: Re: Level sensitive latches in Xilinx Virtex
        34558: 01/08/29: Chris Softley: Re: Level sensitive latches in Xilinx Virtex
            34567: 01/08/29: Philip Freidin: Re: Level sensitive latches in Xilinx Virtex
    34828: 01/09/10: Falk Brunner: Re: Level sensitive latches in Xilinx Virtex
    34555: 01/08/29: Jim E: Re: Urgent Help Needed
        34561: 01/08/29: Mike Treseler: Re: Urgent Help Needed
            34600: 01/08/30: Jim E: Re: Urgent Help Needed
        34566: 01/08/29: Philip Freidin: Re: Urgent Help Needed
            34599: 01/08/30: Jim E: Re: Urgent Help Needed
34540: 01/08/28: sadik khan: Any body used ACEX1K series for testing the design??
    34562: 01/08/29: Mike Treseler: Re: Any body used ACEX1K series for testing the design??
34542: 01/08/29: kahhean: Gate Count Definition
    34545: 01/08/29: Rick Filipkiewicz: Re: Gate Count Definition
        34559: 01/08/29: Austin Lesea: Re: Gate Count Definition
34543: 01/08/29: EuroEDA Information: X-HDL translation tool now available in Europe from EuroEDA
34551: 01/08/29: Johan Ditmar: global VHDL signals and FPGA express
    34557: 01/08/29: AlexP: Re: global VHDL signals and FPGA express
    34563: 01/08/29: Mike Treseler: Re: global VHDL signals and FPGA express
34553: 01/08/29: ananth: beginner
34556: 01/08/30: Tracy Briscoe: Ethernet CRC
    34571: 01/08/29: Douglas Grant: Re: Ethernet CRC
        34584: 01/08/30: Tracy Briscoe: Re: Ethernet CRC
            34602: 01/08/30: Mike Treseler: Re: Ethernet CRC
34568: 01/08/29: Sosgez: Atmel JTAG cable
34576: 01/08/29: Abhimanyu Rastogi: Urgent Please
    34582: 01/08/29: John_H: Re: Urgent Please
34578: 01/08/29: Jack Tai: Model sim vhdl simulation crash
    34748: 01/09/06: Srinivasan Venkataramanan: Re: Model sim vhdl simulation crash
34581: 01/08/29: Jen: Virtex II sizing rule of thumb
    34704: 01/09/04: Vikash Rungta: Re: Virtex II sizing rule of thumb
    34735: 01/09/05: Jen: Re: Virtex II sizing rule of thumb
        34743: 01/09/06: Ray Andraka: Re: Virtex II sizing rule of thumb
34583: 01/08/29: Muzaffer Kal: sharing a PROM between configuration and the FPGA
34587: 01/08/29: jaideep: XC2V3000-4BF957
    34636: 01/08/31: Andy Peters <andy [@] exponentmedia: Re: XC2V3000-4BF957
    34709: 01/09/04: Konrad Burylo: Re: XC2V3000-4BF957
34591: 01/08/30: Michael Boehnel: Big SR in Virtex-E
    34594: 01/08/30: Tim: Re: Big SR in Virtex-E
        34611: 01/08/30: Ray Andraka: Re: Big SR in Virtex-E
34595: 01/08/30: David Wright: WebPack Con-Game
    34606: 01/08/30: Eric Smith: Re: WebPack Con-Game
        34607: 01/08/30: Dave Colson: Re: WebPack Con-Game
            34612: 01/08/30: Eric Smith: Re: WebPack Con-Game
                34626: 01/08/31: Dave Colson: Re: WebPack Con-Game
                    34637: 01/08/31: Eric Smith: Re: WebPack Con-Game
                        34640: 01/08/31: Dave Colson: Re: WebPack Con-Game
                            34644: 01/08/31: Eric Smith: Re: WebPack Con-Game
        34726: 01/09/05: David Wright: Re: WebPack Con-Game
            34737: 01/09/05: Eric Smith: Re: WebPack Con-Game
            34874: 01/09/12: Kevin Brace: Re: WebPack Con-Game
    34622: 01/08/31: Santiago de Pablo: Re: WebPack Con-Game
        34645: 01/09/01: Peter Ormsby: Re: WebPack Con-Game
    34667: 01/09/02: Ben Franchuk: Re: WebPack Con-Game
        34703: 01/09/04: Speedy Zero Two: Re: WebPack Con-Game
    34668: 01/09/02: Kevin Brace: Re: WebPack Con-Game
34597: 01/08/30: Nisreen Taiyeby: FPGA: time_sim.sdf does not have the setup times f
    34635: 01/08/31: Andy Peters <andy [@] exponentmedia: Re: FPGA: time_sim.sdf does not have the setup times f
        34650: 01/09/01: Nisreen Taiyeby: Re: FPGA: time_sim.sdf does not have the setup times f
    34701: 01/09/04: Brian Philofsky: Re: FPGA: time_sim.sdf does not have the setup times f
34604: 01/08/30: Dereck: XCV800 : Jbits
    34614: 01/08/30: Tim: Re: XCV800 : Jbits
        34642: 01/09/01: Neil Franklin: Re: XCV800 : Jbits
34605: 01/08/30: Dereck: Jbits: more info required
    34629: 01/09/01: Terrence Mak: Re: Jbits: more info required
        34641: 01/08/31: Neil Franklin: Re: Jbits: more info required
    34634: 01/08/31: Andy Peters <andy [@] exponentmedia: Re: Jbits: more info required
        34638: 01/08/31: Eric Smith: Re: Jbits: more info required
    34632: 01/08/31: Andy Peters <andy [@] exponentmedia: Re: timing delay problem
34618: 01/08/31: Abhimanyu Rastogi: Timing delay problem
34619: 01/08/31: DIVERSEG: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34623: 01/08/31: Tim: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34625: 01/08/31: Ray Andraka: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
    34631: 01/08/31: Andy Peters <andy [@] exponentmedia: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
        34639: 01/08/31: Ray Andraka: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
            34648: 01/09/01: DIVERSEG: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
            34707: 01/09/04: Andy Peters: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
                34711: 01/09/04: Ray Andraka: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
34620: 01/08/31: Petter Gustad: Xilinx Device Update under Solaris
    34660: 01/09/02: <hamish@cloud.net.au>: Re: Xilinx Device Update under Solaris
        34661: 01/09/02: Petter Gustad: Re: Xilinx Device Update under Solaris
            34698: 01/09/04: <hamish@cloud.net.au>: Re: Xilinx Device Update under Solaris
34621: 01/08/31: Noddy: Ugly signal output...
    34627: 01/08/31: John_H: Re: Ugly signal output...
    34630: 01/08/31: Andy Peters <andy [@] exponentmedia: Re: Ugly signal output...


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