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Threads Starting Sep 2002
46492: 02/09/01: Niv: Multiplexing a tristate bus?
46499: 02/09/01: John_H: Re: Multiplexing a tristate bus?
46502: 02/09/01: Philip Freidin: Re: Multiplexing a tristate bus?
46500: 02/09/01: Nicholas C. Weaver: Logic on Virtex CLB, what's the YB and XB used for?
46559: 02/09/03: John_H: Re: Logic on Virtex CLB, what's the YB and XB used for?
46565: 02/09/03: Nicholas C. Weaver: Re: Logic on Virtex CLB, what's the YB and XB used for?
46569: 02/09/03: John_H: Re: Logic on Virtex CLB, what's the YB and XB used for?
46503: 02/09/01: Dan: In 2 clk domains. How to xfer data from 1 bus to the another ?
46506: 02/09/02: Peter Alfke: Re: In 2 clk domains. How to xfer data from 1 bus to the another ?
46548: 02/09/03: Paul: Re: In 2 clk domains. How to xfer data from 1 bus to the another ?
46507: 02/09/01: Eyal Shachrai: virtex2 : high pulse during configuration
46510: 02/09/02: Arguo: high-speed design rule on FPGAs?
46514: 02/09/02: Paul Baxter: Re: high-speed design rule on FPGAs?
46538: 02/09/02: Stan: Re: high-speed design rule on FPGAs?
46516: 02/09/02: jan: synthesizing hard coded numbers
46525: 02/09/02: Mike Treseler: Re: synthesizing hard coded numbers
46537: 02/09/02: Stan: Re: synthesizing hard coded numbers
46541: 02/09/02: John_H: Re: synthesizing hard coded numbers
46587: 02/09/04: Stan: Re: synthesizing hard coded numbers
46517: 02/09/02: Kunal: Hardware Code Morphing?
46521: 02/09/02: Stephen Fuld: Re: Hardware Code Morphing?
46522: 02/09/02: Falk Brunner: Re: Hardware Code Morphing?
46527: 02/09/02: Robin KAY: Re: Hardware Code Morphing?
46529: 02/09/02: Nicholas C. Weaver: Re: Hardware Code Morphing?
46533: 02/09/02: Peter: Re: Hardware Code Morphing?
46534: 02/09/02: Nicholas C. Weaver: Re: Hardware Code Morphing?
46572: 02/09/03: Austin Franklin: Re: Hardware Code Morphing?
46528: 02/09/02: Terje Mathisen: Re: Hardware Code Morphing?
46530: 02/09/02: Nicholas C. Weaver: Re: Hardware Code Morphing?
46546: 02/09/03: David Brown: Re: Hardware Code Morphing?
46550: 02/09/03: Peter Mayne: Re: Hardware Code Morphing?
46597: 02/09/04: Robert Wessel: Re: Hardware Code Morphing?
46603: 02/09/04: Ketil Malde: Re: Hardware Code Morphing?
46606: 02/09/04: Robin KAY: Re: Hardware Code Morphing?
46634: 02/09/04: Robert Wessel: Re: Hardware Code Morphing?
46662: 02/09/05: Robin KAY: Re: Hardware Code Morphing?
46678: 02/09/05: hack: Re: Hardware Code Morphing?
46531: 02/09/02: Nick Maclaren: Re: Hardware Code Morphing?
46532: 02/09/02: Nicholas C. Weaver: Re: Hardware Code Morphing?
46553: 02/09/03: Bernd Paysan: Re: Hardware Code Morphing?
46557: 02/09/03: Peter da Silva: Re: Hardware Code Morphing?
46562: 02/09/03: Richard Steven Walz: Re: Hardware Code Morphing?
46564: 02/09/03: Richard Steven Walz: Re: Hardware Code Morphing?
46526: 02/09/02: Jan-Hinnerk Reichert: Re: Hardware Code Morphing?
46552: 02/09/03: Kunal: Re: Hardware Code Morphing?
46539: 02/09/02: Stephen Pelc: Re: Hardware Code Morphing?
46556: 02/09/03: Peter da Silva: Re: Hardware Code Morphing?
46575: 02/09/03: Nate D. Tuck: Re: Hardware Code Morphing?
46580: 02/09/03: Andy Glew, Public: Re: Hardware Code Morphing?
46629: 02/09/04: Peter da Silva: Re: Hardware Code Morphing?
46703: 02/09/06: Jan C. =?iso-8859-1?Q?Vorbr=FCggen?=: Re: Hardware Code Morphing?
46664: 02/09/05: Martin Thompson: Re: Hardware Code Morphing?
46570: 02/09/03: Austin Franklin: Re: Hardware Code Morphing?
46573: 02/09/03: Steve Casselman: Re: Hardware Code Morphing?
46579: 02/09/04: MooCow: Re: Hardware Code Morphing?
46650: 02/09/05: Thomas Maslen: Re: Hardware Code Morphing?
46518: 02/09/02: Jan Gray: Verilog 2001 < VHDL
46519: 02/09/02: Duy K Do: IT consultant vs Engineer
46549: 02/09/03: Hans Summers: Re: IT consultant vs Engineer
46554: 02/09/03: Nial Stewart: Re: IT consultant vs Engineer
46577: 02/09/04: Rick Filipkiewicz: Re: IT consultant vs Engineer
46520: 02/09/02: Denis Gleeson: Basic question: configuring IOBs ???
46523: 02/09/02: Falk Brunner: Re: Basic question: configuring IOBs ???
46535: 02/09/02: Frank Andreas de Groot: C/C++ to Verilog/VHDL ?!
46536: 02/09/02: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46540: 02/09/03: Jim Granville: Re: C/C++ to Verilog/VHDL ?!
46542: 02/09/03: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46551: 02/09/03: Rene Tschaggelar: Re: C/C++ to Verilog/VHDL ?!
46566: 02/09/03: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46568: 02/09/03: Austin Lesea: Re: C/C++ to Verilog/VHDL ?!
46571: 02/09/03: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46585: 02/09/03: Austin Franklin: Re: C/C++ to Verilog/VHDL ?!
46586: 02/09/04: Stan: Re: C/C++ to Verilog/VHDL ?!
46682: 02/09/05: Dr. Andy Nisbet: Re: C/C++ to Verilog/VHDL ?!
46696: 02/09/06: Tim: Re: C/C++ to Verilog/VHDL ?!
46601: 02/09/04: Noel Klonsky: Re: C/C++ to Verilog/VHDL ?!
46584: 02/09/04: Stan: Re: C/C++ to Verilog/VHDL ?!
46805: 02/09/09: John Jakson: Re: C/C++ to Verilog/VHDL ?!
46819: 02/09/09: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46870: 02/09/10: Pierre-Olivier Laprise: Re: C/C++ to Verilog/VHDL ?!
46876: 02/09/10: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46892: 02/09/11: Jim Granville: Re: C/C++ to Verilog/VHDL ?!
46904: 02/09/11: Frank Andreas de Groot: Re: C/C++ to Verilog/VHDL ?!
46923: 02/09/12: Thomas Stanka: Re: C/C++ to Verilog/VHDL ?!
46547: 02/09/03: BROTO Laurent: Question about IOB, BUFG, IBUF and IBUG.
46558: 02/09/03: Falk Brunner: Re: Question about IOB, BUFG, IBUF and IBUG.
46560: 02/09/03: lng: Re: Question about IOB, BUFG, IBUF and IBUG.
46561: 02/09/03: Ryan Laity: Re: Question about IOB, BUFG, IBUF and IBUG.
47348: 02/09/24: John: Re: Question about IOB, BUFG, IBUF and IBUG.
47364: 02/09/24: Falk Brunner: Re: Question about IOB, BUFG, IBUF and IBUG.
46679: 02/09/05: BROTO Laurent: Re: Question about IOB, BUFG, IBUF and IBUG.
46563: 02/09/03: hristo: why Xilinx does not make its own HDL synthesiser?
46576: 02/09/03: Eric Smith: Re: why Xilinx does not make its own HDL synthesiser?
46581: 02/09/03: Jan Gray: MAP problem: Trivial RPM fails
46684: 02/09/05: John_H: Re: MAP problem: Trivial RPM fails
47329: 02/09/23: Bret Wade: Re: MAP problem: Trivial RPM fails
47334: 02/09/24: Muthu: Re: MAP problem: Trivial RPM fails
47336: 02/09/24: Allan Herriman: Re: MAP problem: Trivial RPM fails
47373: 02/09/24: Bret Wade: Re: MAP problem: Trivial RPM fails
47396: 02/09/24: Jan Gray: RPM_GRID (was MAP problem: Trivial RPM fails)
47695: 02/10/02: <hamish@cloud.net.au>: Re: RPM_GRID (was MAP problem: Trivial RPM fails)
46582: 02/09/03: Jan Gray: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46583: 02/09/03: Jan Gray: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46591: 02/09/04: Stephen Williams: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46592: 02/09/03: Jan Gray: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46595: 02/09/04: Frank Andreas de Groot: Re: Warning: Xilinx 4.2i + Windows 2000 SP3 => blue screen of death
46588: 02/09/04: Sheila Sim: choice of fpga
46590: 02/09/04: Peter Alfke: Re: choice of fpga
46600: 02/09/04: Laurent Gauch: Re: choice of fpga
46593: 02/09/04: Reala: Any resource about MCU and DSP
46605: 02/09/04: Jan Gray: Re: Any resource about MCU and DSP
46616: 02/09/04: Jerry D. Harthcock: Re: Any resource about MCU and DSP
46596: 02/09/04: Charles Wagner: RAM in CCC behavioral FPGA
46602: 02/09/04: Reala: Question for Verilog
46683: 02/09/05: John_H: Re: Question for Verilog
46604: 02/09/04: Neeraj Varma: PPC blocks in XC2VP50
46612: 02/09/04: Austin Lesea: Re: PPC blocks in XC2VP50
46658: 02/09/05: Neeraj Varma: Re: PPC blocks in XC2VP50
46607: 02/09/04: Govind Kharbanda: Handel-C: Undeclared identifier
46608: 02/09/04: Utku Ozcan: Synplify and FPGA Express translates clock from normal I/O differently
46609: 02/09/04: Govind Kharbanda: Handel-C: Undeclared identifier: take2
46631: 02/09/04: Steffan Westcott: Re: Handel-C: Undeclared identifier: take2
46667: 02/09/05: Govind Kharbanda: Re: Handel-C: Undeclared identifier: take2
46930: 02/09/12: Alan Fitch: Re: Handel-C: Undeclared identifier: take2
46613: 02/09/04: Fabien Arrive: CLK DLL problem
46640: 02/09/05: Brijesh: Re: CLK DLL problem
46615: 02/09/04: Gaga: xilinx contact with regard to qpro
46618: 02/09/04: Steve Casselman: Re: xilinx contact with regard to qpro
46623: 02/09/04: Austin Lesea: Re: xilinx contact with regard to qpro
46630: 02/09/04: Ray Andraka: Re: xilinx contact with regard to qpro
47931: 02/10/07: Jeff Wetch: Re: xilinx contact with regard to qpro
46619: 02/09/04: Bill Bishop: ARC-PCI Board
46621: 02/09/04: hristo: why the need for HIGH speed design?
46625: 02/09/04: lng: Re: why the need for HIGH speed design?
46626: 02/09/04: Ray Andraka: Re: why the need for HIGH speed design?
46628: 02/09/04: lng: Re: why the need for HIGH speed design?
46637: 02/09/04: Spam Hater: Re: why the need for HIGH speed design?
46638: 02/09/04: Nicholas C. Weaver: Re: why the need for HIGH speed design?
46639: 02/09/04: Frank Andreas de Groot: Re: why the need for HIGH speed design?
46642: 02/09/04: John: Re: why the need for HIGH speed design?
46740: 02/09/06: hristo: Re: why the need for HIGH speed design?
46669: 02/09/05: Rene Tschaggelar: Re: why the need for HIGH speed design?
46681: 02/09/05: John_H: Re: why the need for HIGH speed design?
46686: 02/09/05: Frank Andreas de Groot: Re: why the need for HIGH speed design?
46739: 02/09/06: hristo: Re: why the need for HIGH speed design?
46743: 02/09/06: John_H: Re: why the need for HIGH speed design?
46756: 02/09/07: hristo: Re: why the need for HIGH speed design?
46744: 02/09/06: Ray Andraka: Re: why the need for HIGH speed design?
46751: 02/09/07: Falk Brunner: Re: why the need for HIGH speed design?
46810: 02/09/09: lng: Re: why the need for HIGH speed design?
47042: 02/09/16: Ray Andraka: Re: why the need for HIGH speed design?
46622: 02/09/04: flora: Virtex-2 BRAM
46624: 02/09/04: Ray Andraka: Re: Virtex-2 BRAM
46635: 02/09/04: Hal Murray: Re: Virtex-2 BRAM
46627: 02/09/04: Martin Guibert: Re: Virtex-2 BRAM
46632: 02/09/04: Hugh: xilinx PCI prototype board
46674: 02/09/05: Kevin Brace: Re: xilinx PCI prototype board
46633: 02/09/04: Rajeev: Viewing Xilinx netlist
46636: 02/09/04: Vikram Pasham: Re: Viewing Xilinx netlist
46653: 02/09/04: Kevin Brace: Re: Viewing Xilinx netlist
46688: 02/09/05: Steven Elzinga: Re: Viewing Xilinx netlist
46706: 02/09/06: Rajeev: Re: Viewing Xilinx netlist
46713: 02/09/06: Steven Elzinga: Re: Viewing Xilinx netlist
46774: 02/09/08: Kevin Brace: Re: Viewing Xilinx netlist
46708: 02/09/06: Rajeev: Re: Viewing Xilinx netlist
46670: 02/09/05: Rajeev: Re: Viewing Xilinx netlist
46659: 02/09/04: Mike Rosing: Re: atmel CPLD documentation
46814: 02/09/09: George Eccles: Re: atmel CPLD documentation
46661: 02/09/04: Muthu: Xilinx's ISE 5.1i
46663: 02/09/05: Giuseppe³: Re: Xilinx's ISE 5.1i
46690: 02/09/05: rickman: Re: Xilinx's ISE 5.1i
46671: 02/09/05: Muthu: Modular Design
46699: 02/09/06: Neeraj Varma: Re: Modular Design
46673: 02/09/05: Amit: library
46705: 02/09/06: Amit: Re: library
46675: 02/09/05: Jerzy: OFDM - looking for something more
46676: 02/09/05: Dave Colson: Actel Libero
46680: 02/09/05: Kevin Brace: Re: Actel Libero
46687: 02/09/05: Jerry D. Harthcock: Re: Actel Libero
46677: 02/09/05: Govind Kharbanda: HAndel-C types not matching
46691: 02/09/05: Steffan Westcott: Re: HAndel-C types not matching
46710: 02/09/06: Govind Kharbanda: Re: HAndel-C types not matching
46711: 02/09/06: Govind Kharbanda: Re: HAndel-C types not matching
46737: 02/09/06: Steffan Westcott: Re: HAndel-C types not matching
46692: 02/09/05: rickman: XCR3384XL availability
46722: 02/09/06: rickman: Re: XCR3384XL availability
46725: 02/09/06: Falk Brunner: Re: XCR3384XL availability
46729: 02/09/06: Mikeandmax: Re: XCR3384XL availability
46806: 02/09/09: rickman: Re: XCR3384XL availability
46812: 02/09/09: Uwe Bonnes: Re: XCR3384XL availability
46832: 02/09/09: rickman: Re: XCR3384XL availability
46835: 02/09/10: Jim Granville: Re: XCR3384XL availability
46838: 02/09/09: rickman: Re: XCR3384XL availability
46842: 02/09/10: Jim Granville: Re: XCR3384XL availability
46847: 02/09/10: rickman: Re: XCR3384XL availability
46848: 02/09/10: Hal Murray: Re: XCR3384XL availability
46865: 02/09/10: rickman: Re: XCR3384XL availability
46868: 02/09/10: rickman: Re: XCR3384XL availability
46872: 02/09/10: Peter Alfke: Re: XCR3384XL availability
46877: 02/09/10: Larry Doolittle: Re: XCR3384XL availability
46878: 02/09/10: Austin Lesea: Re: XCR3384XL availability
46881: 02/09/10: Larry Doolittle: Re: XCR3384XL availability
46882: 02/09/10: Larry Doolittle: Re: XCR3384XL availability
46886: 02/09/10: Austin Lesea: Re: XCR3384XL availability
46889: 02/09/11: Jim Granville: Re: XCR3384XL availability
46884: 02/09/10: Peter Alfke: Re: XCR3384XL availability
46887: 02/09/10: rickman: Re: XCR3384XL availability
46890: 02/09/10: Larry Doolittle: Re: XCR3384XL availability
46895: 02/09/11: Jim Granville: Re: XCR3384XL availability
46885: 02/09/10: rickman: Re: XCR3384XL availability
46888: 02/09/10: Peter Alfke: Re: XCR3384XL availability
46896: 02/09/11: Mikeandmax: Re: XCR3384XL availability
46731: 02/09/06: Austin Lesea: Re: XCR3384XL availability
46735: 02/09/06: Falk Brunner: Re: XCR3384XL availability
46736: 02/09/06: Austin Lesea: Re: XCR3384XL availability
46741: 02/09/06: Peter Alfke: Re: XCR3384XL availability
46752: 02/09/07: Falk Brunner: Re: XCR3384XL availability
46800: 02/09/09: rickman: Re: XCR3384XL availability
46803: 02/09/09: Austin Lesea: Re: XCR3384XL availability
46906: 02/09/11: Kolja Sulimma: Re: XCR3384XL availability
46807: 02/09/09: Peter Alfke: Re: XCR3384XL availability
46815: 02/09/10: Jim Granville: Re: XCR3384XL availability
46833: 02/09/09: rickman: Re: XCR3384XL availability
46839: 02/09/10: Peter Alfke: Re: XCR3384XL availability
46841: 02/09/09: rickman: Re: XCR3384XL availability
46856: 02/09/10: Rick Filipkiewicz: Re: XCR3384XL availability
46798: 02/09/09: rickman: Re: XCR3384XL availability
46693: 02/09/05: John: question about quiescent current
46694: 02/09/05: Peter Alfke: Re: question about quiescent current
46695: 02/09/06: Jim Granville: Re: question about quiescent current
46712: 02/09/06: Steve Prokosch: Re: question about quiescent current
46716: 02/09/06: Falk Brunner: Re: question about quiescent current
46704: 02/09/06: Marek Jaskula: new in fpga
46717: 02/09/06: Falk Brunner: Re: new in fpga
46707: 02/09/06: Dave Colson: Actel Libero Platinum Model Sim slow
46714: 02/09/06: Govind Kharbanda: Handel-C: a bit of a funny 'for loop'
46932: 02/09/12: Alan Fitch: Re: Handel-C: a bit of a funny 'for loop'
47128: 02/09/18: Govind Kharbanda: Re: Handel-C: a bit of a funny 'for loop'
47345: 02/09/24: Ashley: Re: Handel-C: a bit of a funny 'for loop'
46715: 02/09/06: Prashant: Performance degradation when put on an FPGA ?
46719: 02/09/06: John_H: Re: Performance degradation when put on an FPGA ?
46721: 02/09/06: Peter Alfke: Re: Performance degradation when put on an FPGA ?
46746: 02/09/06: Prashant: Re: Performance degradation when put on an FPGA ?
46723: 02/09/06: Nicholas C. Weaver: Re: Performance degradation when put on an FPGA ?
46726: 02/09/06: Pierre-Olivier Laprise: Virtex-II bit-file and strange configuration command
46733: 02/09/06: Phil James-Roxby: Re: Virtex-II bit-file and strange configuration command
46742: 02/09/06: Steve Casselman: Re: Virtex-II bit-file and strange configuration command
46727: 02/09/06: Paul Baxter: Measuring FPGA performance eg max clock speed
46728: 02/09/06: Falk Brunner: Re: Measuring FPGA performance eg max clock speed
46738: 02/09/06: Paul Baxter: Re: Measuring FPGA performance eg max clock speed
47044: 02/09/16: Ray Andraka: Re: Measuring FPGA performance eg max clock speed
46730: 02/09/06: steve synakowski: Synthesis problem, my inputs are never used?
46732: 02/09/06: Goran Bilski: Re: Synthesis problem, my inputs are never used?
46750: 02/09/07: Rick Filipkiewicz: Re: Synthesis problem, my inputs are never used?
46745: 02/09/06: Peter Alfke: Metastability numbers
46759: 02/09/07: Phil Hays: Re: Metastability numbers
46761: 02/09/07: Peter Alfke: Re: Metastability numbers, even better!
46767: 02/09/08: Rick Filipkiewicz: Re: Metastability numbers, even better!
46773: 02/09/08: Peter Alfke: Re: Metastability numbers, even better!
46783: 02/09/09: Jim Granville: Re: Metastability numbers, even better!
46765: 02/09/08: rk: Re: Metastability numbers
46782: 02/09/09: Jim Granville: Re: Metastability numbers
46787: 02/09/09: Peter Alfke: Re: Metastability numbers
46789: 02/09/09: Jim Granville: Re: Metastability numbers
46902: 02/09/11: Hal Murray: Re: Metastability numbers
46804: 02/09/09: Falk Brunner: Re: Metastability numbers
46816: 02/09/09: Peter Alfke: Re: Metastability numbers
46820: 02/09/10: Jim Granville: Re: Metastability numbers
46824: 02/09/09: Peter Alfke: Re: Metastability numbers
46817: 02/09/09: nospam: Re: Metastability numbers
46818: 02/09/09: Peter Alfke: Re: Metastability numbers
46834: 02/09/10: nospam: Re: Metastability numbers
46822: 02/09/09: Peter Alfke: Re: Metastability numbers
46845: 02/09/10: glen herrmannsfeldt: Re: Metastability numbers
46844: 02/09/10: glen herrmannsfeldt: Re: Metastability numbers
46849: 02/09/10: Hal Murray: Re: Metastability numbers
46898: 02/09/11: glen herrmannsfeldt: Re: Metastability numbers
46753: 02/09/07: Nikhil Bhatia: symplicity conv_integer problem
46802: 02/09/09: Mike Treseler: Re: symplicity conv_integer problem
46933: 02/09/12: Jianyong Niu: Re: symplicity conv_integer problem
46755: 02/09/07: Vladimir Ralev: PCI bus problems
46827: 02/09/09: Steen Larsen: Re: PCI bus problems
46757: 02/09/07: hristo: scan insertion is easily feasible
46922: 02/09/12: Stan: Re: scan insertion is easily feasible
46966: 02/09/13: Thomas Stanka: Re: scan insertion is easily feasible
47031: 02/09/15: Ray Andraka: Re: scan insertion is easily feasible
47061: 02/09/16: Mike Treseler: Re: scan insertion is easily feasible
46758: 02/09/07: Masoud Naderi: Fault tolerant FPGA design
46760: 02/09/07: Peter Alfke: Re: Fault tolerant FPGA design
46768: 02/09/08: Masoud Naderi: Re: Fault tolerant FPGA design
46762: 02/09/07: Ray Andraka: Re: Fault tolerant FPGA design
46764: 02/09/08: Frank Andreas de Groot: Re: Fault tolerant FPGA design
46770: 02/09/08: Masoud Naderi: Re: Fault tolerant FPGA design
46772: 02/09/08: Frank Andreas de Groot: Re: Fault tolerant FPGA design
46778: 02/09/09: Ray Andraka: Re: Fault tolerant FPGA design
46769: 02/09/08: Masoud Naderi: Re: Fault tolerant FPGA design
46775: 02/09/09: Steve Casselman: Re: Fault tolerant FPGA design
46925: 02/09/12: Thomas Stanka: Re: Fault tolerant FPGA design
46915: 02/09/11: Masoud Naderi: Re: Fault tolerant FPGA design
46779: 02/09/09: Ray Andraka: Re: Fault tolerant FPGA design
46790: 02/09/09: Thomas Stanka: Re: Fault tolerant FPGA design
46766: 02/09/07: BasePointer: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
46781: 02/09/08: Austin Franklin: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
46857: 02/09/10: Gregory C. Read: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
46873: 02/09/10: strut911: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
46880: 02/09/10: Hal Murray: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
46776: 02/09/09: John Williams: minimalist FPGA system
46777: 02/09/09: Nicholas C. Weaver: Re: minimalist FPGA system
46826: 02/09/10: John Williams: Re: minimalist FPGA system
46828: 02/09/09: Nicholas C. Weaver: Re: minimalist FPGA system
46837: 02/09/09: Jan Gray: Re: minimalist FPGA system
46840: 02/09/10: John Williams: Re: minimalist FPGA system
46846: 02/09/10: Hal Murray: Re: minimalist FPGA system
46785: 02/09/09: Peter Alfke: Re: minimalist FPGA system
46792: 02/09/09: nospam: Re: minimalist FPGA system
46794: 02/09/09: Jerry D. Harthcock: Re: minimalist FPGA system
46859: 02/09/10: Silvio Lauckner: Re: minimalist FPGA system
46784: 02/09/08: Vikram Chandrasekhar: SystemC query
46801: 02/09/09: Vikram Chandrasekhar: SystemC query
46788: 02/09/08: Anjan: X on bus
46793: 02/09/09: Paul Baxter: Altera counter - want an unregistered cout
46795: 02/09/09: chankc: Can FPGA implements ADC?
46797: 02/09/09: Larry Doolittle: Re: Can FPGA implements ADC?
46799: 02/09/09: Austin Lesea: Re: Can FPGA implements ADC?
46796: 02/09/09: Giovanni Galiero: Evaluating FPGA for FFT
46809: 02/09/09: George Eccles: atmel CPLD documentation
46874: 02/09/10: Troy Schultz: Re: atmel CPLD documentation
46883: 02/09/10: George Eccles: Re: atmel CPLD documentation
46905: 02/09/11: Troy Schultz: Re: atmel CPLD documentation
46916: 02/09/12: Jim Granville: Re: atmel CPLD documentation
46821: 02/09/09: John: differences between CoolRunner XPLA3 and CoolRunner-II?
46934: 02/09/12: Laurent Gauch: Re: differences between CoolRunner XPLA3 and CoolRunner-II?
46823: 02/09/10: Jim Granville: Re: Altera Stratix DSP Performance
46825: 02/09/09: John: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
46829: 02/09/09: Mark Ng: Re: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
46830: 02/09/10: Jim Granville: Re: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
46831: 02/09/10: Cool Morning ...: FPGA comes with a DAC?
46836: 02/09/10: John_H: Re: FPGA comes with a DAC?
46893: 02/09/11: Neil Franklin: Re: FPGA comes with a DAC?
46894: 02/09/11: Jim Granville: Re: FPGA comes with a DAC?
46899: 02/09/11: Allan Herriman: Re: FPGA comes with a DAC?
46945: 02/09/12: Lorenzo Lutti: Re: FPGA comes with a DAC?
46965: 02/09/13: Dennis Sneijers: Re: FPGA comes with a DAC?
46910: 02/09/11: James Horn: Re: FPGA comes with a DAC?
46843: 02/09/10: al: 555 schematic or vhdl for xilinx or other clock circuit ?
46851: 02/09/10: Jim Granville: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46853: 02/09/10: Leon Heller: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46854: 02/09/10: al: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46855: 02/09/10: Johann Glaser: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46861: 02/09/10: Leon Heller: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46867: 02/09/10: Peter Wallace: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
46850: 02/09/09: eric: How to make Altera UPX board self bootable?
46852: 02/09/10: Leon Heller: Re: How to make Altera UPX board self bootable?
46858: 02/09/10: hardwire: Re: How to make Altera UPX board self bootable?
46860: 02/09/10: Ulises Hernandez: PowerTheatre for FPGAs?
46863: 02/09/10: Uwe Bonnes: Xilinx Parallell Cable IV and Wine
46864: 02/09/10: Martin: Re: Xilinx Parallell Cable IV and Wine
46871: 02/09/10: Troy Schultz: Re: Xilinx Parallell Cable IV and Wine
46869: 02/09/10: Prashant: Modelsim-Altera gate level simulation
46875: 02/09/10: Mike Treseler: Re: Modelsim-Altera gate level simulation
46908: 02/09/11: Prashant: Re: Modelsim-Altera gate level simulation
47075: 02/09/16: Ben Twijnstra: Re: Modelsim-Altera gate level simulation
46931: 02/09/12: Shareef Jalloq: Re: Modelsim-Altera gate level simulation
46879: 02/09/10: Yan: Saving results with modelsim
46900: 02/09/11: Markus Sponsel: Re: Saving results with modelsim
46926: 02/09/12: Marten van Essen: Re: Saving results with modelsim
46927: 02/09/12: Ulises Hernandez: Re: Saving results with modelsim
46928: 02/09/12: Ulises Hernandez: Re: Saving results with modelsim
46944: 02/09/12: Mike Treseler: Re: Saving results with modelsim
46946: 02/09/12: Jon Schneider: Re: Saving results with modelsim
46891: 02/09/10: Michael Ardai: Looking for programming algorithm for Xilinx 18v00 family
47005: 02/09/13: Brannon King: Re: Looking for programming algorithm for Xilinx 18v00 family
47019: 02/09/14: Alan Nishioka: Re: Looking for programming algorithm for Xilinx 18v00 family
46897: 02/09/10: Anjan: problem with tri state bus
46929: 02/09/12: John Adair: Re: problem with tri state bus
46901: 02/09/11: mark: XC2V Embedded Multipliers and Chipscope Usage
46970: 02/09/13: Symon: Re: XC2V Embedded Multipliers and Chipscope Usage
47098: 02/09/17: mark: Re: XC2V Embedded Multipliers and Chipscope Usage
46907: 02/09/11: Mauricio Lange: Clocking an FPGA with the PCI clock
46912: 02/09/11: Austin Franklin: Re: Clocking an FPGA with the PCI clock
46918: 02/09/11: Kevin Brace: Re: Clocking an FPGA with the PCI clock
46919: 02/09/11: Kevin Brace: Re: Clocking an FPGA with the PCI clock
46921: 02/09/11: Austin Franklin: Re: Clocking an FPGA with the PCI clock
47035: 02/09/15: Mauricio Lange: Re: Clocking an FPGA with the PCI clock
46909: 02/09/11: Prashant: Quartus 2 flow
46911: 02/09/11: Mike Treseler: Re: Quartus 2 flow
46920: 02/09/11: Kevin Brace: Re: Quartus 2 flow
46924: 02/09/12: Matjaz Finc: Re: Quartus 2 flow
46939: 02/09/12: Prashant: Re: Quartus 2 flow
46959: 02/09/13: ds: Re: Quartus 2 flow
46935: 02/09/12: William L Hunter Jr: XILINX FPGA output not right
46936: 02/09/12: Georg Acher: Re: XILINX FPGA output not right
46937: 02/09/12: Rajeev: Xilinx LogicCore Pipelined Divider Clock Cycles
46938: 02/09/12: Rajeev: Xilinx LogicCore Pipelined Divider at 4 Clocks/Division
46943: 02/09/12: Peter Alfke: Re: Xilinx LogicCore Pipelined Divider at 4 Clocks/Division
46940: 02/09/12: Lu Hu: 2-D resistor array
46953: 02/09/12: Mike D: Re: 2-D resistor array
46954: 02/09/13: Roger King: Re: 2-D resistor array
46968: 02/09/13: meta: Re: 2-D resistor array
46972: 02/09/13: Rajeev: Re: 2-D resistor array
46988: 02/09/13: meta: Re: 2-D resistor array
46994: 02/09/14: Jim Granville: Re: 2-D resistor array
46998: 02/09/13: meta: Re: 2-D resistor array
47001: 02/09/14: Jim Granville: Re: 2-D resistor array
46974: 02/09/13: rickman: Re: 2-D resistor array
46989: 02/09/13: meta: Re: 2-D resistor array
46942: 02/09/12: Mike D: Post Synthesis Simulation w/Mentor
47052: 02/09/16: Peter Baltazarovic: Re: Post Synthesis Simulation w/Mentor
46947: 02/09/12: Niv: Xilinx TBUFs
46951: 02/09/12: John_H: Re: Xilinx TBUFs
46952: 02/09/12: rickman: Re: Xilinx TBUFs
46958: 02/09/12: Muthu: Re: Xilinx TBUFs
46979: 02/09/13: Falk Brunner: Re: Xilinx TBUFs
47010: 02/09/14: Muthu: Re: Xilinx TBUFs
47011: 02/09/14: Falk Brunner: Re: Xilinx TBUFs
47013: 02/09/14: Nicholas C. Weaver: Re: Xilinx TBUFs
46957: 02/09/12: Dan: number of IOBs in Spartan IIE is fishy
46962: 02/09/13: rickman: Re: number of IOBs in Spartan IIE is fishy
46981: 02/09/13: Falk Brunner: Re: number of IOBs in Spartan IIE is fishy
46992: 02/09/13: rickman: Re: number of IOBs in Spartan IIE is fishy
46996: 02/09/13: Falk Brunner: Re: number of IOBs in Spartan IIE is fishy
47015: 02/09/14: rickman: Re: number of IOBs in Spartan IIE is fishy
47017: 02/09/14: Falk Brunner: Re: number of IOBs in Spartan IIE is fishy
47020: 02/09/14: rickman: Re: number of IOBs in Spartan IIE is fishy
47023: 02/09/14: Falk Brunner: Re: number of IOBs in Spartan IIE is fishy
47028: 02/09/15: rickman: Re: number of IOBs in Spartan IIE is fishy
47056: 02/09/16: Falk Brunner: Re: number of IOBs in Spartan IIE is fishy
46984: 02/09/13: Marc Baker: Re: number of IOBs in Spartan IIE is fishy
46982: 02/09/13: Marc Baker: Re: number of IOBs in Spartan IIE is fishy
46963: 02/09/13: Jonathan Bromley: re: 2-D resistor array
46967: 02/09/13: meta: Re: 2-D resistor array
46964: 02/09/13: Wojciech Piechowski: exploiting metastability
46971: 02/09/13: rickman: Re: exploiting metastability
46973: 02/09/13: Austin Lesea: Re: exploiting metastability
46986: 02/09/13: rickman: Re: exploiting metastability
46978: 02/09/13: Larry Doolittle: Re: exploiting metastability
47048: 02/09/16: Wojciech Piechowski: Re: exploiting metastability
47055: 02/09/16: rickman: Re: exploiting metastability
46975: 02/09/13: Austin Lesea: Re: exploiting metastability
46976: 02/09/13: Peter Alfke: Re: exploiting metastability
46980: 02/09/13: Hal Murray: Re: exploiting metastability
46983: 02/09/13: Nicholas C. Weaver: Re: exploiting metastability
46987: 02/09/13: Rick Filipkiewicz: Re: exploiting metastability
46993: 02/09/13: rickman: Re: exploiting metastability
46995: 02/09/13: Larry Doolittle: Re: exploiting metastability
47002: 02/09/13: rickman: Re: exploiting metastability
47047: 02/09/16: Wojciech Piechowski: Re: exploiting metastability
47000: 02/09/13: Ricardo Wiggers: Re: exploiting metastability
47003: 02/09/13: rickman: Re: exploiting metastability
46969: 02/09/13: Jonathan Bromley: re: 2-D resistor array
46977: 02/09/13: Jonathan Bromley: re:2-D resistor array
46985: 02/09/13: rickman: Re: 2-D resistor array
46990: 02/09/13: meta: Re: re:2-D resistor array
46991: 02/09/13: rickman: Re: 2-D resistor array
46997: 02/09/13: meta: Re: 2-D resistor array
47004: 02/09/13: rickman: Re: 2-D resistor array
47008: 02/09/14: Stephen Williams: Synthesis of 4:1 and 8:1 MUX devices in Virtex
47033: 02/09/15: MikeJ: Re: Synthesis of 4:1 and 8:1 MUX devices in Virtex
47012: 02/09/14: Bruce (newbie): Clcok divison : Rational clock divider
47014: 02/09/14: Rene Tschaggelar: Re: Clcok divison : Rational clock divider
47018: 02/09/14: Falk Brunner: Re: Clcok divison : Rational clock divider
47016: 02/09/14: Peter Alfke: Re: Clcok divison : Rational clock divider
47022: 02/09/14: Allan Herriman: Re: Clcok divison : Rational clock divider
47024: 02/09/14: Rick Filipkiewicz: Re: Clcok divison : Rational clock divider
47025: 02/09/15: Jim Granville: Re: Clcok divison : Rational clock divider
47027: 02/09/15: Falk Brunner: Re: Clcok divison : Rational clock divider
47029: 02/09/15: Allan Herriman: Re: Clcok divison : Rational clock divider
47021: 02/09/14: rickman: XCR3xxxXL family architechture
47026: 02/09/14: Mike Rosing: Re: xilinx jtag chain question
47030: 02/09/16: Young-Su Kwon: Readback size for virtex2
47032: 02/09/15: Neil Franklin: Re: Readback size for virtex2
47104: 02/09/17: Steve Casselman: Re: Readback size for virtex2
47034: 02/09/15: Pete H.: Custom plug-in for HDL Designer
47049: 02/09/16: Thomas Reinemann: Re: Custom plug-in for HDL Designer
47036: 02/09/16: Pete Dudley: Re: EDIF and JHDL information
47037: 02/09/16: Pete Dudley: ieee.math_real for presynthesis table calculation in vhdl
47043: 02/09/16: John Williams: Re: ieee.math_real for presynthesis table calculation in vhdl
47045: 02/09/16: Ray Andraka: Re: ieee.math_real for presynthesis table calculation in vhdl
47062: 02/09/16: Mike Treseler: Re: ieee.math_real for presynthesis table calculation in vhdl
47074: 02/09/16: Ray Andraka: Re: ieee.math_real for presynthesis table calculation in vhdl
47095: 02/09/17: Brian Gogan: Re: ieee.math_real for presynthesis table calculation in vhdl
47206: 02/09/20: <hamish@cloud.net.au>: Re: ieee.math_real for presynthesis table calculation in vhdl
47212: 02/09/20: Ray Andraka: Re: ieee.math_real for presynthesis table calculation in vhdl
47148: 02/09/19: Pete Dudley: Re: ieee.math_real for presynthesis table calculation in vhdl
47038: 02/09/16: Brad: FPGA work in the Bay Area (CA)?
47111: 02/09/18: Blackie Beard: Re: FPGA work in the Bay Area (CA)?
47039: 02/09/15: Dan: 1.8V regulator needed for Spartan IIE
47040: 02/09/15: rickman: Re: 1.8V regulator needed for Spartan IIE
47041: 02/09/16: Ray Andraka: Re: 1.8V regulator needed for Spartan IIE
47046: 02/09/16: Jim Granville: Re: 1.8V regulator needed for Spartan IIE
47051: 02/09/16: Dan: Re: 1.8V regulator needed for Spartan IIE
47057: 02/09/16: Falk Brunner: Re: 1.8V regulator needed for Spartan IIE
47073: 02/09/16: Ray Andraka: Re: 1.8V regulator needed for Spartan IIE
47082: 02/09/16: Austin Lesea: Re: 1.8V regulator needed for Spartan IIE
47086: 02/09/17: Ray Andraka: Re: 1.8V regulator needed for Spartan IIE
47087: 02/09/17: Nicholas C. Weaver: Re: 1.8V regulator needed for Spartan IIE
47097: 02/09/17: Russell: Re: 1.8V regulator needed for Spartan IIE
47050: 02/09/16: David Frith: Re: 1.8V regulator needed for Spartan IIE
47053: 02/09/16: Javier Serrano: Question about Virtex-II DCM's jitter
47054: 02/09/16: Austin Lesea: Re: Question about Virtex-II DCM's jitter
47058: 02/09/16: Javier Serrano: Re: Question about Virtex-II DCM's jitter
47059: 02/09/16: jakab tanko: Re: Question about Virtex-II DCM's jitter
47063: 02/09/16: John_H: Re: Question about Virtex-II DCM's jitter
47064: 02/09/16: Austin Lesea: Re: Question about Virtex-II DCM's jitter
47068: 02/09/16: Larry Doolittle: Re: Question about Virtex-II DCM's jitter
47077: 02/09/16: Austin Lesea: Re: Question about Virtex-II DCM's jitter
47085: 02/09/17: Larry Doolittle: Re: Question about Virtex-II DCM's jitter
47090: 02/09/17: Javier Serrano: Re: Question about Virtex-II DCM's jitter
47100: 02/09/17: Austin Lesea: Re: Question about Virtex-II DCM's jitter
47065: 02/09/16: Javier Serrano: Re: Question about Virtex-II DCM's jitter
47078: 02/09/16: Austin Lesea: Re: Question about Virtex-II DCM's jitter
47060: 02/09/16: Uwe Bonnes: Virtex II packaging, why no QFP?
47066: 02/09/16: Austin Lesea: Re: Virtex II packaging, why no QFP?
47070: 02/09/16: Uwe Bonnes: Re: Virtex II packaging, why no QFP?
47071: 02/09/17: Jim Granville: Re: Virtex II packaging, why no QFP?
47079: 02/09/16: Austin Lesea: Re: Virtex II packaging, why no QFP?
47067: 02/09/16: emanuel stiebler: Re: Virtex II packaging, why no QFP?
47069: 02/09/16: Larry Doolittle: Re: Virtex II packaging, why no QFP?
47080: 02/09/16: Austin Lesea: Re: Virtex II packaging, why no QFP?
47072: 02/09/16: Denis Gleeson: Multiple divide by 10
47081: 02/09/16: John_H: Re: Multiple divide by 10
47093: 02/09/17: Denis Gleeson: Re: Multiple divide by 10
47099: 02/09/17: sweir: Re: Multiple divide by 10
47103: 02/09/17: John_H: Re: Multiple divide by 10
47083: 02/09/16: Peter Alfke: Re: Multiple divide by 10
47120: 02/09/17: Andreas Loew: Re: Multiple divide by 10
47124: 02/09/18: Peter Alfke: Re: Multiple divide by 10
47145: 02/09/18: Ray Andraka: Re: Multiple divide by 10
47180: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47181: 02/09/20: Peter Alfke: Re: Multiple divide by 10
47182: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47186: 02/09/20: Ray Andraka: Re: Multiple divide by 10
47189: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47198: 02/09/20: Muzaffer Kal: Re: Multiple divide by 10
47203: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47205: 02/09/20: Andrew MacCormack: Re: Multiple divide by 10
47213: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47388: 02/09/25: bulletdog7: Re: Multiple divide by 10
47398: 02/09/25: Ray Andraka: Re: Multiple divide by 10
47403: 02/09/25: Blackie Beard: Re: Multiple divide by 10
47419: 02/09/25: Ray Andraka: Re: Multiple divide by 10
47586: 02/09/30: bulletdog7: Re: Multiple divide by 10
47584: 02/09/30: bulletdog7: Re: Multiple divide by 10
47207: 02/09/20: Ray Andraka: Re: Multiple divide by 10
47208: 02/09/20: Ray Andraka: Re: Multiple divide by 10
47192: 02/09/20: rickman: Re: Multiple divide by 10
47204: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47228: 02/09/20: Peter Alfke: Re: Multiple divide by 10
47230: 02/09/20: Nicholas C. Weaver: Re: Multiple divide by 10
47183: 02/09/20: Blackie Beard: Re: Multiple divide by 10
47076: 02/09/16: Adolfo Mora: ISE 4.2i: Some bugs in ECS, State CAD Modelsim_XE.
47084: 02/09/16: Brijesh: Viewing internal signals during Post route simulation.
47089: 02/09/17: Utku Ozcan: Re: Viewing internal signals during Post route simulation.
47102: 02/09/17: admin: Re: Viewing internal signals during Post route simulation.
47088: 02/09/17: Tina Falkenberg: FPGA Design and IP Cores
47091: 02/09/17: Leon Qin: Has ISE 5.1i shipped?
47092: 02/09/17: Rick Filipkiewicz: Re: Has ISE 5.1i shipped?
47112: 02/09/18: Phil Hays: Re: Has ISE 5.1i shipped?
47116: 02/09/17: Andreas: Re: Has ISE 5.1i shipped?
47170: 02/09/19: qlyus: Re: Has ISE 5.1i shipped?
47226: 02/09/20: Ken Ryan: Re: Has ISE 5.1i shipped?
47094: 02/09/17: DJohn: C\C++ to VHDL Converter
47096: 02/09/17: Thomas Vogel: Re: C\C++ to VHDL Converter
47101: 02/09/17: Brannon King: Re: C\C++ to VHDL Converter
47146: 02/09/19: mike: Re: C\C++ to VHDL Converter
47149: 02/09/19: Ray Andraka: Re: C\C++ to VHDL Converter
47674: 02/10/02: Brett Cline: Re: C\C++ to VHDL Converter
47679: 02/10/02: Ray Andraka: Re: C\C++ to VHDL Converter
47704: 02/10/02: Nicholas C. Weaver: Re: C\C++ to VHDL Converter
47714: 02/10/02: Austin Franklin: Re: C\C++ to VHDL Converter
47723: 02/10/02: Ray Andraka: Re: C\C++ to VHDL Converter
47738: 02/10/03: Martin Thompson: Re: C\C++ to VHDL Converter
47742: 02/10/03: Tim: Re: C\C++ to VHDL Converter
47792: 02/10/04: Martin Thompson: Re: C\C++ to VHDL Converter
47745: 02/10/03: Ray Andraka: Re: C\C++ to VHDL Converter
47791: 02/10/04: Martin Thompson: Re: C\C++ to VHDL Converter
49156: 02/11/03: Noel Klonsky: Re: C\C++ to VHDL Converter
49180: 02/11/04: Austin Franklin: Re: C\C++ to VHDL Converter
49202: 02/11/05: Phil Hays: Re: C\C++ to VHDL Converter
49203: 02/11/05: Ray Andraka: Re: C\C++ to VHDL Converter
49206: 02/11/05: Austin Franklin: Re: C\C++ to VHDL Converter
49222: 02/11/05: Ray Andraka: Re: C\C++ to VHDL Converter
49229: 02/11/05: Austin Franklin: Re: C\C++ to VHDL Converter
49515: 02/11/14: Ray Andraka: Re: C\C++ to VHDL Converter
49566: 02/11/15: Austin Franklin: Re: C\C++ to VHDL Converter
49574: 02/11/15: Mike Treseler: Re: C\C++ to VHDL Converter
49579: 02/11/15: Austin Franklin: Re: C\C++ to VHDL Converter
49716: 02/11/19: Ray Andraka: Re: C\C++ to VHDL Converter
49774: 02/11/20: Austin Franklin: Re: C\C++ to VHDL Converter
49781: 02/11/21: Ray Andraka: Re: C\C++ to VHDL Converter
49802: 02/11/21: Austin Franklin: Re: C\C++ to VHDL Converter
49816: 02/11/21: Ray Andraka: Re: C\C++ to VHDL Converter
49875: 02/11/23: Austin Franklin: Re: C\C++ to VHDL Converter
49877: 02/11/23: Ray Andraka: Re: C\C++ to VHDL Converter
49715: 02/11/19: Ray Andraka: Re: C\C++ to VHDL Converter
49230: 02/11/05: Mike Treseler: Re: C\C++ to VHDL Converter
49401: 02/11/12: Phil Hays: Re: C\C++ to VHDL Converter
49458: 02/11/12: Austin Franklin: Re: C\C++ to VHDL Converter
49476: 02/11/13: Phil Hays: Re: C\C++ to VHDL Converter
47809: 02/10/04: Ray Andraka: Re: C\C++ to VHDL Converter
47869: 02/10/06: Brett Cline: Re: C\C++ to VHDL Converter
47874: 02/10/06: Phil Hays: Re: C\C++ to VHDL Converter
47879: 02/10/07: Ray Andraka: Re: C\C++ to VHDL Converter
47886: 02/10/07: Thomas Stanka: Re: C\C++ to VHDL Converter
47907: 02/10/07: Brett Cline: Re: C\C++ to VHDL Converter
47911: 02/10/07: Nicholas C. Weaver: Re: C\C++ to VHDL Converter
47929: 02/10/08: Phil Hays: Re: C\C++ to VHDL Converter
47930: 02/10/07: Austin Franklin: Re: C\C++ to VHDL Converter
49189: 02/11/04: john jakson: Re: C\C++ to HDL Converter, why not HDL -> C instead
49191: 02/11/05: Jim Granville: Re: C\C++ to HDL Converter, why not HDL -> C instead
49209: 02/11/05: Andrew MacCormack: Re: C\C++ to HDL Converter, why not HDL -> C instead
49211: 02/11/05: Tim: Re: C\C++ to HDL Converter, why not HDL -> C instead
49210: 02/11/05: john jakson: Re: C\C++ to HDL Converter, why not HDL -> C instead
47153: 02/09/19: Sameer D. Sahasrabuddhe: Re: C\C++ to VHDL Converter
47171: 02/09/19: Pierre Lafrance: Re: C\C++ to VHDL Converter
47420: 02/09/25: Uncle Noah: Re: C\C++ to VHDL Converter
47105: 02/09/17: Nicholas C. Weaver: Any Virtex 2 pro development boards yet?
47125: 02/09/18: Sanket Xilinx FAE Insight: Re: Any Virtex 2 pro development boards yet?
47133: 02/09/18: Nicholas C. Weaver: Re: Any Virtex 2 pro development boards yet?
47107: 02/09/18: SAKAKIHARA Kazuya: Using CVS with Quartus
47108: 02/09/17: John: Can I run a 3.3V CPLD off of 3V?
47115: 02/09/18: Laurent Gauch: Re: Can I run a 3.3V CPLD off of 3V?
47127: 02/09/18: George: Re: Can I run a 3.3V CPLD off of 3V?
47131: 02/09/18: Steve Prokosch: Re: Can I run a 3.3V CPLD off of 3V?
47109: 02/09/17: John: termination of JTAG pins
47110: 02/09/18: John_H: Re: termination of JTAG pins
47114: 02/09/17: Dongho: Feasibility of 100 tap adaptive FIR design on FPGA
47118: 02/09/18: Muzaffer Kal: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47143: 02/09/18: Ray Andraka: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47151: 02/09/18: Dongho: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47209: 02/09/20: Ray Andraka: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47117: 02/09/18: Jason Crawford: linear-log converter required
47132: 02/09/18: Larry Doolittle: Re: linear-log converter required
47144: 02/09/18: Ray Andraka: Re: linear-log converter required
47119: 02/09/18: Giuseppe³: Xilinx ISE5.1 and Windows NT
47142: 02/09/18: Kamal Patel: Re: Xilinx ISE5.1 and Windows NT
47161: 02/09/19: Kolja Sulimma: Re: Xilinx ISE5.1 and Windows NT
47193: 02/09/20: rickman: Re: Xilinx ISE5.1 and Windows NT
47196: 02/09/20: rickman: Re: Xilinx ISE5.1 and Windows NT
47224: 02/09/20: emanuel stiebler: Re: Xilinx ISE5.1 and Windows NT
47227: 02/09/20: Uwe Bonnes: Re: Xilinx ISE5.1 and Windows NT
47229: 02/09/20: Stephen Williams: Re: Xilinx ISE5.1 and Windows NT
47232: 02/09/20: Giuseppe³: Re: Xilinx ISE5.1 and Windows NT
47233: 02/09/20: Duane Clark: Re: Xilinx ISE5.1 and Windows NT
47247: 02/09/21: Uwe Bonnes: Re: Xilinx ISE5.1 and Windows NT
47279: 02/09/22: Duane Clark: Re: Xilinx ISE5.1 and Windows NT
47301: 02/09/23: Kolja Sulimma: Re: Xilinx ISE5.1 and Windows NT
47240: 02/09/21: <hamish@cloud.net.au>: Re: Xilinx ISE5.1 and Windows NT
47244: 02/09/21: Giuseppe³: Re: Xilinx ISE5.1 and Windows NT
47252: 02/09/21: Georg Acher: Re: Xilinx ISE5.1 and Windows NT
47253: 02/09/21: Uwe Bonnes: Re: Xilinx ISE5.1 and Windows NT
47262: 02/09/21: Stephen Williams: Re: Xilinx ISE5.1 and Windows NT
47698: 02/10/02: <hamish@cloud.net.au>: Re: Xilinx ISE5.1 and Windows NT
47263: 02/09/21: Simon: Re: Xilinx ISE5.1 and Windows NT
47237: 02/09/20: rickman: Re: Xilinx ISE5.1 and Windows NT
47239: 02/09/21: Stephen Williams: Re: Xilinx ISE5.1 and Windows NT
47242: 02/09/20: rickman: Re: Xilinx ISE5.1 and Windows NT
47246: 02/09/21: Rick Filipkiewicz: Re: Xilinx ISE5.1 and Windows NT
47339: 02/09/24: Petter Gustad: Re: Xilinx ISE5.1 and Windows NT
47335: 02/09/24: Petter Gustad: Re: Xilinx ISE5.1 and Windows NT
47200: 02/09/20: Rick Filipkiewicz: Re: Xilinx ISE5.1 and Windows NT
47215: 02/09/20: <hamish@cloud.net.au>: Re: Xilinx ISE5.1 and Windows NT
47225: 02/09/20: emanuel stiebler: Re: Xilinx ISE5.1 and Windows NT
47241: 02/09/21: <hamish@cloud.net.au>: Re: Xilinx ISE5.1 and Windows NT
47121: 02/09/18: Laurent Gauch: GCLK pin used like an standard input
47157: 02/09/19: Rajeev: Re: GCLK pin used like an standard input
47162: 02/09/19: Laurent Gauch: Re: GCLK pin used like an standard input
47211: 02/09/20: Ray Andraka: Re: GCLK pin used like an standard input
47277: 02/09/22: Falk Brunner: Re: GCLK pin used like an standard input
47122: 02/09/18: Stamatis Sotiropoulos: State of FPGA I/O pins before programming
47136: 02/09/18: Peter Alfke: Re: State of FPGA I/O pins before programming
47123: 02/09/18: Bernhard Holzmayer: Simple parallelport IP for Spartan2
47126: 02/09/18: Laurent Gauch: Re: Simple parallelport IP for Spartan2
47130: 02/09/18: Peter Wallace: Re: Simple parallelport IP for Spartan2
47459: 02/09/26: Bernhard Holzmayer: Re: Simple parallelport IP for Spartan2
48563: 02/10/21: Bernhard Holzmayer: Re: Simple parallelport IP for Spartan2
50214: 02/12/05: Laurent Gauch: Re: Simple parallelport IP for Spartan2
47129: 02/09/18: Govind Kharbanda: Handel-C: Unhandled exception: uncaught exception in compiler
47475: 02/09/26: Ash: Re: Handel-C: Unhandled exception: uncaught exception in compiler
47134: 02/09/18: John: using CPLD's inverter in oscillator circuit
47135: 02/09/18: Peter Alfke: Re: using CPLD's inverter in oscillator circuit
47155: 02/09/19: Marcin E. Hamerla: Re: using CPLD's inverter in oscillator circuit
47138: 02/09/19: Jim Granville: Re: using CPLD's inverter in oscillator circuit
47140: 02/09/18: Tom Burgess: Re: using CPLD's inverter in oscillator circuit
47139: 02/09/18: Test: Xilinx Spartan II PIN Status?
47141: 02/09/18: Peter Alfke: Re: Xilinx Spartan II PIN Status?
47150: 02/09/18: douglas: xilinx jtag chain question
47164: 02/09/19: douglas: Re: xilinx jtag chain question
47154: 02/09/19: Bruce: VHDL : Lookup Table
47165: 02/09/19: Rajeev: Re: VHDL : Lookup Table
47276: 02/09/22: Falk Brunner: Re: VHDL : Lookup Table
47280: 02/09/22: Ray Andraka: Re: VHDL : Lookup Table
47156: 02/09/19: Kolja Sulimma: XST ROM Synthesis
47159: 02/09/19: Simon Gornall: What software package
47235: 02/09/20: Simon Gornall: Re: What software package
47270: 02/09/22: Simon: Webpack and Wine (was: What software package)
47160: 02/09/19: Thijs: slightly OT: does anyone know free parallel flash programmer schematics?
47166: 02/09/19: Mikhail Matusov: Apex unused pins voluntarily assigned by Quartus?
47167: 02/09/19: Rene Tschaggelar: Re: Apex unused pins voluntarily assigned by Quartus?
47168: 02/09/19: Mikhail Matusov: Re: Apex unused pins voluntarily assigned by Quartus?
47220: 02/09/20: Christoph Fritsch: Re: Apex unused pins voluntarily assigned by Quartus?
47302: 02/09/23: Mikhail Matusov: Re: Apex unused pins voluntarily assigned by Quartus?
47221: 02/09/20: jakab tanko: Re: Apex unused pins voluntarily assigned by Quartus?
47169: 02/09/19: tony: Modelsim XE question
47172: 02/09/19: Duane Clark: Re: Modelsim XE question
47197: 02/09/20: tony: Re: Modelsim XE question
47217: 02/09/20: Duane Clark: Re: Modelsim XE question
47188: 02/09/20: alexi: Re: Modelsim XE question
47190: 02/09/20: Blackie Beard: Re: Modelsim XE question
47173: 02/09/19: Russell May: Altera A+PLUS software
47174: 02/09/19: Pierre Lafrance: Overheat with XCV-600E
47175: 02/09/19: Peter Alfke: Re: Overheat with XCV-600E
47195: 02/09/20: Dziadek: Re: Overheat with XCV-600E
47185: 02/09/20: Blackie Beard: Re: Overheat with XCV-600E
47187: 02/09/20: Ray Andraka: Re: Overheat with XCV-600E
47199: 02/09/20: Jerzy: Re: Overheat with XCV-600E
47222: 02/09/20: Farhad Abdolian: Re: Overheat with XCV-600E
47289: 02/09/22: Philip Freidin: Re: Overheat with XCV-600E
47309: 02/09/23: Pierre Lafrance: Re: Overheat with XCV-600E
47176: 02/09/19: John: XCV600 Version and Firmware
47202: 02/09/20: Ray Andraka: Re: XCV600 Version and Firmware
47219: 02/09/20: Ryan Laity: Re: XCV600 Version and Firmware
47177: 02/09/20: Reala: IC layout
47184: 02/09/20: Blackie Beard: Re: IC layout
47331: 02/09/24: Veli-Matti Karppinen: Re: IC layout
47387: 02/09/25: Spam Hater: Re: IC layout
47456: 02/09/26: Reala: Re: IC layout
47178: 02/09/19: Baoliang Wang: porblem about mapping spartenII design using schematic
47179: 02/09/19: James Wong: designing DDR I/O in CPLD
47191: 02/09/20: ds: Re: designing DDR I/O in CPLD
47243: 02/09/21: Spam Hater: Re: designing DDR I/O in CPLD
47194: 02/09/19: Norbert Pedersen: Old xc5200 with new software
47210: 02/09/20: Theron Hicks: Question on Spartan2E maximum toggle frequency
47214: 02/09/20: Peter Alfke: Re: Question on Spartan2E maximum toggle frequency
47216: 02/09/20: Alan Raphael: Functional VHDL Simulation Problem with Xilinx Coregen Async FIFOs
47223: 02/09/20: Mike Treseler: Re: Functional VHDL Simulation Problem with Xilinx Coregen Async FIFOs with Modelsim
47218: 02/09/20: Brannon King: Xilinx logiCore PCIX controller issues w/ Virtex2
48663: 02/10/22: Brannon King: Re: Xilinx logiCore PCIX controller issues w/ Virtex2
47231: 02/09/20: frank: SDRAM<--->FPGA<--->IDE interface
47265: 02/09/22: Blackie Beard: Re: SDRAM<--->FPGA<--->IDE interface
47416: 02/09/25: frank: Re: SDRAM<--->FPGA<--->IDE interface
47234: 02/09/20: John: pulldown resistor value for Xilinx CPLD
47236: 02/09/20: Peter Alfke: Re: pulldown resistor value for Xilinx CPLD
47408: 02/09/25: Hal Murray: Re: pulldown resistor value for Xilinx CPLD
47435: 02/09/25: Peter Alfke: Re: pulldown resistor value for Xilinx CPLD
47543: 02/09/28: Hal Murray: Re: pulldown resistor value for Xilinx CPLD
47245: 02/09/21: Ray Andraka: RPM zippering redux
47260: 02/09/21: Jan Gray: Re: RPM zippering redux
47261: 02/09/21: Ray Andraka: Re: RPM zippering redux
47248: 02/09/21: Dan: Can a fpga replace external inverters in a crystal osc ?
47250: 02/09/21: Ray Andraka: Re: Can a fpga replace external inverters in a crystal osc ?
47255: 02/09/21: Dan: Great feedback as always Ray . Thanks
47257: 02/09/21: Peter Alfke: Re: Can a fpga replace external inverters in a crystal osc ?
47273: 02/09/22: Rick Filipkiewicz: Re: Can a fpga replace external inverters in a crystal osc ?
47274: 02/09/22: Jim Granville: Re: Can a fpga replace external inverters in a crystal osc ?
47281: 02/09/22: Ray Andraka: Re: Can a fpga replace external inverters in a crystal osc ?
47407: 02/09/25: Hal Murray: Re: Can a fpga replace external inverters in a crystal osc ?
47294: 02/09/22: Jay: Re: Can a fpga replace external inverters in a crystal osc ?
47468: 02/09/26: Ray Andraka: Re: Can a fpga replace external inverters in a crystal osc ?
47472: 02/09/26: Austin Lesea: Re: Can a fpga replace external inverters in a crystal osc ?
47251: 02/09/21: Frank Adalater: Cheap development package for beginner?
47254: 02/09/21: Uwe Bonnes: Re: Cheap development package for beginner?
47256: 02/09/21: ds: Re: Cheap development package for beginner?
47258: 02/09/21: Kevin Brace: Re: Cheap development package for beginner?
47259: 02/09/21: Jim: Re: Cheap development package for beginner?
47272: 02/09/22: Marcel: Re: Cheap development package for beginner?
47275: 02/09/22: Uwe Bonnes: Re: Cheap development package for beginner?
47292: 02/09/22: Al Williams: Re: Cheap development package for beginner?
47264: 02/09/21: John: external switch to CPLD input
47267: 02/09/22: Jim Granville: Re: external switch to CPLD input
47318: 02/09/23: John: Re: external switch to CPLD input
47321: 02/09/24: Jim Granville: Re: external switch to CPLD input
47268: 02/09/22: Blackie Beard: Re: external switch to CPLD input
47266: 02/09/21: Leon Qin: Xilinx will not provid free ISE Allanice 5.1i?
47497: 02/09/26: Eric Smith: Re: Xilinx will not provid free ISE Allanice 5.1i?
47513: 02/09/27: Thomas Kurth: Re: Xilinx will not provid free ISE Allanice 5.1i?
47269: 02/09/21: Tony Dean: Spartan II JTAG reconfiguration bug - workaround
47271: 02/09/22: Marcel: Re: Spartan II JTAG reconfiguration bug - workaround
47278: 02/09/22: Blackie Beard: Re: Spartan II JTAG reconfiguration bug - workaround
47282: 02/09/22: Ray Andraka: Re: Spartan II JTAG reconfiguration bug - workaround
47283: 02/09/22: Falk Brunner: Re: Spartan II JTAG reconfiguration bug - workaround
47287: 02/09/22: Pierre-Olivier Laprise: Re: Spartan II JTAG reconfiguration bug - workaround
47355: 02/09/24: Tony Dean: Re: Spartan II JTAG reconfiguration bug - workaround
47372: 02/09/24: Peter Alfke: Re: Spartan II JTAG reconfiguration bug - workaround
47382: 02/09/24: Alan Nishioka: Re: Spartan II JTAG reconfiguration bug - workaround
47293: 02/09/23: Dali: Re: Spartan II JTAG reconfiguration bug - workaround
47296: 02/09/22: Andrew Bridger: Re: Spartan II JTAG reconfiguration bug - workaround
47365: 02/09/24: Neil Glenn Jacobson: Re: Spartan II JTAG reconfiguration bug - workaround
47430: 02/09/25: Steve Casselman: Re: Spartan II JTAG reconfiguration bug - workaround
47284: 02/09/22: Lorenzo Lutti: Timing accuracy with Modelsim
47285: 02/09/22: Falk Brunner: Re: Timing accuracy with Modelsim
47286: 02/09/22: Rick Filipkiewicz: Re: Timing accuracy with Modelsim
47288: 02/09/22: Brijesh: Re: Timing accuracy with Modelsim
47290: 02/09/22: Muzaffer Kal: Re: Timing accuracy with Modelsim
47322: 02/09/23: Lorenzo Lutti: Re: Timing accuracy with Modelsim
47342: 02/09/24: Christopher Saunter: Re: Timing accuracy with Modelsim
47368: 02/09/24: Lorenzo Lutti: Re: Timing accuracy with Modelsim
47486: 02/09/26: Rick Filipkiewicz: Re: Timing accuracy with Modelsim
47291: 02/09/23: Cool Morning ...: Re: VHDL Training Formal and Self-Study
47295: 02/09/22: newb: fpga eval kits
47312: 02/09/23: Rene Tschaggelar: Re: fpga eval kits
47324: 02/09/23: A. Nelson: Re: fpga eval kits
47405: 02/09/24: newb: Re: fpga eval kits
47476: 02/09/26: Steen Larsen: Re: fpga eval kits
47561: 02/09/28: Rudolf Usselmann: Re: fpga eval kits
47297: 02/09/23: Cool Morning ...: Any online M.Sc level engineering programs from a reputable university?
47298: 02/09/23: itsme: Xilinx RAM16x1D, Write fails in functional Simulation
47299: 02/09/23: Allan Herriman: Re: Xilinx RAM16x1D, Write fails in functional Simulation
47303: 02/09/23: Ray Andraka: Re: Xilinx RAM16x1D, Write fails in functional Simulation
47300: 02/09/23: cheponis: Altera Cyclone low-cost FPGA chips?
47304: 02/09/23: ds: Re: Altera Cyclone low-cost FPGA chips?
47306: 02/09/23: rickman: Re: Altera Cyclone low-cost FPGA chips?
47310: 02/09/23: rickman: Re: Altera Cyclone low-cost FPGA chips?
47352: 02/09/24: Marc Randolph: Re: Altera Cyclone low-cost FPGA chips?
47354: 02/09/24: Austin Lesea: Re: Altera Cyclone low-cost FPGA chips?
47357: 02/09/24: Tim: Re: Altera Cyclone low-cost FPGA chips?
47376: 02/09/24: Peter Alfke: Re: Altera Cyclone low-cost FPGA chips?
47369: 02/09/24: Xanatos: Re: Altera Cyclone low-cost FPGA chips?
47371: 02/09/24: Austin Lesea: Re: Altera Cyclone low-cost FPGA chips?
47377: 02/09/25: Jim Granville: Re: Altera Cyclone low-cost FPGA chips?
47385: 02/09/24: Marc Randolph: Re: Altera Cyclone low-cost FPGA chips?
47391: 02/09/25: Peter Alfke: Re: Altera Cyclone low-cost FPGA chips?
47393: 02/09/25: Nicholas C. Weaver: Re: Altera Cyclone low-cost FPGA chips?
47394: 02/09/25: Phil Hays: Re: Altera Cyclone low-cost FPGA chips?
47399: 02/09/25: ds: Re: Altera Cyclone low-cost FPGA chips?
47423: 02/09/25: Jack: Re: Altera Cyclone low-cost FPGA chips?
47425: 02/09/25: Austin Lesea: Re: Altera Cyclone low-cost FPGA chips?
47552: 02/09/28: Steve Mensor: Re: Altera Cyclone low-cost FPGA chips?
47397: 02/09/25: Jim Granville: Re: Altera Cyclone low-cost FPGA chips?
47424: 02/09/25: rickman: Re: Altera Cyclone low-cost FPGA chips?
47428: 02/09/25: Jay: Re: Altera Cyclone low-cost FPGA chips?
47434: 02/09/25: John_H: Re: Altera Cyclone low-cost FPGA chips?
47436: 02/09/25: Nicholas C. Weaver: Re: Altera Cyclone low-cost FPGA chips?
47542: 02/09/28: Hal Murray: Re: Altera Cyclone low-cost FPGA chips?
47547: 02/09/28: Pete Ormsby: Re: Altera Cyclone low-cost FPGA chips?
47455: 02/09/25: Marc Randolph: Re: Altera Cyclone low-cost FPGA chips?
47492: 02/09/26: Marc Randolph: Re: Altera Cyclone low-cost FPGA chips?
47314: 02/09/23: Jack: Re: Altera Cyclone low-cost FPGA chips?
47316: 02/09/23: Jan Gray: Re: Altera Cyclone low-cost FPGA chips?
47305: 02/09/23: Manuel Zaera Sanz: MTBF
47308: 02/09/23: Austin Lesea: Re: MTBF
47320: 02/09/23: Peter Alfke: Re: MTBF
47330: 02/09/24: Peter Alfke: Re: MTBF
47366: 02/09/24: Jon Elson: Re: MTBF
47374: 02/09/24: Austin Lesea: Re: MTBF
47379: 02/09/25: Stephen Williams: Re: MTBF
47390: 02/09/25: Peter Alfke: Re: MTBF
47307: 02/09/23: Markus Meng: Fast serial interconnect bus using spartan-II
47313: 02/09/23: Falk Brunner: Re: Fast serial interconnect bus using spartan-II
47315: 02/09/23: Nicholas C. Weaver: Re: Fast serial interconnect bus using spartan-II
47323: 02/09/23: Stephen Bradshaw: Re: Fast serial interconnect bus using spartan-II
47326: 02/09/23: Jason Daughenbaugh: Re: Fast serial interconnect bus using spartan-II
47353: 02/09/24: Theron Hicks: Re: Fast serial interconnect bus using spartan-II
47375: 02/09/24: TC: Re: Fast serial interconnect bus using spartan-II
47311: 02/09/23: Leon Heller: Altera Cyclone 'FPGA'
47344: 02/09/24: Xanatos: Re: Altera Cyclone 'FPGA'
47499: 02/09/26: Eric Smith: Re: Altera Cyclone 'FPGA'
47505: 02/09/27: Peter Alfke: Re: Altera Cyclone 'FPGA'
47686: 02/10/02: Rick Filipkiewicz: Re: Altera Cyclone 'FPGA'
47317: 02/09/23: Prashant: Unused pins in Apex20KE
47319: 02/09/23: Christoph Fritsch: Re: Unused pins in Apex20KE
47332: 02/09/24: Daryl: Re: Unused pins in Apex20KE
47361: 02/09/24: Prashant: Re: Unused pins in Apex20KE
47565: 02/09/29: Cédric Gaudin: Re: Unused pins in Apex20KE
47577: 02/09/29: Blackie Beard: Re: Unused pins in Apex20KE
47646: 02/10/01: Richard Damon: Re: Unused pins in Apex20KE
48584: 02/10/21: Prager Roman: Re: Unused pins in Apex20KE
47325: 02/09/23: A. Nelson: writing across a column in an SDRAM
47327: 02/09/23: rickman: Re: writing across a column in an SDRAM
47328: 02/09/23: Ray Andraka: Re: writing across a column in an SDRAM
47346: 02/09/24: A. Nelson: Re: writing across a column in an SDRAM
47389: 02/09/25: Spam Hater: Re: writing across a column in an SDRAM
47338: 02/09/24: Allan Herriman: Re: writing across a column in an SDRAM
47445: 02/09/25: Ray Andraka: Re: writing across a column in an SDRAM
47478: 02/09/26: Falk Brunner: Re: writing across a column in an SDRAM
47333: 02/09/24: rahul joshi: querries regarding cpld
47337: 02/09/24: Jim Granville: Re: querries regarding cpld
47340: 02/09/24: Dennis Sneijers: upcoming trened: analogue Fpga's?
47341: 02/09/24: Jim Granville: Re: upcoming trened: analogue Fpga's?
47406: 02/09/25: Dennis Sneijers: Re: upcoming trend: analogue Fpga's?
47343: 02/09/24: Jérémie WEBER: FPGA fail when Electrostatic discharge Occurs
47356: 02/09/24: Peter Alfke: Re: FPGA fail when Electrostatic discharge Occurs
47402: 02/09/25: Jeremie WEBER: Re: FPGA fail when Electrostatic discharge Occurs
47360: 02/09/25: Jim Granville: Re: FPGA fail when Electrostatic discharge Occurs
47404: 02/09/25: Jeremie WEBER: Re: FPGA fail when Electrostatic discharge Occurs
47409: 02/09/25: Jim Granville: Re: FPGA fail when Electrostatic discharge Occurs
47426: 02/09/25: Ray Andraka: Re: FPGA fail when Electrostatic discharge Occurs
47367: 02/09/24: Jon Elson: Re: FPGA fail when Electrostatic discharge Occurs
47433: 02/09/25: Austin Lesea: ESD Undressing Story
47444: 02/09/25: Ray Andraka: Re: ESD Undressing Story
48409: 02/10/17: Paul: Re: FPGA fail when Electrostatic discharge Occurs
47347: 02/09/24: Derek Wallace: Xilinx: Marking some latches for pass-thru timing
47349: 02/09/24: John_H: Re: Xilinx: Marking some latches for pass-thru timing
47350: 02/09/24: Matthew E Rosenthal: fpga comparisons???
47351: 02/09/24: Peter Alfke: Re: fpga comparisons???
47414: 02/09/25: Rene Tschaggelar: Re: fpga comparisons???
47461: 02/09/26: help me: Re: fpga comparisons???
47358: 02/09/24: Andy Peters: OT: Ulticap/Ultiboard 2001 netlist import failure
47359: 02/09/24: pbpc: xilinx demo board
47831: 02/10/04: pbpc: Re: xilinx demo board
47362: 02/09/24: Aki Niimura: Installing ISE5.1i (Alliance) on Solaris 7.
47395: 02/09/25: Petter Gustad: Re: Installing ISE5.1i (Alliance) on Solaris 7.
47363: 02/09/24: Thomas Wambera: Xilinx Cordic Core and Square Root...help
47751: 02/10/03: Thomas Wambera: Re: Xilinx Cordic Core and Square Root...help
47755: 02/10/03: fred: Re: Xilinx Cordic Core and Square Root...help
47370: 02/09/24: Verilog USER: JHDL Help
47378: 02/09/24: Clyde R. Shappee: Unpredictable Place and Route
47421: 02/09/25: Marc Randolph: Re: Unpredictable Place and Route
47441: 02/09/25: Dali: Re: Unpredictable Place and Route
47496: 02/09/26: Clyde R. Shappee: Re: Unpredictable Place and Route
47530: 02/09/27: Peter Young: Re: Unpredictable Place and Route
47538: 02/09/27: Clyde R. Shappee: Re: Unpredictable Place and Route
47697: 02/10/02: <hamish@cloud.net.au>: Re: Unpredictable Place and Route
47453: 02/09/25: Clyde R. Shappee: Re: Unpredictable Place and Route
47380: 02/09/25: Jim Lyke: Where can I get XC6200 series FPGAs
47392: 02/09/25: Peter Alfke: Re: Where can I get XC6200 series FPGAs
47386: 02/09/24: Leon Qin: Can I implement a PCI Master in a ACEX EP1k30-3 FPGA?
48476: 02/10/17: Kevin Brace: Re: Can I implement a PCI Master in a ACEX EP1k30-3 FPGA?
47400: 02/09/24: Dan: virtex II pro development board
47422: 02/09/25: jakab tanko: Re: virtex II pro development board
47429: 02/09/25: Marty: Re: virtex II pro development board
47572: 02/09/29: Peter Vandenabeele: Re: virtex II pro development board
47410: 02/09/25: Jarmo: PCB Design for Altera FPGA
47415: 02/09/25: Rene Tschaggelar: Re: PCB Design for Altera FPGA
47427: 02/09/25: Jay: Re: PCB Design for Altera FPGA
47489: 02/09/26: Steen Larsen: Re: PCB Design for Altera FPGA
47493: 02/09/26: rickman: Re: PCB Design for Altera FPGA
48477: 02/10/17: Kevin Brace: Re: PCB Design for Altera FPGA
48526: 02/10/18: Steen Larsen: Re: PCB Design for Altera FPGA
47813: 02/10/04: Jarmo: Re: PCB Design for Altera FPGA
47816: 02/10/04: Noddy: Re: PCB Design for Altera FPGA
47411: 02/09/25: John Daae: Clock balancing in DDR SDRAM design
47432: 02/09/25: John_H: Re: Clock balancing in DDR SDRAM design
47448: 02/09/26: David R Brooks: Re: Clock balancing in DDR SDRAM design
47412: 02/09/25: Jamba: spartan II and PCI 5 volt
47418: 02/09/25: Stephan Neuhold: Re: spartan II and PCI 5 volt
47440: 02/09/26: dohi: Re: spartan II and PCI 5 volt
47413: 02/09/25: Tim Plant: FPDP
47549: 02/09/28: Paul Baxter: Re: FPDP
47431: 02/09/25: Ken Mac: coregen DA FIR 7.0 singlerate/interpolated, floorplans, SRL16s and flip-flops
47437: 02/09/25: David Horner: FPGA programming via microcontroller
47438: 02/09/25: Mikhail Matusov: Re: FPGA programming via microcontroller
47450: 02/09/25: Leon Heller: Re: FPGA programming via microcontroller
47458: 02/09/26: ds: Re: FPGA programming via microcontroller
47460: 02/09/26: Johann Glaser: Re: FPGA programming via microcontroller
47439: 02/09/25: Rajeev: Virtex2 Block Multiplier: Faster, Faster
47443: 02/09/25: Peter Alfke: Re: Virtex2 Block Multiplier: Faster, Faster
47446: 02/09/25: Ray Andraka: Re: Virtex2 Block Multiplier: Faster, Faster
47449: 02/09/25: Yenni Totong: Re: Virtex2 Block Multiplier: Faster, Faster
47483: 02/09/26: Rajeev: Re: Virtex2 Block Multiplier: Faster, Faster
47490: 02/09/26: Yenni Totong: Re: Virtex2 Block Multiplier: Faster, Faster
47515: 02/09/27: Alan Fitch: Re: Virtex2 Block Multiplier: Faster, Faster
47447: 02/09/25: Ray Andraka: Re: Virtex2 Block Multiplier: Faster, Faster
47465: 02/09/26: Rajeev: Re: Virtex2 Block Multiplier: Faster, Faster
47442: 02/09/25: Dali: Re: Finding nets in hierarchy
47471: 02/09/26: Farhad Abdolian: Re: Finding nets in hierarchy
47533: 02/09/27: Peter Young: Re: Finding nets in hierarchy
47817: 02/10/04: Rajeev: Re: Finding nets in hierarchy
47451: 02/09/26: Russell: Re: Running Webpack under Linux :-)
47452: 02/09/26: Brijesh: any simulation models for hard disk or ATA interface?
47562: 02/09/28: Rudolf Usselmann: Re: any simulation models for hard disk or ATA interface?
47454: 02/09/26: David R Brooks: Finding nets in hierarchy
47481: 02/09/26: Steven Elzinga: Re: Finding nets in hierarchy
47799: 02/10/04: Utku Ozcan: Re: Finding nets in hierarchy
47462: 02/09/26: help me: comp.arch.fpga : mapping of fpga
47463: 02/09/26: help me: mapping of fpga
47473: 02/09/26: Mike D: Re: mapping of fpga
47464: 02/09/26: Nagaraj: Dual Port RAM
47467: 02/09/26: Ray Andraka: Re: Dual Port RAM
47519: 02/09/27: Nagaraj: Re: Dual Port RAM
47528: 02/09/27: Hal Murray: Re: Dual Port RAM
47534: 02/09/27: Nicholas C. Weaver: Re: Dual Port RAM
47535: 02/09/27: Muzaffer Kal: Re: Dual Port RAM
47600: 02/09/30: Rick Filipkiewicz: Re: Dual Port RAM
47474: 02/09/26: Jay: Re: Dual Port RAM
47477: 02/09/26: Sylvain Yon: Re: Dual Port RAM
47466: 02/09/26: Valentin Tihomirov: My CPLD (XC9536) is overheated
47480: 02/09/26: Lorenzo Lutti: Re: My CPLD (XC9536) is overheated
47545: 02/09/28: Lorenzo Lutti: Re: My CPLD (XC9536) is overheated
47546: 02/09/28: Valentin Tihomirov: Re: My CPLD (XC9536) is overheated
47536: 02/09/27: Jon Elson: Re: My CPLD (XC9536) is overheated
47469: 02/09/26: David: Looking for a dead Virtex
47482: 02/09/26: lng: Re: Looking for a dead Virtex
47495: 02/09/27: John_H: Re: Looking for a dead Virtex
47525: 02/09/27: Pierre Lafrance: Re: Looking for a dead Virtex
47470: 02/09/26: Martin E.: Choosing Virtex II Speed grade
47479: 02/09/27: dohi: Re: Choosing Virtex II Speed grade
47484: 02/09/26: Martin E.: Re: Choosing Virtex II Speed grade
47485: 02/09/26: Peter Sommerfeld: Nios interrupt latency?
47634: 02/10/01: Matjaz Finc: Re: Nios interrupt latency?
47664: 02/10/01: Lara Simsic: Re: Nios interrupt latency?
47670: 02/10/01: Jesse Kempa: Re: Nios interrupt latency?
47487: 02/09/26: ChristopheGuelff: CPCNG project : website updated
47491: 02/09/27: Jim Granville: Re: CPCNG project : website updated
47494: 02/09/26: ChristopheGuelff: Re: CPCNG project : website updated
47522: 02/09/27: Christopher Saunter: Re: CPCNG project : website updated
47488: 02/09/26: Dongho: implementation of adaptive FIR with many input channels?
47527: 02/09/27: Falk Brunner: Re: implementation of adaptive FIR with many input channels?
47781: 02/10/03: Dongho: Re: implementation of adaptive FIR with many input channels?
47801: 02/10/04: Falk Brunner: Re: implementation of adaptive FIR with many input channels?
47924: 02/10/07: Ray Andraka: Re: implementation of adaptive FIR with many input channels?
48134: 02/10/11: Dongho: Re: implementation of adaptive FIR with many input channels?
47498: 02/09/27: Dali: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47500: 02/09/27: Cool Morning ...: Is it possible to build a Ring Oscillator in an FPGA chip?
47501: 02/09/26: rickman: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47503: 02/09/27: Jim Granville: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47510: 02/09/27: Allan Herriman: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47511: 02/09/27: Jim Granville: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47509: 02/09/27: Valentin Tihomirov: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47529: 02/09/27: rickman: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47502: 02/09/27: Steve Casselman: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47504: 02/09/27: Ray Andraka: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47508: 02/09/27: Karl: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47518: 02/09/27: Ray Andraka: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47523: 02/09/27: Austin Lesea: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47506: 02/09/27: Peter Alfke: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47507: 02/09/27: Karl: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47524: 02/09/27: Peter Alfke: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47516: 02/09/27: luigi funes: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47512: 02/09/27: Michael Tornow: Quartus 2 Error: "Full compilation was cancelled due to an error"
47531: 02/09/27: Mike Treseler: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47936: 02/10/08: Michael Tornow: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47958: 02/10/08: Mike Treseler: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47559: 02/09/29: ds: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47597: 02/09/30: Ralph: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47514: 02/09/27: Jonathan Bromley: re: Timing accuracy with Modelsim
47517: 02/09/27: Valentin Tihomirov: JTag question
47520: 02/09/27: Valentin Tihomirov: Re: JTag question
47526: 02/09/27: Steve Casselman: Re: JTag question
47521: 02/09/27: Ken Mac: (repost) coregen DA FIR 7.0 singlerate/interpolated, floorplans, SRL16s and flip-flops
47532: 02/09/27: Mike Hubert: Xilinx CoreGenerator/IP Capture
47537: 02/09/27: hristo: Block Ram maximum speed
47539: 02/09/28: Ray Andraka: Re: Block Ram maximum speed
47544: 02/09/28: Falk Brunner: Re: Block Ram maximum speed
47548: 02/09/28: Ray Andraka: Re: Block Ram maximum speed
47550: 02/09/28: Nicholas C. Weaver: Re: Block Ram maximum speed
47553: 02/09/28: John_H: Re: Block Ram maximum speed
47554: 02/09/28: Nicholas C. Weaver: Re: Block Ram maximum speed
47540: 02/09/27: Jan Gray: Why no ROC for Xilinx Verilog sim and synthesis?
47551: 02/09/28: Rudolf Usselmann: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47555: 02/09/28: Jan Gray: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47558: 02/09/28: Rudolf Usselmann: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47560: 02/09/28: Jan Gray: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47570: 02/09/29: Rudolf Usselmann: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47569: 02/09/29: Allan Herriman: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47541: 02/09/28: Anonymous: Ignore me - just a test
47556: 02/09/28: Ru-Chin Tsai: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47557: 02/09/28: Farhad Abdolian: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47574: 02/09/29: Dali: Re: Does it need any protection circuit for Interfacing FPGA device
47575: 02/09/29: Blackie Beard: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47587: 02/09/29: rickman: Re: Does it need any protection circuit for Interfacing FPGA device with
47588: 02/09/30: Hal Murray: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47589: 02/09/30: rickman: Re: Does it need any protection circuit for Interfacing FPGA device
47590: 02/09/30: Blackie Beard: Re: Does it need any protection circuit for Interfacing FPGA device with PC ISA slot?
47564: 02/09/29: RCU: Getting started
47576: 02/09/29: Blackie Beard: Re: Getting started
47582: 02/09/29: RCU: Re: Getting started
47591: 02/09/30: Blackie Beard: Re: Getting started
47638: 02/10/01: Rudolf Usselmann: Re: Getting started
47657: 02/10/01: RCU: Re: Getting started
47676: 02/10/02: Tony Burch: Re: Getting started
47566: 02/09/29: Dennis: design multiplier
47571: 02/09/29: Peter Alfke: Re: design multiplier
47580: 02/09/30: ds: Re: design multiplier
47585: 02/09/30: Farhad Abdolian: Re: design multiplier
47606: 02/09/30: Ray Andraka: Re: design multiplier
47607: 02/09/30: Farhad Abdolian: Re: design multiplier
47610: 02/09/30: D Lee: Re: design multiplier
47611: 02/10/01: Ray Andraka: Re: design multiplier
47625: 02/10/01: Martin Thompson: Re: design multiplier
47654: 02/10/01: Falk Brunner: Re: design multiplier
47612: 02/09/30: Peter Alfke: Re: design multiplier
47688: 02/10/02: Rick Filipkiewicz: Re: design multiplier
47567: 02/09/29: H.L: Chipscope cores
47583: 02/09/29: Jay: Re: Chipscope cores
47568: 02/09/29: Sudip Saha: memory block instantiation in altera devices/FPGAs
47573: 02/09/29: ds: Re: memory block instantiation in altera devices/FPGAs
47578: 02/09/29: Matthew E Rosenthal: xilinx size historical information
47581: 02/09/29: Matthew E Rosenthal: altera size historical information
47593: 02/09/30: news.terra.es: SOC interconexion
47639: 02/10/01: Rudolf Usselmann: Re: SOC interconexion
47594: 02/09/30: Moky: Large Multiplexer
47595: 02/09/30: Xu Qijun: Re: Large Multiplexer
47596: 02/09/30: Paul Baxter: Re: Large Multiplexer
47599: 02/09/30: Christopher Saunter: Re: Large Multiplexer
47694: 02/10/02: Christopher Saunter: Re: Large Multiplexer
47737: 02/10/02: Muthu: Re: Large Multiplexer
47746: 02/10/03: Ray Andraka: Re: Large Multiplexer
47750: 02/10/03: Ray Andraka: Re: Large Multiplexer
47598: 02/09/30: Ensoul Chee: system item in synplify report
47821: 02/10/04: Ken McElvain: Re: system item in synplify report
47834: 02/10/04: Jay: Re: system item in synplify report
47601: 02/09/30: Jean-Luc Cooke: Diving in for the first time
47602: 02/09/30: Jean-Luc Cooke: correction
47603: 02/09/30: Tinoosh Mohsenin: Simulating mixed Verilog and VHDL files
47604: 02/09/30: Theron Hicks: FFT in FPGA?
47605: 02/09/30: Ray Andraka: Re: FFT in FPGA?
47613: 02/09/30: Theron Hicks (Terry): Re: FFT in FPGA?
47629: 02/10/01: Paul Baxter: Re: FFT in FPGA?
47640: 02/10/01: Ray Andraka: Re: FFT in FPGA?
47645: 02/10/01: Theron Hicks: Re: FFT in FPGA?
47609: 02/09/30: Dali: Re: Rounting of non-global IO pad to a GCLKIOB site.
47615: 02/10/01: Dali: Re: Rounting of non-global IO pad to a GCLKIOB site.
47653: 02/10/01: David Rogoff: Re: Rounting of non-global IO pad to a GCLKIOB site.
47626: 02/10/01: Ho Wong: Re: Rounting of non-global IO pad to a GCLKIOB site.
47655: 02/10/01: Falk Brunner: Re: Rounting of non-global IO pad to a GCLKIOB site.
47671: 02/10/02: Ray Andraka: Re: Rounting of non-global IO pad to a GCLKIOB site.
47684: 02/10/02: Dali: Re: Rounting of non-global IO pad to a GCLKIOB site.
47614: 02/09/30: Cisa: Configuration:Startup
47641: 02/10/01: Ray Andraka: Re: Configuration:Startup
47673: 02/10/01: Cisa: Re: Configuration:Startup
47689: 02/10/02: Ulises Hernandez: Re: Configuration:Startup
47733: 02/10/02: Cisa: Re: Configuration:Startup
47739: 02/10/03: Ulises Hernandez: Re: Configuration:Startup
47782: 02/10/03: Cisa: Re: Configuration:Startup
47788: 02/10/04: Ulises Hernandez: Re: Configuration:Startup
47808: 02/10/04: Ray Andraka: Re: Configuration:Startup
47837: 02/10/04: Cisa: Re: Configuration:Startup
47616: 02/09/30: Cisa: Search help about architecture of STARTUP?
47617: 02/10/01: Spam Hater: Re: Search help about architecture of STARTUP?
47628: 02/10/01: Ulises Hernandez: Re: Search help about architecture of STARTUP?
47635: 02/10/01: Cisa: Re: Search help about architecture of STARTUP?
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