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Loi Tran wrote: > > I've been trying to get a simple GAL22v10 programmed so that I can get my > little personal project going. I grabbed the old PALASM software off the net > get a JEDEC file from it just fine. I buy some 22v10 except they're not GALs. > They're PALs. I have an EMP10 (needham's) programmer, but it won't take PAL > parts. Only Lattice GAL parts. I try anyway. The programming software tells > me that the number of fuses in the file doesn't match the number of fuses in > the device. Silly me! I thought 22V10 parts were all the same. It tells me > that there are 5892 fuses in the GAL22V10 I specified in software and that the > loaded JEDEC file only indicates 5828 fuses. Then it gives me an option to > fill in the last 64 fuse map addresses with 0. So here are my questions. > > 1) Can I just tell it to fill in the remaining 64 and program a Lattice > GAL22v10 just fine? > > 2) The palasm software spits out JEDEC files for the old PAL22V10. Can I use > it to program a "modern" GAL part? Or do I have to juggle some more to get > the proper software? If not, can anyone direct me to where I can find free or > relatively cheapish software that will put out modern GAL jedec files? I don't know about your programmer, but for a Xeltek, you have to define the manufacturer of the 'read from' PAL/GAL ... and then choose a different manufacturer of the new IC to 'write to' . So I'd choose from AMD ? PALCE22V10 and write to Lattice GAL22V10. With Palasm did you run the simulation? Trace ? What's the history say? > 3) Here's the other problem. The EMP10 programmer gives me 2 options in the > GAL selection. One is GAL22V10 and the other is GAL22V10B (note the B > suffix). I searched high and low and I can't find the GAL22V10B. It's been > obseleted. All they sell are D suffix parts. What's the difference? > > If anyone can answer these questions, please answer. Don't be shy. You won't > get much for your altruism, but you'll get a warm fuzzy for doing it. I hope. > > Thanks, > > LTArticle: 46701
The reason for my post was to argue that claims that a Linux version of Quartus (usage or not of WINE is immaterial to me) providing a full development environment need to be substantiated. My particular feeling is that the Quartus 2 synthesiser and VHDL parsing/error checking (as of v1.1 SP2 admittedly) are far too poor to be considered for any non-trivial development. > Could you clarify your statement "I really have given the native Quartus > 2 synthesiser lots of outings" by specifying the version of Quartus II was > used ? The reply to Prager referred to Quartus II 2.1, and maybe you could > share your results for the quality of the HDL processing for Quartus II 2.1, > for your unmodified design with GENERICS. OK Used version 1.0 through ver 1.1 SP2. A large project began whilst using v1.1 SP2 so I have frozen development to using that version. I have monitored subsequent releases but haven't found a compelling feature or bug fix that would warrant the update considering I'd probably need to do my timing simulations again. That said until I hear reports on the ng extolling new-found virtues I will not use windows Quartus 2 for synthesis - just place and route. I would LOVE someone to tell me its hugely better now though as an integrated design flow is preferred from ease of use standpoint. Since I haven't used v2.1 I cannot comment definitively. I really hope it is a lot better, but until a Linux Quartus 2 user definitively tells me it is a robust useful development environment (and not just something that works some of the time) I'm not willing to take Altera at face value. I urge others to be cautious before relying on it too. Please don't mistake this for Linux-bashing. I would LOVE Quartus 2 to be available on both Windows and Linux (and elsewhere for that matter) just evaluate its strengths and weaknesses before claiming it a complete development environment. I'm fairly happy with using Leonardo for the synthesis (which I did upgrade to fix a couple of annoying synthesis bugs in 2001_1d) and Quartus II just for place/route. This route is sadly not available on Linux (though I would imagine this would be far easier to port to Linux than Quartus 2 was). I just had a LOT of grief and several months of ultimately wasted effort with the Quartus 2 synthesiser so when I see recommendations to use it in a practical system I feel the need to answer. Frankly I wish Altera were more up front about the deficiencies of its synthesiser. There is a reason they bundle Leonardo to get any sort of reasonable results. You are right that I should look at 2.0 and 2.1 but only when this project closes. Back to you. My questions: 1) Generics - you imply they are fully supported now. That's great. I can pass generics of all types? or just integers? to all code or just megafunctions? 2) Has the VHDL parser/syntax checker been re-written more robustly? Crashing during 3) Have Altera made claims that the synthesis results are improved and perhaps even on a par with say Leonardo level 1? Can they show large designs that bear this out? Oh and are you connected with Altera or just a concerned citizen? Paul Just to clarify, there is a lot to praise about the Altera software too particularly in ease of use for beginners. I just wish sometimes that rather than adding new bolt-on features and making big increases to the version number they'd focus on getting right what they have.Article: 46702
reply in the newsgroup wrote: > "Havatcha" <nospam@nospam.com> wrote in message > news:3D77377E.9070006@nospam.com... > >>Petres, Zoltan wrote: > > > [deleted] > > >>You define the entire network in a hardware description language (like >>VHDL or verilog) and download this onto the FPGA, so you know implicitly >>the entire architecture of the network. Assuming you have prior >>programming experience you should be able to learn VHDL, it can be a bit >>confusing since you have to think in terms of parallel hardware but it >>is worth a go. You can download software that will do this from >>www.xilinx.com for free but you will need to buy the cable to connect >>from your PC to the FPGA board. (100 dollars) >>You will also need to build the board to mount the FPGA onto so some >>electronics knowledge would be advisable. > > > Where on that rather large website? LOL, here is the URL http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack > Do you have to already have a > license for some particular product to even see the part of the website > where you can do the download? > No, but you do have to register to download it. > I'd like to learn VHDL also, while I'm unemployed and therefore have > little money to buy anything. > > If you are serious about using VHDL, I can also recommend ModelSim (http://www.model.com/products/release.asp) as a development tool. I am not sure if you can get a free version though.....Article: 46703
> This is where things like out-of-order execution come in, too, yes no?
Don't think so. Out-of-order is enabled by breaking the CISCy intructions
down into simpler ("RISCy") ones - the important feature being that in the
former, there no longer are intra-instruction dependencies, so that you can
really get useful work down out of order. Where you store them (if at all)
and whether your microengine tries to optimize this "translated" code is not
relevant to execution out of order.
Jan
Article: 46704Hello, I'm beginners in fpga devices. I have Spartan XC2S200 board with IO2, XCS10 board and XC95108 with 8032 board. I'm looking any basic examples which can be simply implemanted on thos chips. I have to lerne programming it very quicly. Could you send me examples, simple work to help me? Of course if you klno any WWW pages with examples it will be usefull too. Marek P.S. Plese send also on my e-mail. Marek.Jaskula@ps.plArticle: 46705
getamit_leo@hotmail.com (Amit) wrote in message news:<cd334b5b.0209050604.199a7734@posting.google.com>... > Hi All, > I am vlsi engineer and mainly deal in synthesis part. I have got a > problem .. > I am compiling a library .lib and creating it's .db but when i use for > synthesis it shows an error that either a 2 input OR or AND or NOR > gate is not available for mapping. When i read .lib there these gates > are defined. > If someone has any solution for it then please send to me. > > Thanks & Regards > Amit Hi, I have got the solution. Since in my library compiler certain features were not enabled that's why it was treating the cells as black box.Article: 46706
Steven, OK, I'll bite :-) Steven Elzinga <steven.elzinga@xilinx.com> wrote in message news:<3D77B576.7166323B@xilinx.com>... <...> > Kevin Brace wrote: > > > What I don't understand about Xilinx is that, XST of ISE 4.x can > > actually generate an EDIF netlist, but Xilinx refuses to let people use > > it from ISE's VHDL or Verilog GUI design flow. > > Since an EDIF file from XST is not a supported flow I think that we would be > giving mixed messages if we were to allow EDIF as an output option. However <...> In this ISE 4.x 'supported design flow', how is a user supposed to diagnose errors coming from an XST-generated net-name ? Regards, -rajeev-Article: 46707
Hello, I am running the 45 day full eval of the Libero Platinum tool from Actel. I am running a design that is about 80% of a ProAsicPlus APA300, about 6400 logic tiles used. When I start a pre-synthesis ModelSim simulation I get the following message (see end), which is similar to the Xilinx ModelSim. That is, the simulator will be intentionally slowed down. The idea behind this is to motivate people to buy the full simulator of course. However, on the Actel ModelSim, it goes to a crawl, where on the Xilinx ModelSim it is not slowed too badly and reasonable simulation runs can be done. Does anyone own the Platinum version of this tool and does it really run this slow? I look at the license file and I do not see anything that would lead me to believe this is a "Eval" crippled version of the simulator. I had at one point owned the Gold version and it also experienced the same crippled behavior. Thanks for any input. Dave Colson # WARNING: Design size of 1676 instances exceeds ModelSim ACTEL recommended capacity. # Expect performance to be adversely affected.Article: 46708
Vikram, Thanks for your suggestions. Vikram Pasham <Vikram.Pasham@xilinx.com> wrote in message news:<3D767E5E.93EBF076@xilinx.com>... > Rajeev, > > A good place to look is XST log file. XST might have given some warnings on nets > with multiple drivers. Also, search on support.xilinx.com for answer records on > Ngdbuild multiple driver error messages. The answer records did in fact help. The message I saw can be generated from disconnected logic, which I had disconnected a ChipScope ILA in the hope that it would be optimized away. Completely removing the ILA did solve the problem. Nevertheless it does seem that an error message that identifies a netname should be traceable. The EDIF output (thanks to Kevin, in this thread) permits me to do this. > ISE 5.1i provides an NGC to EDIF translator to generate a readable netlist file. > ISE5.1i also provides a RTL schematic viewer which can be used to track such > re-named internal nets. I'll look forward to it, when I step up my tools revision. Thanks, -rajeev- > > -Vikram > > > Rajeev wrote: > > > Hi, > > > > I'm stymied, and I'm hoping some Xilinx guru out there will take > > pity and show me the way ! > > > > Tools: ISE 4.1i, using XST VHDL > > When I translate my design I get the following message > > > > ERROR:NgdBuild:455 - logical net 'N867' has multiple drivers > > One or more errors were found during NGDBUILD. No NGD file will be written. > > > > How do I find N867 ? > > > > I can't find a text netlist to view. And without NGD file, I'm unable to get > > to the FPGA Editor. This is driving me nuts. > > > > Thanks for any help !!!!! > > > > -rajeev-Article: 46709
> ...and the index values for both arrays will be 8 bit values, not 9 as > you've been using, since they range from 0 to 255 inclusive. You will need > to spend more time on correcting the bitwidth issues in your program - This > is common when porting C to Handel-C. > > > This hopefully should start you on your way : Good luck! Thanks... I'm making a lot of progress already now. I would have never spotted that out[] needed an index of less than 32 bits... I could do with advice on a couple of matters still: iX, oX are originally ints, but these are being used to access elements of arrays inp and out which only go from 0....255. Therefore I'm declaring them as unsigned log2n iX, oX; where log2n is a macro expression (8 in this case) similarly the trig array is accessed by the variable T, again trig only goes from 0...320 (= 5*n/4) so I'd need to do something like unsigned <5*n/4> T; my problem is that the block size n, eventually will be passed as a parameter from the software which sends the block to be processed across. The block size n is either 256 or 2048. So this won't be known at compile time... I guess I'll have to force the arrays to be the larger size always??? Cheers, GovindArticle: 46711
Ooops. What I wrote in my last posting was wrong. Hope my logic is better this time. For a block size of n = 256, the array trig_256 has 320 (= 5*n/4) elements, each of which is a signed 32. Since T is used to index the trig_256 array, T should be of width 9. Therefore, macro expr trigsize log2ceil(5*n/4); unsigned <trigsize> T; should do the trick. Would this work?! GovArticle: 46712
If you want to estimate mAh for CoolRunner-II CPLDs, there is a good web link that allows you to enter design constraints and see how long it will run on different battery types http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=coolrunner2_page click on the power comparison link John wrote: > I was wondering what exactly quiescent/static/standby current are (if > they are in fact different). > > I am planning to run an FPGA or CPLD (probably the Xilinx > CoolRunnerII) off of a watch battery or two. The design has around > four counters and some decoders, and the clock speed will be 32.768 > kHz. > > Most watch batteries seem to be rated at about 50 mAh. The particular > CoolRunnerII i have in mind has a quiescent current of 14uA. Does this > mean that I will get about 50/.014=3571 hours of FPGA usage with one > battery? Or will the actual current drawn be significantly more than > the quiescent current? > > The CoolRunnerII family also claims to have a Static Icc of <100uA at > all times. Is the static Icc what I should be looking at? > > Thanks in advance!Article: 46713
Rajeev, I think that the suggestions that Vikram gave were very good suggestions on dealing with the types of errors that you were running into. Also, in stating that an EDIF output from XST is unsupported only means that if you are having problems implementing your XST EDIF file and you call the hotline they will want you to implement the NGC file to see if there is a problem. Also, if there is a problem with the way XST is writing the EDIF file Xilinx will not fix it. The EDIF output from 4.1i XST is useful for tracking down issues like you were having. Steve Rajeev wrote: > Steven, > > OK, I'll bite :-) > > Steven Elzinga <steven.elzinga@xilinx.com> wrote in message news:<3D77B576.7166323B@xilinx.com>... > > <...> > > > Kevin Brace wrote: > > > > > What I don't understand about Xilinx is that, XST of ISE 4.x can > > > actually generate an EDIF netlist, but Xilinx refuses to let people use > > > it from ISE's VHDL or Verilog GUI design flow. > > > > Since an EDIF file from XST is not a supported flow I think that we would be > giving mixed messages if we were to allow EDIF as an output option. However > > <...> > > In this ISE 4.x 'supported design flow', how is a user supposed to diagnose > errors coming from an XST-generated net-name ? > > Regards, > -rajeev-Article: 46714
Usually when for loops are put into HandelC, it's best to recode them
as a while loop as the index variable can be incremented in parallel
with whatever action is performed on each iteration.
I've got a bit of an odd for loop here, and I'm not sure if I've done
it right. Here it is:
unsigned trigwidth T; /* index to init->trig */
unsigned log2n stages; /* number of butterfly stages */
unsigned log2n i,j; /* index variables for loops */
stages = log2n - 5; /* n = 256 usually, so stages = 3 */
/* log2n defined as a macro expr */
/*
* Following lines are a little tricky:
* originally stated:
*
* for (i=1; --stages>0; i++){
* for (j=0; j<(1<<i);j++)
* mdct_butterfly_generic(T,x+(points>>i)*j),points>>i,4<<i);
* }
*
* Here follows my attempt
*/
i=1;
do
{
stages--;
par
{
for(j=0;j<(i<<i);j++)
mdct_butterfly_generic(T,x+(points>>i)*j,points>>i,4<<i);
i++;
}
}while (stages>0);
this could be taken further:
i=1;
do
{
stages--;
par
{
j=0;
do
{
par
{
mdct_butterfly_generic(T,x+(points>>i)*j,points>>i,4<<i);
j++;
}
}while (j<(1<<i));
i++;
}
}while (stages>0);
Also the compiler is throwing up width errors, for instance width '8'
doesn't match width '4'. For instance
while (j<(1<<i))
j is of width 8, how come 1<<i is being inferred to have a width of 4?
Cheers,
Gov
Article: 46715Hi, What sort of degradation can be expected in performance of a design once it is ported onto an FPGA. for e.g. if a 20000 LE design works at 40 MHz when synthesized in Quartus II on a Apex20KE1500 device, how much worse can it get when it actually gets implemented on the above device ? Also, Altera seems to offer an online course for Examining & Improving Timing Results in Quartus Software for $95 for a month. Has anyone had any experience with this course ? Does it really help as it claims ? I appreciate all the help. Thanks, PrashantArticle: 46716
"John" <jjjkkl@hotmail.com> schrieb im Newsbeitrag news:4a50e479.0209051449.2684001@posting.google.com... > I was wondering what exactly quiescent/static/standby current are (if > they are in fact different). > > I am planning to run an FPGA or CPLD (probably the Xilinx > CoolRunnerII) off of a watch battery or two. The design has around > four counters and some decoders, and the clock speed will be 32.768 > kHz. > > Most watch batteries seem to be rated at about 50 mAh. The particular > CoolRunnerII i have in mind has a quiescent current of 14uA. Does this > mean that I will get about 50/.014=3571 hours of FPGA usage with one > battery? Or will the actual current drawn be significantly more than > the quiescent current? I dont want to disdrag you from FPGAs/CPLDs especially not Xilinx parts ;-) But for such a application a small low-power uC would be a better choice. Have a look at www.ti.com they have a nice looking one (MSP430) Current <1uA in standby. -- MfG FalkArticle: 46717
"Marek Jaskula" <Marek.Jaskula@ps.pl> schrieb im Newsbeitrag news:3D7876A0.4030802@ps.pl... > Hello, I'm beginners in fpga devices. I have Spartan XC2S200 board with > IO2, XCS10 board and XC95108 with 8032 board. > > I'm looking any basic examples which can be simply implemanted on thos > chips. I have to lerne programming it very quicly. Could you send me > examples, simple work to help me? Of course if you klno any WWW pages > with examples it will be usefull too. www.opencores.org www.fpga-faq.com www.xilinx.com (go to the support section, there you will find a lot of good stuff, even if it is not for a total FPGA beginner) Do a google search for "VHDL cockbook", this will get you into the business a little bit easier. -- MfG FalkArticle: 46718
"Havatcha" <nospam@nospam.com> schrieb im Newsbeitrag news:3D787371.20404@nospam.com... > If you are serious about using VHDL, I can also recommend ModelSim > (http://www.model.com/products/release.asp) as a development tool. I am > not sure if you can get a free version though..... Xilinx supplies a free version of Modelsim along with Webpack. Its limited in simulation speed depending on VHDL code lines <500 lines 100% speed 500...2000? lines 1% >2000? 0.1 % ?? -- MfG FalkArticle: 46719
If the static timing analysis says you can achieve 40 MHz, 40MHz is the speed you can achieve. The only caveat I know of is if your clock to the device isn't jitter-free, you should add the amount of period jitter to your design margin. If you have a 40MHz clock with 250ps of jitter, specify 24.75ns for your period, not 25ns. Prashant wrote: > Hi, > > What sort of degradation can be expected in performance of a design > once it is ported onto an FPGA. for e.g. if a 20000 LE design works at > 40 MHz when synthesized in Quartus II on a Apex20KE1500 device, how > much worse can it get when it actually gets implemented on the above > device ? > > Also, Altera seems to offer an online course for Examining & Improving > Timing Results in Quartus Software for $95 for a month. Has anyone had > any experience with this course ? Does it really help as it claims ? > > I appreciate all the help. > > Thanks, > PrashantArticle: 46720
Paul Baxter wrote:
> The reason for my post was to argue that claims that a Linux version of
> Quartus (usage or not of WINE is immaterial to me) providing a full
> development environment need to be substantiated. My particular feeling is
> that the Quartus 2 synthesiser and VHDL parsing/error checking (as of v1.1
> SP2 admittedly) are far too poor to be considered for any non-trivial
> development.
Quartus has good schematic capture and place&route.
The "native synthesis and simulation" claim is a bad joke
as it wastes new user's time.
Rather than touting free hdl tools that disappoint,
Altera ought to be talking about a their best deal
for new users: a pc license for leo+modelsim+quartus for $2k.
-- Mike Treseler
Article: 46721I obviously cannot speak for Altera, but... I found your first paragraph confusing. When you synthesize a design and it works at 40 MHz, well than it does work at 40 MHz. How could it possibly get slower? You must have some question on your mind, but I do not understand it. Always glad to help. Peter Alfke, Xilinx Applications ====================================== Prashant wrote: > Hi, > > What sort of degradation can be expected in performance of a design > once it is ported onto an FPGA. for e.g. if a 20000 LE design works at > 40 MHz when synthesized in Quartus II on a Apex20KE1500 device, how > much worse can it get when it actually gets implemented on the above > device ? > > Also, Altera seems to offer an online course for Examining & Improving > Timing Results in Quartus Software for $95 for a month. Has anyone had > any experience with this course ? Does it really help as it claims ? > > I appreciate all the help. > > Thanks, > PrashantArticle: 46722
I have received an email reply from Xilinx which says that the XCR3384XL device is significantly more expensive to make than the XCR3256XL and so there are no plans to significantly reduce the price. rickman wrote: > > I have not been in touch with my disti on this as that is usually a slow > process. Anyone know what the current story is on the CoolRunner > XCR3384? I see them listed on the disti web sites, but there is nearly > no inventory and the prices are way through the roof! > > The XCR3256XL-12FT256C is "only" $17, but the XCR3384XL-12FT256C is > $60!!! This must be the early leadin price. Anyone know what the > target price is for 3-5 months out, like in January? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46723
In article <ea62e09.0209060713.74faede1@posting.google.com>, Prashant <prashantj@usa.net> wrote: >Hi, > >What sort of degradation can be expected in performance of a design >once it is ported onto an FPGA. for e.g. if a 20000 LE design works at >40 MHz when synthesized in Quartus II on a Apex20KE1500 device, how >much worse can it get when it actually gets implemented on the above >device ? Who's tsiming numbers? IF it is the vendor's static timing analysis, it RUNS at 40 MHZ. IF it is the synthesis tool's reported numbers, it is a Well Constructed Wild Ass Guess, and you should take the design through placement, routing, and timing analysis -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46724
John_H wrote: > > rickman wrote: > <snip> > > > I can understand Altera (or anyone else) wanting to protect their IP. > > In fact, I think Altera makes the IP available with no royalties because > > the idea is that you are paying for the royalty when you buy their chips > > to put the design in. > > > > But they certainly don't have the same issue with the bitstream. I > > understand that the court has ruled that ClearLogic must cease making > > these parts. But as I said, I would expect to have full rights to my > > own design. I am surprised that running it through Altera tools would > > limit my rights. > > <snip> > > You absolutely have rights to your own design. But the bitstream isn't your > design - it's the digested, processed, mapped, placed and routed version of your > design. If Altera, Xilinx, et. al. had the ability to lose silicon revenue to > the likes of ClearLogic, would they have the same motivation to improve the > tools to the extent that they do? While I still don't believe either of those > major brands have a tool suite that gets us to finished high speed or high > density designs without significant hurdles, the tools haven't lost > (significant) ground to the silicon. > > Your verilog code, your VHDL... it's all yours, even if you created it with > their editors. The getting your design into their parts is what's proprietary. > > This is of course only a counter viewpoint to the "everything I produce is mine" > view and I don't feel strongly on the issue. I'm just giving a little > perspective to the less-than-clear situation from another user's standpoint. I don't want to argue needlessly, but in analogy to software where the compiled code is also a "protected work", the bitstream is just a restatement of the original design. Copyright law is clear on this. But obviously owning the rights to a protected work does not mean that you can express that work any way you wish... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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