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I can remember not too long ago when a 25K gate FPGA was huge (see my paper "An
FPGA Based Processor Yields a Real Time High Fidelity Radar Environment
Simulator" which was done on 25K gate Xilinx 4025E's when they were the newest
parts). You can do quite a bit with a 50K gate array, especially if you have
the luxury of sample rates under 10MHz or so. We've done some pretty
sophisticated image processing in the Spartann 50, for example. The best part,
is you can use the webpack tools for the design, which means free tools. Same
is true for the low end Altera parts. There are even universities putting
boards on-line with web interfaces so that you don't need your own board to
download and run a design. There is one I am aware of that duplicates the
pushbuttons and displays on a webpage, and even puts a webcam shot of the board
up so you can see the smoke when you fry it :-) That particular one I think
will be open for anyone to use.
Ralph Mason wrote:
> Hi,
> A am wanting to learn verilog (it seems easier that VHDL) and play with an
> FPGA ( I quite like the idea if designing my own CPU, make dram controllers
> etc) I am looking for an easy low cost start. I have written a little VHDL
> before and done GALS etc.
>
> Currently I have my eye on the XSA-50 from Xcess because it has a fpga and a
> cpld and ram and flash
> ( http://xess.com/prod027.php3) - What can you fit in a 50k gat FPGA - A
> processor, memory controller, video and io support?
>
> A am also interested in FPSLIC but I understand you can only use the tools
> for 4 months and then they cost many $$$$ after that
>
> Are there any other boards that anyone can suggest that are reasonably
> prices and include tools. Does anyone have any comments on either of these.
>
> Thanks for any advice
> Ralph
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48401Neil Franklin wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > > Neil Franklin wrote: > > > > > > I care for whatever chip solves my problem. The 2 year old ones do so. > > > > date. If that is all you need, then great. But don't expect the design > > community to welcome open source with open arms. :) > > Did I ever do thet? I only said that I was doing something. You then > decided to jump on me. I did not jump on you. If that is what this conversation has come to, then I will stop. :) > > > Seem to sell, so there seem to be quite a few people who do not need > > > then newest possible. > > > > You clearly don't understand the FPGA market. > > I expect that Xilinx does understand it. They launched Spartan-II. I > will take their estimate over yours. You don't understand that I am agreeing with Xilinx. You are saying you want to use second level chips and by the time you have support for SpartanII it will be a second level chip. > > Yes, you are not an FPGA designer. You are on the fringe and you can > > use whatever you want. But this discussion was about the viability of > > open source tools and I think you will still find that they will not be > > well received by the FPGA design community. > > For me it is, and has allways been, about making them, and those > people I know who intend to use them. It you were labouring under > the impression that I intended to take over the market, then you were > reading my stuff wrong. No, but you have been saying that open source tools will become "better" than X or A tools. I don't agree that this will ever happen. > Given that they put out Webpack (and Alteras counterpart) for free, I > doubt they will feel any financial impact. Not if the open source tools are not widely used. Webpack is an introductory tool. If you are doing a significant design you won't want to work with limited and "crippled" tools. You will pay for them, that is, assuming that you are a company with a financial interest in the result. > > have said that they feel they have to provide support to anyone using > > their chips regardless of the tools they are using. > > Simply point out, that it is not out tool - no support - come back > if problem also happens with our official tool. Open source users > understand this. I don't know what this means. > > > The bitstream is the target. Back end makes that. From there on to > > > the front is ever increasing comfort. > > > > What will you feed into the backend? Output from the X or A front end? > > At present just interest to feed in my own simple language. May add > XDL if that is sufficiently interesting. > > > > > > Huh? I never said "all" CPUs, nor did I say all FPGAs. I clearly > > > > > stated 2 markets, "mass" and "specialist". > > > > > > > > What is your point? NO ONE can make a Xilinx compatible FPGA except > > > > Xilinx. NO ONE can make an Altera FPGA except Altera... > > > > > > I have my doubts. Where there is a will (enough money) competitors > > > will appear. > > > > You don't understand patent law, copyright and the economics of chip > > design and manufacture. > > You seem to be good at missestimating. I actually know law quite > well. To the extent that I am usually the persone everyone around here > ask for legal advise. Most likely due to me having actually read the > relevant law texts. If you feel that anyone can make compatible, viable FPGAs then you don't understand the law or the technology. There are simply too many barriers. Instead of playing word games, perhaps you can tell us *how* this will happen. > > How could anyone make a bitstream compatible > > FPGA? Can you explain how they would get around the legal IP issues? > > As I said: worst case get an license, in absolute worst case by > tripping up one of the existing players (if they blankly refuse). IP > law can be very interesting in that respect. > > Also anyone with enough financial interest can actually take an patent > to court and have it declared irrelevant on an whole range of issues. > It takes time and cost. But if enough profit are waiting, things like > that happen. Where do open source advocates get the financial backing??? X and A regularly fight over patents. They spend tons of money on this because they know it is what they have to do. Then they settle down and agree to cooperate. But if you don't *have* IP, how will you bargan with them? > Lesser case: You do know, that nearly all the fundamental patents in > FPGAs appeared around/pre 1985 (XC2000) and are now nearing their 17 > year, and so at end of life? Give a few years (needed for any hypothetical > bit-compatible scenario that makes cloning interesting anyway), and > quite a lot of them will be gone. > > Don't forget that then the only patents remaining are detail patents, > i.e. on the actual implementation. And that can be varied, without > losing bit compatibility. The situation is getting simpler the longer > time goes. That is the part I don't agree with. But I will let you show us. > Also you may want to take into account, that Altera managed to > survive Xilinxes patents, despite starting when they Xilinx had > maximal protection, and with Altera an latecomer. Any new competitor > has an easier situation. > > And an further scenario: assume bit compatible becomes important. > Either X or A is the winner in becoming the standard. How long do you > think will the other of the 2 look at declining sales, until they > clone? And we already know that a patent battle between them 2 ends in > stalemate. I disagree that a newcomer *now* has an easier time of it. Now you have not only X to deal with, you have the X&A cartel. They have a vested interest in keeping others out. They are now sharing more patents than ever before because each one has IP that the other wants. They don't need anything from others. > The short conclusion: IP law is in no way the "no chance" you seem to > regard it as. In particular when one has got enough money to run > through an dedicated battle. Well, then show us the money :) > > > > Just ask > > > > Clearlogic. :) > > > > > > AFAIK, they did not make FPGAs. They made ASICs that were layouted > > > automatically from Altera bitstreams. And it was not their ASICs that > > > got them into trouble, but rather that every single use of their > > > technology being helping Altera software licensees break the license. > > > > You misunderstand. The did nothing to "help break the license" other > > than to use the bitstream that came from an Altera tool. > > And that is exactly the entire meaning of "help break the license". > Offering an service that is auxillary to an crime, without any other > legal use for that service. Look up "contributary infringement" if you > want an interesting read. I understand the legal concept here very > well, having read quite a bit on the Napster/Kazaa/etc cases and the > deCSS/2600/websites cases, and the argumentation against them. But you make a point that has nothing to do with the discussion. We are talking about making chips. > > Likewise the > > innards of an FPGA are patented and otherwise protected IP. If you try > > to make an FPGA that is bitstream compatible you will either violate > > patents or end up with a very unworkable chip design or both. > > You can get around an patent. Altera survived Xilinxes ones. AMD has > wrung patents off of Intel, by tripping them over other stuff. Via has > stopped Intel attacks by tripping them up. Ask an good IP lawyer about > all the possibilities. IP law is not the clear "you lose" that you > believe it to be. > > In fact the very name IP is an error, they are no property, but rather > privileges, granted for very specific terms. And many patents do not > fit those terms, and only survive because being not challenged, because > fighting them is not profitable. Add an good slice of potential profit > and the overturning starts. Who is going to go up against X and A over these patents? Who has this money? > > > So they are not particularly a good example for "cloning not possible". > > > > > > In fact in an hypothetical world with open source (no-Altera) tools, > > > user using them could develop on Altera and then manufacture on > > > Clearlogic, and those would not be violation licences, and so there > > > would be an non-infringing use for Clearlogic -> Altera loses case. > > > > Yes, but that is not an FPGA is it? The point is that Altera felt a > > threat and used their IP to shut them down. > > The point is that they only just managed. That IP is not the surefire > "end of competition" you seem to regard it as. You say they "just managed" but Clearpoint was not making FPGAs were they? So how is their case relevant? > > o you know > > about the student who wrote an HDL version of an ARM processor? I don't > > remember the name, but he pulled it from the web after the ARM people > > had a chat with him. > > Yes, I know the case. I also know that IP owners (and any other > financially strong party) can push financially weak opponents aside, > ever if the patent would not hold up. > > AFAIK ARMs patent claim was not that strong, they had luck that their > opponent was weak or possibly simply not interested (better stuff to > do than fight[1]) and caved in. MIPS had a stronger case against a > cloner, but their patent is also near/in EOL. If the ARM case is not strong, then why does everyone including the behemoth Intel license rather than "break" the patents? > [1] A motive I know well, having also given up against a weak trumped > up claim (of violating data protection laws), because the cost (in > time, the case was classic multiple appeals type stuff, with an good > chance of going right up to the supreme court) of defending was larger > than the loss of giving in. > > And yes, that is an other reason why I know quite a lot about law. > > > > Sockets can not be copyrighted, can not be patented, can not be > > > trademarked, so no protection. Signaling protocols can be patented, > > > that is what Intel then did on PentiumII. > > > > > > Same issue that they had with numbers not being trademarkable, so AMD > > > copied the 486 name with impunity. So Intel renamed the becomeing 586 > > > into Pentium, to prevent AMD being able to copy it. > > > > So you *do* understand that companies will protect their IP!!! Glad you > > could grasp this concept. > > I understand IP law very well. Glad that you have noticed it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 48402
Dave, please consider uploading your test bench to OpenCores (www.opencores.org). Thats a depository for Open/Free IP Cores and everything that goes along with them ... Best Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores: http://www.asics.ws/free_ip.shtml Dave Nelson <pci_model@nelsim.com> wrote in message news:<pan.2002.10.15.17.15.43.388152.4631@nelsim.com>... > I have a PCI model for verilog simulators which includes: > arbiter > master(s) > slave(s) > monitor with GUI > > It is designed to interface with PCI designs to exercise them and display > activity and protocol errors. > > If there is interest, I will release this as open-source software for > free download. > > Requirements: Unix/Linux/Solaris system with gcc compiler > Verilog simulator with PLI interface > > Please email me if you would find this useful. > > Dave Nelson > pci_model@nelsim.comArticle: 48403
>> If you can't take advantage of multi-threading then you wouldn't >> be able to use multi-processing either. >Is that true? >Don't you need to actually have two threads in order to use the multi-threading >but multiprocessor parallelism can be more fine grain. From the software view, a multi-threaded CPU is just like an SMP. It's just time multiplexed rather than replicated in space. >ex. A code where the inner loop has a function call where some > operations take place. > Is it easier to thread that function or just place the function > in another processor? There is a separate issue of whether you are doing fine grained (dozen instructions?) or course grained (millisecond) switching. Executing a function on another processor/thread doesn't do any good unless you have something else to do while it runs. Perhaps the sort of example you are looking for on fine grained work is fortran loops. If you are going around a loop 100 times and you have 2 processors, you could get one to do the odd slots and let the other do the even slots. Lots of compiler work to find where you can do it. It obviously doesn't work (at least not in the simple minded way) if one iteration refers to the results of the previous iteration. The classic coarse grained example is reading your mail while PAR or simulation is crunching away on the other CPU. > Isn't it how data is move between two processor/threads that is > more crucial? It's not a big deal on coarse grained work since it doesn't happen very often. For fine grained work the details (hardware and software) are probably more important than we can evaluate without a solid design to discuss. The straw man is that all the data goes through main memory to get from one CPU to the other one, but since that probably hits in the cache it shouldn't take long. Adding hacks to copy registers from the other (logical) CPU might be a significant help. I'm not really a wizard on this stuff. There are probably many relevant PhD thesis out there. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48404
The DLL's within the Spartan-IIE can only multiply an incoming clock frequency by two, but can divide it by 1.5, 2, 2.5, 3, 4, 5, 8, and 16. You could create a 120MHz clock externally, drive it into the FPGA, have the FPGA create its internal 120MHz, 40MHz, and 24MHz, and then feed the 24MHz out (from the FPGA) to the other IC. You should read-up on the Xilinx DLL's. They're pretty flexible. If you ever move to the Virtex-II family, you'll love their DCM's. DCM's can multiply frequency (even fractionally), adjust phase-shift, and they'll do your laundry, too. Bob "Jamie Morken" <jmorken@shaw.ca> wrote in message news:INor9.524711$v53.21823110@news3.calgary.shaw.ca... > Hi, > > I'm working on a board that requires a 120MHz clock, a 24Mhz clock and a > 40MHz clock. > The board has a SpartanIIE device on it. I've never used a PLL (which the > Spartan device has) > so I'm unsure if I should use multiple crystals or if I can use the PLL to > give the needed frequencies. > > One of the IC's requires 24 MHz so would it be possible to use a 24MHz > crystal for this IC and also > feed the output to the FPGA to generate the 40 and 120 MHz clocks? > > cheers, > Jamie Morken > > >Article: 48405
In article <uqshqkrgkhjb48@corp.supernews.com>, Hal Murray <hmurray@suespammers.org> wrote: >>Don't you need to actually have two threads in order to use the >>multi-threading but multiprocessor parallelism can be more fine >>grain. >From the software view, a multi-threaded CPU is just like an SMP. >It's just time multiplexed rather than replicated in space. The big difference is the interfearance effects. On a shared memory SMP, if the two processes share a common memory working set, you have coherancy misses where writes cause ping-ponging of memory ownership and generally reduce memory performance considerably. In a multithreaded architecture with a cache, the misses occur for the exact opposite reason: the two tasks use different working sets, thrashing the cache. In the P4 style, there is yet another interferance effect: the two threads, when competing for the same functional units, will slow each other down. >The classic coarse grained example is reading your mail while >PAR or simulation is crunching away on the other CPU. Or simply having a separate thread for the kernel on a web server. >> Isn't it how data is move between two processor/threads that is >> more crucial? > >It's not a big deal on coarse grained work since it doesn't happen >very often. > >For fine grained work the details (hardware and software) are probably >more important than we can evaluate without a solid design to discuss. >The straw man is that all the data goes through main memory to >get from one CPU to the other one, but since that probably hits >in the cache it shouldn't take long. Adding hacks to copy >registers from the other (logical) CPU might be a significant >help. Only by a couple of cycles, but it IS useful, some of teh RAW work has benefitted greatly from the fast move between processors. >I'm not really a wizard on this stuff. There are probably >many relevant PhD thesis out there. Although alot can be answtered by just thinking about things. I would like to see an actual study of where the P4 multithreading has interferance effects. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48406
That is exactly what I was trying to get at.
Jan Gray wrote:
> See also http://www.fpgacpu.org/log/nov01.html#011122:
>
> "One can also build a simple barrel processor (say 4 threads (slots) x 32
> regs = 128 entries of 32-bits = 2 16-bit ports on a single 256x16 BRAM,
> tripled cycled, or two BRAMs double cycled) and switch threads on each
> cycle. Then you can have a 4-deep pipeline without need for any result
> forwarding muxes (by the time you read an operand on thread[i], you have
> already retired that threads' previous result to the register file).
>
> This seems to me to be a perfectly simple and practical basis to issue
> instructions faster than the ALU + result forwarding mux + operand register
> recurrence critical path. Unfortunately single-thread performance is not so
> hot but in workloads such as a "network processing", who cares?
>
> This idea was taken to sublime levels in the 20-stage pipelined 5-threaded 1
> GHz MicroUnity MediaProcessor (which would have needed some result
> forwarding, but not 18 stages worth)."
>
> Jan Gray, Gray Research LLC
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48407
In article <INor9.524711$v53.21823110@news3.calgary.shaw.ca>, "Jamie
Morken" <jmorken@shaw.ca> wrote:
> Hi,
>
> I'm working on a board that requires a 120MHz clock, a 24Mhz clock and a
> 40MHz clock.
> The board has a SpartanIIE device on it. I've never used a PLL (which the
> Spartan device has)
> so I'm unsure if I should use multiple crystals or if I can use the PLL to
> give the needed frequencies.
>
> One of the IC's requires 24 MHz so would it be possible to use a 24MHz
> crystal for this IC and also
> feed the output to the FPGA to generate the 40 and 120 MHz clocks?
>
> cheers,
> Jamie Morken
Your description of the problem is very open ended.
Starting with a 120MHz oscillator and dividing down sounds very easy and
would have very low jitter.
Multiplying up is OK, but using a PLL would add jitter. I presume a DLL
would do so as well. You should check the datasheet for the SpartanIIE,
to see if it uses a PLL or DLL and then study up on the jitter
characteristics on whatever you find.
What you are doing is called "clock architecture" and is a separate concern
for each digital design you do. Some questions that come to my mind are:
1) Do the devices driven by these three clocks talk to each other
synchronously ? You may want a preferred phase relationship between
the clocks, if this is the case. For example, if you divide the 120MHz
clock, to make the other two clocks, those two clocks will always
be later in time, by the CLK-Q of the flip-flops doing the dividing.
If you use a PLL to make the 120MHz from one of the other clocks, the
edges of the 120MHz will probably be +/- 1 ns with respect to the
source clock, so your timing will have to consider the plus and the
minus cases. Meeting hold time can be impossible, depending on your
choice.
2) Does your design time an outgoing I/O interface ? If you are driving
an optical link, for example, there could be tight specs on jitter.
Generally, this means no PLLs between the oscillator and the optical
device.
For simple digital devices, the maximum value of the jitter comes
out of your clock period timing budget.
3) Do any of the devices have clock duty cycle requirements ? If one
of your chips has a 45/55 maximum duty cycle requirement, you would
pretty well have to get the clock directly from an oscillator. Most
simple buffer chips have too much difference between Tplh and
Tphl, to allow passing a clock without disturbing the duty cycle.
4) Is this a prototype or a final, cost reduced, high volume product.
For lab use, having separate oscillators makes retrofitting easy.
With the careful use of 0603 series resistors, you can even
place more oscillators than you need, and then do a stocklist
change, to change the way the clocking is done.
_______
| |
| Src |---- Series Resistor --- --------
| #1 | | |
|------| | | Digital
|----------------| Device
_______ | |
| | | |--------
| Src |---- Series Resistor ---
| #2 |
|------|
Note: Design the copper trace at the junction, so that when one
resistor is removed, there is no stub left to cause a reflection.
The value of the remaining resistor should be selected to match
the impedance of the copper trace.
You should also think about signal integrity. If cost is no object,
make copies of the clock with a Cypress CY2308. then do a resistor
series damping, point to point interface to each clock destination.
I don't recommend doing a daisy chain, multi-drop clock line, unless
you have done an analog simulation to prove it meets specs.
Also, at 120MHz, the propagation delay of the data signals is
significant in the timing budget. You will find that high frequency
design is iterative, as placing two 120MHz parts too far away from one
another will break the timing, and perhaps require revisiting how
you do the clocking.
Paul
Article: 48408Multi-threaded = Is this a barrel processor ? If this is a cpu implemented in an FPGA the need is probably not so much for performance (which markets well 'gee whiz factor') but rather for functionality in a small size. I've tried taking the "hands on approach" experimenting with several design options and come to the following conclusions: - designing a processor to run in an FPGA is different than designing the processor for custom logic. Methods used to gain performance in processors designed for custom logic simply don't work well in an FPGA. In an FPGA twice as big = half as fast, which is not the case for a processor built out of custom logic. - it's probably not a good idea to build an FPGA processor with more than a three stage pipeline, all the additional routing, register bypass multiplexing, and control logic makes the design bigger and consequently slower. There is no real difference in performance for a more complex design, it is simply more complicated. - it is possible to build a really fast barrel cpu, but most of the performance gain is lost trying to interface it to a memory system - assuming that the processor has to be interfaced to *external* memory (a requirement of many real world apps), this is a significant design consideration. The memory space and bandwidth has to be shared with the FPGA application in many circumstances. This bandwidth limit puts a limit on the performance needed of the FPGA cpu. - using BRAM's for caches is much slower than using them as raw ram resources, they were not designed to be used as caches. They lack cache tag comparators, and a way to clear the cache or cache lines in a simple manner. They could also use more ports. Recognizing that this is not likely to change also puts a limit on the performance. With a little bit of work, I can make a cpu much faster than the cache, but there is no point in doing this. - the design of the whole system is important. It is way too easy to get caught up in the process of designing a really fast component and then realize that the rest of the system can't keep up with it anyway. - if a high performance processor is required, use a real one. Don't try to build one in an FPGA because this is not their strongpoint. Sample Stats (SpartanII - slowest speed grade) Sparrow2 processor (version1 32 bits, 32 reg ) - no pipeline, executes most instructions as one single long instruction cycle. Is simple, but has a lot of functionality including 32 bit barrel shifter and hardware multiply. Runs at 25 MHz (same speed as external memory) Sparrow2 processor (version2) - three stage pipeline with register bypassing - same functionality as above. Runs at 40+MHz using an instruction cache. The design is significantly larger and more complex however. Which one is better ? Rob BTW: I have a relatively small and fast 6502 compatible core available at www.birdcomputer.ca (lacks docs yet - on the way)Article: 48409
In article <ampl73$6kt$1@d03.completel.fr>, "Jérémie WEBER"
<j.weber@digigram.com> wrote:
> I have a problem with a design ( 200k spartan II E ) that fail when an
> Electrostatic discharge occurs.
>
> I presume that some flip-flop are reseted but not all. That means that my
> design fail and is unstable.
>
> I have set some hardware things to avoid a large part of this problems but
> when it occurs I always fail.
>
> Have you got any Idea to secure the FPGA design itself ?
>
> Regards.
>
> Jérémie WEBER
ESD can affect a design directly, by changing a rail voltage etc., or it
can work by inducing a potential in adjacent signal leads.
In board design, you have to worry about EMI and susceptability. EMI is
the RF emissions that come from the signals on the board, while
susceptability is the affect on your circuit, that someone elses
RF emissions make on you.
Emissions and susceptability go hand in hand -- techniques to reduce one
will reduce the other as well.
One thing that helps, on a multi-layer board, is to copper flood-fill the
top and bottom of the board with ground planes. If you can afford the
routing resources, don't do any signal routing on the top and bottom of
the board. Unfortunately, this will force you to use a six or eight layer
board.
Once you do this, I think you will find that the tiny apertures around
the vias in the board won't let any significant RF inside the board or
out.
ESD is a microsecond phenomenon, with nanosecond harmonics. Reducing the
susceptability of the board to external emissions, will reduce the
coupling from an ESD discharge. Using ground planes and removing any
antennas from the surface of your baord, will go a long way to fixing
the ESD problem.
A harder thing to fix is conducted ESD. Ideally, put no connectors
on the faceplate of your card and make the front of the faceplate
out of plastic, so the ESD cannot discharge into your board. (i.e.
Use a plastic fascia over a metal plate, as the metal plate keeps your
remaining emissions from getting out!) If you must have a connector,
then you are probably stuck with the need to run the connector shroud
ground to the frame ground in the equipment. FInd a way to route this
ground as far away as possible from digital ground or from
data signals.
Also, now that you know you have a problem, try placing an intervening
buffer chip between the Spartan and any external connector pins. Or,
if that isn't possible, try placing clamp diodes on the external
connector signals to ground, next to the connector. (These techniques
might or might not help - the ground plane should make a major
difference.)
At some point, you have to stop improvements of this type. In your
equipment spec, it should state something like -
ESD -
2Kv discharge - no circuit disturbance or permanent damage
5Kv discharge - circuit disturbance could happen
15Kv discharge - permanent damage will result
Testing for ESD is done with a "human body model" of something like
300pF and 2K ohms series resistance. You can buy testers that have
these components in the probe tip, to allow controlled testing of
your finished board with kilovolt zaps.
No board is completely immune to ESD.
Paul
Article: 48410Ralph, have a look at our Spartan II Eval Board. Prices start at 99.-EUR See: http://www.trenz-electronic.de/prod/proden6.htm Key Features: - 200k/50k gate Spartan-II FPGA - Download cable included - ISE Webpack included - Bundles with Ram and Flash available best regards Thorsten Ralph Mason schrieb: > Hi, > A am wanting to learn verilog (it seems easier that VHDL) and play with an > FPGA ( I quite like the idea if designing my own CPU, make dram controllers > etc) I am looking for an easy low cost start. I have written a little VHDL > before and done GALS etc. > > Currently I have my eye on the XSA-50 from Xcess because it has a fpga and a > cpld and ram and flash > ( http://xess.com/prod027.php3) - What can you fit in a 50k gat FPGA - A > processor, memory controller, video and io support? > > A am also interested in FPSLIC but I understand you can only use the tools > for 4 months and then they cost many $$$$ after that > > Are there any other boards that anyone can suggest that are reasonably > prices and include tools. Does anyone have any comments on either of these. > > Thanks for any advice > Ralph > > > >Article: 48411
Josh, you can buy the manuals from Altera. The ordering code is PL-MANUAL and I think they sell for US-$ 89,-. Up to now there's a PDF version of the Getting Started manual but no PDF for the AHDL manual. It would be easier however to just get a free MAX+plus II Baseline software from Altera's website or the Altera Digitial Library CD. The on-line help has all the AHDL information from the manual. You can install, start and use the on-line help without licensing the MAX+plus II software. Hope this helps Wolfgang http://www.elca.de "josh forgione" <Joshua.Forgione@gsfc.nasa.gov> schrieb im Newsbeitrag news:aoh97e$n3t$1@skates.gsfc.nasa.gov... > Good Morning. > > I have a need to modify an FPGA design that was created in Altera HDL. > Though it is similar to VHDL and Verilog, I would like to get my hands on a > command reference or users' manual. Does anyone know where I could get a > copy? > > You would think Altera would be the obvious answer, but they have not been > much help... > > Thanks. > > Josh > >Article: 48412
rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0210161251.7554ff96@posting.google.com>... > Hello all, > > I've perused various Xilinx/Altera threads in this > newsgroup with due interest, and would now like to > invite comments and thoughts on the situation I > find myself in: > > I've done a modest amount of design recently with > Xilinx and am overall comfortable with the design > flow, assorted support, and achievable performance. > Recently a new application has come up requiring more > horsepower (a PCI accelerator card for some compute- > intensive portions of an imaging application). > > To make this fly, I need for three things to come > together: (1) devices (2) tools (3) a development > board. > > In a nutshell the Altera offering is tempting... > > (1) Devices: The Stratix prices I'm being offered are > aggressively low. I'm comparing slow speed grades of > EP1S10/20 with 2V1000/2000 and I get the feeling that > Stratix has the edge on raw speed and on DSP block > capability. Things like distributed memory and SRL > that are strengths of Virtex-2 don't seem too important > for this application. > > (2) Tools: I went to a Quartus seminar. Quartus seems > learnable, no huge leaps for an ISE user. Overall the > Altera tools cost considerably less too, when you look > at the packages available and the implications of Xilinx' > Time-Based License. I'm unsure about the level of > support and bugginess of Quartus, but then reports of > ISE 5.1i aren't exactly flattering. > > (3) With some difficulty I have identified suitable > development boards (PCI + enough off-chip memory) for > both Stratix and Virtex-II, as it happens none of them are > available today. So that's a wash. > > Anyway, I would be eager to hear from other folks re: wisdom > of your experience, or re: pitfalls for the unwary, or if > you've been looking at the same kind of decision... > > Thanks, > -rajeev- Interesting point about the Altera pricing. My company has traditionally always used Xilinx parts - and we have no complaints. Recently we spoke with Altera, and their pricing was far better than what Xilinx would offer for an equivalent part. But, typically, we have no time to invest in changing to an Altera part - so we end up staying with Xilinx because we know the parts - and pay more for them. I feel that maybe Xilinx trade on this point of view - and this allows them to keep their prices high. Thoughts ?Article: 48413
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<aok4nl$mrukm$1@ID-84877.news.dfncis.de>... > "Itsaso Zuazua" <izuazua@ikerlan.es> schrieb im Newsbeitrag > news:709383e9.0210160719.72bc0dfb@posting.google.com... > > Hi, > > > > I would like to know if I need any terminator technology for Altera`s > > APEX 20KE I/O pins. I have read a lot about this feature for Stratix > > devices, but nothing for APEX devices. I think that the terminator > > technology will depend on the standard I/O used. For more information > > I add that I'm using LVTTL for all the pins. HELP, please! > > It all depends on how fast you signals are switching and how long the > connections to the other ICs are. > Fast switching doesnt always mean high frequency, fast switching means > rise/fall time of you signals. In Xilinx devices, you can adjust the driver > stength and speed to different levels (2,4,6..24 mA, Slow/fast). I dont know > if this is possible in APEX20K.Then the lenght of the traces comes into > play. If the lenght of the trace is greater than 1/6 of the propagation time > of a rising/falling edge (whichever is faster), than you better go for > termination. > > An example. Propagation speed on a trace is ~20cm/ns. So if you rise/fall > times are 2ns (=40cm), so every trace longer than 40/6 = ~6.5 cm better gets > some termination. Thanks a lot Falk!!!Article: 48414
"Theron Hicks" <hicksthe@egr.msu.edu> writes: > "Martin Thompson" <martin.j.thompson@trw.com> wrote in message > > So... is there a market for someone to supply V-II devices mounted on > > a "bodge-board" with a high-density connector? (Can't fix number 2) > > though :-) > > > > Anyone else think this might be useful? > > > > Cheers, > > Martin > > > > -- > > martin.j.thompson@trw.com > > TRW Conekt, Solihull, UK > > http://www.trw.com/conekt > > I would think that, even in a simple I/O design like I had proposed, the > EMI/EMC and signal integrity problems would be horrid on that type of > design. Some of the issues could be resolved with a place for an on board > clock connector (SMA, SMB, MCX etc.). Perhaps two would be required to > allow for diferential clock schemes. > > Virtex-II has lots of configurability in its IOs, so as long as you don't want to do 150MHz external IO, you would probably be alright. Some simulation could prove it. Using the stacking connectors that eg. Samtec produce with a ground plane should help in keeping the problem well-defined at least. I don't think you could ever use such a kluge for a high-performance IO system, but it would be workable for many of the hobby projects that people seem to want to do if only they didn't have to deal with BGAs! Cheers, Maritn -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 48415
Hello
I did that locking of pin
But Implementation could not be done.
I have attached the map report with this mail.
Illegal physical site was the message.
But pin#77 is a valid GCLK Pin for the Device(SEE MAP Report for details)
Reply
Sanjay
Here is the Map report:
Release 4.2i - Map E.35
Xilinx Mapping Report File for Design 'reg_4'
Design Information
------------------
Command Line : map -p xc2s200-pq208-5 -cm area -k 4 -c 100 -tx off
reg_4.ngd
Target Device : x2s200
Target Package : pq208
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.58 $
Mapped Date : Thu Oct 10 00:32:31 2002
Design Summary
--------------
Number of errors : 1
Number of warnings : 1
Section 1 - Errors
------------------
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "clk" (Pad Signal = clk)
BUF symbol "clk_IBUF" (Output Signal = clk_IBUF)
Each of the following constraints specifies an illegal physical site for
a
component of type IOB:
Symbol "clk" (LOC=P77)
Please correct the constraints accordingly
"S Embree" <sre3@duke.edu> wrote in message news:ee79989.1@WebX.sUN8CHnE...
> If you want to use an external clock, you should use one of the dedicated
global clock pins (GCK0, GCK1, etc.). Determine which GCK pin you want to
use and then lock your system clock to that pin using the .UCF file.
Article: 48416I've just installed the immense ocean of bits that is FPGA software, and I'm having problems with Java in Internet Explorer. For example if I go to Kelkoo (a UK price checking site): http://uk.kelkoo.com/ and click on their books section: http://uk.kelkoo.com/b/a/c_100801_books.html I get a page of Java/Javascript errors. I didn't get these before installing the FPGA tools. PCs here without Xilinx tools are fine. The Xilinx tools install Sun's Java Runtime Environment 1.4.0 (it needs it for CoreGen, amongst other things). You can see the JRE gubbins in C:\Xilinx\java\. It seems this JRE has displaced the Microsoft Java VM in IE. How can I restore the Microsoft Java VM? Has anyone else seen this problem? No reference to this on the Xilinx website The tools I have loaded are: Mentor Graphics HDL Designer 2002.1a Leonardo Spectrum 2002c.36 Modelsim 5.6d Xilinx Project Navigator 5.1.01.i I'm running Windows 2000 Professional. I know there *used* to be problems with Xilinx tools last year, but I thought they had been fixed?? -- JP Nicholls / jpnicholls@pwav.com Powerwave UK Ltd Embassy House Queen's Avenue Bristol, BS8 1SB United Kingdom Tel: +44 (0)117 910 5600 Fax: +44 (0)117 910 5601 Web: http://www.powerwave.com ___________________________________ The information in this communication and any attached documents contains confidential information of Powerwave Technologies, Inc. If you are not the intended recipient, or an agent responsible for delivering it to the intended recipient, you may not read, copy, distribute or use this information. If you have received this transmission in error, please notify the sender immediately by reply e-mail and then delete all electronic copies and destroy any hard copies.Article: 48417
Hi, Nicholas C. Weaver wrote: > In article <3DADAAB7.E96D53F2@Xilinx.com>, > Goran Bilski <Goran.Bilski@Xilinx.com> wrote: > > >>You can't just double the number of pipestage for a processor without >>major impacts. For streaming pipeline which hardware pipelines are I >>agree but for processor that can't be done. > > > Uhh, yes it can. > > Double all the pipeline stages, double the register file, rebalance > the delays now that you have more pipelining, and out drops a 2-thread > multithreaded architecture. Each single thread now runs slower, but > aggregate throughput (sum of the two threads) is increased. > > It is so obvious yet unintuitive that nobody has actually DONE it > before. :) I think there has been a lot of research done in this field. Perhaps not for FPGAs as a target but I remember reading some research papers that talked about different kinds of hardware support for multithreading. E.g., one paper talked about a design with a very deep pipeline (I think it had more than 10 stages; unfortunately, I forgot paper title and author names). This architecture were capable of running N (N = number of stages) threads in parallel. However, each thread submitted only one instruction every N-th cycle. Using this approach there is no need for bypassing (no raw hazards), there are no control hazards (ok, if memory is fast enough), ... In fact, each thread submits a new instruction AFTER its previous instruction reached the end of the pipeline. As a result, each thread executes at a 1/N th of the clock rate, but without any problems caused by raw or control hazards. Further, N threads are running in parallel. For this architecture the pipeline register are independent from the number of threads. However, each threads needs its own register set (i.e., total register are N * register set per thread). This can be handled more efficiently using register renaming... I am not sure, but this approach sounds similar to what I've read in this thread (?) -- EdwinArticle: 48418
Hi all, I am new here... I was running an extest in x2s100(vq64) and when I update data registers, appropriate pins goes down. Now I am trying to run an extest in x2s150(pq208) and as soon as I update instruction register (with extest instruction) all pin outputs fall down to LOW level. I expect that all pins will be in HIGH level (as it was in x2s100). By changing of data register nothing happens. Where could be a problem? Please help. Petr P.Article: 48419
Leon Heller wrote: > > "Kolja Sulimma" <kolja@bnl.gov> wrote in message > news:25c81abf.0210151403.1e436c4a@posting.google.com... > > Did you address the problems that are described in this thread: > > > > > http://groups.google.de/groups?hl=de&lr=&ie=UTF-8&selm=25c81abf.0210081329.e > d45bc4%40posting.google.com > > > > The are also a couple of older threads on this topic. > > Thanks, Kolja. I remember that thread, now you've mentioned it. I just > copied the Xilinx schematic, I'll bear it in mind if there are problems. The > chips can be socketed, so different ones could be tried, and it would be > easy to modify the PCB. I've never had any problems with the standard Xilinx > Cable III, with my FPGA and CPLD hardware. Perhaps I should open it up, to > check if it matches the schematic. > > Interestingly, the Altera ByteBlaster uses a 74HC244 buffer, does not use > any capacitors or diodes and has 2K2 pull-ups on all inputs. I also made my > own version of it as Altera charges a lot more for their adaptor than > Xilinx. The real byteblaster has a bypass capacitor. It's not shown on the schematic.Article: 48420
"Russell" <rjshaw@iprimus.com.au> wrote in message news:3DAE9B39.40E5EC1F@iprimus.com.au... > > The real byteblaster has a bypass capacitor. It's not shown > on the schematic. I put one on mine anyway. Force of habit. 8-) Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48421
Hi all I'm designing LCD Controller using ALTERA Quartus Ver2.1. I want to assign output FF signal to IOE register by Quartus Ver2.1. However, I don't know how to assign using this software.Article: 48422
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:Z_or9.8019$Os6.1108829@news.xtra.co.nz... > Hi, > A am wanting to learn verilog (it seems easier that VHDL) and play with an > FPGA ( I quite like the idea if designing my own CPU, make dram controllers > etc) I am looking for an easy low cost start. I have written a little VHDL > before and done GALS etc. > > Currently I have my eye on the XSA-50 from Xcess because it has a fpga and a > cpld and ram and flash > ( http://xess.com/prod027.php3) - What can you fit in a 50k gat FPGA - A > processor, memory controller, video and io support? > > A am also interested in FPSLIC but I understand you can only use the tools > for 4 months and then they cost many $$$$ after that > > Are there any other boards that anyone can suggest that are reasonably > prices and include tools. Does anyone have any comments on either of these. If you use the older chips in PLCC packages like the smaller Xilinx Spartan/SpartanXL and Altera Flex 10K devices, you can build your own hardware very cheaply, using ordinary prototyping techniques, or make your own PCBs. They probably won't work reliably at 100 MHz, but are quite adequate for hobbyists. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48423
Hello I'm looking for information about pins in J1 and J2 conectors but FOR REVISION B. (5 pushbutton) Do you have it? This board is for Digilab II MarekArticle: 48424
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3DADEC2C.59DF33D0@xilinx.com>... > Marc (and all), > > Peter wandered by a few moments ago, and asked me why I was so against pq packages? > > I'm not, honestly! > > The Spartan family always has small and inexpensive packages for their parts. Howdy Austin, You're points are all valid, but I think the point of the two guys that originated this typic was that there are a few (perhaps too few?) customers that need some of the features of the V-II , but for some reason, feel they can't move to a BGA. That means they are stuck waiting for the top-of-the-line features to filter down to the Spartan family in a year or three. > Well, as it so happens, most places close to big technology centers have assembly services > just for prototyping! And it isn't that expensive! In fact, it costs a lot less than having > all of the stuff and people yourself, and not using it (which is what most prototyping > consists of: 5% building, and 95% debugging what was built). They do rework too. > > So ask around. Large assembly services sometimes have a small proto line just for this, and > in areas where there is a lot more business, there are small specialty shops that just do > proto runs. > > And I am talking here about five, two, and sometimes even one board for a reasonable price. In general, I agree with you that the cost of having a board assembled is rather inexpensive (probably less expensive than the original posters realize), especially if they were to include the cost of their own time assembling it rather than paying someone else. But you have to admit there are a few downsides: 1. Turn-around time 2. Correct assembly (even with perfect drawings, from time to time we'll have a few boards with assembly problem). Basicly, nobody is going to be as careful as you in assembling your boards. And if it *MUST* be correct the first time around (due to schedule, or can't afford to do it a second time), who are you going to trust? 3. Location (you point out that contract manufacturing/assembly works best when you're close to technology centers. If I'm not mistaken, at least one of the original posters was in Europe - where I'd expect contract manufacturing/assembly to cost considerably more than in the USA). 4. Cost Any one of these items is probably not overwhelming, but if the original posters had to face two or three of them, I wouldn't blame them for wanting to do the assembly themselves. Our boards are so complex, we don't have a choice but to contract it out. > Of course, you will have to learn how to assemble the kit of parts, and identify them, and > have a good schematic, and a good bill of materials, and have a good assembly drawing. All of > that you already have, right? My original response in this thread (about assembly and x-ray) was directed only at the other posters. We use contract manufacturing for everything, including reworking all but the simple packets. Our boards come back assembled and ready for testing (although they are habitually late by 3-5 days). This whole discussion is a really a product management discussion though (engineering could solve any of problems discussed in this thread). Is there enough PQFP volume to make it worth Xilinx's time to develop, document, make, stock, market, and sell that part? I'm guessing not (almost certainly based on customer survey), otherwise they would have already done it. Have fun, Marc
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