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You can read our WebPack tutorials at http://tutor.al-williams.com -- They are meant for CPLDs, but the design flow is pretty much the same and the tool interface is exactly the same, so you should have no trouble. Al Williams AWC http://www.al-williams.com k_guichard@hotmail.com (Kyle Guichard) wrote in message news:<dc00661e.0210171949.46c5fe86@posting.google.com>... > I am a student at SJSU working on my senior project. For this, I will > be creating an FPGA using Xilinx software, but I am really overwhelmed > with the ammount of information on how I can actually do this. > > Can anyone direct me to some good documentation on creating FPGA's > when I have the verilog/VHDL code? > > > thanks! > kyleArticle: 48501
"MikeJ" <pacman@fpgaarcade.com> schrieb im Newsbeitrag news:1034898996.97215.0@dyke.uk.clara.net... > More importantly you can play pacman and space invaders in a 300e (ok, > external program rom required) ! Should also work with a 200k part, if you move the char ROM also outside. Iam working on it. ;-) -- MfG FalkArticle: 48502
"Meg" <meghnaag7@hotmail.com> schrieb im Newsbeitrag news:2a1195bc.0210171814.1ad98bc6@posting.google.com... > hi > i am new to FPGAs. i want to run compression algorithms on virtex > xcv50 configuration file. i have consulted the xilinx app. notes as > well as other few websites. The xilinx website says the configuration > bits needed are 559,200bits (= 69,900 bytes) but at > fpgaconfigurator.com, it is mentioned tht 559,232 bits are needed. The > bit file generated by Xilinx tools has the size 69,967 bytes which is > 67 bytes more than specified by xilinx. I am really confused about > what's going on ?? The *-bit file contains also non-bitstream information. If you want the TRUE number of bytes, use *.mcs or *.hex (no binary format, but can e easy converted) -- MfG FalkArticle: 48503
>Is it simply a case of describing a series of registers and XOR's to fit my >polynomial? Depends. The simple description of a CRC is bit serial. That takes many clocks per word if you have a wide word. You can do N bits in parallel with a big cloud of XORs. If you are good at software, you might want to write some hack code to work out all the "details" of which way to shift and which way around the polynomial goes and things like that. A web search on software CRCs via table lookup might be interesting. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48504
1. The .bit file has a header.
http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm
2. The .bit file data is a series of frames that is interpreted by the FPGA.
Depending on contents of the FPGA, the exact number of frames can vary.
3. The .bit file compresses like binary data (about 50%). For example, I
have several .bit files concatenated together for 7530508 bytes. Using
gzip -9, this compresses to 4072712 bytes.
Alan Nishioka
alann@accom.com
meghnaag7@hotmail.com (Meg) wrote in message news:<2a1195bc.0210171814.1ad98bc6@posting.google.com>...
> hi
> i am new to FPGAs. i want to run compression algorithms on virtex
> xcv50 configuration file. i have consulted the xilinx app. notes as
> well as other few websites. The xilinx website says the configuration
> bits needed are 559,200bits (= 69,900 bytes) but at
> fpgaconfigurator.com, it is mentioned tht 559,232 bits are needed. The
> bit file generated by Xilinx tools has the size 69,967 bytes which is
> 67 bytes more than specified by xilinx. I am really confused about
> what's going on ??
>
> moeover from what i understand, xcv50 needs 15,876 32-bit words for
> CLBs, 780*2 for ram and 39 words for issuing commands. The sum of all
> these is less than the number of configuration bits required
> (559,232), So, how exactly is this figure calculated ??
>
> Meghna
Article: 48505In article <ur0eean4a0hgc1@corp.supernews.com>, Hal Murray <hmurray@suespammers.org> wrote: >>Is it simply a case of describing a series of registers and XOR's to fit my >>polynomial? > >Depends. > >The simple description of a CRC is bit serial. That takes many clocks >per word if you have a wide word. You can do N bits in parallel with >a big cloud of XORs. > >If you are good at software, you might want to write some hack code >to work out all the "details" of which way to shift and which way around >the polynomial goes and things like that. A web search on software >CRCs via table lookup might be interesting. Hell, the space is small enough that you can probbaly just given the CRC code, brute force the equation for 2 in //, use that to brute for the equations for 4 in //, etc. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48506
On 18 Oct 2002 09:42:09 -0700, Alan Nishioka <alann@accom.com> wrote:
>
>3. The .bit file compresses like binary data (about 50%). For example, I
> have several .bit files concatenated together for 7530508 bytes. Using
> gzip -9, this compresses to 4072712 bytes.
That very much depends on how much of the chip's logic is in use.
Unused bits are set to zero, which compress really well. ;-)
I find the gzip-compressed file size and the slice utilization
track pretty closely.
- Larry
Article: 48507Kevin I am new in PCI and PCIX design. I am going to design my own PCIX core, and this core has to be backward compatible with PCI. Right now I am thinking to start with PCI CORE and then upgrade to PCIX, I don't know how much work it is going to be. I am using Verilog, and am very intersted in starting with some kind of PCI core. Could you please kindly send the Xilinx verilog PCI core to me? my email address is: hxie168@hotmail.com You guys are great! I have learned a lot just by reading your messages. I appreciate your help. Best Regards! Huijun "Kevin Brace" <killspam4kevinbraceusenet@killspam4hotmail.com> wrote in message news:ahn2ha$9if$1@newsreader.mailgate.org... > > > Jeff Reeve wrote: > > > > I'm looking for a synthesizeable 32-bit 33MHz PCI Target only design to be > > placed into a FPGA or large CPLD. Minimal implementation is fine. Does > > anybody know if such a thing is available in VHDL or Verilog and is open > > sourced? I seem to recall Xilinx publishing a target only design quite some > > time ago but I can no longer find it on their web site. > > > > Any help is much apprecieated! > > Jeff > > > This is what you are probably talking about. > > ftp://ftp.xilinx.com/pub/applications/pci/ > ftp://ftp.xilinx.com/pub/applications/pci/00_index.htm > > > For some reason, a Verilog version of the reference design is missing, > but if you want it I can E-mail it to you (Some kind, long time Xilinx > user sent it to me.). > I also believe Lattice Semiconductor and Quicklogic also have their own > PCI reference design (I know the Lattice one is written in Verilog, but > not sure about the Quicklogic one.). > However, here is a caveat of using reference designs offered by > device manufacturers. > Even if the design is written in a device independent form (Uses generic > Verilog or VHDL statements, and no vendor specific primitives.), when > using reference designs offered by device manufacturers, you are often > legally required to use the reference designs on their devices. > Opencores.org also has a free PCI IP core, but it is a lot more > complex (Supports initiator and target transfers.) than any of the above > mentioned reference designs, so I feel like you will likely have a hard > time modifying it to suit your own needs. > When modifying a PCI interface, PCI specification Appendix B's > state machine examples and the following article may be helpful. > > http://www.eedesign.com/editorial/1995/fpgafeature9502.html > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 48508
Thomas Buerner <buerner@lrs.e-technik.uni-erlangen.de> wrote: : Does anybode know, where I can download the 4.2 version of Webpack ? Why do you want 4.2 when there is 5.1? Xilinx has some promises to make old versions abailable. Did you check if that happened? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 48509
Kevin I am new in PCI and PCIX design. I am going to design my own PCIX core, and this core has to be backward compatible with PCI. Right now I am thinking to start with PCI CORE and then upgrade to PCIX, I don't know how much work it is going to be. I am using Verilog, and am very intersted in starting with some kind of PCI core. Could you please kindly send the Xilinx verilog PCI core to me? my email address is: hxie168@hotmail.com You guys are great! I have learned a lot just by reading your messages. I appreciate your help. Best Regards! Huijun "Kevin Brace" <killspam4kevinbraceusenet@killspam4hotmail.com> wrote in message news:ahn2ha$9if$1@newsreader.mailgate.org... > > > Jeff Reeve wrote: > > > > I'm looking for a synthesizeable 32-bit 33MHz PCI Target only design to be > > placed into a FPGA or large CPLD. Minimal implementation is fine. Does > > anybody know if such a thing is available in VHDL or Verilog and is open > > sourced? I seem to recall Xilinx publishing a target only design quite some > > time ago but I can no longer find it on their web site. > > > > Any help is much apprecieated! > > Jeff > > > This is what you are probably talking about. > > ftp://ftp.xilinx.com/pub/applications/pci/ > ftp://ftp.xilinx.com/pub/applications/pci/00_index.htm > > > For some reason, a Verilog version of the reference design is missing, > but if you want it I can E-mail it to you (Some kind, long time Xilinx > user sent it to me.). > I also believe Lattice Semiconductor and Quicklogic also have their own > PCI reference design (I know the Lattice one is written in Verilog, but > not sure about the Quicklogic one.). > However, here is a caveat of using reference designs offered by > device manufacturers. > Even if the design is written in a device independent form (Uses generic > Verilog or VHDL statements, and no vendor specific primitives.), when > using reference designs offered by device manufacturers, you are often > legally required to use the reference designs on their devices. > Opencores.org also has a free PCI IP core, but it is a lot more > complex (Supports initiator and target transfers.) than any of the above > mentioned reference designs, so I feel like you will likely have a hard > time modifying it to suit your own needs. > When modifying a PCI interface, PCI specification Appendix B's > state machine examples and the following article may be helpful. > > http://www.eedesign.com/editorial/1995/fpgafeature9502.html > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 48510
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:aopg16$mo5$2@news.tu-darmstadt.de... > Thomas Buerner <buerner@lrs.e-technik.uni-erlangen.de> wrote: > > : Does anybode know, where I can download the 4.2 version of Webpack ? > > Why do you want 4.2 when there is 5.1? Hello Uwe, the version 5.1 runs only on WIN-2000/XP but 4.x runs on WIN98 too. Best Regards HelmutArticle: 48511
Hello all
I'm working with Xilinx ISE 4.1 tools. I have a small design manually
floorplanned and have created an RPM with all the logic, but
without IOBs or BUFGs.
Now I want to use this RPM as a design black block in a larger design.
How do I instantiate it into my VHDL model?
Or am I completely wrong on the use of RPMs?
Regards
Francisco
====================================================
Francisco Rodriguez Ballester (prodrig@disca.upv.es)
Dept. DISCA, EUI - Univ. Politecnica de Valencia
c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
tlf: +(34) 96 387 75 77 - fax: +(34) 96 387 75 79
====================================================
Article: 48512
If it was created in the floorplanner, you are restricted to using it in
that design, at least as of v4.2i. You can export it as a UCF file, which
essentially puts LOCs on all the pieces, so you could bring it into
another design only if the device is the same size and the hierarchical
names are unchanged. Not all that useful, I know. The problem with the
floorplanner (well, one of many problems actually) is that it is not
hierarchical: it works on a flat representation of your design, so you
wind up having to floorplan each copy of multiple identical instances
instead of doing it once unless you do the floorplanning in your source.
You can also create hard macros using the FPGA editor and bring them in as
black boxes into your source. I don't like doing that because it makes
simulation and timing analysis difficult.
We put RLOCs directly into our VHDL so that we end up with placed RPMs
that can be used in any design without having to go through floorplanning
every time. In that case, you just instantiate the RPM as a component in
the HDL code (and stick an RLOC on that component if it is forming a
larger RPM). Of course, Xilinx says they've never heard of people making
big RPMs out of smaller ones like this, and the 5.1 tools barf on big
RPMs...but that is beside the point.
Francisco Rodriguez wrote:
> Hello all
>
> I'm working with Xilinx ISE 4.1 tools. I have a small design manually
> floorplanned and have created an RPM with all the logic, but
> without IOBs or BUFGs.
>
> Now I want to use this RPM as a design black block in a larger design.
> How do I instantiate it into my VHDL model?
>
> Or am I completely wrong on the use of RPMs?
>
> Regards
> Francisco
> ====================================================
> Francisco Rodriguez Ballester (prodrig@disca.upv.es)
> Dept. DISCA, EUI - Univ. Politecnica de Valencia
> c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
> tlf: +(34) 96 387 75 77 - fax: +(34) 96 387 75 79
> ====================================================
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48513"rickman" <spamgoeshere4@yahoo.com> wrote > Yes, I understand that. But when you replicate the hardware, you > replicate *all* of the hardware. I have not heard anyone say that there > are multiple copies of the program counter (PC). If you are working off > one PC how do you switch between the threads on a clock cycle basis? > Additionally, how do you start up a thread? When this multiple thread > CPU starts following reset, each of the threads will need to be running > *something*. How is that managed? Do they all boot the BIOS or > whatever startup code you have? Yes, there are multiple PCs. For example, in LUT RAM. Each PC is initialized with some reset vector value. They can all be the same reset vector, or one PC can be a distinguished reset vector, which releases a software semaphore-like-entity after the single boot thread has done one-time initialization of the rest of the system. Each thread will know its identity, for example by starting the PCs at different addresses, or by preloading the thread# in a particular register, for each thread, in the barrel register file. An RTOS would presumably be employed to schedule logical threads/tasks to 'physical' threads. Most state (reg file, PC, poss. PSR or other special regs) would be replicated per thread; however, most function units and other parts of the datapath would be shared (time multiplexed) amongst the threads. Jan Gray, Gray Research LLCArticle: 48514
Hello: I am working on a xilinx cpld XC95144XL. Now I am able to program it using c code. But I also want to write a c code to verify the programing is successful.Does anyone know how to write code to read back the usercode? thanks hao xingArticle: 48515
"Ray Andraka" <ray@andraka.com> wrote > ... Of course, Xilinx says they've never heard of people making > big RPMs out of smaller ones like this ... I can only presume that you spoke to someone who didn't know what they were talking about. Hierarchical composition is specifically supported by RPMs, has been since day one, and is an essential facility. For example, in March '01, I PAR'd a design that filled a V600E with 60 processors. That was 60 instances of a processor RPM (actually 30 and 30 mirror-image processor RPMs), each processor RPM a composition of some bus interface RPMs and a datapath RPM, each datapath RPM a composition of some register RPMs, LUT RAM RPMs, ALU RPMs, addmux RPMs, etc. That design would have taken ages to process through your favorite synthesis tool in one lump. So you synthesize *one* 8x6x4 LUT processor RPM and instantiate it as a black box 60 times, RLOC'ing or RLOC_ORIGIN'ing each one (instead of making a single, monolithic, monstrous 48x72x4 LUT RPM). I asked Synplicity to provide a convenient one-step process to synthesize my design of 60 copies of an RPM by something like a black-box primitive that only expands (and then reuses) one identical submodule of a design (instead of wastefully expanding 60 topologically-identical-copies-but-with-renamed-synthesized-netnames-submodu les-and-their-sub-submodules-etc.) No interest -- so I continued to run Synplicity twice, once to synthesize one instance of the processing-element submodule (disabling I/O insertion) and once to synthesize the 60 instantiations (with the submodule converted to a black box instantiation). To put it another way, if I mark a module as syn_hier="hard", e.g. "hands off, don't optimize into or out of my module, please!", why would two instantiations of the module generate two quasi-identical-copies of the expanded module in the EDIF, when one shared copy would suffice? This is also the project where I complained to Synplicity that Synplify generates EDIF with unused VCC and GND nets for each of the many, many thousands of explicitly technology mapped 1-LUT ALU and addmux RPMs modules in my design, causing several minutes of unused-net warnings from MAP (IIRC) for each build cycle. See also http://www.fpgacpu.org/log/mar02.html#020302. Jan Gray, Gray Research LLCArticle: 48516
I wish that were the case. This is something that broke in 5.1 that causes map
to take 25+ hours to complete where it completed in less than 2 hours on a
machine with half the speed and memory (and paging like crazy on that machine)
using 4.2. It isn't hierarchical composition that is broken, it is RPMs with a
large number of slices (the open case has about 17,000 slices and consists of 50
identical tiles). In this case, I also ran the tile separately through synplify
for exactly the same reasons you did, and then algorithmically placed the tiles
in the next level up. I've also had the same beef about synplify, but haven't
bothered to complain there. At least Xilinx pretends to listen.
Do me a favor, run some of your big RPMs through 5.1sp1 and see what it does to
the map time. In my case, it expanded it more than 10x. Then if/when you see
the problem, complain to xilinx loudly about it. You can reference case
444377. Xilinx appears to be sweeping this one under the rug with a 'no one
else has this problem so perhaps your methodology is flawed' type of response.
The exact quote was:
"The developers have identified the bottlenecks in map 5.1i sp1. It seems are
sensetive to the 17,000 slice RPM in your design. This was an unforseen use
case which the new map architecture neglects. This is the only design anyone
at Xilinx has seen that uses an RPM this large.
Therefore, the developers are wondering what problem this RPM solves. Either
you are trying to solve a problem no other designer is trying to solve, or this
is just
a different approach to it. Would you mind explaining what problem you are
solving
with this giant RPM and why you have chosen this method as opposed to some
other method. "
Likewise, anyone else who uses a similar methodology, please try it out under
5.1sp1, and if it slows down map, complain to Xilinx about it. Any additional
input to Xilinx to convince them that it isn't an off-the-wall approach would be
welcome (and I would like to be copied on any case, if you care to).
Jan Gray wrote:
> "Ray Andraka" <ray@andraka.com> wrote
> > ... Of course, Xilinx says they've never heard of people making
> > big RPMs out of smaller ones like this ...
>
> I can only presume that you spoke to someone who didn't know what they were
> talking about. Hierarchical composition is specifically supported by RPMs,
> has been since day one, and is an essential facility.
>
> For example, in March '01, I PAR'd a design that filled a V600E with 60
> processors. That was 60 instances of a processor RPM (actually 30 and 30
> mirror-image processor RPMs), each processor RPM a composition of some bus
> interface RPMs and a datapath RPM, each datapath RPM a composition of some
> register RPMs, LUT RAM RPMs, ALU RPMs, addmux RPMs, etc.
>
> That design would have taken ages to process through your favorite synthesis
> tool in one lump. So you synthesize *one* 8x6x4 LUT processor RPM and
> instantiate it as a black box 60 times, RLOC'ing or RLOC_ORIGIN'ing each one
> (instead of making a single, monolithic, monstrous 48x72x4 LUT RPM).
>
> I asked Synplicity to provide a convenient one-step process to synthesize my
> design of 60 copies of an RPM by something like a black-box primitive that
> only expands (and then reuses) one identical submodule of a design (instead
> of wastefully expanding 60
> topologically-identical-copies-but-with-renamed-synthesized-netnames-submodu
> les-and-their-sub-submodules-etc.) No interest -- so I continued to run
> Synplicity twice, once to synthesize one instance of the processing-element
> submodule (disabling I/O insertion) and once to synthesize the 60
> instantiations (with the submodule converted to a black box instantiation).
>
> To put it another way, if I mark a module as syn_hier="hard", e.g. "hands
> off, don't optimize into or out of my module, please!", why would two
> instantiations of the module generate two quasi-identical-copies of the
> expanded module in the EDIF, when one shared copy would suffice?
>
> This is also the project where I complained to Synplicity that Synplify
> generates EDIF with unused VCC and GND nets for each of the many, many
> thousands of explicitly technology mapped 1-LUT ALU and addmux RPMs modules
> in my design, causing several minutes of unused-net warnings from MAP (IIRC)
> for each build cycle.
>
> See also http://www.fpgacpu.org/log/mar02.html#020302.
>
> Jan Gray, Gray Research LLC
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48517I've been keeping track of just the raw number of posts to both comp.arch.fpga and comp.dsp and in the last 2 months arch.comp.fpga has had more posts per day. I'm wondering if fpgas are going more mainstream or dsps are just so well known that people don't ask as many questions... Any thoughts??? SteveArticle: 48518
> Unused bits are set to zero, which compress really well. ;-) This is not ture. If you go into the fpga editor and create a blank part you will see lots of ones and zeros. What is ture is that the if a lot of the chip is not used there is a repeating pattern that is the same for each unused tile and so a low utillization design gives better compression results. For example if you just have one input and one output and one wire inbetween in a V1000 it compress about 100x.. SteveArticle: 48519
CRS currently has a position available for an Electrical Engineer in at their offices in Fairfax, VA. Candidates must have FPGA design and VHDL programming experience. Additional hardware experience is a plus. Experience: 2+ years designing complex FPGA solutions (preferably Xilinx) and high speed PCBs (i.e. clock speeds > 60 MHz). Skill set: FPGA design, Simulation, Timing Analysis, high speed PCB design. Tools: VHDL, Xilinx ISE, ModelSim, logic analyzers. We are looking for someone who has a good energy level, is a self-starter, loves challenges, committed and honest. Bachelor's degree in EE or CE is a must. Master's degree would be a plus Salary is dependent on the candidate's skill set and experience Candidates interested in this position should submit their resume to admin@cfrsi.com. Please no 3rd party submittals. Please include "FPGA Engineer" in the subject line. Thank YouArticle: 48520
Jan Gray wrote: > "Ray Andraka" <ray@andraka.com> wrote > >>... Of course, Xilinx says they've never heard of people making >>big RPMs out of smaller ones like this ... >> > ... > > I asked Synplicity to provide a convenient one-step process to synthesize my > design of 60 copies of an RPM by something like a black-box primitive that > only expands (and then reuses) one identical submodule of a design (instead > of wastefully expanding 60 > topologically-identical-copies-but-with-renamed-synthesized-netnames-submodu > les-and-their-sub-submodules-etc.) No interest -- so I continued to run > Synplicity twice, once to synthesize one instance of the processing-element > submodule (disabling I/O insertion) and once to synthesize the 60 > instantiations (with the submodule converted to a black box instantiation). I belive that the feature you want has just gone out in the 7.2 Beta. Why don't you download it and look up what we call a "locked" compile point. This is part of the MultiPoint technology, another part is an automatic (other than selecting compile points) incremental flow that extends through synthesis into both Altera and Xilinx P&R tools. The results are better than a black box based bottom up flow because the timing of the subdesign is taken into account when optimizing other parts of the design. It uses LogicLock for Altera and the new incremental P&R flow based on area groups in Xilinx. I think you will also find the excess VCC/GND net problem you mention below about below fixed in 7.2 as well. > > To put it another way, if I mark a module as syn_hier="hard", e.g. "hands syn_hier="hard" means that we won't change the port list of the module - no boundary optimization, but differences in timing flow through and can cause different instances to produce different structures. > off, don't optimize into or out of my module, please!", why would two > instantiations of the module generate two quasi-identical-copies of the > expanded module in the EDIF, when one shared copy would suffice? > > This is also the project where I complained to Synplicity that Synplify > generates EDIF with unused VCC and GND nets for each of the many, many > thousands of explicitly technology mapped 1-LUT ALU and addmux RPMs modules > in my design, causing several minutes of unused-net warnings from MAP (IIRC) > for each build cycle. > > See also http://www.fpgacpu.org/log/mar02.html#020302. > > Jan Gray, Gray Research LLC > > >Article: 48521
Thomas, please try: http://www.xilinx.com/webpack/classics/wpclassic/ regards, Larry Thomas Buerner wrote: > Does anybode know, where I can download the 4.2 version of Webpack ? > > thanx > ThomasArticle: 48522
"Ken McElvain" <ken@synplicity.com> wrote > I belive that the feature you want has just gone out in the 7.2 Beta. > Why don't you download it and look up what we call a "locked" > compile point. Thank you, I will, as time permits. And thanks for addressing the VCC/GND problem. I would like to clarify that I have no complaints with respect to Synplicity support -- the two issues/suggestions in my earlier post in this thread were both communicated to Synplicity through unconventional channels (such as their newsgroup) and so were not formally tracked as support issues. I appreciate your contributions to this group. Thanks. Thanks also to Peter and Austin and the other vendor 'ambassadors' who make this newsgroup so useful. ----- Product development is sometimes a thankless job. When it works as designed, everyone takes it for granted. When it's broken, even "a little", (or even when it's "user error"), everybody is unhappy. When you change something for a good reason, those that benefit don't realize their good fortune, and those that don't benefit, complain. Either you get support calls, or more happily, the phone doesn't ring at all. But rare indeed is the spontaneous customer compliment "Wow, your product worked great for my application, and I have no complaints. Great work." (Of course I don't consider turning a 2 hr run into a 25 hour run a good thing. Clearly some device-sized RPMs (quite easy to create) belong in the PAR test suite, and the PAR test suite apparently needs some performance regression tests.) (Which reminds me: "There is nothing more difficult to take in hand, more perilous to conduct, or more uncertain in its success, than to take the lead in the introduction of a new order of things. Because the innovator has for enemies all those who have done well under the old conditions, and lukewarm defenders in those who may do well under the new." -- Machiavelli) ----- OK, everybody, Monday is Appreciation Day. Post a success story. Take your FAE to lunch, etc. Go forth and share some good will. Jan Gray, Gray Research LLCArticle: 48523
Actually, one of there reasons I follow this new group is to find out about those annoying problems that people suffer with but are too small to bother logging through formal channels. The VDD/GND issue was a perfect example, I'm pretty sure you or someone else posted it here and that's why it got fixed. - Ken Jan Gray wrote: > "Ken McElvain" <ken@synplicity.com> wrote > >>I belive that the feature you want has just gone out in the 7.2 Beta. >>Why don't you download it and look up what we call a "locked" >>compile point. >> > > Thank you, I will, as time permits. And thanks for addressing the VCC/GND > problem. > > I would like to clarify that I have no complaints with respect to Synplicity > support -- the two issues/suggestions in my earlier post in this thread were > both communicated to Synplicity through unconventional channels (such as > their newsgroup) and so were not formally tracked as support issues. > > I appreciate your contributions to this group. Thanks. Thanks also to > Peter and Austin and the other vendor 'ambassadors' who make this newsgroup > so useful. > > ----- > Product development is sometimes a thankless job. When it works as > designed, everyone takes it for granted. When it's broken, even "a little", > (or even when it's "user error"), everybody is unhappy. When you change > something for a good reason, those that benefit don't realize their good > fortune, and those that don't benefit, complain. > > Either you get support calls, or more happily, the phone doesn't ring at > all. But rare indeed is the spontaneous customer compliment "Wow, your > product worked great for my application, and I have no complaints. Great > work." > > (Of course I don't consider turning a 2 hr run into a 25 hour run a good > thing. Clearly some device-sized RPMs (quite easy to create) belong in the > PAR test suite, and the PAR test suite apparently needs some performance > regression tests.) > > (Which reminds me: "There is nothing more difficult to take in hand, more > perilous to conduct, or more uncertain in its success, than to take the lead > in the introduction of a new order of things. Because the innovator has for > enemies all those who have done well under the old conditions, and lukewarm > defenders in those who may do well under the new." -- Machiavelli) > > ----- > OK, everybody, Monday is Appreciation Day. Post a success story. Take your > FAE to lunch, etc. Go forth and share some good will. > > Jan Gray, Gray Research LLC > > >Article: 48524
Ray, This is planned to be fixed in our 5.2i release. We might be able to create a tactical patch for you before that, but it sounds like you are not using 5.1i and since no other customers have run into this problem, the current plan is to wait until 5.2i (Feb). Steve Ray Andraka wrote: > I wish that were the case. This is something that broke in 5.1 that causes map > to take 25+ hours to complete where it completed in less than 2 hours on a > machine with half the speed and memory (and paging like crazy on that machine) > using 4.2. It isn't hierarchical composition that is broken, it is RPMs with a > large number of slices (the open case has about 17,000 slices and consists of 50 > identical tiles). In this case, I also ran the tile separately through synplify > for exactly the same reasons you did, and then algorithmically placed the tiles > in the next level up. I've also had the same beef about synplify, but haven't > bothered to complain there. At least Xilinx pretends to listen. > > Do me a favor, run some of your big RPMs through 5.1sp1 and see what it does to > the map time. In my case, it expanded it more than 10x. Then if/when you see > the problem, complain to xilinx loudly about it. You can reference case > 444377. Xilinx appears to be sweeping this one under the rug with a 'no one > else has this problem so perhaps your methodology is flawed' type of response. > The exact quote was: > > "The developers have identified the bottlenecks in map 5.1i sp1. It seems are > sensetive to the 17,000 slice RPM in your design. This was an unforseen use > case which the new map architecture neglects. This is the only design anyone > at Xilinx has seen that uses an RPM this large. > > Therefore, the developers are wondering what problem this RPM solves. Either > you are trying to solve a problem no other designer is trying to solve, or this > is just > a different approach to it. Would you mind explaining what problem you are > solving > with this giant RPM and why you have chosen this method as opposed to some > other method. " > > Likewise, anyone else who uses a similar methodology, please try it out under > 5.1sp1, and if it slows down map, complain to Xilinx about it. Any additional > input to Xilinx to convince them that it isn't an off-the-wall approach would be > welcome (and I would like to be copied on any case, if you care to). > > Jan Gray wrote: > > > "Ray Andraka" <ray@andraka.com> wrote > > > ... Of course, Xilinx says they've never heard of people making > > > big RPMs out of smaller ones like this ... > > > > I can only presume that you spoke to someone who didn't know what they were > > talking about. Hierarchical composition is specifically supported by RPMs, > > has been since day one, and is an essential facility. > > > > For example, in March '01, I PAR'd a design that filled a V600E with 60 > > processors. That was 60 instances of a processor RPM (actually 30 and 30 > > mirror-image processor RPMs), each processor RPM a composition of some bus > > interface RPMs and a datapath RPM, each datapath RPM a composition of some > > register RPMs, LUT RAM RPMs, ALU RPMs, addmux RPMs, etc. > > > > That design would have taken ages to process through your favorite synthesis > > tool in one lump. So you synthesize *one* 8x6x4 LUT processor RPM and > > instantiate it as a black box 60 times, RLOC'ing or RLOC_ORIGIN'ing each one > > (instead of making a single, monolithic, monstrous 48x72x4 LUT RPM). > > > > I asked Synplicity to provide a convenient one-step process to synthesize my > > design of 60 copies of an RPM by something like a black-box primitive that > > only expands (and then reuses) one identical submodule of a design (instead > > of wastefully expanding 60 > > topologically-identical-copies-but-with-renamed-synthesized-netnames-submodu > > les-and-their-sub-submodules-etc.) No interest -- so I continued to run > > Synplicity twice, once to synthesize one instance of the processing-element > > submodule (disabling I/O insertion) and once to synthesize the 60 > > instantiations (with the submodule converted to a black box instantiation). > > > > To put it another way, if I mark a module as syn_hier="hard", e.g. "hands > > off, don't optimize into or out of my module, please!", why would two > > instantiations of the module generate two quasi-identical-copies of the > > expanded module in the EDIF, when one shared copy would suffice? > > > > This is also the project where I complained to Synplicity that Synplify > > generates EDIF with unused VCC and GND nets for each of the many, many > > thousands of explicitly technology mapped 1-LUT ALU and addmux RPMs modules > > in my design, causing several minutes of unused-net warnings from MAP (IIRC) > > for each build cycle. > > > > See also http://www.fpgacpu.org/log/mar02.html#020302. > > > > Jan Gray, Gray Research LLC > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759
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