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Hello all - I've just started to use the xilinx webpack (4.2wp3). Compiling a simple demo project gives me : WARNING:NetListWriters:108 - In order to compile this verilog file successfully, please add $XILINX/verilog/src/glbl.v to your compile command. when I try to run "Generate post-translate Simulation Model". I've looked in the documentation, but I cannot find a way how do add that file ? Any advice will be appreciated. Thanks in advance, - FrankArticle: 48851
In news:comp.arch.fpga Michael Nicklas <michaeln@nospam.slayer.com> wrote: "Hi does anybody have any problems running Xilinx ISE 4.2i Student edition on Windows XP. It seemed to be going OK until I installed the most recent service pack - downloaded from the Xilinx University Program website www.xup.msu.edu/ Now it wont even open up. -- Cheers! Mike" I have been running Xilinx ISE WebPACK version about 5.1i on Windows XP Home edition. I only recently got Windows XP, but I have not had problems yet. After registering, it is free to download from HTTP://WWW.Xilinx.com/webpack/static/index.htm (about 106 megabytes, before you run the self-extracting uncompressing executable, also a 30 megabyte download for the compressed file for Modelsim).Article: 48852
Martin Thompson said: "[..] VHDL looks like ADA :-) [..]" Will <wv9557@yahoo.com> wrote: "[..] What do you expect, it [VHDL] comes from the same folks that invented that sick language[Ada]. [..]" Ada is not sick, it is used for many sick things but the language is fine.Article: 48853
The tools do sometimes split the carry chain, but even with a perfectly constructed
carry chain 24 bits puts you right around 200 MHz in a -4 part. a single instance
will get a tad higher, however when you have many carry chains on the design, the
4.2 router invariably routes one or two poorly, so that the top clock is
considerably less--around 180 MHz. That is a function of the laziness of the newer
router rather than the silicon though.
In our case, it is more of a problem with adders than counters, but I brought up
the counter because that appears to be a likely carry chain in the subject design.
Pipelining is of course good, but there are times when a carry chain cannot be
pipelined. In Virtex2, the win for pipelining a carry chain is not all that large
because the lion's share of the delay is getting on an off the carry chain, not in
the additional bits. Our designs are also maximally pipelined (it not only helps
with performance, it also helps with floorplanning and believe it or not, with
power consumption).
Parallel processing paths at lower rates is great if you have the area for the
additional instances AND your algorithm can tolerate it. Some processing depends
on previous samples, so it is harder to do that.
Joseph H Allen wrote:
> In article <3DB87064.181FD533@andraka.com>,
>
> I've seen the tools split a carry chain- you should definitely check for
> this (oddly, the floorplanner doesn't let you do it).
>
> Now for counters, carry chains are never really a problem. You can always
> make a pipelined counter: register the carry output from bit 11 and feed
> that into a second coutner for the upper 12-bits. The same goes for adders
> if you can afford a pipeline stage.
>
> I hate floorplanning, so I usually pipeline the sh*t out of everything.
> I've gotten 170+ MHz floorplanning free designs this way.
>
> Context swapping is your friend: it is better to run 4 problems at once,
> each taking four times the time than one problem in 1/4 the time. The cost
> is usually more buffering, which the FPGAs typically have lots of. Use LUT
> shift registers for local context buffers.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48854
At these data rates I usually recommend using a DSP microprocessor. The
talent to do the design is cheaper and easier to find, the tools are more
mature, and there are more choices for devices.
sean da wrote:
> HI,
>
> I am designing a low speed(less than 1MHz clock) digital signal
> processing unit.
>
> It comprise:
> 1)4K bit ROM
> 2)8*8 multiplier
> 3)2 12 bit accumulators
> 4)1K SRAM
> 5) 1 dozen registor and some control logic circuits.
>
> Please recommend a right choice for the FPGA chips, which has the
> right capacity and good price. I have a ISE 4.2 foundation package
> from Xilinx, nor sure which series FPGA I should choose, X4000, X9000,
> Vertex , Spartan ..., Other vendors product also are considered.
>
> Appreciate!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48855Sean, To answer this question properly, you'll need to figure (1) IO pins required (2) power supplies available (3) do you require either 5V outputs or 5V tolerant inputs. Not knowing those, I would start with Xilinx XC2S30 which works with 3.3V IO and 2.5V core and should have plenty of resources. XC2S15 may have enough also. If you pick the TQ144 package, you have flexibility to go up or down in the family later on. The VQ100 package only shows available in 2S15 and 2S30. DigiKey Qty1 prices for these devices are $10/$20. http://www.digikey.com I have had excellent experience with the Digilent Digilab2 board, it comes with XC2S200, plenty of room if you want to buy and use the ChipScope logic analyzer for easier debugging. (I use it with a JTAG cable) http://www.digilentinc.com If you want easier-to-use tools, I would opt for Altera ACEX devices say 1K30 with the MaxPlus software (if it's still available). Best, -rajeev- -------------- swda_ic@yahoo.com (sean da) wrote in message news:<c8f47ccb.0210242054.5cad2e17@posting.google.com>... > HI, > > I am designing a low speed(less than 1MHz clock) digital signal > processing unit. > > It comprise: > 1)4K bit ROM > 2)8*8 multiplier > 3)2 12 bit accumulators > 4)1K SRAM > 5) 1 dozen registor and some control logic circuits. > > Please recommend a right choice for the FPGA chips, which has the > right capacity and good price. I have a ISE 4.2 foundation package > from Xilinx, nor sure which series FPGA I should choose, X4000, X9000, > Vertex , Spartan ..., Other vendors product also are considered. > > Appreciate!Article: 48856
Sean -
If you have the Xilinx tools already, can you just try to
synthesize, translate, PAR, etc., and see what is the smallest Xilinx
device you can get away with based on the resources you need?
Don't see why people suggest NOT using an FPGA just because of your
low speed requirements. You already have invested in the (SW) tools,
and based on your volume requirements that could be the largest part of
your budget...
Bill
sean da wrote:
>
> HI,
>
> I am designing a low speed(less than 1MHz clock) digital signal
> processing unit.
>
> It comprise:
> 1)4K bit ROM
> 2)8*8 multiplier
> 3)2 12 bit accumulators
> 4)1K SRAM
> 5) 1 dozen registor and some control logic circuits.
>
> Please recommend a right choice for the FPGA chips, which has the
> right capacity and good price. I have a ISE 4.2 foundation package
> from Xilinx, nor sure which series FPGA I should choose, X4000, X9000,
> Vertex , Spartan ..., Other vendors product also are considered.
>
> Appreciate!
Article: 48857I'm looking for an inexpensive 3.3V Device Programmer specifically for XC17S200APD8C DIP-8 Serial EPROM. Any recommendations ? Any suggestions on second-hand sources ? Thanks in advance, -rajeev-Article: 48858
Hey folks, i'm working with an Xess XSV-300 board here and having timing issues with the CPLD that shouldnt be there. I need to verify which speed grade is on the board. The CPLD is the xilinx XC9500 series model 108, form tq100. Here's the markings XC95108 TQ100AEM9941 F1102142A 20C does that last 20c mean its commercial temp range and -20 speed grade? Thanks, TonyArticle: 48859
I'm having a problem with high fanout (>=1000) on the CLK signal. I tried
running it through a BUFG, but the delay on that destroys the timing. I
tried running it into a DCM to make a new signal that matched that CLK
coming into the userapp portion, but that had the same problem as the single
BUFG (with both duty cycle settings). Perhaps someone familiar with Xilinx's
PCI core could tell me what to do about this code to make it meet the timing
spec:
attribute DLL_FREQUENCY_MODE : string;
attribute DUTY_CYCLE_CORRECTION : string;
attribute DLL_FREQUENCY_MODE of U2a: label is "HIGH";
attribute DUTY_CYCLE_CORRECTION of U2a: label is "FALSE";
attribute DLL_FREQUENCY_MODE of U2b: label is "HIGH";
attribute DUTY_CYCLE_CORRECTION of U2b: label is "FALSE";
begin
logic_0 <= '0';
U2a : DCM port map (
CLKFB => CLK_spread0,
CLKIN => CLK,
DSSEN => logic_0,
PSCLK => logic_0,
PSEN => logic_0,
PSINCDEC => logic_0,
RST => RST,
CLK0 => CLK_dcma
);
U2b : DCM port map (
CLKFB => CLK_spreadbf,
CLKIN => CLK,
DSSEN => logic_0,
PSCLK => logic_0,
PSEN => logic_0,
PSINCDEC => logic_0,
RST => RST,
CLK0 => CLK_dcmbf,
CLK180 => CLK_dcmb
);
U3a : BUFG port map (I => CLK_dcma, O => CLK_spread0);
U3b : BUFG port map (I => CLK_dcmb, O => CLK_spread180);
U3bf : BUFG port map (I => CLK_dcmbf, O => CLK_spreadbf);
USER_IXPA0: IFDDRCPE port map (Q0 => my_wide_regXPA(0), Q1 =>
my_wide_regXPA(32), PRE => '0', D => XPA(0), CE => '1', C0 => CLK_spread0,
C1 => CLK_spread180);
USER_OXPA0: OFDDRTCPE port map (O => XPA(0), T => my_wide_reg0(9), PRE =>
'0', D0 => my_wide_reg1(0), D1 => my_wide_reg1(32), CE => '1', C0 =>
CLK_spread0, C1 => CLK_spread180, CLR => RST);
.
.
.
. (repeated 640 times)
Thanks for your time.
Article: 48860In adapative filter coefficients are updated at every sample. Using DA, LUT should be updated at every sample. So it looks adaptive DA filter no longer efficient way to implment adaptive filter because we need to prepare updated LUT. Is it right? I understand that DA is the most efficient way to implment FIR in FPGA when we know the coefficients but I'm curious in adaptive FIR case. Another question is if I have to implment DA adaptive filter how to generate LUT? Assume I have a updated coefficients, then how to implment the logic to update LUT? Any references or advices? thanks, dongho Ray Andraka <ray@andraka.com> wrote in message news:<3DAC2555.3A36A742@andraka.com>... > The DA LUT contains all the possible sums of the 1xN products. See > the tutorial on distributed arithmetic on my website. > > No, the LPM multiplier is not a DA multiplier. DA reduces the logic > for a sum of products. It works by rearranging the partial sums > then using a scaling accumulator to do all the multiplies. In the > extreme case where there is only one product term, DA is reduced to > a scaling accumulator. If that is done in a full parallel > implementation, then you arrive at a regular multiplier. I refer > you to both the multiplier and distributed arithmetic tutorials on > my website. > > Dongho wrote: > > > Somebody know how to generate LUT for DA FIR with Altera? > > Another question is if I use LPM multiplier using EAB, it this a > > DA multiplier? If not, what's the difference from DA multiplier? > > > > thanks for your help > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 48861
Hello, I have a 6809E VHDL model compiled into and Altera FPGA and running in a CoCo3. I would like to validate my design in other 6809 or 6809E systems. If you have a 6809 or 6809E system board that is small enough and self-contained enough to send to me, it would help me alot. It will also help you, if you are looking for a 6809 FPGA solution. Please email me if you are interested and we can discuss the details. Regards, Scott L Baker scd @ teleport . comArticle: 48862
"Giuseppe " <gziggio.pleasedontsendmeanything@tin.it> wrote in message news:<apanur$t8v8l$1@ID-61213.news.dfncis.de>... > > >My problem > > >isn't so much the download of the data but that this download only > > >works one time. If the security bits are set in the Xilinx bitmap, you can't re-program the part without toggling the PROGRAM pin or powering off the system. It may be possible to toggle the PROGRAM pin via JTAG, but I have never tried it. Alan Nishioka alann@accom.comArticle: 48863
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3db8dfd9.243269883@netnews.agilent.com>... > On 24 Oct 2002 21:54:35 -0700, swda_ic@yahoo.com (sean da) wrote: > > >HI, > > > >I am designing a low speed(less than 1MHz clock) digital signal > >processing unit. > > > >It comprise: > >1)4K bit ROM > >2)8*8 multiplier > >3)2 12 bit accumulators > >4)1K SRAM > >5) 1 dozen registor and some control logic circuits. > > > >Please recommend a right choice for the FPGA chips, which has the > >right capacity and good price. I have a ISE 4.2 foundation package > >from Xilinx, nor sure which series FPGA I should choose, X4000, X9000, > >Vertex , Spartan ..., Other vendors product also are considered. > > 1MHz is very slow. A software emulation of your function on a CPU may > be more cost effective than an FPGA. > > Regards, > Allan. Thanks for the input. This Small DSP unit is going to be integrated with other analog circuit for the final design. Right now, I just want to make a hardware demo of the DSP algorithm and prove it fuinctional working. A CPLD or FPGA is closer to the final chip implementation plus the Verilog code is same for this Programmable logic and final ASIC. Except CPU(microcontroller), any other small capacity CPLD and FPGA choice?Article: 48864
"sean da" <swda_ic@yahoo.com> schrieb im Newsbeitrag news:c8f47ccb.0210250902.f16053b@posting.google.com... > allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3db8dfd9.243269883@netnews.agilent.com>... > > On 24 Oct 2002 21:54:35 -0700, swda_ic@yahoo.com (sean da) wrote: > > > > >HI, > > > > > >I am designing a low speed(less than 1MHz clock) digital signal > > >processing unit. > > > > > >It comprise: > > >1)4K bit ROM > > >2)8*8 multiplier > > >3)2 12 bit accumulators > > >4)1K SRAM > > >5) 1 dozen registor and some control logic circuits. I would suggest a small Spartan-II or Spartan-IIE. Even the smallest (Xc2S15) should do the work. -- MfG FalkArticle: 48865
"Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag news:1035529157.441767@turtle.ru.ac.za... > (a) I installed ModelSim with ISE, but do not have a license for ModelSim so > have to use starter license. When ModelSim was called for the watch tut, I > got a warning that the design was too big. Does this mean I am going to be > severely limited in simulations when I move onto bigger and better things? Modelsim with an evaluationlicense will slow down to 1% if you design is largen than 500 lines HDL. IT will further slow down to 0.1% after 200 lines, AFAIK. > > (b) What, if there are any, the equivalents of the Functional Simulation and > Timing Simulation in Foundation? Functional -> Behavioural Timing -> Post Place& Route BUT, as this toppic has been discussed a few times, in general it is sufficient to do a Behavioural sim to ckech the logic function. Then apply a timing constaint to your clock(s) and IOs and let the static timing analyzertell you if you design meets the speed you need or not. This is much faster and checks more (all?) datapaths, which can be hardlx covered in a timing sim. > (c) Is there another way to simulate my schematic in ISE without it using > ModelSim? Use another simulator. But IMHO Modelsim runs fine after you got over the critical point. > (d) It was never very apparent in Foundation, so I didn't really bother > about it, but upon completion of schematic design, does the system convert > this design into HDL before simulation? ?? Dunno. -- MfG FalkArticle: 48866
"Brannon King" <bking@starbridgesystems.com> schrieb im Newsbeitrag news:3db97439$1@news.splitrock.net... > I'm having a problem with high fanout (>=1000) on the CLK signal. I tried > running it through a BUFG, but the delay on that destroys the timing. I The description of the problem is a little bit confusing. How is timing destroyed? If a BUFG should drive 1000 clock loads (FlipFlops, RAMS etc.), this is absolutely NO problem. Please describe the problem a little bit more in detail. -- MfG FalkArticle: 48867
I know that a board I'm using uses a Xilinx coolrunner CPLD for the conversion. It might cost a bit more, but you could offload some of the logic from the VirtexII to the CPLD. There are possibly some other advantages... Pierre-Olivier jakab tanko <jtanko@ics-ltd.com> wrote: > Hello, > Does anybody know how to (safely) drive Virtex2 > inputs with 5V TTL levels? > Thanks, > jakabArticle: 48868
The problem is that the aforementioned code will not trce to 100MHz like I need it to. It trces to 40MHz as listed, 50MHz without the DCM, 60MHz with out the DCM or the BUFG, and the full 100MHz when I register the CLK (except that breaks the app). I understand that sticking in an extra BUFG is going to add a little delay to the line, but I thought the DCM was how you "repeated" the CLK without slowing things down, but if my code is right then that is not true. I'm assuming the CLK is coming out of the PCIX core riding a BUFG already.Article: 48869
Rajeev wrote: > I'm looking for an inexpensive 3.3V Device Programmer > specifically for XC17S200APD8C DIP-8 Serial EPROM. > > Any recommendations ? > > Any suggestions on second-hand sources ? > > Thanks in advance, > -rajeev- After realizing that our Data/IO support contract had expired one version short of being able to burn recent Xilinx SPROMs, I purchased the Roman-Jones programmer (about $120) and am quite happy with it. Details at http://www.roman-jones.com/ I think DigiKey distributes this as well. regards, TomArticle: 48870
Thanks for the info... > Modelsim with an evaluationlicense will slow down to 1% if you design is > largen than 500 lines HDL. IT will further slow down to 0.1% after 200 > lines, AFAIK. Ok... so are you saying that in order to simulate your design that you have made in ISE, you have to go out and get a license for ModelSim aswell??? Otherwise, ISE has no internal simulator?? Why doesn't Xilinx make a simulator part of ISE to save customers a whole stack of cash? adrianArticle: 48871
I don't know but the data sheets for it should have the info?Article: 48872
You can use the crippled version of ISE, but for serious design (more than a
once in a blue moon, or for larger designs) you'll want to pony up for a full
simulator. If you are buyng full simulators, I'd recommend looking at the
Aldec suite, IMHO you get a lot more for the money than you do with Modelsim.
Noddy wrote:
> Thanks for the info...
>
> > Modelsim with an evaluationlicense will slow down to 1% if you design is
> > largen than 500 lines HDL. IT will further slow down to 0.1% after 200
> > lines, AFAIK.
>
> Ok... so are you saying that in order to simulate your design that you have
> made in ISE, you have to go out and get a license for ModelSim aswell???
> Otherwise, ISE has no internal simulator?? Why doesn't Xilinx make a
> simulator part of ISE to save customers a whole stack of cash?
>
> adrian
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48873Speed grades are -7, -10, -15, and -20, with -20 (your part) being the slowest. Peter Alfke, Xilinx Applications ae wrote: > I don't know but the data sheets for it should have the info?Article: 48874
I am using the evaluation version with a minimum of problems. While it
does slow down I thing the previous poster may be overstating the case.
Where did you get those numbers? By the way, what does Modelsim go for
anyway?
Thanks,
Theron Hicks
"Noddy" <g9731642@campus.ru.ac.za> wrote in message
news:1035571048.576396@turtle.ru.ac.za...
> Thanks for the info...
>
> > Modelsim with an evaluationlicense will slow down to 1% if you design is
> > largen than 500 lines HDL. IT will further slow down to 0.1% after 200
> > lines, AFAIK.
>
> Ok... so are you saying that in order to simulate your design that you
have
> made in ISE, you have to go out and get a license for ModelSim aswell???
> Otherwise, ISE has no internal simulator?? Why doesn't Xilinx make a
> simulator part of ISE to save customers a whole stack of cash?
>
> adrian
>
>
>
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z