Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"yusuke" <yusuke_and@yahoo.com> schrieb im Newsbeitrag news:cdda3803.0210251635.61199ff@posting.google.com... > Hello there, > I'm working on a reverse engineering project in which i need to > overwrite a signal(8 bits) at a bus at 5 MHz. I'm using a xilinx > 9572xl cpld to do this task. Unfortunately, when i write the signal i > want, my cpld holds it for a while at the bus and then the chip at the > bus overwrite mine. And xilinx enters on a "strange behavior" like > missing clock rising edges. Do you tristate the output of the CPLD when the writing period to the bus is over? > PS. (1)Sorry for posting this e-mail at this group, i couldn't find > comp.arch.cpld. Never mind, you are just right here. > (2)Sorry for my poor English skills Never mind too. -- MfG FalkArticle: 48901
Hi there,
I need some help in designing my project. I have to design a Data
Acquisition Card for gathering a 5MHz coming analog signal through a
12-bit A/D ,going through some kind of logic for connecting to the PCI
bus ,via the PCI 9052 IC(which is a target controller PCI interface IC
from the PLX technology company).
The ADC I intend to use is the 10MHz "ADC12181"(from the National
Semiconductor),which seems proper for this application.
I thought about using a FIFO (or any memory device),for saving the
data coming out the A/D,and entering the PCI 9052 IC.But I have some
difficulties in what sort of logic I have to use for controlling the
data Out of the A/D into the FIFO,and Out of the FIFO ,going into the
data bits of the PCI 9052. I would like to get some help in designing
the Logic Circuit Section(The FPGA or CPLD using VHDL),for controlling
the incoming data.
I would be so thankful if anyone could give me some advice for
this hardware design,and show me some hardware examples of these kind
of Data Acquisition Cards.
Miad Faezipour
Article: 48902
"Miad Faezipour" <miad_fz@hotmail.com> schrieb im Newsbeitrag
news:6373102b.0210260321.2deaea5f@posting.google.com...
> Hi there,
> I need some help in designing my project. I have to design a Data
> Acquisition Card for gathering a 5MHz coming analog signal through a
^^^^^^^^^^^^^^^^
> 12-bit A/D ,going through some kind of logic for connecting to the PCI
> bus ,via the PCI 9052 IC(which is a target controller PCI interface IC
> from the PLX technology company).
> The ADC I intend to use is the 10MHz "ADC12181"(from the National
^^^^^^^^^^^^^^
Do you think this leaves enough room? In theory, the shannon theorem says
that sampling at twice the maximum frequency is sufficcient to reconstruct a
signal, but in practice, you need a low-pass filter in front of your ADC to
prevent aliasing. But since this low-pass filter has a limited roll-off, it
will get very hard to design a low pass filter that has almost no
attenuation @ 5MHz and >60 dB Attenuation @5.01 MHz.
I think, if you really have signal componets up to 5MHz, you need to sample
with at least 20 MHz, maybe better 30 or more. The higher the sampling
frequency, the easier the low-pass filter design.
> Semiconductor),which seems proper for this application.
> I thought about using a FIFO (or any memory device),for saving the
> data coming out the A/D,and entering the PCI 9052 IC.But I have some
> difficulties in what sort of logic I have to use for controlling the
> data Out of the A/D into the FIFO,and Out of the FIFO ,going into the
> data bits of the PCI 9052. I would like to get some help in designing
> the Logic Circuit Section(The FPGA or CPLD using VHDL),for controlling
> the incoming data.
Hmm, I dont know if the PLX has already some FIFOs inside. If yes, a
midrange CPLD (100++ macrocells) should be enough for glueing the ADC to the
PLX. If not, you need to build this FIFO yourself, which is most probably
best done using a small FPGA. A Spartan.II(E) will work well. Yes, there are
also Altera/Actel/Atmel/dunno parts that will do the trick ;-))
--
MfG
Falk
Article: 48903Nice! Thank you! Tony "Ryan Laity" <ryan.laity@xilinx.com> wrote in message news:apcbr4$1c52@cliff.xsj.xilinx.com... > All, > > There is an answer record with the information that you're looking for > here: > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=1067 > > It didn't come up immediately when I searched for "part marking", so > I'll make sure that our web team has a look at that. Hopefully this > clears up future confusion. > > > Cheers, > Ryan > > > > > > Tony M wrote: > > They have purchasing information on how to specify a part number (c/i speed > > grade, etc), but nothing on chip labeling > > > > > > <ae> wrote in message news:ee79f55.0@WebX.sUN8CHnE... > > > >>I don't know but the data sheets for it should have the info? > > > > > > >Article: 48904
Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3DB59DE1.1040009@dplanet.ch>... > Why is the price of 48$ that hard to find ? > > Rene > > James Wang wrote: > > Hi, > > > > We are making Download ByteBlasterMV for Altera FPGA and EPLD > > configuration/programming. It's reliable, affordale and suitable for > > PLD development and somebody who want's to learn PLD. Details please > > check at: http://www.minford.ca. Because it was exchanged to canadian dollars. This problem was fixed already to US$ 30. Please check the www.minford.ca again.Article: 48905
Thanks Martin. BTW, I looked up a Digikey part number for this part: TC7SU04FCT-ND TC7SU04F (TE85L package) Regards, Scott L Baker "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:i0tu9.165945$N_6.2385302@news.chello.at... > > Is it possible to build a crystal oscillator circuit using > > standard FPGA IO pins? i.e. 1 input an 1 output > > pin connect internally by an inverter and the crystal > > connect externally across the pins? > Thats not a good idea! Use the simple inveter oscillator with an 74hcu04. > The 'u' is importand, because it's the unbuffered version. > Martin > > -- > JOP - a Java Optimized Processor for FPGAs. > http://www.jopdesign.com > >Article: 48906
Hi People, We are making Altera ByteBlaster to program/configure EPLD or EPLD device. It's reliable and affordable, replace for Altera ByteBlaster and ByteBlaster MV with only US$30.00. For more details please check at www.minford.ca. Thanks James Wang Minford TechnologyArticle: 48907
I wrote: > I need to switch four 3.3V PCI signals, and am currently using a 5V > Quickswitch because I thought the 3.3V Quickswitch would clamping the > signals to substantially below the Vdd of the switch. I can't figure > out from the data sheet whether the PI3B3125 and PI3B3245 will clamp > the signals to a lower voltage or not. What's the relevant > specification? Vik? Rick Filipkiewicz <rick@algor.co.uk> writes: > There are 2 Pericom ranges of `pass transistors in a box' powered from 3.3V. > They start with either PI3B or PI3C. > > PI3C: Uses NMOS transistors with a charge pump on the gate. VCC range > 2.5-3.3V. The output can go up to VCC+0.5V. > > PI3B: Uses a CMOS pair. The output can go to VCC but not beyond. > > So either use PI3B or PI3C + 2.8V supply. Thanks for the info. But why would I want a 2.8V supply on the PI3C, rather than simply using the 3.3V supply I've already got? Both sides of my switch are 3.3V levels. I know there might be some overshoot, but it was never a problem before I started using a PI5C switch, so I'd think either a PI3B or PI3C on 3.3V should be OK.Article: 48908
Ken McElvain <ken@synplicity.com> writes:
> I don't think you tested very much. There never was a 4.x version of
> Synplify, we skipped from 3.x to 5.x because of beliefs in Asia about
> the number 4. The current version of Synplify supports
> XC4000 and XC3000 designs.
Don't customers in Asia worry that when they buy version five of your
product, it's really version four?
Eric
It's bad luck to be superstitious.
-- Andrew W. Mathis
Article: 48909Goran Bilski <goran.bilski@xilinx.com> writes: > But when customer has asked for RTOS, we ask them why. And in most of > the cases they want just want some kernel functionality or network > services. So what we have added in the just released EDK many of > these services in our own libraries. And your marketing department hasn't been savvy enough to describe these libraries as an RTOS? Amazing!Article: 48910
"scd" <scd@nospam.com> writes: > I have a 6809E VHDL model compiled into and Altera FPGA > and running in a CoCo3. Is this model available somewhere?Article: 48911
Hi! I'm new to FPGA and i'd like to know for what kind of an aplication they are better suited than dsp or microcontroller. Is it more easy to design with uc an dsp or with FPGA? thanksArticle: 48912
Thanks for the idea on ACTEL ProAsic FPGA. May I ask, Do other vendors carry such FPGA with flash memory inside? say, Xilinx. the security feature is good option. Alos, what is the hardware requirement for this FPGA development, for example programming flash memory? Where can I buy for small volume (<10)? appreciate! jerry@quickcores.com (Jerry D. Harthcock) wrote in message news:<c4cfbb5c.0210251301.2e3e78c5@posting.google.com>... > swda_ic@yahoo.com (sean da) wrote in message news:<c8f47ccb.0210242054.5cad2e17@posting.google.com>... > > HI, > > > > I am designing a low speed(less than 1MHz clock) digital signal > > processing unit. > > > > It comprise: > > 1)4K bit ROM > > 2)8*8 multiplier > > 3)2 12 bit accumulators > > 4)1K SRAM > > 5) 1 dozen registor and some control logic circuits. > > > > Please recommend a right choice for the FPGA chips, which has the > > right capacity and good price. I have a ISE 4.2 foundation package > > from Xilinx, nor sure which series FPGA I should choose, X4000, X9000, > > Vertex , Spartan ..., Other vendors product also are considered. > > > > Appreciate! > > Take a look at Actel's ProASIC+ "flash-based", re-programmable FPGA. > The advantage is it's more ASIC-like in that it does not require an > external serial EEPROM to boot-load on power-up. In other words, it > instantly comes up live. > > A second advantage is that you can "sample" your design to prospective > buyer/licensee as a single, pre-programmed chip as opposed to a XILINX > and a pre-programmed boot ROM combination. > > A third advantage is security. If you set the security bit, it can't > be copied. If you set the "never-erase" bit, it can never be > re-programmed or copied. > > Regards, > > Jerry D. Harthcock > www.quickcores.comArticle: 48913
There is stuff that a micocontroller is better at and there is stuff where an FPGA is better at. They do not compete, but enhance each other. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Klemen wrote: > Hi! > > I'm new to FPGA and i'd like to know for what kind of an aplication they are > better suited than dsp or microcontroller. Is it more easy to design with uc > an dsp or with FPGA?Article: 48914
The 2.8V supply voltage is needed when using the PI3C as a translator between 5V logic and 3.3V logic. Since both sides are 3.3V, you should be OK with a 3.3V supply for the PI3C. Note that the PI3C has lower on capacitance while the PI3B has faster on/off times. Daniel Lang "Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message news:qhfzut5i43.fsf@ruckus.brouhaha.com... > I wrote: > > I need to switch four 3.3V PCI signals, and am currently using a 5V > > Quickswitch because I thought the 3.3V Quickswitch would clamping the > > signals to substantially below the Vdd of the switch. I can't figure > > out from the data sheet whether the PI3B3125 and PI3B3245 will clamp > > the signals to a lower voltage or not. What's the relevant > > specification? Vik? > > Rick Filipkiewicz <rick@algor.co.uk> writes: > > There are 2 Pericom ranges of `pass transistors in a box' powered from 3.3V. > > They start with either PI3B or PI3C. > > > > PI3C: Uses NMOS transistors with a charge pump on the gate. VCC range > > 2.5-3.3V. The output can go up to VCC+0.5V. > > > > PI3B: Uses a CMOS pair. The output can go to VCC but not beyond. > > > > So either use PI3B or PI3C + 2.8V supply. > > Thanks for the info. But why would I want a 2.8V supply on the PI3C, rather > than simply using the 3.3V supply I've already got? Both sides of my > switch are 3.3V levels. I know there might be some overshoot, but it was > never a problem before I started using a PI5C switch, so I'd think either > a PI3B or PI3C on 3.3V should be OK.Article: 48915
This question has been asked many times, and the answer is always: Do not do this! It might work occasionally, but you just have too many gain stages in the loop for a reliable behavior. You want a single-stage amplifier, and no FPGA ( after XC3000) has that. Buy a canned crystal oscillator. Itis built by people who know their business... Peter Alfke Xilinx Applications scd wrote: > Hi, > > Is it possible to build a crystal oscillator circuit using > standard FPGA IO pins? i.e. 1 input an 1 output > pin connect internally by an inverter and the crystal > connect externally across the pins? > > Has anyone had any luck doing this? > > Thanks, > ScottArticle: 48916
Let's not be too proud here: How many European and American hotels have a thirteenth floor, or a room number 13? Not many. Same reason. Peter Alfke =============== Eric Smith wrote: > Ken McElvain <ken@synplicity.com> writes: > > I don't think you tested very much. There never was a 4.x version of > > Synplify, we skipped from 3.x to 5.x because of beliefs in Asia about > > the number 4. The current version of Synplify supports > > XC4000 and XC3000 designs. > > Don't customers in Asia worry that when they buy version five of your > product, it's really version four? > > Eric > > It's bad luck to be superstitious. > -- Andrew W. MathisArticle: 48917
Here is a very short answer: FPGAs are very fast, they can perform many (many!) tasks in parallel in a few nanoseconds. A microprocessor is good at complex tasks, but needs (many) microseconds to do anything meaningful. Peter Alfke, Xilinx Applications =============================== Klemen wrote: > Hi! > > I'm new to FPGA and i'd like to know for what kind of an aplication they are > better suited than dsp or microcontroller. Is it more easy to design with uc > an dsp or with FPGA? > > thanksArticle: 48918
Falk Brunner <Falk.Brunner@gmx.de> wrote in message news:ape4m7$og4q$1@ID-84877.news.dfncis.de... ... > Do you think this leaves enough room? In theory, the shannon theorem says > that sampling at twice the maximum frequency is sufficcient to reconstruct a > signal... <nitpick on> I thought that was the Nyquist critereon. <nitpick off> JeffArticle: 48919
Apart from the suggestions made by other posters, another good place to check is I2C's "younger sibling" the SMBus ... They are very similar, and you can get the full specs at: www.smbus.org. cheers -- ============================= Kristofer Vorwerk, BASc Master's Student, VLSI CAD Group University of Waterloo > I went to yahoo for "Lecture I2C Bus" and it returned me a bunch of french > websites. > Has anyone seen a good decent lecture notes on I2C bus? > > Thanks. > > >Article: 48920
Hi there, > Does anyone know any reliable tools that convert C code into Verilog, VHDL > or some other format that can be mapped > into FPGAs very very quickly? > > OR maybe there are tools that compile C into FPGA directly. Hmm... bad idea, IMO. Not only is converting C to an HDL likely not going to create a fast & tight design, the code that it generates will likely be gross (read: illegible). I'd be surprised if a C-to-HDL converter would be smart enough to use mainly synchronous logic to achieve better P&R in high-speed designs, or if it would instantiate the right black-box components when necessary, or how it would accomodate timing latencies with FPGA components (like BRAMs), or if it would use tri-state busses all over the place in your design (ick -- it could kill any notion of good place & route), etc. etc. If you really want to be writing this in C, have you considered a microprocessor-based solution? ======================== Kristofer Vorwerk, BASc Master's Student, VLSI Cad Group University of WaterlooArticle: 48921
1. How in verilog can you delay a signal, like if you are writing ram, delay the WE signal until the address is stable - is it normal just to run a clock speed that is faster than the ram and just clock of the other edge from the address setup, or is there a way to make a delay line? 2. How can you get a 'rom' into a test fixture, is there any way to encode data rather than mem[1] = 1234 ; mem[2]=234 in an intital section? Thanks RalphArticle: 48922
Hi Friends, We are making a FPGA demo board which is suitable for prototype development and FPGA study. It has an Altera Flex10K devices EPF10K10LC84, feature ICs(24LC64, LM75, 50MHz oscillator), RS232 port, LED display and switch input. FPGA pins are expandable to outside. It comes with a download ByteBlaster, power supply, source code run on the demo board. It's ideal for people who are learning FPGA and new product prototyping. Details please check at www.minford.ca James Wang Minford Technology minfordtec@aol.com http://www.minford.caArticle: 48923
yusuke wrote: > > Hello there, > I'm working on a reverse engineering project in which i need to > overwrite a signal(8 bits) at a bus at 5 MHz. I'm using a xilinx > 9572xl cpld to do this task. Unfortunately, when i write the signal i > want, my cpld holds it for a while at the bus and then the chip at the > bus overwrite mine. And xilinx enters on a "strange behavior" like > missing clock rising edges. > I have alredy tried to short some output pins to increase the current > suplied. Even though, the same problem continues. I have read xilinx > datasheets and application notes, but i couldn't find nothing useful > to solve this problem. Sounds like you are talking about bus contention ( both the CPLD, and another device driving hard at the same time ) then you should try and avoid this, with proper signal decode. The high contention currents can cause ground bounce, and level shifts inside the device. ( => "strange behavior" ) NB : The data only gives MAX/damage values, not 'working reliably' values :) If you need to research 'who drives when', to find the proper signal decode, you can add series resistors between the CPLD and the BUS.Article: 48924
Hi Mark and Falk, thank you both for replying.
Mark wrote:
>Most likely, you have the Bus-Hold circuitry enabled -
>You can find an explanation of bus hold and learn how to disable it
here.
Ok, I've read Xilinx Answer #5175 and #15206, your e-mail to Len
Chisholm (at comp.arch.fpga 2002-04-29 18:00:44 PST) and xilinx
datasheets (IOB /Bus-hold circuitry section) and I think i didn't make
myself clear at the first message. My vhdl source code is something
like the folowing:
(the code below is not intend to be free of syntax errors. It's much
like a pseudo-code to give you an ideia of what i'm trying to do. I've
got a serious problem on remembering programming lang. syntaxes :) )
libray IEEE...
port( clk : in : std_logic;
data : inout: std_logic_vector( 0 to 7) )
....
constant pattern_x : std_logic_vector( 0 to 7):="10101100";
..
process(clk,data)
if(clk'event and clk='1')then --rising edges of clk
data<="ZZZZZZZZ"; --high Z
if(data=pattern_x)then --if pattern_x is at the bus, its time to
overwrite it with the byte i want
data<="11110000"; --after this rising edge
end if;
end if;
Then, it seems to me that i must keep bus hold because it may help me
to keep the xilinx data at the bus as explained below at ds049.pdf
Xilinx datasheet.
"The bus-hold feature eliminates the need to tie unused pins either
High or Low by holding the last known state of the input until the
next input signal is present."
To Falk:
>Do you tristate the output of the CPLD when the writing period to the
bus is
over?
Yes, if i'm not mistaken, the code above let the i/o at tristate
unless it's time to overwrite the bus data.
thanks you both indeed.
Yusuke
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z