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I used this a year a go to generate software filters. It can also generate a VHDL filter. http://www.digitalfilter.com/dfa.html Ralph "Bob" <stenasc@yahoo.com> wrote in message news:20540d3a.0210280751.7efb8790@posting.google.com... > Hi. > > I want to create a filter on an FPGA. The filter is a 25 tap FIR. It > is to be used for an audio application. What kind of chip resources > ie no. of flops > would this use. Is it possible to use existing C code for a DSP to > implement this? > > Thanks for your help > > BobArticle: 49026
Hi, The max3000 family is indeed supported in Q2WE and so is ACEX (no constrains on denisties). What is more important is that the new Cylone family is completly supported. (The lowest cost FPGA ever according to Altera). It is the realy big FPGA's that is not supported and when designig a big Stratix or APEX2 you will porobly any way need the extra features you getting for that 2000$ your paying for a full blown version of quartus. I do agree with Karl about MaxPlus2, the time has passed when there was preformance benifits in the MAX familys to use MaxPlus2 according to Alteras benchmarks. Cheers Fredrik Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3DBEDDC8.7010209@dplanet.ch>... > Oh no, to the contrary. > They don't have the Max3000 family on the webedition of Quartus2. > That to convince the users to get the the professional version for > 2000$US. The pro version does support Max3000. > The same with APEX1k, I think. > Call it politics. > Anyway, both together cover the lower end. > > Rene > > Karl de Boois wrote: > > You don't wanna use the families that are not supported by QuartusII ! The > > main reason for using MAXPlus2 would be the relaxed system requirements for > > your workstation. > > > > Karl. > > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > > news:3DBD9B6A.5030508@dplanet.ch... > > > >>Not all families are supported by the web edition. > >>For some the MaxPlus2 is required. > >> > >>Rene > >> > >>Fredrik wrote: > >> > >>>Hi, > >>>There is a learning curve but it is no big think to get used to > >>>Alteras software. There is indeed a free version of QuartusII avalible > >>>called QuartusII Web Edition, this software supports all familys but > >>>not all densities. Full information is avalible on Alteras Web. > >>>Cheers > >>>Fredrik > >>>"Soul in Seoul" <Far@East.Design> wrote in message > >> > > news:<3dbcedf0$1@news.starhub.net.sg>...Article: 49027
Answered my own question: Atmel AT17LV256A-10PC "scd" <scd@nospam.com> wrote in message news:CWIv9.2785$V15.288656@newsread2.prod.itd.earthlink.net... > Hi, > > I'm looking for a recommendation for a serial EEPROM > to use to program an Altera 1k100. I prefer an 8-pin DIP > package that is pin-compatible with the Altera EPC1PC8. > > Thanks, > ScottArticle: 49028
scd napisal(a): >Answered my own question: Atmel AT17LV256A-10PC A few weeks ago my Atmel dealer told me there was no such a chip - only PLCC. IIRC I found 17256A on the Atmel web page and then asked dealer a question. >> I'm looking for a recommendation for a serial EEPROM >> to use to program an Altera 1k100. I prefer an 8-pin DIP >> package that is pin-compatible with the Altera EPC1PC8. -- Pozdrowienia, Marcin E. Hamerla "If we can put a man on the moon, we can build a computer made entirely of recycled paper"Article: 49029
Falk Brunner wrote: > "Patrik Eriksson" <patrik.eriksson@netinsight.net> schrieb im Newsbeitrag > news:3DBEB12F.50504@netinsight.net... > >>Hi >> >>I wonder if it there is any internal generated clock inside the >>Virtex-II devices that I could use to clock a register. The XC4000 had a >>component called OSC4 that could be used internal. Is it possible to >>connect to the CCLK from within the Virtex-II? I need this during system >>initialization. >> > > No, there is no such internal clock. > Why do you need this? The device is fitted on a hot swap board and the board/device should indicate that it is "ready" before any signals are applied to the board, including the system clock (stupid but true). Before the device should signal ready I would like to perform some reset/setup sequences and therefore I need this clock. One way to do this is maybe to apply a patch to the board that connects the CCLK output to an input and use this clock signal. I think it is possible to force the clock to stay active after configuration. /Patrik -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 49030
Hi NG, I'm looking for a data sheet of the above mentioned pld. This chip is obsolete, so altera download support for it is no longer available :-( I had found some ic's in a old network router and would like to play around with them. Could you tell me in addition to this if this pld is one time programmable or in flash technology. Would be nice to get some hints on it. Many thanks in advance Markus ============================================ Markus Wolfgart DLR ============================================ PS.: remove the xx_ from email adr. to reply ============================================Article: 49031
Hello, I'm doing some research on the Microsoft 68HC11 Chip. I have no prior experience with using Handel-C or FPGA. I'm really stuck. Does anyone out there have coding in Handel-C for either this particular chip or any other similar chip. I would really appreciate it. Thank you JaneArticle: 49032
I think you have to check the Altera webpage on this: http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html Both MAX3000A & ACEX 1K families are fully supported by the Web Edition. Bye, Karl. Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3DBEDDC8.7010209@dplanet.ch>... > Oh no, to the contrary. > They don't have the Max3000 family on the webedition of Quartus2. > That to convince the users to get the the professional version for > 2000$US. The pro version does support Max3000. > The same with APEX1k, I think. > Call it politics. > Anyway, both together cover the lower end. > > Rene > > Karl de Boois wrote: > > You don't wanna use the families that are not supported by QuartusII ! The > > main reason for using MAXPlus2 would be the relaxed system requirements for > > your workstation. > > > > Karl. > > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > > news:3DBD9B6A.5030508@dplanet.ch... > > > >>Not all families are supported by the web edition. > >>For some the MaxPlus2 is required. > >> > >>Rene > >> > >>Fredrik wrote: > >> > >>>Hi, > >>>There is a learning curve but it is no big think to get used to > >>>Alteras software. There is indeed a free version of QuartusII avalible > >>>called QuartusII Web Edition, this software supports all familys but > >>>not all densities. Full information is avalible on Alteras Web. > >>>Cheers > >>>Fredrik > >>>"Soul in Seoul" <Far@East.Design> wrote in message > >> > > news:<3dbcedf0$1@news.starhub.net.sg>...Article: 49033
My license is expired, it could have changed. Rene Karl wrote: > I think you have to check the Altera webpage on this: > > http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html > > Both MAX3000A & ACEX 1K families are fully supported by the Web Edition. > > Bye, Karl. > > Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3DBEDDC8.7010209@dplanet.ch>... > >>Oh no, to the contrary. >>They don't have the Max3000 family on the webedition of Quartus2.Article: 49034
Ok, YAFPB (Yet another FPGA prototyping board), so lets write about the differences: The FPGA is ACEX 1K50TC144 the newest (available) 'low cost' chip from Altera, supported by their free version of Quartus and Max+Plus. 512 KB flash (Am29LV040B) and 128 KB ram are on board. The flash can be used to store conifguration data (and application data) for the FPGA. A small PLD (EPM7032) can configure the ACEX from flash (in PPA mode). No switches, LEDs but serial line driver and watchdog. All what's needed to build a cpu module (I'm using it with JOP a Java processor core). The periphery is connected to the board the other way round. The board has the connectors (female) on the bottom side. So it can be used a a module (60mm x 48mm) being part of a larger board with the periphery. The link: http://www.jopdesign.com/board.html Comments, flames and suggestions are welcome Martin SchoeberlArticle: 49035
Hi Gary
garys@altera.com (Gary Sugita) wrote in message news:<a2058d2c.0210291941.371a89c7@posting.google.com>...
> Hi Stephen,
>
> Without seeing your .ESF file itself it is hard to definitely pinpoint
> the problem However, here are some questions and suggestions.
>
>
> 1) Have you tried to move the regions at all through TCL? You mention
> this later on in your posting (just changing the ll_origin assignment
> does NOT refresh the node locations. Currently this must be done
> through the GUI). Changing the LL_ORIGIN statement through TCL is an
> almost sure-fire way to break things.
I noticed this. Here is a way I figured out to move LogicLock regions
from a Tcl script.
. Import the existing logicLock regions from .esf files
. For the ones you need to move :
. create a new region of the same size that the one you need
to move (fixed size)
. set the position of the new region (fixed position)
. use this region as a parent for the one you want to move.
This way the fitter moves the region to the right place and the cells
are inside. This method isn't very elegant but it works.
> 2) Have you tried changing the LL_PARENT assignment through TCL?
> Changing the parent may require the region to be moved. The GUI knows
> how to handle this, but the TCL interface does not. As a result, some
> regions may not be within their parent region. This will also
> generate messages like the ones you are seeing. Again, do not change
> the LL_PARENT from TCL.
Changing the LL_PARENT seems to work when I first import the region
and then change the assignment. I got the results I expected when I
opened the project from the gui. I guess it works because the regions
are converted to FLOATING and moved to the right place by the fitter.
> 3) It is always a good idea to have registered boundaries between
> modules.
I did.
> Some things you can check to help you narrow down what is going wrong
> are:
>
> 1) Use the GUI to do the same steps that you are trying to do from
> TCL. Does it work there? (if it does, I would guess that your
> problems are related to number 1 or 2 above) Do the regions show up
> RED in the Logiclock Window after you import them? Or does everything
> look okay and you still get these error messages when compiling? (in
> this case I would say #3 above is part of your problem)
>
> 2) Use the GUI in the lower level to see if the regions are okay (ie
> all nodes are within the region boundaries)
>
I followed your advice. It seems that things become difficult at the 3rd
level of imbrication. Some of the cells, but not all, are moved outside
lower level regions. They are still inside the parent region but not any more
in the child region.
>
> On a side note, here are some comments about your methodology:
>
> You say that multiple people are working co-operatively on this
> design. I assume that you need the TCL script because people may
> change the placement of lower level modules and you want to have an
> automatic merge and update of the top-level design.
Right. I also want them to be able to integrate their modifications
without my help. For exemple we have a person working on a memory
controller which interacts with the rest of the design. During the
debug phase he often changes his code. To recompile he only has to run the
makefile, without knowing to much about how quartus works. So he
could focus on his design.
Doing things on a makefile / script basis make it possible to reproduce
the same result on each resynthesis. Using the gui people often didn't
remember what they did and where unable to know why things worked yesterday
and not today.
> I would recommend you go about doing this as follows:
>
> Do your initial merge using the GUI. Do your importing, moving,
> changing parents etc. all through the GUI the first time. Now that
> you have a "good" top level design where everything works and makes
> sense, you are are ready to use the TCL script to "update" any of the
> regions that need changing.
>
> Using the cmp logiclock_import 0 1 0 1 0 "region_name"
> Where region_name is the name of the region you want to update, and in
> your case you would run this command once for every region. This
> command preserves the placement of the region in the top level, and
> the LL_PARENT settings.
>
> With this flow, you can do all of your top-level floorplanning, and
> only update the contents of the regions. As an additional benefit, it
> also eliminates the need to try to move regions around using TCL,
> while only forcing you to use the GUI once.
I changed I bit my aproach because I noticed that compilation times of
intermediate LogicLock level are very long. Here is an exemple : lets
say I have 3 regions AAA AAB AAC which should be grouped together into
region AA. There are almost no more LE than the ones contained in
AAA AAB AAC. So, as the position of almost every LE is known fitting of
AA should be very fast. This is not what happens. I guess the reason
it that quartus redoes the routing each time. As the result of the routing
couldn't be locked down things are redone at every level, right ?
So now I only create the lowest level logic lock regions (AAA ...)
and I directly place them into the top level. This is much faster than
creating the regions AA and A first. This way the others problems also
disappear.
Here is an other question. Is there a way to lock down the routing or is
it redone in every case. If for exemple only one (small) LogicLock region
changes is quartus redoing the hole routing ? Is there a way to only change
the content of a ROM without redoing a complete fit ?
Thank you very much for your help
Stephen
>
> Hope this helps.
>
> -Gary Sugita
>
>
>
> stephen.busch@web.de (stephen) wrote in message news:<6643d19f.0210240712.62595be2@posting.google.com>...
> > Hi,
> > I'm using the LogicLock design flow to incrementally place and route
> > a design on a APEX1500KE device. Several people work on the project
> > and I
> > need to automate the compilation flow, so everything is done with tcl
> > scripts.
> >
> > I followed the instructions from Altera but I still have some
> > problemes. The structure of the design is something like this :
> > top +-- A
> > | +--- AA
> > | +--- AB
> > | +---ABA
> > | +---ABB
> > +-- B
> > | +--- BA
> > | +--- BB
> > | +---BBA
> > | +---BBB
> >
> > Here is what I do :
> > . I generate a edf file for each module (AA, BA, ABA, ABB, BBA, BBB)
> > with Leonardo.
> > . I run quartus for each submodule (AA, BA, ABA, ABB, BBA, BBB) to
> > generate the esf and vqm files. Each submodule contains one or
> > more
> > LogicLock regions.
> > . to generate the esf and vqm file of bloc AB I use the vqm and esf
> > files
> > generated for ABA and ABB plus an additional edf file. To enforce
> > the
> > hierarchie I use the LL_PARENT assignment. I change this
> > assignment
> > after importing the lower level .esf files, otherwise it doesn't
> > work.
> > ...
> > . for the final place and route I use the files A.vqm A.esf B.vqm
> > B.esf and
> > top.edf. The LogicLock regions defined are visible and have the
> > correct
> > size at the top level. The position is chosen automaticly by
> > quartus
> > for the moment.
> >
> > For the lower levels everything is fine but I get some problems at the
> > top
> > level. I get a lot of messages like the one :
> > Warning: Ignored back-annotated location assignment on node
> > bmicro:bmicro_inst|i2c:i2c_enabled_i2c_inst|i2c_intermediaire:i2c_intermediaire_inst|i2c_reste:reste|modgen_eq_445_ix46~I_I
> > assigned to LogicLock region
> > i2c_i2c:i2c_enabled_i2c_inst_bmicro:bmicro_inst because location is
> > outside region boundaries
> > How could this happen ? At the lower levels all the cells where inside
> > the
> > logiclock region and I didn't get the message. For the moment I didn't
> > try
> > to move manually the regions.
> >
> > Quartus also complains about carry chains it couldn't place inside a
> > low level
> > logiclock region. But I didn't get this message when it fitted this
> > region or
> > the next higher level.
> >
> > My next problem is that I need to chose the position of the logiclock
> > regions
> > because of timing issues. I can do this using the quartus gui but I
> > want to
> > move them from a tcl script. When I only change the LL_ORIGIN
> > assignment
> > the LL_LOCATION assignments aren't updated. Does anyone know which
> > command
> > I need to run ?
> >
> > thanks for you help
> > stephen
Article: 49036
Dear all,
I am looking for an FPGA prototyping board with
the Virtex-II implemented.
My requirements for a board are blow.
* it's not so expensive(hence smaller Virtex-II than XC2V250)
and to develop with ISE WebPack
* I can access as many usable FPGA I/Os as possible
via on-board pin headers(which have its space of 100mil)
* I can select vcco voltage arbitrarily(especially for LVDS standard)
*A oscillator is installed which is in form of PLL or crystal
with socket mounted for various frequency generation.
Anyone who has any information please let me know.
Sincerely,
Hironobu Takemae
Article: 49037Hi Xanatos, I wasn't able to find the tag you talked about. For the moment I use the option "-hierarchy preserve" when I run the optimize command. Is this the same thing ? All my outputs are already registered. The carry chain problem I got is about an aritmic operation inside a module. Thanks for your help, Stephen "Xanatos" <fpsbb98@yahoo.com> wrote in message news:<29_t9.61531$mxk1.39083@news04.bloor.is.net.cable.rogers.com>... > Hi Stephen, > > I've had problems simular to what you have. One thing I suggest is that you > put in the hierarchy=hard tag into Leonardo around the top level modules. > > The other problem that you may have with the carry chains is some > combinational signal that is the output of one module going into another. > Older version of Quartus did not allow that. Make sure your outputs are > registered. > > Cheers, > Xanatos > > "stephen" <stephen.busch@web.de> wrote in message > news:6643d19f.0210240712.62595be2@posting.google.com... > > Hi, > > I'm using the LogicLock design flow to incrementally place and route > > a design on a APEX1500KE device. Several people work on the project > > and I > > need to automate the compilation flow, so everything is done with tcl > > scripts. > > > > I followed the instructions from Altera but I still have some > > problemes. The structure of the design is something like this : > > top +-- A > > | +--- AA > > | +--- AB > > | +---ABA > > | +---ABB > > +-- B > > | +--- BA > > | +--- BB > > | +---BBA > > | +---BBB > > > > Here is what I do : > > . I generate a edf file for each module (AA, BA, ABA, ABB, BBA, BBB) > > with Leonardo. > > . I run quartus for each submodule (AA, BA, ABA, ABB, BBA, BBB) to > > generate the esf and vqm files. Each submodule contains one or > > more > > LogicLock regions. > > . to generate the esf and vqm file of bloc AB I use the vqm and esf > > files > > generated for ABA and ABB plus an additional edf file. To enforce > > the > > hierarchie I use the LL_PARENT assignment. I change this > > assignment > > after importing the lower level .esf files, otherwise it doesn't > > work. > > ... > > . for the final place and route I use the files A.vqm A.esf B.vqm > > B.esf and > > top.edf. The LogicLock regions defined are visible and have the > > correct > > size at the top level. The position is chosen automaticly by > > quartus > > for the moment. > > > > For the lower levels everything is fine but I get some problems at the > > top > > level. I get a lot of messages like the one : > > Warning: Ignored back-annotated location assignment on node > > > bmicro:bmicro_inst|i2c:i2c_enabled_i2c_inst|i2c_intermediaire:i2c_intermedia > ire_inst|i2c_reste:reste|modgen_eq_445_ix46~I_I > > assigned to LogicLock region > > i2c_i2c:i2c_enabled_i2c_inst_bmicro:bmicro_inst because location is > > outside region boundaries > > How could this happen ? At the lower levels all the cells where inside > > the > > logiclock region and I didn't get the message. For the moment I didn't > > try > > to move manually the regions. > > > > Quartus also complains about carry chains it couldn't place inside a > > low level > > logiclock region. But I didn't get this message when it fitted this > > region or > > the next higher level. > > > > My next problem is that I need to chose the position of the logiclock > > regions > > because of timing issues. I can do this using the quartus gui but I > > want to > > move them from a tcl script. When I only change the LL_ORIGIN > > assignment > > the LL_LOCATION assignments aren't updated. Does anyone know which > > command > > I need to run ? > > > > thanks for you help > > stephenArticle: 49038
Hi Stephane,
I had problems similar to your using leonardo together with quartus.
In leonardo it is posible to integrate the generics into the entity
name.
This is usefull because for synthesis all generics have to be defined.
So if you have a module used in the same design with different generic
values it can distingish them. Exemple you have and entity add, one
for
10 bits and the other for 20 bits. It both are called add things would
get mixed up. So he will call them add_10 and add_20.
The problem is leonardo doesn't use the same conventions. It expects
the lpm_ram_dp to be called lpm_rm_dp and not
lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED
So there are 3 solutions :
. create custom variations of the lpm with the rigth name
. disable this naming convention in leonardo. The flags are
set append_generics_to_toplevel "TRUE"
set append_generics_to_blackbox "FALSE"
. create wrapper (.vhd) files to rename the modules. This is usefull
if you use a large
number of variations and you dont want to do it with the GUI
Hope this helps,
Stephen
"Mancini Stéphane" <stephane.mancini@inpg.fr> wrote in message news:<apjq7j$qco$1@new-news.grenet.fr>...
> Hi all,
> I'm in trouble with leonardo : I have a design
> in vhdl which instanciates lpm functions such as lpm_ram_dp
> and I would like to synthesize it with leonardo for the APEX20Ke
> technology.
> The problem is that it seems that leonardo doesn't recognize those
> primitives : it generates black boxes with name such as :
> lpm_ram_dp_REGISTERED_REGISTERED_8_tp_tperg4_tperg4lf_stephane_nios_essai_soft_onchip_memory_0_lane1mif_UNREGISTERED_8_USE_EAB_ON_REGISTERED
>
> wich can't be read by the P&R quartus.
> So, my question is :
> Do I have to :
> 1) configure leonardo to directly synthesize lpm megafunctions (how ?)
> 2) tell leonardo not to change the name (ie keep lpm_ram_dp) by not adding
> generic parameters (how ?)
> 3) Not synthesize entities containing lpm (but somes are in an ugly generated code)
> 4) other ?
>
> thanks very much for your help . I'm on it for a long time now
> and I'm getting mad.
>
> Thanks a lot.
>
> Stephane
Article: 49039Hi, has anybody tried a 2-nios parallel design using SOPC builder? I am trying to build one which can run separate pieces of code concurrently. Any comments would be helpful. thanks, regards, SatchitArticle: 49040
Hello Altera has started shipping a new DSP Development Kit. The board contains a large Stratix 1S25 FPGA and 2 channel 12-bit, 125 MSPS A/D, 2 channel 14-bit, 165 MSPS D/A. The kit also contains a copy of Quartus, DSP Builder (the Matlab Simulink to Quartus interface) and a 30 day eval of Matlab/ Simulink. The price is $1995. Regards Justin Cowling Director IP Marketing Altera ____________ Michael Hosemann <hosemann@ifn.et.tu-dresden.de> wrote in message news:<aparjd$nrl$1@rks1.urz.tu-dresden.de>... > hello, > > we are looking for a board with one or more FPGAs which will be used to > implement a first version of a DSP chip we are currently designing. > > Since the chip will be fairly large in terms of gates and memory ( around > 2MBit), only the latest Xilinx Virtex II or Altera Stratix will do. > > We found a series of boards from avidda on the altera webpage. These boards > have a PCI connection which would help us a lot getting the data on and off > chip since we wouldnt have to build our own hardware around it > > Does anybody already have experience with such boards, avidda and others? > > All comments and sugestions are appreciated. > > Michael HosemannArticle: 49041
>I'm doing some research on the Microsoft 68HC11 Chip. I have no prior >experience with using Handel-C or FPGA. I'm really stuck. Does anyone >out there have coding in Handel-C for either this particular chip or >any other similar chip. I would really appreciate it. There is a free 68HC11 VHDL core, (not Handel-C...) available from Green Mountain Computing Systems: http://www.gmvhdl.com/hc11core.html Literature for the 68HC11 can be freely downloaded from Motorola. Roberto WaltmanArticle: 49042
"Roberto Waltman" <bad.address.to.avoid.spam@bellatlantic.net> wrote in message news:n380suceh7eej3d7vmfhda1omlipvkelfp@4ax.com... > >I'm doing some research on the Microsoft 68HC11 Chip. I have no prior > >experience with using Handel-C or FPGA. I'm really stuck. Does anyone > >out there have coding in Handel-C for either this particular chip or > >any other similar chip. I would really appreciate it. > > There is a free 68HC11 VHDL core, (not Handel-C...) available > from Green Mountain Computing Systems: > > http://www.gmvhdl.com/hc11core.html Hi, For what is is worth, I have played with the Green Mountain device and it works fairly well. Their clock generator is not synthesisable, but the remainder of the code is. The clock generator is quite easy to code in a synthesizable fashion. Theron > > Literature for the 68HC11 can be freely downloaded from Motorola. > > > > Roberto WaltmanArticle: 49043
Hello folks, I am seeking some (very) introductory doc on FPGA concepts and some popular and novel applications of FPGAs, progressing upward (or downward) in complexity. Need a hand-holding from high-level concepts, right down to programming techniques and tools - and the full process (obtaining the FPGA, installing it, testing it (simulations?), supporting circuitry, development, etc.). Yeah, I know, but I'm betting that some folks out there have some great resources. Thanks much. Sincerely, -- VirtualSeanArticle: 49044
This sounds like a good question for Altera. My guess is that powering VCCINT will be enough to maintain state, HOWEVER, you may end up indirectly powering the VCCIO bus anyway from inside the chip, so you'll still pull a lot of current if your I/Os are driving pins on other unpowered chips. You may have to do the big thing and power the board but just stop the clocks (assuming a CMOS board). That FPGA core probably represents your largest leakage current source anyway. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- satishkmys@yahoo.com (Satish K) wrote in message news:<380e8c67.0210290155.4f709999@posting.google.com>... > Dears, > I am implementing RAM in ACEX device ALTERA. We wants to know > whether written data into EAB is retained when vccio supply > fails, Can we avoid the data loss by having Supply backup for only > vccint . (nINIT_CONG pulled to vccint.). > > Explained below > > After writing memory initialize data into EAB during power on > configuration, later I have loaded application data into EAB. > This application data has to be retained , when ever there is power > failure. > > Now the question is , whether vccint supply voltage is sufficient > as backup power supply to retain memory data or both Vccint & > Vccio are required to hold memory data . > > please help me in deciding ,for adverse conditions. > > -Satish KArticle: 49045
You might want to use the floor plan editor to check and see if your reset is REALLY using the global buffer. President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "fpga admirer" <> wrote in message news:<ee79ec7.1@WebX.sUN8CHnE>... > Thanks for the reply... I am working with a design that was done for an XC4062XL (I know, I know prehistoric but no option to upgrade). This chip has 8 BUFGs available that can be used for clocks or other signals according to the library guide. Two of the BUFGs were being used for clocks. I instantiated a BUFG primitive to get their GlobalReset signal off of the logic routing resources but with this change... the design seems dead.Article: 49046
Petter, I think I understand, however the devices of interest are 17S200A in 8-pin DIP and are not JTAG devices. While I have no objection to using the 18V family, they're bigger packages only and won't fit the socket on my development board. Thanks, -rajeev- ----------------- Petter Gustad <newsmailcomp3@gustad.com> wrote in message news:<87fzuqcqq4.fsf@filestore.home.gustad.com>... > rrr@ieee.org (Rajeev) writes: > > > One question, Petter, I use the parallel cable all the time for JTAG > > download to my test FPGA, and also for ChipScope... but I don't know how > > If the SPROM is in the same scan chain as your FPGA you will only need > to generate MCS files and change your impact configuration. > > > to go about using it to program the SPROM. Is there an AppNote or something > > that explains how to do this... or where should I start my learning ? Will > > I also need to write some software ? > > See article: > > http://groups.google.com/groups?safe=images&ie=UTF-8&oe=UTF-8&as_umsgid=87smyva5qd.fsf%40filestore.home.gustad.com&lr=&hl=en > > > PetterArticle: 49047
global reset should be done with a STARTUP component, not a BUFG. fpga admirer wrote: > Thanks for the reply... I am working with a design that was done for an XC4062XL (I know, I know prehistoric but no option to upgrade). This chip has 8 BUFGs available that can be used for clocks or other signals according to the library guide. Two of the BUFGs were being used for clocks. I instantiated a BUFG primitive to get their GlobalReset signal off of the logic routing resources but with this change... the design seems dead. >Article: 49048
Michael Van Oostende wrote:
> I recently bought a Spartan II 2S200 PCI card. The application we want to
> use it for, will be designed under linux and so will have to work under
> linux. I'm having difficulties to get the card running. I found sourecode
> for this driver, but it's for windows only, so a lot of header files can't
> be used properly.
>
> Can somebody help me to find a working linux driver for this card (or for
> a similar card, which i can change untill it works for me)?
>
> kind regards,
>
> Michael Van Oostende
> Suminvent - Belgium
Quick notes: What you need to do is probably something like.
* Downloading fimware to PCI board (in this case your code)
The problematic part here might be - does it behave as a PCI board directly
after power on. Or is that part too necessary to download?
There are other devices that needs to download firmware at startup.
Look at sound cards (alsa driver for rme9652)
and network cards (acenic, ...)
/RogerL
--
Roger Larsson
Skellefteå
Sweden
Article: 49049<insert neophyte question> What is "clock edge"??? Anyone care to take a moment to enlighten the unwashed? Thanks much. -- VirtualSean
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