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Which Altera device are you targeting?
Anyhow, here is how you do it for FLEX10KE/ACEX1K.
Create a file called "Your_Project_Name".esf or
"Your_Top_Entity_File_Name".esf.
In it, copy the following text.
_____________________________________________________
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
Your_Input_Pin : FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS = ON;
Your_Input_Pin : FAST_INPUT_REGISTER = ON;
Your_Output_Pin : FAST_OUTPUT_REGISTER = ON;
}
_____________________________________________________
The setting you are looking for is FAST_OUTPUT_REGISTER option which
allows an output FF to get pushed into an IOE, but when you do that, you
won't be able to use FAST_INPUT_REGISTER option for that pin because
FLEX10KE/ACEX1K IOE has only one FF.
Other than that, you need to know that output register has to have
fanout of 1 to get pushed into IOE with no feedback.
In order to have feedback, you need to get the synthesis tool to
duplicate the output FF.
Also, an IOE FF cannot be asynchronously reset (It can only be
asynchronously set.).
If the output FF has to be asynchronously reset, you have to use a
regular FF.
If you want more information about FAST_OUTPUT_REGISTER, do a search of
Quartus II's Help with FAST_OUTPUT_REGISTER as the keyword.
Although you didn't ask for it, you may want to also know about
an option called FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS that
decreases input pin delay significantly (The delay decreases by about
75%.).
That option might be relevant to you in case you are struggling with
setup time issues.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
momo wrote:
>
> Hi all
>
> I'm designing LCD Controller using ALTERA Quartus Ver2.1.
> I want to assign output FF signal to IOE register by Quartus Ver2.1.
> However, I don't know how to assign using this software.
Article: 48476
lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0209241840.48fb73e9@posting.google.com>...
> meet PCI 2.2 spec
Here are the reasons why I don't recommend using
FLEX10KE/ACEX1K for PCI.
1) Altera's fitter for FLEX10KE/ACEX1K is flaky
Altera's fitter does a pretty poor job of meeting setup time
timings, and usually meeting the setup time is the hardest part of
developing a PCI IP core.
To Altera's credit, Altera fitter does a good job of maximizing fmax,
but since meeting fmax of 33.3MHz isn't too hard with most recent
FPGAs, that's not a big deal.
However, I have seen so many cases of questionable automatic
placements that wastes several ns (2ns to 3ns) in routing delay . . .
Since 33MHz PCI's setup time is only 7ns, if 2ns to 3ns is being
wasted in routing delay between two LUTs then that will make it pretty
hard to meet the setup time requirement because you still need to
consider other delays like input pin delay, LUT delay through multiple
LUTs (usually 3 to 4 LUTs), FF setup time, and the routing delay
between logic resources (i.e., input pin to LUT, several LUT to LUT,
LUT to FF.).
2) The Altera floorplanner is broken
The thing I don't like about Altera floorplanner is that even
if I place a certain LUT to a certain LAB, sometimes the fitter will
duplicate the LUT for some reason, and when the LUT is duplicated, the
placement information gets ignored by the fitter.
For example, if a LUT called ix7342 gets duplicated as ix7342~1 by the
fitter, the fitter will ignore ix7342's placement information when
placing ix7342~1.
That problem pretty much makes the Altera floorplanner useless.
3) FLEX10KE/ACEX1K has only one FF per IOE
Unlike Xilinx Spartan-II, FLEX10KE/ACEX1K has only one FF per
IOE, which means that you can use the IOE FF as an input FF or an
output FF.
When using IOE FF as an output FF, you need to be worried with the
fitter satisfying PCI's requirement of Thold <= 0ns for the input FF.
When using IOE FF as an input FF, you need to be worried with where
the fitter is going to place the output FF, so that Tval < 11ns will
be met.
I have often seen the fitter placing output FF really far away from
the pin that the output FF did not meet 33MHz PCI's Clock-to-Output
(Tval or Tco) requirement of < 11ns.
4) FLEX10KE/ACEX1K doesn't allow an active low FF to be pushed into an
IOE
This problem basically means output FF of PCI control signals
(i.e., FRAME#, IRDY#, DEVSEL#, TRDY#, STOP#, PERR#, REQ#, etc.) cannot
be pushed into IOE because they need to be high (1) when RST# is
asserted.
The reason for that is because FLEX10KE/ACEX1K IOE FF doesn't support
asynchronous preset (Only supports asynchronous reset.).
Yes, you can use regular FFs, but then Tval will be unpredictable.
While I did trash Altera FLEX10KE/ACEX1K pretty badly, it is
not impossible to do PCI with FLEX10KE/ACEX1K since Altera has a PCI
IP core that runs at 66MHz. (But Altera PCI IP core with bus master
costs $9,000 I am told.)
However, the point I am trying to make here is that the learning curve
of doing PCI with Altera FLEX10KE/ACEX1K will be far steeper compared
Xilinx Spartan-II because Spartan-II doesn't suffer from any of the
problems I just mentioned (P&R is much better than Altera, P&R doesn't
duplicate a LUT even when the placement location is specified by the
floorplanner, has three FF per IOB, and supports asynchronous
preset.).
On top of that, you still need to develop a PCI IP core and understand
the PCI protocol which take time.
If you want a PCI development card right now, you may want to get
Insight Electronics Spartan-II 200 PCI Development Kit which costs
only $250.
You can use ISE WebPACK and ModelSim XE-Starter for development.
Other than that, I also have to say that Altera only
guarantees -1 speed grade ACEX1K to comply with 5V PCI electrical
specification (According to their datasheet.), ACEX1K -3 speed grade's
tLUT is much slower than -1 speed grade (I believe it is 1.1ns vs.
0.7ns.), and EP1K30 is pretty small (Consider using EP1K100 if you
still want to stick with Altera which I don't recommend.).
Finally, I don't work for Altera's competitors or the
competitors' distributors, I am not short selling Altera's stock right
now, and I don't own shares of other PLD firms (Who wants to own them
when Nasdaq is tanking pretty fast. Whoever owning shares of
technology companies should trash them or consider short selling them
now because they are tanking pretty fast.).
All the comments I made comes from my own bad experiences dealing with
FLEX10KE/ACEX1K.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 48477
steen@tech-forge.com (Steen Larsen) wrote in message news:<3e8d96d6.0209261303.2163efb2@posting.google.com>...
>
> I am finishing a PCI 33MHz board (www.tech-forge.com) with two layers
> and have not seen much of a power decoupling problem. (Plenty of
> design problems though!)
>
>
> Good luck,
> -Steen
Steen,
While I have never designed a printed circuit board, PCI specification
seems to imply that you need to use at least a 4 layer PCB.
Also, looking at the picture of the PCI card you designed, your PCI
card doesn't seem to have any high-speed ceramic capacitors near the
edge connector in which the specification says you need to have.
Another thing I will say from my experience of developing a
PCI IP core is that perhaps the use of an Altera device is not
terribly a good idea for PCI.
Looking at your PCI card, you are using a FLEX10K30E-3 which is the
slowest FLEX10KE available.
Not only that particular part of FLEX10KE is not guaranteed to meet
PCI's V/I curve (You need a speed grade -1 FLEX10KE part to meet 5V
PCI's V/I curve according to FLEX10KE datasheet.), but also I will bet
you that with FLEX10K30E-3, your PCI interface probably won't meet the
setup time requirement of Tsu < 7ns that easily unless you heavily
floorplan it because FLEX10K30E-3's 4-input LUT's delay (tLUT) is
already at 1.1ns, and some unregistered signals usually have to pass
through 3 to 4 levels of 4-input LUT before reaching a FF. (Also, you
have to add the interconnect delay between LUTs which is very
unpredictable in Altera FLEX because the fitter is so flaky, input pin
delay, and FF setup time.)
The problem I had with Altera floorplanner is that even if I place a
certain LUT to a certain LAB, often the fitter will duplicate the LUT
for some reason, and when the LUT is duplicated, the placement
information gets ignored. (i.e., ix7342 gets duplicated as ix7342~1 by
the fitter. The fitter will ignore ix7342's placement information when
placing ix7342~1.)
That problem pretty much makes the Altera floorplanner useless.
Besides the Altera floorplanner problem, Altera's fitter does a pretty
poor job of meeting setup time timings, and usually meeting the setup
time is the hardest part of developing a PCI IP core. (To Altera's
credit, Altera fitter does a good job of maximizing fmax, but since
meeting fmax of 33.3MHz isn't too hard with most recent FPGAs, that's
not a big deal.)
Personally, I have used Xilinx Spartan-II to test my PCI IP
core, and unlike when I ported my PCI IP core to Altera
FLEX10K100EFC484-1 (tLUT = 0.7ns), Xilinx's software (ISE WebPACK) met
Tsu < 7ns without having to use the floorplanner.
Meeting Tval < 11ns and Thold <= 0ns requirement of PCI was also much
easier with Spartan-II than FLEX10KE because unlike FLEX10KE IOE which
has only one FF, Spartan-II IOB has three FFs for input, output, and
tri-state control.
If you still want to stick with Altera which I don't recommend, you
may want to consider using ACEX 1K instead which is much cheaper than
FLEX10KE, but essentially has the same features FLEX10KE has.
I hate to be a nay-sayer, but since Insight Electronics sells
a well constructed Spartan-II XC2S200-based PCI prototype card with
8MB of SDRAM for $250, I am not sure how many people will buying your
2 layer PCB-based PCI card with FLEX10K30E-3 without external SDRAM
even if you give out the a PCI IP core for free.
My suggestion will be that you may want to use 4 layer PCB, use a
larger ACEX1K (Consider using ACEX1K EP1K100-1 if you want to stick
with Altera.), have an SDRAM SO-DIMM slot, and have an expansion
connector just like what Insight Electronics Spartan-II PCI card has.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 48478"Phil Hays" <SpamPostmaster@attbi.com> wrote in message news:3DAF9855.62FB10E8@attbi.com... > Brijesh wrote: > > > The xilinx app note: xapp253 ( DDR SDRAM controller using Virtex II) talks about using HEX lines for low skew routing. Here is the snippet from the app note. > > > > "As described in the Virtex-II data sheet, each I/O tile contains four IOBs that share a switchmatrix.IOB PAD4 is the top IOB in a I/O tile. In order for the DQS to access a local low-skew clock line, DQS must be placed on the top IOB, PAD4 in the I/O tile. If IOB PAD4 is not available in a tile, or is unbonded, then it cannot be used to place the DQS signal. > > > > Placing the DQS signal in PAD4 gives access to a local clock line which is a HEX line spanning > > five rows above the chosen I/O tile and six rows below the chosen I/O tile. The data (DQ) pads > > should be placed in the bonded IOBs available within these specific rows." > > > > Question is > > 1) How does one locate the "IOB pad4: top IOB of an I/O tile" ? > > FPGA Editor. The app note gives information on how to use it to find > the subset of pads that can be DQS pins > > > > 2) We know that 4 adjacent IOB's share the routing resources. > > Word of warning. Remember that some IOBs are unbonded, so there may be > only two bonded IOBs that share routing resources. And remember that > the routing of clocks for DDR is shared between pairs of IOBs even more > closely. These pairs are easy to identify: the name in the pinout > tables shows pairs, for example: IO_L06N_0 IO_L06P_0. > > > > How do we know which four? > > FPGA Editor. > > > > Virtex II data sheets and hand book mention this but do not give any info on how to locate them . > > So where will I find this info. > > If you find a better source, please post it. > > > -- > Phil Hays > Take a look at XAPP266. It's for FCRAM, but still applicable to standard DDR rams, and it was more useful to me than XAPP253 (as I recall). Even with the help of XAPP266, it took me and our local Xilinx FAE several hours to get the IOB selection correct for all the blocks of 8 DQ's and their associated DQS line. I believe that the FAE had to consult the factory, too. It took a lot of work in FPGA editor, and some test code runs to confirm that we were assigning the IOB's properly. Too hard, Xilinx! I think that this is one area that Altera has an advantage with their new line of FPGA's. I don't use them myself, but I've been told that they directly support the DQS lines for ram read operation. I hope Xilinx is listening (Peter, Austin?). Also, be aware that you do not have to use the DQS line (for reads) if your data rate is low enough. We're attempting to do DDR333 (167Mhz clock), so we feel that it it's necessary to go through the trouble of using the DQS's to strobe the incoming data into the IOB's, and then a separate/continuous (but sync'd) clock to transfer the data from the IOB flops into CLB flops. The timing of this task is critical, too. BobArticle: 48479
Insight Electronics runs seminars every now and then. If you bought your chip from them, they will help you. Xilinx also has a "University Program". Check it out. If all else fails: http://www.xilinx.com Click on products, then design resources, then free technical lectures SH7 On 17 Oct 2002 20:49:46 -0700, k_guichard@hotmail.com (Kyle Guichard) wrote: >I am a student at SJSU working on my senior project. For this, I will >be creating an FPGA using Xilinx software, but I am really overwhelmed >with the ammount of information on how I can actually do this. > >Can anyone direct me to some good documentation on creating FPGA's >when I have the verilog/VHDL code? > > >thanks! >kyleArticle: 48480
Hi, I want to learn how to access a compact flash card with an FPGA. I have written .wav files from my PC into the card and now I read it out byte by byte. Can anyone give some websites which will teach how to handle the Windows-related aspect in the CompactFlash? Thanks. K. K.Article: 48481
>> It's just like SMP. The hardware is time interleaved rather than replicated. >Yes, I understand that. But when you replicate the hardware, you >replicate *all* of the hardware. I have not heard anyone say that there >are multiple copies of the program counter (PC). If you are working off >one PC how do you switch between the threads on a clock cycle basis? >Additionally, how do you start up a thread? When this multiple thread >CPU starts following reset, each of the threads will need to be running >*something*. How is that managed? Do they all boot the BIOS or >whatever startup code you have? As far as I know, we are just waving our hands here. Nobody has worked out and tested anything. I've been assuming that registers like the PC would get duplicated since that's the only thing that makes sense. How things get started is normally one of those system-specific parts. (aka hacks and kludges) You could do things like smash both PCs to 0 and then read a status register that contained a bit to tell you which CPU you are. Typical SMP initialization code lets CPU 0 do a lot of the work while the rest keep out of the way. But often the each have to setup the local caches. It's a delciate dance, and yes, it is often relegated to the BIOS. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48482
Hi! Is there any (higher level) control mechanism over the two carry chains on these post-flex architectures? In the MAX-PLUS II, there's a CARRY/CASCADE component, that can be placed between any two signals implying that there is a correspondent connection, but this is insufficient for a double chain architecture.Article: 48483
Hey, I'm developing a hardware version of a software algorithm... I've run into a problem where the software algorithm decides to take logs. I have found plenty of power series to approximate the log function, however, these insist that x is between +/- 1. Unfortunately for me, x can range between 0 and 10000000. Does anyone know a good algorithm for calculating logs efficiently, or a different power series without the above limitation. Any suggestions? Please email me. t.nicolson@signal.qinetiq.com Regards, TimArticle: 48484
sok, figured it. just have to represent the number as fp, find the log of the mantissa, then just add the exponent to it. thx anyway. "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote in message news:1034934981.583376@bengal... > Hey, > > I'm developing a hardware version of a software algorithm... > > I've run into a problem where the software algorithm decides to take logs. > > I have found plenty of power series to approximate the log function, > however, these insist that x is between +/- 1. Unfortunately for me, x can > range between 0 and 10000000. > > Does anyone know a good algorithm for calculating logs efficiently, or a > different power series without the above limitation. > > Any suggestions? > > Please email me. > > t.nicolson@signal.qinetiq.com > > Regards, > > Tim > >Article: 48485
sok, figured it. just have to represent the number as fp, find the log of the mantissa, then just add the exponent to it. thx anyway. "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote in message news:1034934981.583376@bengal... > Hey, > > I'm developing a hardware version of a software algorithm... > > I've run into a problem where the software algorithm decides to take logs. > > I have found plenty of power series to approximate the log function, > however, these insist that x is between +/- 1. Unfortunately for me, x can > range between 0 and 10000000. > > Does anyone know a good algorithm for calculating logs efficiently, or a > different power series without the above limitation. > > Any suggestions? > > Please email me. > > t.nicolson@signal.qinetiq.com > > Regards, > > Tim > >Article: 48486
sok, figured it. just have to represent the number as fp, find the log of the mantissa, then just add the exponent to it. thx anyway. "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote in message news:1034934981.583376@bengal... > Hey, > > I'm developing a hardware version of a software algorithm... > > I've run into a problem where the software algorithm decides to take logs. > > I have found plenty of power series to approximate the log function, > however, these insist that x is between +/- 1. Unfortunately for me, x can > range between 0 and 10000000. > > Does anyone know a good algorithm for calculating logs efficiently, or a > different power series without the above limitation. > > Any suggestions? > > Please email me. > > t.nicolson@signal.qinetiq.com > > Regards, > > Tim > >Article: 48487
Hav a look at the datasheet at sandisk(google). Rene Karl wrote: > Hi, > > I want to learn how to access a compact flash card with an FPGA. I have > written .wav > files from my PC into the card and now I read it out byte by byte. > > Can anyone give some websites which will teach how to handle the > Windows-related aspect > in the CompactFlash?Article: 48488
Hi I need to implement a CRC generator polynomial using VHDL. I am using Xilinx Foundation student edition 4.2i software and don't really mind which device it is targeted at - the main objective is familiarity with design and simulation tools. Is it simply a case of describing a series of registers and XOR's to fit my polynomial? -- Cheers! MikeArticle: 48489
Hi Michael, This site (easics) includes a web tool to generate synthesizable VHDL\Verilog CRC functions. It is great. I hope it helps. -- Ulises Hernandez ECS Technology Limited ulisesh@ecs-tech.com "Michael Nicklas" <michaeln@nospam.slayer.com> wrote in message news:aoopch$de9$1$8300dec7@news.demon.co.uk... > Hi > > I need to implement a CRC generator polynomial using VHDL. I am using > Xilinx Foundation student edition 4.2i software and don't really mind which > device it is targeted at - the main objective is familiarity with design and > simulation tools. > > Is it simply a case of describing a series of registers and XOR's to fit my > polynomial? > > -- > Cheers! > > Mike > >Article: 48490
See my quick and dirty log post on comp.dsp
http://www.dspguru.com/comp.dsp/tricks/alg/quicklog.htm. Basically, normalize
your input by left shifting to eliminate redundant leading sign bits, recording
the shift as an exponent as you do. See my previous posts here on how to do
that with a merged tree. Then you can get to 1/2 dB just using a 4 input LUT
to find the log of the mantissa (dropping the leading 1).
Tim Nicolson wrote:
> Hey,
>
> I'm developing a hardware version of a software algorithm...
>
> I've run into a problem where the software algorithm decides to take logs.
>
> I have found plenty of power series to approximate the log function,
> however, these insist that x is between +/- 1. Unfortunately for me, x can
> range between 0 and 10000000.
>
> Does anyone know a good algorithm for calculating logs efficiently, or a
> different power series without the above limitation.
>
> Any suggestions?
>
> Please email me.
>
> t.nicolson@signal.qinetiq.com
>
> Regards,
>
> Tim
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48491Sorry, I forgot the link http://www.easics.be/webtools/crctool Regards, Ulises -- "Ulises Hernandez" <ulises@britain.agilent.com> wrote in message news:1034939553.736708@cswreg.cos.agilent.com... > Hi Michael, > > This site (easics) includes a web tool to generate synthesizable > VHDL\Verilog CRC functions. > It is great. > > I hope it helps. > > -- > Ulises Hernandez > ECS Technology Limited > ulisesh@ecs-tech.com > > > "Michael Nicklas" <michaeln@nospam.slayer.com> wrote in message > news:aoopch$de9$1$8300dec7@news.demon.co.uk... > > Hi > > > > I need to implement a CRC generator polynomial using VHDL. I am using > > Xilinx Foundation student edition 4.2i software and don't really mind > which > > device it is targeted at - the main objective is familiarity with design > and > > simulation tools. > > > > Is it simply a case of describing a series of registers and XOR's to fit > my > > polynomial? > > > > -- > > Cheers! > > > > Mike > > > > > >Article: 48492
The Xilinx software manuals should have a lot of introductory material, but if you are using their ISE software, I would suggest trying the ISE 4 in depth tutorial found on http://support.xilinx.com/support/techsup/tutorials/tutorials4.htm If that doesn't help, dig through the rest of the website. Kyle Guichard wrote: > I am a student at SJSU working on my senior project. For this, I will > be creating an FPGA using Xilinx software, but I am really overwhelmed > with the ammount of information on how I can actually do this. > > Can anyone direct me to some good documentation on creating FPGA's > when I have the verilog/VHDL code? > > > thanks! > kyleArticle: 48493
Does anybode know, where I can download the 4.2 version of Webpack ? thanx ThomasArticle: 48494
On Fri, 18 Oct 2002 10:56:21 +0100, "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote: >Hey, > >I'm developing a hardware version of a software algorithm... > >I've run into a problem where the software algorithm decides to take logs. > >I have found plenty of power series to approximate the log function, >however, these insist that x is between +/- 1. Unfortunately for me, x can >range between 0 and 10000000. Well THINK! This is easy to resolve. Just like when we used log tables for base 10 --- values were only given for numbers between 1 and 10! If you mean base 10 logs and you want log(N) write it as log[(10^n )*(N/10^n)] and take n large enough to get between 0 and 1! Then log(N) = n + log(N/10^n) If you mean natural logs ln(N) then use powers of e instead of 10 > >Does anyone know a good algorithm for calculating logs efficiently, or a >different power series without the above limitation. > >Any suggestions? > >Please email me. > >t.nicolson@signal.qinetiq.com > >Regards, > >Tim > >Article: 48495
Bob wrote: > Even with the help of XAPP266, it took me and our local Xilinx FAE several > hours to get the IOB selection correct for all the blocks of 8 DQ's and > their associated DQS line. I believe that the FAE had to consult the > factory, too. It took a lot of work in FPGA editor, and some test code runs > to confirm that we were assigning the IOB's properly. Too hard, Xilinx! I agree. > I think that this is one area that Altera has an advantage with their new > line of FPGA's. I don't use them myself, but I've been told that they > directly support the DQS lines for ram read operation. I hope Xilinx is > listening (Peter, Austin?). A small programmable delay block on the documented DQS pins are nice features. Hint hint. > We're attempting to do DDR333 (167Mhz clock), so we > feel that it it's necessary to go through the trouble of using the DQS's to > strobe the incoming data into the IOB's, and then a separate/continuous (but > sync'd) clock to transfer the data from the IOB flops into CLB flops. The > timing of this task is critical, too. 167MHz might be fast enough for us as well. Or we might need 200MHz... I hope not. -- Phil HaysArticle: 48496
Hi does anybody know a good on-line reference/guide to scripting testbenches? -- Cheers! MikeArticle: 48497
An excellent book on the subject (IMO) is "Writing Testbenches" by Janick Bergeron. "Michael Nicklas" <michaeln@nospam.slayer.com> wrote in message news:aop7dg$ctg$1$8302bc10@news.demon.co.uk... > Hi > > does anybody know a good on-line reference/guide to scripting testbenches? > > -- > Cheers! > > Mike > > >Article: 48498
Strange, can't find xapp266. Search for FCRAM didn't turn up anything either. If you have th appnote could you email it to me. Thanks brijesh brijesh at vt dot edu brijesh at cfrsi.com "Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:v0Or9.581$071.45408@newsread1.prod.itd.earthlink.net... > > "Phil Hays" <SpamPostmaster@attbi.com> wrote in message > news:3DAF9855.62FB10E8@attbi.com... > > Brijesh wrote: > > > > > The xilinx app note: xapp253 ( DDR SDRAM controller using Virtex II) > talks about using HEX lines for low skew routing. Here is the snippet from > the app note. > > > > > > "As described in the Virtex-II data sheet, each I/O tile contains four > IOBs that share a switchmatrix.IOB PAD4 is the top IOB in a I/O tile. In > order for the DQS to access a local low-skew clock line, DQS must be placed > on the top IOB, PAD4 in the I/O tile. If IOB PAD4 is not available in a > tile, or is unbonded, then it cannot be used to place the DQS signal. > > > > > > Placing the DQS signal in PAD4 gives access to a local clock line which > is a HEX line spanning > > > five rows above the chosen I/O tile and six rows below the chosen I/O > tile. The data (DQ) pads > > > should be placed in the bonded IOBs available within these specific > rows." > > > > > > Question is > > > 1) How does one locate the "IOB pad4: top IOB of an I/O tile" ? > > > > FPGA Editor. The app note gives information on how to use it to find > > the subset of pads that can be DQS pins > > > > > > > 2) We know that 4 adjacent IOB's share the routing resources. > > > > Word of warning. Remember that some IOBs are unbonded, so there may be > > only two bonded IOBs that share routing resources. And remember that > > the routing of clocks for DDR is shared between pairs of IOBs even more > > closely. These pairs are easy to identify: the name in the pinout > > tables shows pairs, for example: IO_L06N_0 IO_L06P_0. > > > > > > > How do we know which four? > > > > FPGA Editor. > > > > > > > Virtex II data sheets and hand book mention this but do not give any > info on how to locate them . > > > So where will I find this info. > > > > If you find a better source, please post it. > > > > > > -- > > Phil Hays > > > > Take a look at XAPP266. It's for FCRAM, but still applicable to standard DDR > rams, and it was more useful to me than XAPP253 (as I recall). > > Even with the help of XAPP266, it took me and our local Xilinx FAE several > hours to get the IOB selection correct for all the blocks of 8 DQ's and > their associated DQS line. I believe that the FAE had to consult the > factory, too. It took a lot of work in FPGA editor, and some test code runs > to confirm that we were assigning the IOB's properly. Too hard, Xilinx! > > I think that this is one area that Altera has an advantage with their new > line of FPGA's. I don't use them myself, but I've been told that they > directly support the DQS lines for ram read operation. I hope Xilinx is > listening (Peter, Austin?). > > Also, be aware that you do not have to use the DQS line (for reads) if your > data rate is low enough. We're attempting to do DDR333 (167Mhz clock), so we > feel that it it's necessary to go through the trouble of using the DQS's to > strobe the incoming data into the IOB's, and then a separate/continuous (but > sync'd) clock to transfer the data from the IOB flops into CLB flops. The > timing of this task is critical, too. > > > Bob > >Article: 48499
Thanks Phil and Bob. I did look into FPGA editor, but gave up pretty soon. Guess I have to go back to it now. Wondering why doesn't the FPGA floor planner have any info on this. Cause that's what we are supposed to use to plan our IOB placements right? If they indicate which four pads share resource by some sort of color code etc...would make our life so much easier. One other question, can we neglect Dqs lines (for reading) if we are operating it at 100MHz and still get the design to work reliably? Is the timing margin enough? This is assuming that the PCB layout is done properly. Thanks for everything. brijesh "Brijesh" <brijesh_spamNot@vt.edu> wrote in message news:aEKr9.146898$IL6.7352272@news2.east.cox.net... > The xilinx app note: xapp253 ( DDR SDRAM controller using Virtex II) talks about using HEX lines for low skew routing. Here is the snippet from the app note. > > "As described in the Virtex-II data sheet, each I/O tile contains four IOBs that share a switchmatrix.IOB PAD4 is the top IOB in a I/O tile. In order for the DQS to access a local low-skew clock line, DQS must be placed on the top IOB, PAD4 in the I/O tile. If IOB PAD4 is not available in a tile, or is unbonded, then it cannot be used to place the DQS signal. > > Placing the DQS signal in PAD4 gives access to a local clock line which is a HEX line spanning > five rows above the chosen I/O tile and six rows below the chosen I/O tile. The data (DQ) pads > should be placed in the bonded IOBs available within these specific rows." > > Question is > 1) How does one locate the "IOB pad4: top IOB of an I/O tile" ? > 2) We know that 4 adjacent IOB's share the routing resources. How do we know which four? > > Virtex II data sheets and hand book mention this but do not give any info on how to locate them . > So where will I find this info. > > Thanks > Brijesh > brijesh at vt dot edu > >
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