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Y K:
61752: 03/10/09: Inferring an accumulator using Verilog on Xilinx Spartan 2e
61759: 03/10/10: Re: Inferring an accumulator using Verilog on Xilinx Spartan 2e
Y Nagaonkar:
76238: 04/11/29: Configuring FPGA & PROM with serial Cable (DB9)
Y Varma:
53471: 03/03/13: Re: Timing Simulation Glitches
56286: 03/06/02: FPGAs - buyer's guide ?
Y. B. Williams:
Y. Jason Hou:
1998: 95/09/29: Re: Xilinx Flash FPGA ??
2053: 95/10/06: Re: VHDL and Xilinx (Hard/Soft) Macros
Y. P. Wheeler:
y.doganc:
7876: 97/10/26: example dct
<y.tachwali@gmail.com>:
136144: 08/11/03: How to move project files from ISE 7.1 to ISE 10.1
136148: 08/11/03: Re: How to move project files from ISE 7.1 to ISE 10.1
136186: 08/11/05: Re: How to move project files from ISE 7.1 to ISE 10.1
136187: 08/11/05: Re: How to move project files from ISE 7.1 to ISE 10.1
y_mh:
129475: 08/02/25: sFPDP IP Core
y_p_w:
57092: 03/06/23: Q: regarding I2C protocols
57113: 03/06/23: Re: regarding I2C protocols
57130: 03/06/24: Re: regarding I2C protocols
57155: 03/06/24: Re: regarding I2C protocols
58941: 03/08/04: Patent granted for "system on a chip" framework?
58968: 03/08/05: Re: Patent granted for "system on a chip" framework?
59064: 03/08/07: Re: Patent granted for "system on a chip" framework?
59082: 03/08/07: Re: Patent granted for "system on a chip" framework?
71092: 04/07/07: Re: Urgent : Xilinx PACE question
Yacine EL KOLLI:
20857: 00/02/24: Re: Installing Xilinx Foundation on PC
22094: 00/04/21: Re: Fast (> 100Mb) serial link to PC
23940: 00/07/17: Re: Renoir/Update Symbol from HDL
Yad:
78286: 05/01/28: Re: Cheap source for GAL's
<yadurajj@yahoo.com>:
95198: 06/01/21: FPGA-Programmable power supply
Yaju N:
77864: 05/01/18: Re: Programming Virtex II in slave select MAP mode?
77983: 05/01/21: Configuring FPGA using PROM/uP
78138: 05/01/25: Re: Configuring FPGA using PROM/uP
79278: 05/02/16: Efficient Voltage Regulators Spartan 3 Current Requirements
79703: 05/02/23: Re: Efficient Voltage Regulators Spartan 3 Current Requirements
79844: 05/02/24: Re: Efficient Voltage Regulators Spartan 3 Current Requirements
79911: 05/02/25: Maximum Current utilized by Spartan-3
79922: 05/02/25: Re: Maximum Current utilized by Spartan-3
80249: 05/03/02: Re: Maximum Current utilized by Spartan-3
83258: 05/04/26: Re: Virtex 4 Power consumption
86736: 05/07/05: Re: Individual study-activity on FPGA's - which subsubject?
Yaju Nagaonkar:
87533: 05/07/25: VHDL soft-core portability to Xilinx, Altera, Atmel....
87541: 05/07/25: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
87926: 05/08/03: 3.3V tolerant configuration interface Spartan 3
87929: 05/08/03: Re: 3.3V tolerant configuration interface Spartan 3
93654: 05/12/27: serial configuration of Spartan 3 FPGA
95850: 06/01/26: Current to sink PROG_B low?
95858: 06/01/26: Re: Current to sink PROG_B low?
95874: 06/01/26: Re: Current to sink PROG_B low?
96210: 06/01/31: Re: Current to sink PROG_B low?
96019: 06/01/27: Debugging Spartan3 slave serial configuration
96215: 06/01/31: Re: Debugging Spartan3 slave serial configuration
96225: 06/01/31: Re: Debugging Spartan3 slave serial configuration
96267: 06/02/01: Re: Debugging Spartan3 slave serial configuration
Yaman Umuroglu:
157974: 15/06/09: Re: Open/Free HLS weapon of choice ?
157983: 15/06/10: Re: Open/Free HLS weapon of choice ?
Yan:
46879: 02/09/10: Saving results with modelsim
146982: 10/04/07: Re: FMC Boards ?
147030: 10/04/09: Re: FMC Boards ?
Yana:
62208: 03/10/22: Virtex II MJA
Yang Li:
21302: 00/03/16: PCI Synthesis Question
22503: 00/05/10: ASIC question
Yang Yungchiang:
11760: 98/09/08: FPGA Cost ?
Yang-Tzu:
54846: 03/04/20: Is there any information about Xilinx bitstream file format?
54859: 03/04/20: Re: Is there any information about Xilinx bitstream file format?
54970: 03/04/23: Re: configuration file
70288: 04/06/11: Problems about Using Xilinx Command Line !
70334: 04/06/12: Re: Problems about Using Xilinx Command Line !
70336: 04/06/13: Xilinx .bit to .svf...
70455: 04/06/17: Re: Xilinx .bit to .svf...
yang_li1:
21228: 00/03/11: Synthesis question ( PCI based ASIC )
21235: 00/03/12: Synthesis question ( PCI based ASIC )
yanggg:
45721: 02/08/02: a chip which can trans ethenet data through E1 interface
Yanick:
45308: 02/07/18: Virtex-II variable vs fixed DCM phase-shift ?
45324: 02/07/18: Re: Virtex-II variable vs fixed DCM phase-shift ?
45697: 02/08/01: Looking for VHDL clock generator with jitter control ?
45957: 02/08/12: Xilinx IBUFGDS with both inputs grounded ?
45998: 02/08/13: Re: Xilinx IBUFGDS with both inputs grounded ?
Yanick Viens:
32647: 01/07/03: Re: Driven clocks balancing
32648: 01/07/03: Re: Virtex II Block RAM's - Is the second port free?
yankee:
9206: 98/03/02: Re: The case for Linux and EDA
9408: 98/03/10: Re: The case for Linux and EDA
Yann:
39310: 02/02/06: Virtex 2 rect->pol conversion
Yann Guidon:
13306: 98/11/25: VHDL->boolean equation
Yann Thoma:
64712: 04/01/12: Modify Memory after P&R in Xilinx Virtex2
Yannick:
126487: 07/11/24: Start-up Xilkernel on Microblaze
126539: 07/11/27: Re: Start-up Xilkernel on Microblaze
yannick:
56497: 03/06/06: some book advises ??
Yannick Lamarre:
160039: 17/05/16: Configuration fault recovery
160043: 17/05/17: Re: Configuration fault recovery
Yannis Koryfidis:
89497: 05/09/16: Re: problem with programming avnet edk board over LPT
89498: 05/09/16: Re: problem with programming avnet edk board over LPT
89512: 05/09/16: Re: problem with programming avnet edk board over LPT
Yannis Mitsos:
17805: 99/09/06: differences between ALTERA-XILINX
Yao Qi:
114313: 07/01/11: Re: Interlock and stall in CPU design?
Yao Sics:
119885: 07/05/29: How to calculate IFFT based on FFT result?
120165: 07/06/02: How to execute application code out of external memory using EDK?
120304: 07/06/05: How to Access CompactFlash by using SystemACE?
120362: 07/06/06: Weird! sysace_fwrite() cannot be found!!!???
120363: 07/06/06: Re: How to Access CompactFlash by using SystemACE?
120364: 07/06/05: Re: Weird! sysace_fwrite() cannot be found!!!???
120576: 07/06/11: How to put part of program data into local ram, the rest into external memroy?
120609: 07/06/11: Re: How to put part of program data into local ram, the rest into external memroy?
121716: 07/07/12: Chipscope 9.1: Any easy way to rename and regroup signals?
121720: 07/07/11: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121725: 07/07/12: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
129851: 08/03/06: how to Load file data into memory by NIOS II IDE?
<yao.sics@gmail.com>:
119039: 07/05/09: ISE 8.1.03: Bizarre MAP removes almost everything of my design!!!
yaohan:
25904: 00/09/26: Re: Announce: Free HC11 CPU Core
25905: 00/09/26: Point to point core
28253: 01/01/04: Serial interface (urgent)
28325: 01/01/07: Re: Altera free software
28837: 01/01/26: choose device
35269: 01/09/27: sensitivity list
35294: 01/09/28: Re: sensitivity list
35347: 01/09/30: MAX Plus Division
yaron kretchmer:
99: 94/08/15: synopsys fpga libraries prices
533: 94/12/26: fpga-compiler (synopsys)
Yaron Kretchmer:
1154: 95/05/07: Re: ASIC group ?
Yaron Wolfsthal:
5344: 97/02/09: israel: formal verification
Yaseen Zaidi:
75022: 04/10/24: ISE Mapping problem
74467: 04/10/12: Reading RAM while
74524: 04/10/13: simprim errors
80271: 05/03/02: IBUFG as ? component
86537: 05/06/29: edn macro in ISE
96950: 06/02/13: Dual Port Block RAM Inference
100703: 06/04/16: Boolean as port type
101182: 06/04/26: Modelsim Simulation
104636: 06/07/03: Synthesis changes after ISE upgrade
113722: 06/12/20: Tracing UNKNOWN drivers
113723: 06/12/20: Tracing UNKNOWN drivers
116313: 07/03/06: No Clock in ChipScope Pro Analyzer
116377: 07/03/07: Re: No Clock in ChipScope Pro Analyzer
<yaseenzaidi@NETZERO.com>:
86037: 05/06/20: Post Translate Timing
<yaseenzaidi@netzero.com>:
134500: 08/08/14: Real port types in VHDL
Yash Bansal:
58638: 03/07/29: Parallel Port EPP in FPGA
58674: 03/07/30: Re: Parallel Port EPP in FPGA
58736: 03/07/31: Re: Parallel Port EPP in FPGA
60652: 03/09/18: VHDL and ModelSIM question
<yash.r.modi@gmail.com>:
117457: 07/03/31: microblaze bootloader
Yashinovsky Benny:
10438: 98/05/19: Re: Altera 3.3V and 5V
yashu:
114842: 07/01/24: virtex II pro development board(xupv2p) : maximum current driving strength from hirose connector
<yasirmm@gmail.com>:
116799: 07/03/18: FPGA vs. GPP anyone?
Yasser Y. Hanafy:
8165: 97/11/23: Which size of Xilinx Fits the DLX
Yau Man Wai , Roger:
6110: 97/04/13: XC5204PQ160 Configuration
7206: 97/08/15: 10K100 socket?
9616: 98/03/26: Re: CMOS or TTL?
9617: 98/03/26: Re: CMOS or TTL?
9697: 98/04/01: Re: Digital PLL's or Manual Synching?
9698: 98/04/01: Re: Digital PLL's or Manual Synching?
Yavuz Doganc:
7874: 97/10/26: example DCT.
11039: 98/07/14: compile warning
ybc:
42277: 02/04/19: Re: ModelSim closes for unknown reason
42449: 02/04/24: Xilinx XC2S150 PQ208 slave parallel mode for flash download program error !!!
ycp:
19168: 99/12/03: ghd
YD:
64493: 04/01/06: Re: 4-bit binary divider circuit PLEASE!!!!!!!
65644: 04/02/04: Re: 4 bit divisor with flip-flop ?
65697: 04/02/05: Re: 4 bit divisor with flip-flop ?
112609: 06/11/26: Re: board - T562.jpg
112714: 06/11/27: Re: board - T562.jpg
112715: 06/11/28: Re: board - T562.jpg
112727: 06/11/28: Re: board - T562.jpg
ydHeVVur:
19285: 99/12/10: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
yeah:
124863: 07/10/08: Need suggestion on FPGA kit
124899: 07/10/10: Re: Need suggestion on FPGA kit
yehuda yizraeli:
2335: 95/11/21: Re: request for RTL netlists
Yekta Ayduk:
8541: 98/01/07: serial conf. PROMS
17880: 99/09/15: xilinx v2.1i
23640: 00/07/04: 2.1i better than 1.5?
yekta ayduk:
12540: 98/10/15: Re: XILINX 4000XL configuration using M 1.5 JTAG programmer
Yeller4505:
5209: 97/01/31: Re: FPGA Lab.
Yen:
62773: 03/11/07: Re: not replaced by logic error
62801: 03/11/07: Re: not replaced by logic error
Yenni Totong:
26239: 00/10/09: Re: Problem Foundation 3.1 sp 3
47449: 02/09/25: Re: Virtex2 Block Multiplier: Faster, Faster
47490: 02/09/26: Re: Virtex2 Block Multiplier: Faster, Faster
#YEO WEE KWONG#:
13400: 98/12/01: Viewlogic setup with Xilinx and Altera Backend PAR
13766: 98/12/23: Xilinx Simulator
17643: 99/08/18: Xilinx DPM error : FE-PADMAP-02 error
18921: 99/11/22: Most micros (PIC/8051 etc) have TCP/IP stacks freely available.
18922: 99/11/22: implementing TCP/IP on PLD
19055: 99/11/26: implementing TCP/IP on PLD
19054: 99/11/26: XTP
19422: 99/12/21: automated testbench
19500: 99/12/28: HDL to graphic conversion
19631: 00/01/05: REad function query
19900: 00/01/17: Further to board
22111: 00/04/25: Segregation between synthesis code and simulation code
22253: 00/05/03: Wait until statement problem in synthesis
22328: 00/05/05: Code request
yerbby:
55152: 03/04/28: ModelsimSE5.6/5.7 crashes with ISE5.1i
YesMann:
58874: 03/08/03: Proasic APA300 RAM synthetisable model
59099: 03/08/08: Compilation error
59106: 03/08/08: Re: Compilation error
YetAnotherLurker - Rickman:
11210: 98/07/26: Re: Delay Element for async design.
YEUNG-CHUEL:
20959: 00/03/01: help me!...please...
Yevgeny K.:
55824: 03/05/20: Using GERMS monitor with NIOS CPU on non-Altera board
55905: 03/05/22: Re: Using GERMS monitor with NIOS CPU on non-Altera board
55936: 03/05/23: Re: Using GERMS monitor with NIOS CPU on non-Altera board
58428: 03/07/23: Altera Nios 3: Using Interface To User Logic Problem
58787: 03/08/01: Re: Altera Nios 3: Using Interface To User Logic Problem
58913: 03/08/04: Re: Altera Nios 3: Using Interface To User Logic Problem
YFLuo:
108894: 06/09/18: How to change coefficient word length
108950: 06/09/19: Fixed-point FIR eyediagram problem
108957: 06/09/19: Re: Fixed-point FIR eyediagram problem
109530: 06/09/27: System Generator implement to FPGA problem
YH:
152059: 11/06/29: JESD204A and Spartan-6 GTPs
YhhK:
<yhirbawi@my-dejanews.com>:
11215: 98/07/26: Re: Caluclation of gates in FPGA
yhl:
44264: 02/06/15: Lattice download cable schematic?
yhs2012:
154066: 12/07/26: Strange behavior with counter (decreases instead of increasing)
154069: 12/07/26: Re: Strange behavior with counter (decreases instead of increasing)
yi don:
45094: 02/07/12: some questions from a fpga newer
Yi-Shin Li:
33294: 01/07/22: a newbie question -- The cost between 3-to-1 MUX and 4-to-1 MUX
yickma:
154035: 12/07/17: use differential I/O simultaneously
Yifei Luo:
107943: 06/09/02: FIR Implementation with System Generator 8.2
<yigitcomez1993@gmail.com>:
157644: 15/01/14: Re: please help and advice : Error: Pack:1107 - Unable to combine the
yihua xu:
26216: 00/10/08: Help me! the limit of a signal's drive capacity
yijun_lily@yahoo.com:
84803: 05/05/27: Design flow of Spartan3 for my own embedded processor and HW logic?
85156: 05/06/06: IC engineer or Embedded system software engineer?
88764: 05/08/27: Should I use DCM for every FPGA design?
88765: 05/08/27: Re: Should I use DCM for every FPGA design?
88766: 05/08/27: Clock skew in FPGA Xilinx?
88874: 05/08/30: Gated clock for FPGA (verilog)???
<Yim>:
80366: 05/03/05: Re: Newby Getting started with FPGA
yin wang:
43632: 02/05/28: Strange error message from MaxPlus II !
Ying C.:
7923: 97/10/30: Re: Altera EPC1 and Chipmaster 6000
8227: 97/12/01: Re: Altera vs Xilinx
8346: 97/12/10: Re: Q: MAX+ Plus II External connections
8448: 97/12/16: Re: bus design in Altera 10K, how to increase speed
8777: 98/01/26: Re: ALtera Devices.
8805: 98/01/28: Re: ABEL to Altera-HDL? Group FAQ?
8950: 98/02/08: Re: Free FPGA tools???
8962: 98/02/09: Re: Free FPGA tools???
9427: 98/03/13: Re: SOS!! Big Urgent Problem
9650: 98/03/27: Re: Command line input for Maxplus2?
10086: 98/04/26: Re: Altera 10K20 Configuration problem
10422: 98/05/18: Re: Turbo bit in Altera 7000
14952: 99/02/26: Re: JTAG HANG UP......
16793: 99/06/08: Re: ALtera 20KE LVDS IO
18877: 99/11/19: Re: Altera Files vho and sdo too big
19112: 99/11/29: Re: Configuration of ALTERA EPC2LC20 Please help!
19477: 99/12/23: Re: Global buffer insertion (Synplify/Flex10K)
19774: 00/01/11: Re: Altera Flex10K bitstream compatibility ?
Ying Hu:
72709: 04/08/29: The Effect of Pin Assginment
72713: 04/08/29: Re: The Effect of Pin Assginment
72735: 04/08/30: Re: The Effect of Pin Assginment
72792: 04/09/01: Re: The Effect of Pin Assginment
Ying Zhang:
3219: 96/04/29: Where to buy IC chips...
yingqigang:
140071: 09/04/27: virtex-4 questions
Yip:
17040: 99/06/27: Re: fast counter in 4013XL?
yippeeyang:
119137: 07/05/12: plb_tft_cntlr_ref in XUP
YiQi:
101816: 06/05/07: A constant value of 0 in block
101817: 06/05/07: EDIFParser in JHDL / EDIF simulator?
101819: 06/05/07: Re: A constant value of 0 in block
101853: 06/05/07: Re: A constant value of 0 in block
102070: 06/05/10: EDIF simulator???
102231: 06/05/12: difference of variable and signal
102270: 06/05/12: Re: difference of variable and signal
102324: 06/05/15: Re: difference of variable and signal
102439: 06/05/16: sending multiple char on RS232
102443: 06/05/16: Re: sending multiple char on RS232
102446: 06/05/16: Re: sending multiple char on RS232
102453: 06/05/16: Re: sending multiple char on RS232
102877: 06/05/22: Re: sending multiple char on RS232
102891: 06/05/22: Re: sending multiple char on RS232
103207: 06/05/28: Re: sending multiple char on RS232
103209: 06/05/28: Re: sending multiple char on RS232
Yiu-Man, Mr Yip:
16091: 99/05/02: Re: Counters
YiYin Wang:
73645: 04/09/27: problems about Behavioral Compiler
yjhgj:
151335: 11/03/24: Re: Cortex M1 and GUI
ykagarwal:
60265: 03/09/09: pipelined divider
60295: 03/09/09: Re: pipelined divider
60356: 03/09/11: Re: pipelined divider
60405: 03/09/11: Re: pipelined divider
60454: 03/09/13: Re: pipelined divider
60734: 03/09/20: Re: pipelined divider
60760: 03/09/22: Re: pipelined divider
60880: 03/09/24: Re: Synchronous counter enable pulse length
61350: 03/10/02: Re: Parameterized Multiplier in Xilinx FPGA
<yl_model@Netvision.net.il>:
1777: 95/08/30: seccond hand altera wanted !!
ylc199:
92806: 05/12/07: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion )
92850: 05/12/07: Re: Stratix EP1S80 DSP development board (Problem for ADC/DAC conversion )
±è¾ç·¡_YLKIM:
25981: 00/09/29: some question about synplify tool
26102: 00/10/04: [Req] Schematic for using Xilinx XC4000E Series.
ymlee:
16140: 99/05/06: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
<ymtiwu@yahoo.com>:
Yo:
yogesh tripathi:
160514: 18/03/12: How to handle a data packet while calculating CRC.
160516: 18/03/12: Re: How to handle a data packet while calculating CRC.
160521: 18/03/15: Re: How to handle a data packet while calculating CRC.
160546: 18/03/21: Re: How to handle a data packet while calculating CRC.
160632: 18/06/05: How to analyes IBERT ip results for highspeed signals?
Yogesh Varma:
<yohyyr@nowasia.net>:
33258: 01/07/20: The PC and Software Museum
Yonatan Mittlefehldt:
17267: 99/07/15: Beginner in need of help
Yong Zhu:
76018: 04/11/22: Re: Xilinx OPB custom interface
79116: 05/02/14: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79117: 05/02/14: Re: opencore under edk 6.3i
86394: 05/06/27: Re: PLB registers
Yong-il Yoon:
13550: 98/12/09: BCD 2 Binary
Yongjie Liu:
75912: 04/11/18: microblaze: execute program from external memory
75959: 04/11/20: Re: microblaze: execute program from external memory
75960: 04/11/20: Microblaze: reading files using sysace compactflash
75966: 04/11/20: Re: Microblaze: reading files using sysace compactflash
76096: 04/11/24: microblaze: initiate the systemace device
YongKook Kim:
11459: 98/08/17: PCI BUS Master's Performance
11523: 98/08/21: Re: Video 256 colors interface HELP!
11701: 98/09/02: FIFO Design problem
11714: 98/09/03: Curious problem...FPGA/CPLD Architecture and Logic Implementations
11722: 98/09/04: QUESTION
11723: 98/09/04: Assigning IOE on Altera's FLEX10k
<yoni.lan@gmail.com>:
124075: 07/09/11: Address sensitive process, Xilinx virtex2pro
Yoo:
16304: 99/05/14: Who do you know? Motorola FPGA
Yoram Rovner:
33063: 01/07/16: I NEED XILINX FOUNDATION PROFESSIONAL
33850: 01/08/06: I NEED TO BUY A FPGA BOARD
39946: 02/02/22: CPLD PROJECT
40100: 02/02/27: Webpack symbol library
Yoram Stern:
33669: 01/08/01: deskewing PLL/DLL paper
<yorams70@my-deja.com>:
17245: 99/07/14: Virtual CPU of SUMMIT design
25034: 00/08/24: largest fpga in the industry
25090: 00/08/25: Re: largest fpga in the industry
<yorams@hywire.com>:
30295: 01/04/02: xapp258 question
30297: 01/04/02: xapp258 question
Yosi Blum:
7306: 97/08/24: Re: 10K100 socket?
yossarian69:
154485: 12/11/14: RE: Has anyone had any luck complining examples for a Virtex-II multimedia board
Yottameter:
133657: 08/07/08: Re: 2 BUFIOs in the same clock-capable pair?
Youn-Long Lin:
87: 94/08/12: Re: Would you like a free C to netlist compiler?
Younes Leroul:
23257: 00/06/19: Wanted: Xilinx VirtexE
23300: 00/06/21: Re: Wanted: Xilinx VirtexE
young:
90909: 05/10/25: Re: RS232 Uart for Virtex-II Pro
97828: 06/02/28: Re: Serious problem with XST
123216: 07/08/20: Re: Reconfiguring a Virtex4 DCM_ADV.
123218: 07/08/20: Multiple MicroBlazes error
123647: 07/08/31: Re: Simple Project involving microblaze
123648: 07/08/31: BlockRAM connection error
123921: 07/09/07: Re: BlockRAM connection error
Young-Su Kwon:
40316: 02/03/05: Writing Synosys library for FPGA using LUT.
44666: 02/06/26: Virtex-E Readback.
47030: 02/09/16: Readback size for virtex2
49362: 02/11/11: EDIF generation from XST of ISE 5.1i
52200: 03/02/04: Quartus II's VQM to EDIF.
youngejoe:
156063: 13/11/21: FPGA Cryptosystem
156073: 13/11/22: Re: FPGA Cryptosystem
Your Name:
5548: 97/02/24: How are states changed in ALTERA
14298: 99/01/23: Re: program flow chart to state machine ?
14178: 99/01/17: Re: looking for an internship
14288: 99/01/23: Re: PLL in FPGA
14289: 99/01/23: Re: DTMF Decoder in a FPGA/XILINX ?
14290: 99/01/23: Re: Foundation V3.1 VHDL synthesis
14299: 99/01/23: Re: PLL in FPGA
14355: 99/01/26: SWAP Home RF 4-FSK Demodulator
14623: 99/02/06: Re: Xilinx de-compiler
Your name:
110879: 06/10/25: Supported bus widths for RLDRAM on Virtex4?
110880: 06/10/25: Xilinx MIG 1.6 doesn't launch
Your Real Name:
1328: 95/06/02: Re: Any company for conversion FPGA to ASIC?
<your.box2@googlemail.com>:
140806: 09/05/26: URGENT help with a CPLD and LCD display chip SED1278F
your_friendly_synplify_support:
121504: 07/07/06: Re: Does synplify 8.8 can support xilinx virtex5?
Youssef Hawwar:
14293: 99/01/23: FPGA Student Design Contest
14305: 99/01/25: FPGA student contest
14345: 99/01/26: FPGA Student Dsign Contest
<yowtzu@gmail.com>:
76597: 04/12/06: Integrate VHDL module with mpram access
yp:
82317: 05/04/11: easyfpga is not easy
82384: 05/04/12: Re: easyfpga is not easy
Yrjola:
116635: 07/03/14: Clearing fpga internal memory...
119848: 07/05/28: SignalTap Analyzer...
<yruvwudu@dulsufef.net.ve>:
yshamir:
24338: 00/08/03: Interview Questions
yt:
9618: 98/03/26: Command line input for Maxplus2?
<ytregubov@yahoo.com>:
87371: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Yttrium:
58063: 03/07/14: Re: How to choose FPGA device?
58237: 03/07/17: Re: state machine generator
58476: 03/07/24: Re: Where do I find model sim xe starter download?
63054: 03/11/13: VIRTEXII IO problem
63655: 03/11/27: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63678: 03/11/28: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63679: 03/11/28: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63683: 03/11/29: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
64563: 04/01/07: newbie question: speed grade + area constraint
64673: 04/01/11: Re: FPGA Size
64723: 04/01/12: Re: Modify Memory after P&R in Xilinx Virtex2
65883: 04/02/09: FIR filter coefficient (with COE file)
66234: 04/02/15: Re: FIR filter coefficient (with COE file)
66343: 04/02/17: Re: FIR filter coefficient (with COE file)
66586: 04/02/23: OpenCore.org DDR SDRAM problems
66877: 04/02/28: area constrains in UCF (or PACE)
68224: 04/03/30: incremental design flow question (PACE)
69156: 04/04/28: timing constraint question (period/timespec)
70290: 04/06/11: Xilinx System Generator problem: ERROR:NgdBuild:604
70572: 04/06/21: Re: pulse generation using SRL16E on a Virtex-II
71107: 04/07/08: Re: Urgent : Xilinx PACE question
71166: 04/07/10: Re: Info on FPGA routing algorithms?
71564: 04/07/22: Re: Area constraint on a sub-module
73319: 04/09/19: Re: Statix II vs. Virtex 4
73487: 04/09/22: Re: edge reset
75407: 04/11/04: chipscope pro problem (par)
75439: 04/11/05: Re: chipscope pro problem (par)
75478: 04/11/07: Re: chipscope pro problem (par)
75950: 04/11/20: Re: Vccaux on Spartan 3
76049: 04/11/23: Re: Performance of Xilinx System Generator RTL?
78836: 05/02/08: Re: EDK+IPIF: Customizing wizard result
78837: 05/02/08: Re: EDK+IPIF: Customizing wizard result
84694: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84699: 05/05/24: warning place and route ise7.1?
84742: 05/05/25: Re: warning place and route ise7.1?
84775: 05/05/26: Re: warning place and route ise7.1?
84891: 05/05/31: regional clk to dcm? possible or not?
85758: 05/06/15: Re: Viewing internal signal in Modelsim (post P&R)
86905: 05/07/08: Re: Ray Andraka when will your book be on store???
87589: 05/07/26: LVDS problem/chipscope VIRTEX4
yttrium:
106927: 06/08/22: Xilinx FPGA editor error ISE8.2
107310: 06/08/26: Re: Xilinx FPGA editor error ISE8.2
107313: 06/08/26: Re: DCM vs. PLL
108655: 06/09/14: Re: Linear Interploation Algorithms
108773: 06/09/16: Re: Linear Interploation Algorithms
108783: 06/09/16: Re: csptool : Chipscope Pro perl script to group buses automatically
110322: 06/10/13: Re: [ISE8.2] DIFF_TERM and unused pin
110406: 06/10/15: Re: [ISE8.2] DIFF_TERM and unused pin
110407: 06/10/15: Re: [ISE8.2] DIFF_TERM and unused pin
110774: 06/10/22: Re: Fixing Down Parts of Logic in ISE (8.2)
111101: 06/10/29: Spartan3E clk/BUFGMUX warning
111455: 06/11/03: Re: reset
111531: 06/11/04: Re: reset
111532: 06/11/04: Re: chipscope
111533: 06/11/04: Re: Scientific Computing on FPGA
111538: 06/11/05: Re: JTAG connection for chipscope
113224: 06/12/08: Re: Implementing DVI EDID on Stratix II GX?
114176: 07/01/06: Re: [XST 8.2.3] DSP48 inference multiply/add
114177: 07/01/06: Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx)
114455: 07/01/16: interesting article FPGA routing field programmable nanowire interconnect
115271: 07/02/05: Re: ISE 9.1 SAY YOURS OPINION
115292: 07/02/06: Re: ISE 9.1 SAY YOURS OPINION
123070: 07/08/15: Re: ChipHit: ASIC, FPGA, EDA Search Engine
Yu Chen:
26532: 00/10/19: How safe is the algorithm implemented with FPGA?
26653: 00/10/23: Re: How safe is the algorithm implemented with FPGA?
26651: 00/10/23: [2]How safe is the algorithm implemented with FPGA?
Yu Haiwen:
55615: 03/05/14: Can XST takes place of Synplify or FPGA Compiler?
55860: 03/05/21: How to verify timing parameters of clock
57702: 03/07/03: Re: Everything need a reset?
57703: 03/07/03: DCM usage question
Yu Jun:
38101: 02/01/04: ASIC faster than VirtexII FPGA?
38168: 02/01/07: 128 bit compare delay kill me!
62764: 03/11/06: ASIC speed
Yu Shi:
57398: 03/06/30: FPGA vs. DSP.
#YU WEI#:
62845: 03/11/10: CF card problem in Virtex-II Multimedia Board
62925: 03/11/11: How to visit the files in CF cards
62994: 03/11/12: None
63220: 03/11/18: None
Yu Xiaodong:
yu zhou:
154935: 13/02/23: about the always block in verilog
Yu, Wenjiang [BVW:KCK2:EXCH]:
30628: 01/04/19: some general questions about FPGA design
YUAN, Nan:
121280: 07/06/30: Re: Bit error counter - how to make it faster
Yuce Beser:
1187: 95/05/12: Re: Power consumption of Xilinx FPGAs
1188: 95/05/12: Re: Power consumption of Xilinx FPGAs
1189: 95/05/12: Re: Power consumption of Xilinx FPGAs
1190: 95/05/12: Re: Power consumption of Xilinx FPGAs
1259: 95/05/23: Re: global clocks in ASYL
1462: 95/06/26: Re: The "InOut" Port mode in the Xilinx FPGA
1476: 95/06/27: Re: The "InOut" Port mode in the Xilinx FPGA
1634: 95/08/09: Re: Xilinx xc4013 routing problems ??
1647: 95/08/10: Re: external connections for efficient internal routing
1907: 95/09/19: Re: Help needed-how to instantiate Xbloc component with synopsys
1932: 95/09/21: Re: Simulation using XC3000 libraries
1938: 95/09/22: Re: Functional simulation of XC3000 libraries
2480: 95/12/14: Re: Gated Clock Problem in Xilinx FPGA Implementation
3834: 96/08/08: Re: Xact 6.0.1: memgen
<yuchiwai@gmail.com>:
115380: 07/02/08: Read CLB information from NCD file
115385: 07/02/08: Re: Read CLB information from NCD file
117881: 07/04/12: Changing LUT input size in synthesize
140748: 09/05/25: Architecture of FPGA
yuebing:
143732: 09/10/22: feof, fseek, ftell on XilFATFS
Yuefang Xiang:
1904: 95/09/19: Altera and Synopsys Interface
Yui:
126918: 07/12/05: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
yujia jin:
72065: 04/08/06: xilinx edk6.2.03i simulation with ncsim
72132: 04/08/09: Re: xilinx edk6.2.03i simulation with ncsim
72135: 04/08/09: Re: xilinx edk6.2.03i simulation with ncsim
Yujie Wen:
148072: 10/06/18: Anyone interested in customizable EDA software for FPGA?
148088: 10/06/20: Re: Anyone interested in customizable EDA software for FPGA?
Yun Feng:
3440: 96/05/30: Help on ALtera FPGA configuration
4360: 96/10/19: help Flex 10K configuration
7161: 97/08/07: Re: Download FLEX10K over the LPT port
YUN SONG HYUN:
18624: 99/11/04: looking for XNF Grammar
Yung Shen:
8592: 98/01/12: 8951 download to xilinx?
YunghaoCheng:
66878: 04/02/28: Active contour model on FPGA
68247: 04/03/30: Real-time Image Process on FPGA
68275: 04/03/31: Re: Real-time Image Process on FPGA
68437: 04/04/04: Re: Real-time Image Process on FPGA
Yunhsianghsu:
40237: 02/03/03: Xilinx MXE 5.5 v.s. ModelSim PE for Xilinx Spartan II only
yuning he:
160089: 17/05/22: Accelerating Face Detection on Zynq-7020 Using High Level Synthesis
160095: 17/05/24: Re: Accelerating Face Detection on Zynq-7020 Using High Level Synthesis
160096: 17/05/24: Re: Accelerating Face Detection on Zynq-7020 Using High Level Synthesis
Yunjian William Jiang:
29477: 01/02/22: Announcement of MVSIS release
Yupik:
80564: 05/03/08: Re: Good, affordable verilog simulator
Yuri:
107018: 06/08/23: Xilinx Virtex-4FC PPC
108603: 06/09/13: Re: Xilkernel pthread_mutex_lock() broken Was: Xilkernel: Problem with mutex
108705: 06/09/15: Re: Xilkernel pthread_mutex_lock() broken Was: Xilkernel: Problem with mutex
Yuri Tregubov:
65599: 04/02/03: ByteBlaster fails on Windows 98
65703: 04/02/05: Re: ByteBlaster fails on Windows 98
Yuri Trifanov:
96: 94/08/14: Re: FPGA Hobbyist and their software/programmer/hardware
129: 94/08/18: Re: FPGA Hobbyist and their software/programmer/hardware
Yury:
31941: 01/06/08: Re: problem: bahavior simulation of xilinx's coregen cores
33551: 01/07/30: Re: Pins state on Spartan XL before config.
37554: 01/12/14: Re: Fondation 4.1 and SpartanXL
37555: 01/12/14: Re: Altera pin drivers
38572: 02/01/17: Coregen Half-Band FIR filter implemenation does not work
38573: 02/01/17: Re: SPARTAN-XL CONFIGURTAION
38597: 02/01/18: Re: Coregen Half-Band FIR filter implemenation does not work
38818: 02/01/25: Re: Coregen Half-Band FIR filter implemenation does not work
38850: 02/01/26: Re: Coregen Half-Band FIR filter implemenation does not work
39627: 02/02/14: Re: Modelsim questions
40814: 02/03/15: Re: PCI design in a Spartan II which crashes in some wintel PCs
41240: 02/03/22: Electronic Parts Locator
41268: 02/03/23: Re: Electronic Parts Locator
41349: 02/03/26: Re: I2C Slave sampling edge
44509: 02/06/21: Re: Multiply by 8 with DLL in Spaertan-II.
44647: 02/06/25: Library declaration in Verilog?
44682: 02/06/26: Re: Library declaration in Verilog?
45205: 02/07/15: Re: Sensitivity list (VHDL) & FPGA pin assignment
61803: 03/10/12: Spartan-IIE Serial vs. JTAG configuration results in different functionality
Yury Wolf-Sonkin:
25956: 00/09/27: RE: timing constraints
<yuryws@banet.net>:
24265: 00/08/01: Re: Variable shifting
24266: 00/08/02: Re: XC4000 select ram
24267: 00/08/02: Re: tbuf
24268: 00/08/02: uDMA66 protocol(ATA-5, ATA-4 Disk controller)
29613: 01/03/01: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
29614: 01/03/01: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
29640: 01/03/03: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
30380: 01/04/05: How to specify Spartan2 GSR/GTS for Synthesis
30486: 01/04/10: Re: How to specify Spartan2 GSR/GTS for Synthesis
<yuryws@my-deja.com>:
24441: 00/08/08: Re: Can i see Gate-delay and Interconnection-delay of circuit on FPGA and where??
24442: 00/08/08: Re: HELP! Strange Xilinx Software Error
25773: 00/09/20: Re: Simulation problem
25774: 00/09/20: Re: PCI-Tip? (for Xilinx Virtex/-E)
25775: 00/09/20: Re: PCI-Tip? (for Xilinx Virtex/-E)
26528: 00/10/19: UCF question
26530: 00/10/19: UCF Question
26553: 00/10/20: Re: PCI Core : Clock Problem
26555: 00/10/20: Any takers for "UCF Question" posted 10/19/2000?
26578: 00/10/20: Re: UCF Question
26581: 00/10/20: Re: UCF Question
26621: 00/10/23: Re: UCF Question
26680: 00/10/25: Re: UCF Question
26681: 00/10/25: Re: UCF Question
26682: 00/10/25: Re: implementing a memory
26771: 00/10/27: Re: UCF Question
26531: 00/10/19: UCF Question
26988: 00/11/07: Re: Need help locking pins for Spartan XL
26989: 00/11/07: Re: Encoding of FSMs internal states
27282: 00/11/17: Re: FPGA Pin Nunber
27403: 00/11/21: Re: Spartan and XC4000 configuration
27404: 00/11/21: Re: Long Island Verilog and VHDL people wanted!!
<yusufilker@gmail.com>:
85670: 05/06/13: Re: Suche FPGA Protoboard
88636: 05/08/24: Re: FPGA Development Board Wish List
91422: 05/11/06: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
91427: 05/11/06: Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
93854: 06/01/02: fx12
95218: 06/01/21: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
95222: 06/01/21: Re: FPGA-Programmable power supply
95652: 06/01/25: encryption
95657: 06/01/25: Re: encryption
95702: 06/01/25: Re: encryption
95684: 06/01/25: Re: encryption
95699: 06/01/25: Re: encryption
95700: 06/01/25: Re: encryption
94977: 06/01/19: Re: OT:Shooting Ourselves in the Foot
98151: 06/03/06: latticexp
107523: 06/08/29: Re: September training?
yusuke:
48889: 02/10/25: cpld I/O modes
48893: 02/10/25: Re: Just some newbie ISE questions...
48924: 02/10/26: Re: cpld I/O modes
59749: 03/08/27: Convert Jedec to logical equations
Yuyuan Lu:
20554: 00/02/14: Altera: how to convert .tdf to .gdf?
yvan.eustache1@etud.univ-ubs.fr:
70068: 04/06/01: Problem with carry reusing RPM with ISE 6.2i and VirtexE
70163: 04/06/07: Problem with the "Write RPM to UCF" command (floorplanner 6)
Yves Bernard:
3013: 96/03/13: Re: SYNARIO tool for CPLD and FPGA ?
Yves Blaquiere:
5732: 97/03/11: Re: Instatiation of Xilinx Primitives in VHDL?
Yves Boudreault:
8974: 98/02/10: PCI Prototyping Board(s)
Yves Deweerdt:
58769: 03/08/01: How to use a TFT screen
58899: 03/08/04: Re: How to use a TFT screen
58964: 03/08/05: Re: Gates Counting?
60042: 03/09/04: Re: New to FPGA, seeking advice
60546: 03/09/16: Re: Digilent board
60931: 03/09/25: Re: Portable computer for FPGA/CPLD tools
60936: 03/09/25: Re: Free WebPack 6.1i Download Available Now for Spartan-3
69174: 04/04/29: Re: good starter kit
Yves Houbion:
10370: 98/05/15: Re: vga gen
10400: 98/05/16: Re: vga gen
Yves Le Henaff:
11785: 98/09/09: Re: DataIO + EPC1 problem
26588: 00/10/21: SPROM size problem
27510: 00/11/26: Xilinx SPROM toaster
Yves Petinot:
41091: 02/03/20: Compilation of VHDL description to target FPGA ... (newbie)
41501: 02/03/30: Compiler library ...
Yves Savard:
15015: 99/03/03: Clock divider
Yves Tchapda:
12202: 98/10/05: Re: A Johnson counter
12504: 98/10/14: 100 MHz FPGA
12944: 98/11/06: Re: Clock Doubler
13102: 98/11/16: Re: Big-Endian vs Little-Endian
15444: 99/03/24: Re:Synplify -> MaxPlus II
15445: 99/03/24: Re:JTAG on Altera Flex 10k (Yves Tchapda)
15770: 99/04/13: Re:One hot comes up cold
16349: 99/05/18: Re: Post route simulation: EDIF or VHDL?
52295: 03/02/06: Re: Clock Enables
52303: 03/02/06: Re: clock ditribution tree
Yves Vandervennet:
12431: 98/10/12: Digital Sine Generator
12654: 98/10/22: Evaluation
Yves Vandervennet TFE:
10360: 98/05/14: Xilinx FPGA Configuration Problem
10647: 98/06/09: Multipliers on FPGA's
Yvon Hache:
21193: 00/03/09: FPGA board
<ywz.oct13@gmail.com>:
98707: 06/03/14: Variable problem
99255: 06/03/21: Re: Variable problem
99680: 06/03/27: Re: Variable problem
Yx Jiang:
45940: 02/08/12: What does the question lie in?
45976: 02/08/13: Re: What does the question lie in?
Yx jiang:
45920: 02/08/10: comp.arch.fpga : How can I join the newsgroup?
yxl:
58032: 03/07/12: How to choose FPGA device?
YY:
54913: 03/04/22: Re: spartan2e vs cyclone
yy:
105664: 06/07/28: Spartan3 5V PCI
105701: 06/07/28: Re: Spartan3 5V PCI
105718: 06/07/29: Interfacing Spartan3 FPGA to 5V PCI
105739: 06/07/31: Re: Interfacing Spartan3 FPGA to 5V PCI
105993: 06/08/04: DDR Controller
106002: 06/08/04: Re: DDR Controller
106039: 06/08/06: Re: DDR Controller
107672: 06/08/30: Spartan 3 PCI-X 133Mhz
107696: 06/08/31: PCI/PCI-X IDSEL
107765: 06/08/31: Re: PCI/PCI-X IDSEL
108222: 06/09/06: Xilinx Spartan 3 Configuration
108382: 06/09/10: Trace under High-Speed Signal
109909: 06/10/07: Spartan 3 DCI
109918: 06/10/08: Re: Spartan 3 DCI
109928: 06/10/08: Re: Spartan 3 DCI
109931: 06/10/08: Re: Spartan 3 DCI
110325: 06/10/13: DDR Address
110362: 06/10/14: Re: DDR Address
110373: 06/10/14: Re: DDR Address
111611: 06/11/06: Chip to Chip LVDS
111638: 06/11/07: Re: Chip to Chip LVDS
111717: 06/11/08: Re: Chip to Chip LVDS
112040: 06/11/15: Synopsys VCS for Windows
<yygcdyla@mailcity.com>:
12938: 98/11/05: Midi archive
yyqonline:
95566: 06/01/24: help:dual-edge flip-flop possible using Verilog?
95627: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95628: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95655: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95654: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95779: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95794: 06/01/26: Re: help:dual-edge flip-flop possible using Verilog?
95695: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95772: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
96153: 06/01/30: a question: task, function vs module
97676: 06/02/25: about Xilinx Chipscope
yyy:
74379: 04/10/09: Re: Daft modelsim question
74380: 04/10/09: RapidIO functional simulation
74382: 04/10/09: Daft RapidIO question
yyz:
71363: 04/07/15: Altera FIR compiler 3.1.0, no filter ouput
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