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hello, I have recently been playing with Nios 16 & 32 bit designs for a range of Cyclones from the 1C20 down to the 1C3 with standalone C code and with the ucos RTK. I would like to do some more formal benchmarks to determine how well this single chip solution compares to a typical design of company A programmable logic part sitting beside company B microcontroller/processor. I am really jazzed by the idea of having a decent 32bit processor , memory interfaces , and a significant amount of logic resources all in a single reasonable cost FPGA. SO MY QUESTION .... what C benchmarks should I use to test the processor ? ... and would there be exisiting performance data for other processors to compare with available somewhere ? I plan on doing the basics like interupt response , task switches , programmed I/O etc... but what else should I do. I do not want huge gazillion line programs but small performance oriented tasks that make sense for this type of processor. Any suggestions invited and if I get anything really useful I will post it on the web. TIA. regards, Khim Bittle khimbittle@cliftonREMOVEsystems.com remove REMOVE to email http://www.cliftonsystems.com/designArticle: 57376
Richard Erlacher wrote: > > One unfortunate side effect of the shift to the major HDL's is the increase > in volume of paperwork. A design that will fit on a single sheet of > schematic often takes dozens if not hundreds of pages of HDL, and that means > one's work is vulnerable to all the simple but common "typer-geographical" > errors we all make from time to time. A 4-page ABEL design takes dozens of > pages of VHDL. Presenting a one-page schematic, or a hierarchy of > schematics makes a lot more sense to managers and software types than does a > listing of HDL. I don't know what designs you do, but I find my HDL is very terse compared to a schematic. Unless the drawing library has some sort of macro generator, a 32 bit wide bus is a lot more work, even with heirarchy, than a single bit data path. In HDL it is normally just a simple notation on the declaration. Random logic is always very hard on schematic. But a 5 schematic page FSM becomes some 20 lines of HDL. Address decoding is just a single line of HDL in most cases, but can be a half a page of gates and wires. > There will always be a place for schematics, since a picture, still, is > worth 1000 words ... perhaps more in VHDL. Only if you have pictures the size of a Greyhound Bus! I use pictures to *document* the HDL since they give a level of clarity to the data path that is not nearly as clear in text. But I don't need schematics, I can use Visio or any other drawing package that works well and is target independant. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57377
Jon Beniston wrote: > > "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message > news:bdikok$1toa$2@agate.berkeley.edu... > > In article <864a80dc.0306271440.79910d76@posting.google.com>, > > Naveed <visualfor@yahoo.com> wrote: > > >As far as technical support go, both companies suck (probably Altera > > >sucks more than xilinx). They normally hire fresh college graduate > > >for support, and those kids can't answer much. > > > > The major exception is comp.arch.fpga, where you have Peter Alfke and > > Austin Lesea answering Xilinx questions. > > The joke is, you probably get better answers in this newsgroup than if you > go through their offical support channels. And it costs a lot less! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57378
"Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message
news:3EFC59CE.8090103@xilinx.com...
> Ralph,
>
> Another method (aside from passing an INIT) is to initialize the signal
> that will be registered:
>
> library ieee;
> ues ieee.std_logic_1164.all;
>
> entity ff is
> port (d, c : in std_logic;
> q : out std_logic);
> end entity;
>
> architecture ff_arch of ff is
> signal q_temp : std_logic := '0'; -- XST will pass the proper INIT
> value based off of the signal initialization
> -- This INIT value is the state to
> which the register will power up
> -- q_temp is the signal that will be
> registered
> begin
> :
> :
>
>
> Steve
>
Hi Steve,
Thanks for the reply.
I am not much of a VHDL person, you wouln't by chance know how to set the
values if the register is declared in a record that in instantiated using
the above syntax?
type v_reg_type is record
-- registers
IOLatch : std_logic_vector(4 downto 0);
IOLatch2 : std_logic_vector(4 downto 0);
end record;
signal r, rin : v_reg_type;
Thanks for any help
Regards
Ralph
Article: 57379Subroto Datta wrote: > > Rick, > > Based on feedback from users like yourself we have expanded the device > coverage to include the Flex10KA devices in QII 3.0, which was released to > production/manufacturing last Friday. Quartus II Timing Analysis > capabilities and algorithms than Max+Plus II. We are constantly working to > improve the design migration experience from Max+Plus II to Quartus, so that > the users can easily access the more advanced capabilities if they need it. > > For a description of the new features available in Quartus II 3.0 please > click on the url below > http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whatsn > ew.jsp?xy=qts1_qwn > > - Subroto Datta > Altera Corp. Thanks for the feedback. I don't want to sound like sour grapes, but this update is a bit late... like two years and about four months of 80 hour work weeks. That summer was one of my "living hell of engineering" memories. On the plus side, I got to work closely with some really talented engineers (maybe a bit too closely) and actually got a thousand dollars as a cash award (a lot cheaper than paying overtime). The only significant issue I might have with Quartus on my new board is the lack of modular configuration. A recent Xilinx post indicated that they actually support this now. Is Altera doing anything like that? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57380
Paul Leventis wrote: <snip> > > I would agree it is preferable to let the tools handle the details of > > routing, BUT you need to be able to control PLACEMENT in such a way > > that there is (almost) only one routing solution. > > My position is that with a given placement, the router will tend to find the > best routing solution; and it will do so in the presence of routing > congestion or many different, often conflicting choices. But I agree that > if a human could find a placement that results in lower routing stress (not > the same as "one solution"), this can in turn result in better routing. All > I'm arguing is that more often than not, the push-button placer will beat > out the human; that appears to be our only point of disagreement. No, I think we agree on that as well. The important point is to maintain feedback to ensure those who write the SW, do not morph 'more often than not' into meaning 'we can leave off manual controls'. ( == Big Green Button mindset ) The best tools find a very good solution AND allow designers to steer/control them. > > BTW, this only applies to Stratix/Cyclone -- in FLEX & APEX with their > hard-boundaries in the routing, it's easier for a human to find a good > floorplan for their design. > > > Then, you should also also be able to 'lock' the routes. so > > that a design block that has been tested, and 'signed off' > > will NOT change due to iterations in an unrelated portion of the chip. > > All of this makes the design more predictable, and SHOULD also > > give significant P&R runtime savings. > > You should be able to, and you can in Quartus II. Locking routing (we call > it routing back-annotation) for the purpose you mention can be handy. Back-annotation in the PCB-EDA world means syncronise of the labels of components/nets and or gate-swap/pin swap align. Words like lock and preserve are more usual tags when talking of routes. > It is especially handy for when you make a small change to an already verified > design and want to minimize changes in the design, or when you want to port > designs between versions of Quartus while maintaining the same fit. IIRC you mentioned this in an earlier post, and I agree it is an important new feature. > But predictability sometimes comes at a price. Using a block-based design > methodology where you lock routing then integrate your blocks may result in > lower performance or worse routability when compared to the same design with > the routing constraints removed. If the router believes it needs to alter > the route in one of your blocks, it's usually for a good reason! With other tools suppliers, I have asked about a user selectable 'spread and squash' algorithm. Think of it as a vibration compactor that iterates from a valid PASS, and trys to maximise headroom, for possible later changes. It would be by nature a slow process (eg weekend run ). In a CPLD context, it would shuffle/swap to reduce fan-in and macrocell usage per-block. In a FPGA context, it could work to give more margin on timing closure. It should have the capability to 'suggest a better pin allocate' To make use of such exhaustive-pass features, some locking/preserve is needed. Sounds like you are close to being able to offer this feature ? -jgArticle: 57381
rickman wrote: > > Subroto Datta wrote: > > > > Rick, > > > > Based on feedback from users like yourself we have expanded the device > > coverage to include the Flex10KA devices in QII 3.0, which was released to > > production/manufacturing last Friday. Quartus II Timing Analysis > > capabilities and algorithms than Max+Plus II. We are constantly working to > > improve the design migration experience from Max+Plus II to Quartus, so that > > the users can easily access the more advanced capabilities if they need it. > > > > For a description of the new features available in Quartus II 3.0 please > > click on the url below > > http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whatsn > > ew.jsp?xy=qts1_qwn > > > > - Subroto Datta > > Altera Corp. > > Thanks for the feedback. I don't want to sound like sour grapes, but > this update is a bit late... like two years and about four months of 80 > hour work weeks. That summer was one of my "living hell of engineering" > memories. :) How does it go ? - "Pioneers are the ones face down in the desert with arrows in their backs" Looking on the bright side, at least (hopefully) the support is now in there, making the task easier for others, and for you 'next time'. Would be interesting to hear if it does actually solve your problems. -jgArticle: 57382
Richard Erlacher wrote: > <snip> > One unfortunate side effect of the shift to the major HDL's is the increase > in volume of paperwork. A design that will fit on a single sheet of > schematic often takes dozens if not hundreds of pages of HDL, and that means > one's work is vulnerable to all the simple but common "typer-geographical" > errors we all make from time to time. A 4-page ABEL design takes dozens of > pages of VHDL. Sounds like a good argument for staying with ABEL ? -jgArticle: 57383
Hi Jim, > With other tools suppliers, I have asked about a user selectable > 'spread and squash' algorithm. > Think of it as a vibration compactor that iterates from a valid PASS, > and trys to maximise headroom, for possible later changes. It would be > by nature a slow process (eg weekend run ). > In a CPLD context, it would shuffle/swap to reduce fan-in and macrocell > usage per-block. In a FPGA context, it could work to give more margin on > timing closure. > It should have the capability to 'suggest a better pin allocate' The default way that Quartus runs will result in it achieving the most timing margin/slack it can (within reason) on all connections. So this fits your timing-margin criteria (and doesn't take all weekend). If you want Quartus to run all weekend for more timing margin, use the Design Space Explorer feature I mentioned in an earlier post. I *think* that getting more timing margin and leaving room for future changes are competing goals -- generally, you want your logic close together in a big ball in order to get the most slack across all connections (well, sort of -- at some point congestion becomes a bigger effect than closeness...). But if you then need to add a bit of logic, the change will be more disruptive -- which leads to the idea you mention of inserting blank space or such. But that could reduce timing margin... So maybe the solution is that the user provides their desired trade-off on whitespace vs. timing margin? > The important point is to maintain feedback to ensure those who write > the SW, do not morph 'more often than not' into meaning > 'we can leave off manual controls'. ( == Big Green Button mindset ) > The best tools find a very good solution AND allow designers to > steer/control them. Agreed. You're not the only user who feels this way, and that's why more and more such capabilities are being added to our tools. At the same time, we keep beating on the quality of the push-button flow. > Back-annotation in the PCB-EDA world means syncronise of the labels of > components/nets and or gate-swap/pin swap align. > Words like lock and preserve are more usual tags when talking of > routes. Well, we are the company that calls place & route "fitting" :-) There is often history behind such terms... I'll dig up the story behind the back-annotation name sometime. Regards, Paul Leventis Altera Corp.Article: 57384
Paul Leventis wrote: > > Hi Jim, > > > With other tools suppliers, I have asked about a user selectable > > 'spread and squash' algorithm. > > Think of it as a vibration compactor that iterates from a valid PASS, > > and trys to maximise headroom, for possible later changes. It would be > > by nature a slow process (eg weekend run ). > > In a CPLD context, it would shuffle/swap to reduce fan-in and macrocell > > usage per-block. In a FPGA context, it could work to give more margin on > > timing closure. > > It should have the capability to 'suggest a better pin allocate' > > The default way that Quartus runs will result in it achieving the most > timing margin/slack it can (within reason) on all connections. So this fits > your timing-margin criteria (and doesn't take all weekend). If you want > Quartus to run all weekend for more timing margin, use the Design Space > Explorer feature I mentioned in an earlier post. I see more info on this is here http://www.altera.com/products/software/pld/design/place/timing_closure/qts_timing_closure_features.html#explorer_script Sounds like what I was asking for :) <snip> > > Back-annotation in the PCB-EDA world means syncronise of the labels of > > components/nets and or gate-swap/pin swap align. > > Words like lock and preserve are more usual tags when talking of > > routes. > > Well, we are the company that calls place & route "fitting" :-) There is > often history behind such terms... I'll dig up the story behind the > back-annotation name sometime. On the Altera WEB I see this terminology: "Enhanced LogicLock™ methodology so routing can be locked down as well as logic placement " "Fitting" shows the PLD ancestory :). The very first PLD tools could be called 'allocators' - they did not have much to do, appart from 'tick off the fuses'. As PLDs got more complex, and ideas like Fan-In appeared, the fuse generation needed more steps, and so I belive 'Fitter' was coined. The newest fitters will re-write eqns if needed to pack better, so do rather more than simply allocate MUXes and Fuse-map. -jgArticle: 57385
while synthesizing using XILINX ISE5, using verilog language, i got this message Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Mcompar__n0003_ALB1:O | NONE(*)(myValid_0_0) | 3 | Mcompar__n0001_ALB:O | NONE(*)(mem_pos_7_0) | 11 | temp:Q | NONE | 22 | clk | BUFGP | 31 | -----------------------------------+------------------------+-------+ (*) These 2 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. I tried to use this constraint as i saw in the refernce, but nothing changed.. i wrote these lines // synthesis attribute clock_signal of myValid_0_0 is no; // synthesis attribute clock_signal of mem_pos_7_0 is no; but when i synthesize it again, nothing changed... Best regards Mandilas AntonyArticle: 57386
i want to write a dual port memory module, but i want to preload it with some values in some specific memory locations. I have written some code for the first part of it. but i can not do it some way to preload values . Does anyone has any idea? Best regards AntonyArticle: 57387
i forgot to mention that i use spartan-II and verilog. Mandilas Antony wrote: > i want to write a dual port memory module, but i want to preload it with > some values in some specific memory locations. I have written some code > for the first part of it. but i can not do it some way to preload values > . Does anyone has any idea? > > Best regards > Antony >Article: 57388
Rick,
Can you elaborate some more on what is meant by modular configuration?
Also, as a fellow engineer I sincerely hope you never have any more of those
living hell memories, at least not due to Altera products. If you do respin
your design using Quartus II 3.0 we'd be keen in obtaining your feedback.
- Subroto Datta
Altera Corp
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3EFE6AC0.3F35884D@yahoo.com...
> Subroto Datta wrote:
> >
> > Rick,
> >
> > Based on feedback from users like yourself we have expanded the device
> > coverage to include the Flex10KA devices in QII 3.0, which was released
to
> > production/manufacturing last Friday. Quartus II Timing Analysis
> > capabilities and algorithms than Max+Plus II. We are constantly working
to
> > improve the design migration experience from Max+Plus II to Quartus, so
that
> > the users can easily access the more advanced capabilities if they need
it.
> >
> > For a description of the new features available in Quartus II 3.0 please
> > click on the url below
> >
http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whatsn
> > ew.jsp?xy=qts1_qwn
> >
> > - Subroto Datta
> > Altera Corp.
>
> Thanks for the feedback. I don't want to sound like sour grapes, but
> this update is a bit late... like two years and about four months of 80
> hour work weeks. That summer was one of my "living hell of engineering"
> memories.
>
> On the plus side, I got to work closely with some really talented
> engineers (maybe a bit too closely) and actually got a thousand dollars
> as a cash award (a lot cheaper than paying overtime).
>
> The only significant issue I might have with Quartus on my new board is
> the lack of modular configuration. A recent Xilinx post indicated that
> they actually support this now. Is Altera doing anything like that?
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 57389Mandilas Antony <mandilas_antony@yahoo.com> wrote: : i want to write a dual port memory module, but i want to preload it with : some values in some specific memory locations. I have written some code : for the first part of it. but i can not do it some way to preload values : . Does anyone has any idea? Look at the Xilinx site for the INIT constraint. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57390
"Mandilas Antony" <mandilas_antony@yahoo.com> schrieb im Newsbeitrag news:3EFE9917.6030805@yahoo.com... > I tried to use this constraint as i saw in the refernce, but nothing > changed.. > > i wrote these lines > > > // synthesis attribute clock_signal of myValid_0_0 is no; > // synthesis attribute clock_signal of mem_pos_7_0 is no; > > but when i synthesize it again, nothing changed... How should it? You use these two signals as a clock (there is somewhere a "myValid_0_0'event" used), so the synthesizer must generate a FLipFlop and connect a clock to its clock input. What you must do is to use it a as a clock enable, NOT as a gateing for a clock like my_clock <= global_clock and my_enable; -- BAD stuff -- Regards FalkArticle: 57391
Jim Granville wrote: > > rickman wrote: > > > > Subroto Datta wrote: > > > > > > Rick, > > > > > > Based on feedback from users like yourself we have expanded the device > > > coverage to include the Flex10KA devices in QII 3.0, which was released to > > > production/manufacturing last Friday. Quartus II Timing Analysis > > > capabilities and algorithms than Max+Plus II. We are constantly working to > > > improve the design migration experience from Max+Plus II to Quartus, so that > > > the users can easily access the more advanced capabilities if they need it. > > > > > > For a description of the new features available in Quartus II 3.0 please > > > click on the url below > > > http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whatsn > > > ew.jsp?xy=qts1_qwn > > > > > > - Subroto Datta > > > Altera Corp. > > > > Thanks for the feedback. I don't want to sound like sour grapes, but > > this update is a bit late... like two years and about four months of 80 > > hour work weeks. That summer was one of my "living hell of engineering" > > memories. > > :) How does it go ? - > "Pioneers are the ones face down in the desert with arrows in their > backs" > > Looking on the bright side, at least (hopefully) the support is now in > there, > making the task easier for others, and for you 'next time'. > Would be interesting to hear if it does actually solve your problems. > -jg I seriously doubt that anyone will ever find out. That design was a product upgrade and it had to be scaled back a bit (along with some very novel design techniques) to get it to fit in the part. The company would have to be managed by total morons for someone to decide to rework that design... maybe that isn't so unlikely after all ;) If you are reading this, you know who you are! All joking aside, I am very glad to be rid of that employer. In a meeting about how to bring the project to completion (about 8 people were still working the various issues of which the FPGA was the only one that had a wide open time line) the second level manager in charge of the entire hardware department indicated that he had sent a memo to marketing before the project had started explaining how difficult the initial FPGA design had been. He indicated that they could not even guarantee that the FPGA design could "ever" be completed due to this timing analysis problem. So they knew about the problem, they knew it would take *lots* of hours to deal with and let us work until we dropped to get it done. They also knew that we might *never* bring the problem to closure. I guess the real problem I have with them is the fact that they hired me as a very experienced engineer to "lead". But when I tried to show them how to deal with problems in a way to minimize effort and risk, they did not want to hear it. They just wanted someone to keep doing what they had been doing for years. All I heard about was a quarter million dollars a month in lost sales and how we didn't have time to explore risk reduction efforts. Hmmm... a project with high risk, an impatient, major customer waiting for the upgrade and management does not want to learn about "risk management". What's wrong with this picture? I guess I am still a bit steamed about the whole thing. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57392
Subroto Datta wrote: > > Rick, > > Can you elaborate some more on what is meant by modular configuration? > Also, as a fellow engineer I sincerely hope you never have any more of those > living hell memories, at least not due to Altera products. If you do respin > your design using Quartus II 3.0 we'd be keen in obtaining your feedback. > > - Subroto Datta > Altera Corp Thanks. I just finished a post explaining what the real problem was, which had to do with management rather than technology. One can't expect the tools to be perfect, even though that was a major bug. But the real problem was that management had known about the problem before this upgrade project was started and they failed to take *any* risk reduction efforts. That was just plain stupid! But the second level manager in charge of the project was a young, inexperienced manager who was technically excellent. So his experience told him that if you put a good engineer on a project all problems would just fall away. Obviously some problems aren't so easily solved. It won't be redone since I am no longer at the company and they have *no* interest in opening that can of worms again. I am building boards for my own company. My current design is using a single FPGA to tie four daughterboards to the main DSP board. Each of the daugherboards can be any of N so in general there will be N^4 combinations of modules and interfaces. Clearly as the variety of daughterboards goes up, the total number of downloads for the FPGA goes up very, very quickly. Instead of making and verifying all 4^N downloads for the FPGA, the interfaces can be designed as "modules" which can be overlayed on the main FPGA download. So the main FPGA is loaded, the module identities are determined and then the corresponding interfaces for each of the modules can be downloaded. Our first similar board used two modules and an FPGA for each interface. But once we decided to go with four interfaces we ran out of room on the board and needed to put it all in one FPGA. Xilinx claims to support this in their tools and a couple of app notes seem to show you how to do this. Does Altera have anything like this or another way to support separate design and download of modules? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57393
Martin Euredjian <0_0_0_0_@pacbell.net> wrote: > Pro's and con's of setting STARTUP_WAIT = "TRUE"? > When to use it and when not. Why? The clock outputs from the DCM need some time to settle down. If your design need a stable clock (driven from a DCM) to work as expected, it is a good choice to set STARTUP_WAIT to true. If your design doesnt care about the "DCM clock garbage" at startup you can leave this attribute at false. WD --Article: 57394
Sander Vesik <sander@haldjas.folklore.ee> wrote in message news:<1054761767.988243@haldjas.folklore.ee>... > Anybody know of Cyclone EP1C12 (preferably) or EP1C20 > (also ok) based PCI development boards? Do such things > even exist - or in other words, what is the approximate > timline after chip availability that one can expect such > to be around? The cyclone PCI board actually does exist, but I guess from korea so docu is a bit hard to read :) hmmm tried to find the link in my favorites but failed, sorry, there was a nice picture with a cyclone device -the 5v level converters also clearly seen- looked like real cool board, but not being able to understand any of the text ... antti mis eestis keegi teeb miskit altera ja PCI ga? paris lobus, tood ei paku? ma ise mangin xilinx ja pci ga praeguArticle: 57395
Hello, I am new with FPGA. Is it possible to simulate a VLIW multiprocessor using a FPGA devise ? If yes which system I should use for design and implementation ? If not do exist any other system capable to simulate such an architecture ? Thank you for your collaboration. Regards, GianArticle: 57396
Jon Beniston wrote: > > The joke is, you probably get better answers in this newsgroup than if you > go through their offical support channels. That's not quite fair to our hot-line engineers. I just counted: Austin and I together have over 70 years of digital design experience under our two belts. But we could not possibly support the tens of thousands of customers that the hotline does. And we appreciate the trust that Xilinx puts in us, letting us answer tricky issues without having to cover our a... Anyhow, we accept the kudos gracefully. PeterArticle: 57397
----------------------------------------------------------------------------
------
HOW DOES SPARTAN-3 DIFFER FROM VIRTEX-II?
Spartan-3 is supposed to be = Virtex-II minus "some features".
Unfortunately,
Xilinx does not appear to provide a comprehensive list of those differences.
The following is my attempt at making such a list based on a first-cut
review
of each families' literature.
Anyone have any comments, corrections, additions, or questions about this
list?
Then post them here and please 'cc' me via email.
Thank you.
Bill Lenihan lenihan3we@earthlink.net
----------------------------------------------------------------------------
------
Vccint = 1.2v ..... instead of V-II's 1.5v
Are there any off-the-shelf, 1-chip linear regulators (not switching
regulators) that can supply 1.2v?
Vccaux = 2.5v ..... instead of V-II's 3.3v
half the slices are NOT full-featured: missing RAM & shift-register
capability
up to 4 DCMs ..... instead of V-II's 12
DCM works on input clocks up to 325 Mhz ..... V-II up to 450 Mhz
8 global clocks ..... instead of V-II's 16
data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II
has both
greater # of I/O, due to staggered pad scheme at chip periphery
LVPECL I/O not available
LVDS only w/ Vcco = 2.5v ..... V-II can run LVDS from Vcco = 2.5v or 3.3v
Is there any capability for Spartan-3's +3.3v LVTTL inputs & outputs to
interact with other devices that use +5v TTL? ..... V-II (and Virtex-E)
+3.3v LVTTL inputs could be driven by +5v TTL outputs if an appropriately
sized current-limiting resistor were in series, while V-II (and Virtex-E)
+3.3v LVTTL outputs could safely connect directly to +5v TTL input devices
with no intervening resistor networks.
configuration pins are LVCMOS25 @ 12mA ..... V-II's are LVTTL @ 12mA
data sheet mentions a Master/Slave "Parallel" configuration mode that LOOKS
the same as V-II's "SelectMap" mode. Are they completely identical? If so,
then why do they have different names? (I know, marketing droids -- who
specialize in renaming that which already has a name -- rule the universe.)
Flip-Chip packages not available
90 nm process ..... V-II uses 120/150 nm [not that the OEM designing with
FPGAs really cares]
Article: 57398Hi, Everybody, I'm looking for recent analytical papers talking about FPGA vs. DSP (advantage comparison, etc). Would be grateful if somebody could point me to any of these? Cheers, Yu ShiArticle: 57399
Hello I am trying to find tools for benchmarking a processor written completely in Verilog as part of my research Projects at the University of Wisconsin- Madison. I bascially needed support for an ARM based processor.(ARMv4T)
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