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On Fri, 01 Aug 2003 17:56:13 -0700, John_H wrote: > "Jay" <se10110@yahoo.com> wrote in message > news:MPG.19944c08c648a2109896bb@news.surfcity.net... <snip> >> Well, I cheated just a bit, I don't have a VCO, I have a motor control >> unit. I'm varying the voltage to the motor control unit to get a >> "frequency" out of it. My VCO "gain" is really the motor gain (RPM/Volt >> translated to Hz / volt). > </snip> > > Rather than using an external phase comparator, could you sample the > motor signal to give you how "far" you are from your desired zero phase? > This error magnitude would work to give a better frequency match. If > you know how far off you are in phase, the integral of the frequency > difference over your period (1Hz to 50Hz) can be calculated to regain > zero phase. The motor control slew rate will need to be part of the > overall phase-locked-loop design. > > <snip> >> Using PWM would work for my application upto 11-12 bits(given a >> 40-60MHz input clock), but beyond that my PWM output frequency drops >> too low. I haven't solved this problem yet...dithering may work here. > </snip> > > You could go to a sigma-delta style converter rather than a simple PWM. > I'm not sure if someone has convenient reference code, but you can get > extreme precision in your control voltage as long as you filter out the > high frequency noise that the converter produces. I've wanted to do > something with this approach using a single-package D-flipflop with nice > analog rails to give me a clean voltage (since FPGA outputs are affected > by what else is going on in the I/O or the core). > An even simpler improvement on straight PWM than a Sigma-delta modulator is to bit-reverse the PWM reference count and magnitude compare that with the PWMVal, giving almost the same interleaving as sigma-delta but a simpler circuit, you can even trade off the size of the bit reversed field in the reference count to give less ripple but more transitions or vice versa... > Given that the motor control may not react as quickly as one cycle, you > may not need high resolution and the PWM output may be fine. I would think that as your (PID or whatever) control loop sample period becomes smaller the needed PWM resolution drops to 1 bit, even ignoring mechanics, the motor inductance will limit your rate of change of current... Peter WallaceArticle: 58826
"Nicholas C. Weaver" wrote: > > In article <3F2A868E.85807215@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > > >Not always true. Anytime you add a register, you have to add setup time > >and output delay to your path. Plus your path must be broken > >arbitrarily and it is not simple to pick the optimal points. By not > >adding registers and using an enable on the one register, you allow the > >full N clock cycles for the logic to settle. This was exactly how we > >designed an ATM chip. Once the cell had been received we had three > >clocks to analyze it and decide what to do with it. Turns out we needed > >all three as a multicycle. If we had pipelined it we would not have met > >the timing budget. > > Of course, two observations: > > 1) Flip-flop setup and clk->Q combined are pretty low compared to > interconnect costs. EG, from the Spartan II datasheet, the additional > time if the flip-flop is the LUT output is ~2 ns. So even if your > design is running at 100 MHz in one of these parts, only 20% of your > time is going to the flops. > > In the Virtex II its in the <1 ns range on the slowest speedgrade. > > 2) Retiming can place those registers in the right place. You can > either do the transformation by hand or use a tool, but I'm not sure > how well Synplify will handle retiming through preplaced blocks, and > the attempt to maintain initial conditions really hurts the power of > this transformation. > > Nonetheless, it is possible, and NOT hard (given a timing model), to > move all the registers manually into the right place, given the > algorithm to solve the problem. If a block is feed forward, and you > just want to repipeline the block, the task is easier. The point is, why bother spending the effort to do something that is going to *slow* down the design and possibly break it? As in the example I gave, we found it was not worth the effort in our design to even consider adding the registers. Besides, they are not anything remotely like free in a design that has a high utilization. I guess you just don't like multi-cycle constraints. But I find they are quite easy to use if used correctly. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58827
Austin Lesea wrote: > > Rick, > > Fair enough. If it has to drive all the way to 5.0 V CMOS, then you have outlined > your constraints. > > Too bad that they did not choose to be TTL compatible. Are you talking about the PC/104 bus? That is based on the ISA bus, which IIRC predates FPGAs. I think you mean too bad it is not limited to TTL thresholds. Even TTL logic outputs can and will rise above 3.6 volts if lightly loaded. The pullup resistors are there for wire ORing of a few signals (like ENDXFER- and IOCH16-) which I am sure you are familiar with. The pullups are stiff to give speed. How else would you have done that? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58828
Rob Judd wrote: > > Rick, > > Yet another example of lack of imagination. Why can't these guys supply > such chips mounted on a small pluggable board? > > Sheesh. Which guys? I am sure you can order an FPGA on a plugin board. I did just that some years ago when QFPs were hard to work with on wirewrap boards. Aries is one company who comes to mind. Regardless, you don't really need to limit your chip packages unless you are on a shoestring. If you can't solder it yourself, there are lots of places that will do it for you. How do you think the modules would get made? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58829
Spam Hater wrote: > > On Thu, 31 Jul 2003 21:27:46 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >I could have emailed this directly to Peter, but I thought it might be > >useful to others. I have a socket on my board which requires 5 volt > >tolerance on a number of pins. It also has to be reasonably low power > >meaning I can't power a high current surge on power up. The part I > >currently have selected is the Altera EP1K30 which seems to do > >everything I need and should live with my 200 mA power on surge > >limitation. But all the other parts on the board can be Xilinx. So I > >would like to find a Xilinx alternative for this socket. > > > >In the Xilinx camp I have considered a couple of devices which are 5 > >volt tolerant. > > > >Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part. > >SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only. > >Spartan2 - 2.5 volt, very high power, block RAM, current part. > > > >Is this a correct summary? Are there any parts that I have not listed > >that I should consider? > > Xilinx 95xx CPLDs. Up to 512 macrocells, I believe. Thanks for the suggestion. But 512 cells in no more than the XCR3512XL and it still does not have any memory. > >I have been given a very good price on the Coolrunner XCR3512XL, but > >even with 512 macrocells, including small FIFOs (8 bits x 16 words, two > >FIFOs) uses up half the chip. > > > >The Spartan 2 is not an option due to the startup power. > > The Spartan2 startup power is not all that bad. Are you thinking of > the Virtex? That one has a nasty startup surge. I have seen little or no indication of this. The last I heard, I got an email from someone at Xilinx saying the startup current of the Spartan II industrial parts would be the same 500 mA as the commercial parts. I don't remember if it was the XC2S or the XC2SE parts and I have not verified this in the data sheet yet. But my total power limit is 250 mA, so 500 is still too high. > >If I am willing to work with the SpartanXL and I can get a good price on > >it, I could put that on the board. I am not crazy about having to use > >older, not so well supported tools. Having to use a different tool is > >the only real reason to not use the Altera part. What tools are > >available exactly? If I don't buy a third party VHDL synthesis tool, is > >there something equivalent to XST in the older "Classic" tools? Are the > >"Classic" tools "paid for" only? > > > > Be warned. The "entrance price" for a Spartan/SpartanXL synthesizer > is around $5K (US). There. Don't say I didn't warn you. > > No, there are no other alternatives at this time. > > Now, if Xilinx were to contact me off-line, I could help them with a > win-win solution for this. Hmmm... what does that mean? Are you marketing a synthesis tool? > >Any other chip family alternatives? > > Cypress? All their stuff is either not 5 volt tolerant or the same old CPLDs that everyone else has as far as I can tell. Too bad the Lattice LC5000 parts are not 5 volt tolerant enough. I thought I had a real winner with them. Looks like I will be using the Altera EP1K30 for this one and the Spartan 3 for the large one. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58830
>So clever people used the DDS to create a sine wave, then filtered the >sine wave with an analog filter, then used a comparator to slice it back >into the digital domain, with reduced jitter. What sort of analog filter do I need for this approach? Do I need a serious narrow band pass filter? Aka a crystal if I want a real good one, which probably means I should just get a packaged osc. Or will a simple R/C low pass filter that cuts off at the target frequency provide enough attenuation at the 3rd/5th harmonics to make a low-jitter clock? R/C filters are pretty cheap. You might need some ugly op-amps and more Rs and Cs to get several poles. [But logic is cheap too, especially if you already have an FPGA and board space is critical.] > But it is a tortuous detour, and faster multi-phase DDS > seems to be so much simpler... That just reduced the jitter by a factor of "multi". Right? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58831
Jon, Yes I've haerd of such techniques. Mind you, a TQ144 is the small end of the range these days and the sort of chip I would have attempted hand-soldering. Once we get to 288 finer pins you can just skip it. All this also assumes a masked board, of course. It won't work otherwise. Rob Jon Elson wrote: > > Rob Judd wrote: > > >Nicholas, > > > >No, manufacturability is the main concern. I don't have easy access to > >high volume production machinery, which is almost guaranteed to be > >necessary for most of the newer packages. If I can plug it in, great. If > >not, I need to be able to hand-solder it with a standard Weller iron. > > > > > I'm hand soldering TQ144 and similar packages with .5 mm lead spacing by > hand. > My procedure uses solder paste applied VERY sparingly with a ground down > hypodermic needle. I think I'm using an 18 Ga needle now, and it is way too > large. I lay a very thin bead of paste down along the pad rows. I then > position the > chip with curved-point tweezers and touch the soldering iron to one > corner lead. > I then adjust position and solder the opposite corner lead. if the > alignment needs to > be touched up, I can "walk" the chip by reheating the corners > alternately. When alignment > is good, I then wipe the iron gently down the rows of pins, such that > the iron tip is > touching the board lands and the end of the chip's pin. This takes > about a minute > per chip. If you get the right amount of solder applied, bridges are > rare. If you > get them, very fine desoldering braid can be used to remove excess > solder, then > the bridges will break by themselves. Apply Iospropyl Alcohol (rubbing > alcohol > works pretty well) or denatured alcohol to the chip, and brush with an old > toothbrush, then wash immediately with the spray hose on a kitchen sink, > shooting > the water under the chip if possible. (You want to get rid of the stray > beads of > solder remaining between leads.) > > JonArticle: 58832
rickman wrote: > > Rob Judd wrote: > > > > Rick, > > > > Yet another example of lack of imagination. Why can't these guys supply > > such chips mounted on a small pluggable board? > > > > Sheesh. > > Which guys? I am sure you can order an FPGA on a plugin board. I did > just that some years ago when QFPs were hard to work with on wirewrap > boards. Aries is one company who comes to mind. > > Regardless, you don't really need to limit your chip packages unless you > are on a shoestring. If you can't solder it yourself, there are lots of > places that will do it for you. How do you think the modules would get > made? At $150.00 each no doubt. I've seen very few, and they're sold as "Development Kits/Aids". The smaller market is being ignored by chip manufacturers (these guys). I don't just want one, I want to be able to buy them for production in small quantities and design with them. As far as the ease of getting them mounted is concerned, you obviously don't live in Australia. RobArticle: 58833
rickman wrote: > The point is, why bother spending the effort to do something that is > going to *slow* down the design and possibly break it? As in the > example I gave, we found it was not worth the effort in our design to > even consider adding the registers. Besides, they are not anything > remotely like free in a design that has a high utilization. This mirrors my experience. In a recent FPGA design, I had to multiply two signed 24 bit numbers. It seemed easier to implement it as a multicycle path than to break it up by hand into pipelined stages. Now if there is some tool that will insert the pipelining automatically that is easy to use and doesn't cost $20K/seat I would like to hear about it, because it is a small hassle to set up the multicycle timing constraints. JCCArticle: 58834
On Thu, 31 Jul 2003 21:27:46 -0400, rickman wrote: > I could have emailed this directly to Peter, but I thought it might be > useful to others. I have a socket on my board which requires 5 volt > tolerance on a number of pins. It also has to be reasonably low power > meaning I can't power a high current surge on power up. The part I > currently have selected is the Altera EP1K30 which seems to do everything > I need and should live with my 200 mA power on surge limitation. But all > the other parts on the board can be Xilinx. So I would like to find a > Xilinx alternative for this socket. How many signals have to be 5V tolerant? Another alternative is to use translators. Translators are small and cheap, you can get 2.5V <-> 5V level shifting transceivers from TI or IDT. It's kind of ironic that as FPGAs get bigger and bigger it becomes necessary to go back to msi when you need to talk to an old 5V bus.Article: 58835
Please help, I'm trying to create combinational latch in XC9536XL (like from help) and there is written that I must incluce NOREDUCE parameter (into schematics). But I don't know where to include it. I tried everything, but still it does warning "The signal(s) 'xlxn_16' are in combinational feedback loops. These signals may cause hazards/glitches. Logic should include hazard reduction circuitry to avoid hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry." I'm trying to write it to nets or instances, clicking, then "add", name NOREDUCE, value "" or "TRUE" or "true". Please help me what i'm doing wrong. OndrejArticle: 58836
Peter, Austin, Is it possible to build 5V IOs on a 90nm process? The world is full of antique buses that aren't going to go away anytime soon. A couple of medium sized devices targeted at the legacy bus interface market would be useful. I'd suggest doing two devices, a XC3S1500 and a XC3S400 with 5V/3.3V IOs. You could toss the multipliers, those aren't useful in this application, as well as all of the fancy modern IO standards which also aren't needed for this application, block RAM is important because bridges need large FIFOs. The other thing that you would want to do is modify the DCM so that it could support lower clock frequencies, 10Mhz -20Mhz is common in this world.Article: 58837
On Sat, 02 Aug 2003 02:59:01 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >> >> Now, if Xilinx were to contact me off-line, I could help them with a >> win-win solution for this. > >Hmmm... what does that mean? Are you marketing a synthesis tool? > I know how to get it done. Too big to do in my 'spare time'; I would need their involvement. > >Looks like I will be using the Altera EP1K30 for this one and the >Spartan 3 for the large one. Sane and rational choice. I like the EP1K. Spartan3 might have availability problems right now... Cheers, SH7Article: 58838
rickman wrote: > I replied to your email about this. I recommend that you not use a > clock buffer for the 1 kHz reference. Instead treat it like a signal > and reclock it into each of the 8 QCM clock domains. There you can > detect the rising edge and use that to enable a 1 second counter (0 to > 999). > > Of course this will use more logic than a single time base counter, but > you will not need a ninth global clock route. Since your chip does not > have a ninth clock input, your only other alternative is to control the > skew on the clock net and to manually verify the skew on every P&R. I > don't think the tools will automatically control this for you. Reclocking the slow clock is probably the best solution, however there is a way to run a clock not using the global clock routes and get the static timing automatically verified. The solution is to use two groups of FFs, one for rising edges of clock and one for falling edges of clocks. Constrain the delay from clock input to these FFs by a FROM::TO constraint. Design the logic so that inputs to rising edge FFs comes only from falling edge FFs, and that inputs to falling edge FFs comes only from rising edge FFs. Constrain the delays from rising edge FFs to falling edge FFs with another FROM::TO constrain, and also from falling edge FFs to rising edge FFs. The use of different edges removes hold time issues, the set up time is verified by insuring that for both clock half periods: (Delay from clock to FF) + (delay from FF to FF) < clock half period -- Phil HaysArticle: 58839
In article <JIPWa.2842$GN6.2539@fe01.atl2.webusenet.com>, Jeff Cunningham <jcc@sover.net> wrote: >This mirrors my experience. In a recent FPGA design, I had to multiply >two signed 24 bit numbers. It seemed easier to implement it as a >multicycle path than to break it up by hand into pipelined stages. > >Now if there is some tool that will insert the pipelining automatically >that is easy to use and doesn't cost $20K/seat I would like to hear >about it, because it is a small hassle to set up the multicycle timing >constraints. Altera's standard flow includes retiming, so if you turn it on and place the registers at the start, they get moved forward into the design. Likewise, Synplify does this as well, and the Xilinx only version I thought was 7K each. The only (and moderate/significant) gotcha is that both tools preserve initial condition/global set-reset semantics, which limits the benefits which retiming achieves. For a large design (eg, a uP core) this can be a significant limitation, but it may be OK for a single smaller module. Also, if you do have to do this by hand for some design piece (after all, the result IS a pipelined, higher throughput design), the retiming algorithm itself is not that bad, and can be simplified: as you don't have to get an exact solution to the all-pairs shortest-path problem, but just want to insure the correctness constraints (the number of registers on each path are unchanged). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58840
B. Joshua Rosen wrote: > > Peter, Austin, > > Is it possible to build 5V IOs on a 90nm process? The world is full of > antique buses that aren't going to go away anytime soon. A couple of > medium sized devices targeted at the legacy bus interface market would be > useful. I'd suggest doing two devices, a XC3S1500 and a XC3S400 with > 5V/3.3V IOs. You could toss the multipliers, those aren't useful in this > application, as well as all of the fancy modern IO standards which also > aren't needed for this application, block RAM is important because bridges > need large FIFOs. The other thing that you would want to do is modify the > DCM so that it could support lower clock frequencies, 10Mhz -20Mhz is > common in this world. If they can make it in a 68-pin PLCC I'll use a mountain of them. :) RobArticle: 58841
news@rtrussell.co.uk wrote in message news:<bgdmcf$73u$1@nntp0.reith.bbc.co.uk>... > I have a design (admittedly making heavy use of the device resources) > which successfully fits into an XC9536 but not an XC9536XL. This is > something I hadn't anticipated when migrating to the newer part. Is > this to be expected, and is it likely that by tweaking any fitter > options (or otherwise) I will be able to get the design to fit ? > > I am using Xilinx Foundation F4.2i, Build 3.1.196. > > Richard. > http://www.rtrussell.co.uk/ I would expect it to fit. Anything you can do in 2 logic blocks of 36V18 can be done in two 54V18. The problem is that for XL chip the placement strategy could be different and less optimal. I developed one design in XC95144XL using 143 (!) logic cells. Most logic blocks used 45-53 inputs out of 54 available. One logic block had 2 or 3 product terms left. The design is runnign well and is worth the time I put in to place signals into logic cell instead of going for the next double-sized CPLD. I would suggest to place the design into 9536 without XL, save the fitter report, run the fitter on 9536XL and compare fitter reports. All outputs will be in same places assuming that chips are pin-compatible. But the rest of logic most likely won't be. Use constraints like: attribute KEEP : string; attribute KEEP of <signal> : signal is "TRUE"; for all signals that end up occupying logic cells in 9536, so they will have readable names that don't depend on phase of moon or daylight saving. Then place them into UCF file: NET "<signal>" LOC = "FB1_11"; This way it should fit. Worked for me, even if i had to spend about a week optimizing the thing.Article: 58842
I hope Google won't eat the first reply, so here's an addition to it,
some parts of fitter report are below:
news@rtrussell.co.uk wrote in message news:<bgdmcf$73u$1@nntp0.reith.bbc.co.uk>...
> I have a design (admittedly making heavy use of the device resources)
> which successfully fits into an XC9536 but not an XC9536XL. This is
> something I hadn't anticipated when migrating to the newer part. Is
> this to be expected, and is it likely that by tweaking any fitter
> options (or otherwise) I will be able to get the design to fit ?
>
> I am using Xilinx Foundation F4.2i, Build 3.1.196.
>
> Richard.
> http://www.rtrussell.co.uk/
cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: iw Date: 4- 1-2003,
4:17AM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful
**************************** Resource Summary
****************************
Macrocells Product Terms Registers Pins Function
Block
Used Used Used Used Inputs
Used
143/144 ( 99%) 558 /720 ( 77%) 100/144 ( 69%) 111/117 ( 94%) 415/432
( 96%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used
Remaining
------------------------------------|---------------------------------------
Input : 58 58 | I/O : 104
5
Output : 44 44 | GCK/IO : 2
1
Bidirectional : 8 8 | GTS/IO : 4
0
GCK : 1 1 | GSR/IO : 1
0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 111 111
*********************Function Block Resource
Summary***********************
Function # of FB Inputs Signals Total O/IO
IO
Block Macrocells Used Used Pt Used Req
Avail
FB1 18 53 53 67 12/0
15
FB2 18 53 53 57 7/0
15
FB3 18 51 51 87 14/0
15
FB4 18 51 51 71 0/1
15
FB5 18 52 52 83 8/0
14
FB6 18 52 52 72 1/7
13
FB7 18 51 51 66 0/0
15
FB8 17 52 52 55 2/0
15
---- ----- -----
-----
143 558 44/8
117
So, in dense design you can't rely on Xilinx tools only, I was always
1-2 cells over 144 when I was playing with options, so I had to
constrain things myself...
Article: 58843kryten_droid wrote: > After I bought one and installed the Xilinx Web Pack, I found that this was > packed with far more useful examples than the non-cheap book. I was after something to read while travelling around where it is impractical to carry a development environment and necessary tools. ``Digital System Design with VHDL'' seems like a reasonable book which I am looking at for now and then I will follow up with the suggestion from Paul. Cheers, Jon.Article: 58844
:: Gabster :: <gabsterblue@hotmail.com> wrote: > My FPGA PCB has 4 layers: ground, power and two signal layers. I'm > wondering if I should put a ground plane on the 2 signals layer. At first I > believe it wasn't required because of the ground layer then I thought about > EMI/RFI protection it could bring. What is the usual way to do it? If yes, > to what ground should I tie it: digital, analog or power? if you need a seperation between (digital) ground (DGND) and chassis at low frequencies use a seperate "chassis plane" which should be placed next to the (digital) ground plane in the layer stack. Keep care about symmetric arrangements of the power planes in the layer stack. If the isolation betweens DGND and chassis doesnt matter in your application, connect DGND to the chassis. a good information source on this topic is Johnson, Graham: "High Speed Digital Design - a handbook of black magic", Prentice Hall. WD --Article: 58845
Hello everyone, I am new in this field.. i just wanted to ask which development boards will be best suited for starters.. are there any sites that gives a comparison of the different development kits from the different vendors, and some cheap distributor of these kits in the US. Also wanted to know abt some projects for beginners in fpga design.. please suggest me some and the associated reading that i will have to do with them. thnks a lot in advance, -- sandeepArticle: 58846
OK, an ad: an EP1C6 on a small pluggable board: http://www.jopdesign.com/cyclone/ Martin > > Yet another example of lack of imagination. Why can't these guys supply > such chips mounted on a small pluggable board? > > Sheesh. > > Rob > > > rickman wrote: > > > > Rob Judd wrote: > > > > > > Hi, > > > > > > My application requires a lot of core but few physical i/o lines. Can > > > anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or > > > 80-pin pqfp package? > > > > > > Thanks, > > > > > > Rob > > > > No, the best you will do is a VQFP100 or you will have to use a CPLD. > > The CPLDs come in some pretty small packages, but not a lot of density > > in them. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58847
In article <ca0b988a.0308021128.7abff2b7@posting.google.com>, Sandeep <sandeep_babel@yahoo.com> wrote: >Hello everyone, > > >I am new in this field.. i just wanted to ask which development boards >will be best suited for starters.. are there any sites that gives a >comparison of the different development kits from the different >vendors, and some cheap distributor of these kits in the US. >Also wanted to know abt some projects for beginners in fpga design.. >please suggest me some and the associated reading that i will have to >do with them. Probably one of the best (which I've bought but haven't powered on/played with yet) for a beginner might be the Charmed Labs X-port board. It fits in a Gameboy advance/Advance SP (which is <$100 for an SP, which has a NICE display and a rechargeable LiIon battery), and the board itself is about $150-180 depending on configuration. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58848
Phil Hays wrote: > > rickman wrote: > > > I replied to your email about this. I recommend that you not use a > > clock buffer for the 1 kHz reference. Instead treat it like a signal > > and reclock it into each of the 8 QCM clock domains. There you can > > detect the rising edge and use that to enable a 1 second counter (0 to > > 999). > > > > Of course this will use more logic than a single time base counter, but > > you will not need a ninth global clock route. Since your chip does not > > have a ninth clock input, your only other alternative is to control the > > skew on the clock net and to manually verify the skew on every P&R. I > > don't think the tools will automatically control this for you. > > Reclocking the slow clock is probably the best solution, however there > is a way to run a clock not using the global clock routes and get the > static timing automatically verified. The solution is to use two groups > of FFs, one for rising edges of clock and one for falling edges of > clocks. Constrain the delay from clock input to these FFs by a FROM::TO > constraint. Design the logic so that inputs to rising edge FFs comes > only from falling edge FFs, and that inputs to falling edge FFs comes > only from rising edge FFs. Constrain the delays from rising edge FFs to > falling edge FFs with another FROM::TO constrain, and also from falling > edge FFs to rising edge FFs. > > The use of different edges removes hold time issues, the set up time is > verified by insuring that for both clock half periods: > > (Delay from clock to FF) + (delay from FF to FF) < clock half period That is a great idea! In his case he doubles the size of his counter and such, but that is much better than 8x! This especially works well for the OP since his ninth clock is only 1 kHz. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58849
>As a study for a project I need to investigate the possibility of >implementing a tiny TCP/IP stack and tiny MAC controller on FPGA. This >stack is capable to transfer some data packets directly into S(D)RAM >without help of the microcontroller. Thus a simple communication via >Ethernet from the desktop PC is required for download/upload to/from >the memory. TCP gets pretty complicated. I expect the best way to do in in an FPGA would be to build a CPU and treat it as a software problem. You might try UDP first. A server-only UDP implementation doesn't need any timers or routing tables. (You can send the packet back where it came from. Be sure to fixup the broadcast case.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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