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I would also like to find out what the status of W2K/SP4 support might be. I'm getting ready to jettison Win XP (big mistake, don't ask) in favor of going back to W2K. I'm looking for a really creative way to destroy the Win XP CD, something commensurate with what I think of the product. One thought I had was to attach it to a high speed motor and let centrifugal force shred it to pieces. That ought to be fun. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F3808AB.4FEE8557@yahoo.com... > rickman wrote: > > > > I seem to recall that at one time the Xilinx tools were not compatible > > with Win2k SP3. Anyone know if that is still an issue? I assume it is > > since I still see SP2 listed under the System Requirements. > > Oh, and I noticed on the MicroSoft website that Windows 2000 is up to > SP4. It seems like an update to the Xilinx support of W2k is needed. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59201
s43ed@myrealbox.com (Saeed Nari) wrote in message news:<d774b6a5.0308110337.49f6e250@posting.google.com>... > Hi, > Thank you for your help, but I can't synthesize the modified code yet, > Which synthesis tool you used to syntheseze the modified code? xilinx XST anttiArticle: 59202
Hi Jason
Several choices, some more recommended than others!
1) Manually instance an IBUF component on the ale input.
2) XST specific attributes in the VHDL.
3) Options in XST
I'm a little rusty on my XST options and attributes, but I'm sure they can
be found in the documentatin somewhere. However, they are obviously specific
to XST and won't work with any of the other synthesis tools, such as
Leonardo or Synplify. The manual IBUF definately works:
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity whatever
port (ale : in std_logic
end entity;
architecture demo of whatever is
signal ale_n:std_logic;
component IBUF is
port (I : in std_logic ; O : out std_logic);
end component;
begin--architecture
Manual_Buffer : IBUF(I => ale , O => ale_n);
end; --architecture
XST will produce a warning :
"WARNING:NgdBuild:479 - The input pad net 'ale' is driving one or more clock
loads that should only use a dedicated clock buffer. This could result in
large clock skews on this net. Check whether the correct type of BUF is
being
used to drive the clock buffer."
HTH
Ian Poole
"Jason Berringer" <look_at_bottom_of@email.com> wrote in message
news:asWZa.4797$Z03.287010@news20.bellglobal.com...
> Hello,
>
> I'm implementing a data bus between a FPGA (XC2S100) and an 8051. Due to
the
> multiplexed data/address bus I have to latch the 16 bit address on the
> falling edge of ALE (before the lower address byte is changed to the data
> byte) so I implement the latch easy enough, however when I sythesize it
> through the webpack it interprets this as a clock signal and gives me an
> error that it is connected to the wrong pin, it states that I should have
it
> connected to a clock input. My question is how do I get the sythesizer to
> overlook this signal as a clock and treat it as a simple input.
>
> Your help would be greatly appreciated.
>
> In case you needed to see the snipit of code that I'm using to latch the
> data here it is (note I've also tried using ale_n'event and ale_n = '0'
> instead of faling_edge just in case the translation was somewhat messed
up).
> This process latches the lower address byte into the signal address_low
from
> the address_data bidirectional port on my entity.
>
> ...
> process(reset, ale_n) begin
> if reset = '1' then
> address_low <= (others => '0');
> elsif falling_edge(clk) then
> address_low <= address_data;
> end if;
> end process;
> ...
>
> Thanks
>
> Jason
>
>
Article: 59203I know this is off topic, but MICROWAVE it. See http://www.hamjudo.com/notes/cdrom.html Obviously its extremely dangerous and bad for you, so don't do it because I said it sounded fun... Ian "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:jJ%Za.709$0t7.279@newssvr25.news.prodigy.com... > I would also like to find out what the status of W2K/SP4 support might be. > I'm getting ready to jettison Win XP (big mistake, don't ask) in favor of > going back to W2K. I'm looking for a really creative way to destroy the Win > XP CD, something commensurate with what I think of the product. One thought > I had was to attach it to a high speed motor and let centrifugal force shred > it to pieces. That ought to be fun. > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F3808AB.4FEE8557@yahoo.com... > > rickman wrote: > > > > > > I seem to recall that at one time the Xilinx tools were not compatible > > > with Win2k SP3. Anyone know if that is still an issue? I assume it is > > > since I still see SP2 listed under the System Requirements. > > > > Oh, and I noticed on the MicroSoft website that Windows 2000 is up to > > SP4. It seems like an update to the Xilinx support of W2k is needed. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > >Article: 59205
Completed process "Generate Post-Translate Simulation Model". ERROR: Hidden remap failed Reason: Launching Application for process "Simulate Post-Translate VHDL Model". not only the software's stupid enough to launch the GUI after the error, but there is not a single entry about this error in the xilinx database, on the modelsim server or even in google (but me complaining about the same problem a month ago) The 'reason' field is as useful as usual :) this time they just didn't bother typing a message that makes no sense, they just left it empty. here's the code: process(Reset, MasterClock) is variable counter : std_logic_vector(2 downto 0); begin if(Reset = '1') then counter := "000"; elsif(rising_edge(MasterClock)) then dividedclock <= counter(2); counter := counter + 1; end if; end process; so, all the calls to modelsim, regardless of the type (post translate, post map, etc) fail the same way. then 'generated expected simulation results' yields another interesting problem: if, in the timing constraints, I select the clock to be rising edge only, it works; if I pick dual edge, it just 'skips' cycles every 30 or so in the display and everything gets out of sync... Any ideas?Article: 59206
Hi - just finished reading this... http://www.us.design-reuse.com/news/news6026.html triggered by some discussions with peers. Does anybody think this affects the FPGAs with on-chip busses? --neerajArticle: 59207
Hi Peter, thank you for your response. The datasheet of the chip which is on the add-on board states a DC Input Current of +/- 20mA. I have a total of 4 pins to provide power to the add-on board. The Virtex datsheet states a output current for one pin of +/- 24mA for LVTTL. As a novice I would expect that one pin with +/- 24mA would be sufficient to source the add-on board which requires +/- 20mA. Is this correct ? How can I determine the value of the experiment resistor. I assume Vcc/Icc. Is this correct ? Regards, Mark Lenz Peter Alfke <peter@xilinx.com> wrote in message news:<3F37E2D9.290AF568@xilinx.com>... > Mark, your question cannot be answered without knowing the Icc > consumption of that extra board. > If it is <10 mA and not too picky about low Vcc, this might work if you > select the strongest Output drive for the pin ( or do you intend to use > multiple pins?) > > Once you know the current, you can experiment with a simple resistive > load. :-) > > Peter Alfke, Xilinx > ========================== > lenz wrote: > > > > Hi ! > > > > I have a PCI Mezzanine Card (PMC) with a Virtex 400 and a front panel > > connector. The Virtex is connected to the SCSI-2 style front panel > > connector with 68 pins.These pins are interleaved signal and ground > > pairs.So, I have 34 free I/O at the front panel connector. > > > > I would like to connect a little add-on board to this front panel > > connector. This board will be populated with a Gigabit Ethernet > > Controller (PMC-Sierra PM3387). Besides data and control signals I > > have to provide power to the add-on board. > > > > I am planning to connect the add-on board VCC plane with the I/O pins > > at the front panel connector. Then the Virtex will drive '1' at the > > front panel connector I/O. The add-on board ground plane will be > > connected with the ground pins at the front panel connector. > > > > Can this provide sufficient power to the add-on board ? > > Is there a better way to provide power ? > > > > Thanks in advance. > > > > Mark LenzArticle: 59208
"Neeraj Varma" <neeraj@cg-coreel.com> wrote in message news:606fb9ef.0308120312.6093c2da@posting.google.com... > Hi - just finished reading this... > http://www.us.design-reuse.com/news/news6026.html > triggered by some discussions with peers. > > Does anybody think this affects the FPGAs with on-chip busses? Ha flippin' ha. Here we go again. Perhaps some of these turkeys should read the AMBA bus spec, or find out about what Inmos were doing and writing in the late 70s. Not all prior art originates in the USA, despite what some USPTO patent examiners seem to think :-) Just one delightful snippet from the "Background" section of this patent on the USPTO website: Static timing analysis is preferably awkward, ... Well, no; but patent lawyers, now, there's quite another thing. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 59209
I have Spartan-II FPGA XC2S100. I wan to implement FIFO interfaced with ADC, DAC and Extended Memory Interface EMIF in Spartan-II Fpga. I can implement the required 256*18 SN74ALVC7806 FIFO by the use of built in 40K block RAM in Spartan-II FPGA. But the implementation is volatile For the non-volatile implementation what is the best most economical component (from for example flash, CPLD, EEPROM, PROM, flash prom etc, preferably one for which I don't have to use parallel port interface ) that can be used with XC2S100 or XC2S50 ? Thanks and Regards Atif Nadeem Research Associate Al-Khawarizmi Institute of Computer Science, UET Lahore, PakistanArticle: 59210
"Jason Berringer" <look_at_bottom_of@email.com> wrote in message news:asWZa.4797$Z03.287010@news20.bellglobal.com... > Hello, > > I'm implementing a data bus between a FPGA (XC2S100) and an 8051. Due to the > multiplexed data/address bus I have to latch the 16 bit address on the > falling edge of ALE (before the lower address byte is changed to the data > byte) so I implement the latch easy enough, however when I sythesize it > through the webpack it interprets this as a clock signal and gives me an > error that it is connected to the wrong pin, it states that I should have it > connected to a clock input. My question is how do I get the sythesizer to > overlook this signal as a clock and treat it as a simple input. > > ... > process(reset, ale_n) begin > if reset = '1' then > address_low <= (others => '0'); > elsif falling_edge(clk) then > address_low <= address_data; > end if; > end process; > ... > > Thanks > > Jason > I'm a newbie myself, but I think you might want to take the ale_n out of the process parentheses. JimArticle: 59211
Hello,
I'm trying to operate the nios processor with my
crypto-processor .
The default clock frequency (33.33 MHz) is too slow for fast
cryptosystem performance. I'd tried to get another clock with 50 MHz
frequency through PLL and generate the nios processor with 50 MHz in
the clock setting. The system still can operate correctly with some
simple application on it's own. But when I tried to run some
application involved the hash processor, sometime it'll automatically
jump into Nios peripheral test menu after display message of (return
address is 0x000000) when it try to display the result. (The
appication runs well in system with 33.33 Mhz clock).
The hardware platform I'm using now is Nios development board
populated by an APEX?20KE device (EP20K200EFC484). Is there anyway
that I can solve this problem?
Article: 59212Paul, The device is an EP20K, 1500EBC652-1X, the user said that he is using <20% in logic and <60% in memory. We've discussed your info and have decided that the first step is, as you recommend, upgrading to 3.0. The reason for the P&R is that we do not have any real lab equipment and the user is bringing signals out to the 3 on-board LEDs. I take it that this requires a new P&R everytime. Don > I have a few questions: > > (a) Why is the user iterating through full P&R so much? Is it for timing > closure? Or are they doing post-P&R simulation when they could be using > pre-P&R simulation for the purposes of debugging their HDL? > (b) What device is being used, and how full is it? 1 hr is not unreasonable > for a medium-sized design, and your observation that Quartus is CPU bound > confirms that the user is not running out of memory for some reason. > > There is an option in Quartus known as "Fast Fit" which will make the fitter > run faster at the expense of a small amount of performance. I'd also > suggest upgrading to the latest version of Quartus II (version 3.0) as I > *think* there has been a bit of a speed up for newer families over the past > few releases, though I don't have the data handy to confirm this. If the > user is iterating to achieve timing closure, a newer version of Quartus > could do the trick as we are constantly improve the quality of push-button > place and route. > > I'm not terribly familiar with the CPU time implications of using logic lock > or incremental compile and will ask a colleague about this on Monday. > > Regards, > > Paul Leventis > Altera Corp. > > > > "Don S" <dshesnicky@yahoo.com> wrote in message > news:b9ff9982.0308081117.164f3b3a@posting.google.com... > > I'm a sysadmin looking at a problem that a designer is having with > > slow turn around times in Altera Quartus. The turn around time on a > > compile is about 1 hr on a AMD 1700+ with 1 gig of memory. Quartus > > version is 2.1 running on Win2K SP2. > > > > The bulk of the time is spent in Logic Synthesis and the Fitter. > > If we just bring up the task manager it shows that we have not tapped > > the memory but the cpu is pegged. > > > > There is apparently a way to lock down the layout of certain blocks > > and/or do an incremental compile so that everything would not have to > > be re-synthesised but the designer says that it doesn't seem to work > > correctly. > > > > Any pointers would be greatly appreciated. > > > > DonArticle: 59213
Hello, Can't really help you right now, but I'm extremely interested in this particular topic. We're about to start a Nios on Cyclone project and I'm expecting to get at least 50MHz operation. Now I'm really curious! I'm troubled that Altera posts little or no performance information on Nios whereas Xilinx posts 85MHz (Spartan3) and even gives benchmark scores for its MicroBlaze offering. Perhaps someone knows what configuration options lead to the highest performance on Nios. We'll see.... Ken "Maxlim" <maxlim79@hotmail.com> wrote in message news:a6140565.0308120522.86a33ec@posting.google.com... > Hello, > I'm trying to operate the nios processor with my > crypto-processor . > The default clock frequency (33.33 MHz) is too slow for fast > cryptosystem performance. I'd tried to get another clock with 50 MHz > frequency through PLL and generate the nios processor with 50 MHz in > the clock setting. The system still can operate correctly with some > simple application on it's own. But when I tried to run some > application involved the hash processor, sometime it'll automatically > jump into Nios peripheral test menu after display message of (return > address is 0x000000) when it try to display the result. (The > appication runs well in system with 33.33 Mhz clock). > The hardware platform I'm using now is Nios development board > populated by an APEX?20KE device (EP20K200EFC484). Is there anyway > that I can solve this problem?Article: 59214
In article <bhampo$eu0$1$8300dec7@news.demon.co.uk>, Jonathan Bromley <jonathan.bromley@doulos.com> wrote: >Not all prior art originates in the USA, despite what some >USPTO patent examiners seem to think :-) Come on, the USPTO patent examiners wouldn't know prior art if it came up and bit them on the ass, mostly because the system largely relies on what the patent filer cites! -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59215
On Fri, 08 Aug 2003 11:35:05 +0200, Aart van Beuzekom wrote: > Hei, > > I will start developing FPGA applications with WebPack. My problem is that > my OS is WinNT, which is not supported by WebPack 5.2i. I've got a CD > laying round here with WebPack version 4.2WP0.0. > > Can anybody tell me if the advantages of v. 5.2i are so much that > upgrading to Win2000 really is necessary? > > My application will run on a Spartan-II device. Clock speed wil not be an > issue, but efficient use of logic cells might be. > > Thanks, > > Aart Upgrade to a real operating system, Linux. The 5.2 tools work fine using wine on Linux. Next month the 6.1 release will run natively on Linux.Article: 59216
Thanks to everyone who contributed to this discussion. I am currently having technical difficulties posting to the Usenet, so please forgive me for the delay. BTW, does anyone knows of a good free news server that would allow posting? Google is very slow to reflect even the messages that have been posted through it and all too frequently doesn't show some of the posts at all (it happened to Avrum's posts this time). I am using newssvr20-ext.news.prodigy.com for reading, but it doesn't allow posting... /MikhailArticle: 59217
Yes, that's what I would use as resistor value.. I would use all 4 pins in parallel, and configure them such that they can only pull High ( the mirror image of opencollector ) which means: output a permanent High level and keep the outputs permanently active (Tristate control input = Low). Viel Erfolg! Peter Alfke ======================= lenz wrote: > > Hi Peter, > > thank you for your response. > > The datasheet of the chip which is on the add-on board states a DC > Input Current of +/- 20mA. I have a total of 4 pins to provide power > to the add-on board. > The Virtex datsheet states a output current for one pin of +/- 24mA > for LVTTL. As a novice I would expect that one pin with +/- 24mA would > be sufficient to source the add-on board which requires +/- 20mA. Is > this correct ? > > How can I determine the value of the experiment resistor. I assume > Vcc/Icc. Is this correct ? > > Regards, > Mark Lenz > > Peter Alfke <peter@xilinx.com> wrote in message news:<3F37E2D9.290AF568@xilinx.com>... > > Mark, your question cannot be answered without knowing the Icc > > consumption of that extra board. > > If it is <10 mA and not too picky about low Vcc, this might work if you > > select the strongest Output drive for the pin ( or do you intend to use > > multiple pins?) > > > > Once you know the current, you can experiment with a simple resistive > > load. :-) > > > > Peter Alfke, Xilinx > > ========================== > > lenz wrote: > > > > > > Hi ! > > > > > > I have a PCI Mezzanine Card (PMC) with a Virtex 400 and a front panel > > > connector. The Virtex is connected to the SCSI-2 style front panel > > > connector with 68 pins.These pins are interleaved signal and ground > > > pairs.So, I have 34 free I/O at the front panel connector. > > > > > > I would like to connect a little add-on board to this front panel > > > connector. This board will be populated with a Gigabit Ethernet > > > Controller (PMC-Sierra PM3387). Besides data and control signals I > > > have to provide power to the add-on board. > > > > > > I am planning to connect the add-on board VCC plane with the I/O pins > > > at the front panel connector. Then the Virtex will drive '1' at the > > > front panel connector I/O. The add-on board ground plane will be > > > connected with the ground pins at the front panel connector. > > > > > > Can this provide sufficient power to the add-on board ? > > > Is there a better way to provide power ? > > > > > > Thanks in advance. > > > > > > Mark LenzArticle: 59218
If you are looking for a FIFO that retains its data and pointers when power is removed ( is that what you need? ), then you are in for quite a search. Non-volatile memories are usually quite slow, and/or allow a limited number of write cycles. I might implement the FIFO inside Spartan, and then dump the content and pointers onto external flash memory before shutting down. Very unusual request... Peter Alfke, Xilinx ============ Atif wrote: > > I have Spartan-II FPGA XC2S100. > I wan to implement FIFO interfaced with ADC, DAC and Extended Memory > Interface EMIF in Spartan-II Fpga. I can implement the required 256*18 > SN74ALVC7806 FIFO by the use of built in 40K block RAM in Spartan-II > FPGA. But the implementation is volatile > For the non-volatile implementation what is the best most economical > component (from for example flash, CPLD, EEPROM, PROM, flash prom etc, > preferably one for which I don't have to use parallel port interface ) > that can be used with XC2S100 or XC2S50 ? > > Thanks and Regards > Atif Nadeem > Research Associate > Al-Khawarizmi Institute of Computer Science, > UET Lahore, PakistanArticle: 59219
"Jason Berringer" <look_at_bottom_of@email.com> wrote in message news:<asWZa.4797$Z03.287010@news20.bellglobal.com>...
> Hello,
>
> I'm implementing a data bus between a FPGA (XC2S100) and an 8051. Due to the
> multiplexed data/address bus I have to latch the 16 bit address on the
> falling edge of ALE (before the lower address byte is changed to the data
> byte) so I implement the latch easy enough, however when I sythesize it
> through the webpack it interprets this as a clock signal and gives me an
> error that it is connected to the wrong pin, it states that I should have it
> connected to a clock input. My question is how do I get the sythesizer to
> overlook this signal as a clock and treat it as a simple input.
>
> Your help would be greatly appreciated.
>
> In case you needed to see the snipit of code that I'm using to latch the
> data here it is (note I've also tried using ale_n'event and ale_n = '0'
> instead of faling_edge just in case the translation was somewhat messed up).
> This process latches the lower address byte into the signal address_low from
> the address_data bidirectional port on my entity.
>
> ...
> process(reset, ale_n) begin
> if reset = '1' then
> address_low <= (others => '0');
> elsif falling_edge(clk) then
> address_low <= address_data;
> end if;
> end process;
A couple of things:
1) You say you want a latch, so why the "falling_edge(clk)" clause?
2) Read the docs, they should tell you what to write to infer a latch.
Probably something like:
process (ale, address_data) begin
if (ale = '1')
address_low <= address_data;
end process;
You might see some complaints about combinatorial latches if the
target architecture doesn't do latches.
--a
Article: 59220The Xilinx tools work fine on SP3 and newer. Here's the trick. After you install and patch, you have to update your windrvr.sys file BEFORE rebooting (or else you end up booting in safe mode and replacing the file from a floppy.) Get the newer windrvr.sys file here: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15380. It appears the last two 5.2 patches have had the correct windrv.sys file in them. Oh, and don't install the multilinx (sp?)driver. If you need that you could be SOL. And if you need the parallel JTAG connection, I've had to play with the LPT port settings both in the BIOS and the Device Manager until I found a combination that actually worked. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F3804C0.2DE7F1F1@yahoo.com... > I seem to recall that at one time the Xilinx tools were not compatible > with Win2k SP3. Anyone know if that is still an issue? I assume it is > since I still see SP2 listed under the System Requirements. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59221
"B. Joshua Rosen" wrote: > > On Fri, 08 Aug 2003 11:35:05 +0200, Aart van Beuzekom wrote: > > > Hei, > > > > I will start developing FPGA applications with WebPack. My problem is that > > my OS is WinNT, which is not supported by WebPack 5.2i. I've got a CD > > laying round here with WebPack version 4.2WP0.0. > > > > Can anybody tell me if the advantages of v. 5.2i are so much that > > upgrading to Win2000 really is necessary? > > > > My application will run on a Spartan-II device. Clock speed wil not be an > > issue, but efficient use of logic cells might be. > > > > Thanks, > > > > Aart > > Upgrade to a real operating system, Linux. The 5.2 tools work fine using > wine on Linux. Next month the 6.1 release will run natively on Linux. Correct me if I am wrong, but this is not Linux exactly. It is Redhat and only one specific version of Redhat if I am not mistaken. If you are running anything else, the tools are not supported. I am not trying to knock Xilinx, I just want it to be clear that there are supported version limitations under *any* OS. I have been told by email that Win2K is supported after SP2, it is just the documentation that says SP2 only. The problems with using the download cable has been worked out and the new version 6.0 or 6.1, which ever it is, will document the wider version support. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 59222
"Andrea" <aa@bb.cc> wrote in message news:<bh7eud$cic$1@lacerta.tiscalinet.it>... > "Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio > news:ca4d800d.0308081334.169fbc89@posting.google.com... > > Hi Andrea, > > > > The clock enable is not supported by the single-port RAM megafunction. > > An easy work-around is to use the dual-port megafunction (via the > > MegaWizard "memory compiler/RAM: 2-port" or the older > > "storage/lpm_ram_dp+"). You can always tie the rdaddress and > > wraddress together to get single-port RM behavior. > > > > - Subroto Datta > > Altera Corp. > > > Thank you!!! > > Which is the difference between "memory compiler/RAM: 2-port and" and > "storage/lpm_ram_dp+"? > > Andrea The MegaWizards in the "memory compiler" tree have a reorganized GUI compared to the MegaWizards in the "storage" tree. The underlying megafunctions and models are identical. The "storage" tree was getting confusing because you had to know which megafunction to select, based on the device family. The "memory compiler" tree, is organized by function, and removes the need for device family knowledge, when making a selection. Using selections from the "memory compiler tree" is the recommended way for new designs. - Subroto Datta Altera Corp.Article: 59223
Anyone have a datasheet for a National PAL20L10? Thanks, Colin Jackson cjackson@regulatedeng.comArticle: 59224
news@rtrussell.co.uk wrote in message news:<bh8el4$24l$1@nntp0.reith.bbc.co.uk>... > Aare Tali <atali@cygrp.com> wrote: > > : I would expect it to fit. Anything you can do in 2 logic blocks of > : 36V18 can be done in two 54V18. > > : I would suggest to place the design into 9536 without XL, save the > : fitter report, run the fitter on 9536XL and compare fitter reports. > > The big difference is that the XC9536 report has the 'wire-AND' > option enabled and the XC9536XL has it disabled. My design makes > heavy use of the 'wire-AND' facility, and it has been suggested > that this is not available on the XC9536XL. Is that correct ? XC9500 uses FASTCONNECT switch matrix that is documented to have wired-AND capability. XC9500XL uses FASTCONNECT II switch matrix that doesn't have it documented, so I would think it's not there. The only option is to use pin-compatible XC9572XL part, I guess...
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