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Yes, it does. The reference design actually comes with the MLD (Microprocessor Library Definition) technology that allows you to automatically generate a BSP for Linux consisting of Xilinx layer 0 and 1 drivers according to the hardware definition (MHS). When you generate the libraries from the system_linux.xmp project file you will get this BSP. The BSP will also contain necessary patches to the Linux kernel to make the design work with MontaVista Linux 3.0 (FYI: the only thing that needs to be patched is the code for the Xilinx interrupt driver since the interrupt controller from V2PDK and EDK are different) - Peter tk wrote: > Hi Peter, > > I would like to ask if the reference design support > MontaVista Linux Pro 3.0 ? > > Thanks very much! > > tk > > Peter Ryser wrote: > > > Antti, > > > > the EDK reference design for ML300 contains > > - 1 PPC 405 > > - 1 PLB DDR > > - 1 PLB bus with arbiter > > - 1 PLB2OPB bridge > > - 1 PLB BRAM controller with 32 KB BRAM attached > > - 1 OPB Uart > > - 2 OPB GPIO > > - 1 OPB 10/100 Ethernet (interrupt driven) > > - 1 OPB IIC > > - 1 OPB System ACE CF > > > > There is no touchscreen, PS/2, TFT, parallel port and AC97. Adding these > > peripherals to the design is planned for a later release that will most > > likely happen towards the end of the year. > > > > There is some documentation in the zip file that lists the peripherals and > > explains the design. > > Again, please contact your Xilinx FAE if you would like to get access to > > this design. > > > > Thanks, > > - Peter > > > > > > > > Antti Lukats wrote: > > > >> Peter Ryser <ryserp@xilinx.com> wrote in message > >> news:<3F1846C0.776CD1F5@xilinx.com>... > >> > > >> > If you want to work with EDK please contact your FAE and ask him to get > >> > you access to the EDK reference design for ML300. He will be able to > >> > get you access to the design. > >> > >> Hi Peter, > >> > >> when we received the EDK + DDR project, I also asked to be notified > >> when a better EDK ref. design will be available, and so far have not > >> got any more info, could you please enlight us what additional cores > >> are available in the EDK ref. design you mentioned? > >> > >> ASFAIK TFT and Touchscreen are not implemented (or hopefully are now?) > >> I have still having trouble to get EDK to work correctly using the > >> obsoleted TFT ref. design - eg. display is looking in stripes 8 pixels > >> missing after 8 ok pixels - if the problem is fixed and ref design > >> availabl would be greate. > >> > >> anttiArticle: 58451
Austin,
Glad you like the idea. Out of curiosity I tried WinZipping some
bit files and got >90% compression on my admittedly only 10% full V2
design. So, I await the first freebie port of WinZip to VHDL or the
PPC. I won't be holding my breath!!
cheers, Syms.
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F1C0521.DD4717BC@xilinx.com>...
> Symon,
>
> Great idea! I will pass it along. To use a soft core is, as you point out, best, as one can
> tailor it to the best method of decompression!
>
> By the way, since you have disclosed this, there is nothing to prevent any of our customers from
> doing this, now. Heck, one could use the PPC in an amazingly complex decompression to unravel the
> bitstream in a virtex II pro ....
>
> Austin
>
<snip>
Article: 58452Symon wrote: > Austin, > Glad you like the idea. Out of curiosity I tried WinZipping some > bit files and got >90% compression on my admittedly only 10% full V2 > design. So, I await the first freebie port of WinZip to VHDL or the > PPC. I won't be holding my breath!! zlib builds cleanly for microblaze with mb-gcc - it would be very simple to write a simple microblaze program to decompress a bitstream file. The trick would be interfacing the microblaze to ICAP and and pumping the bits. As long as the new (decompressed) bitfile didn't overwrite the microblaze that was actually doing the decompression, you'd be off and running. If you eventually used the microblaze in your "final" design then this would be quite a neat way to go. Regards, JohnArticle: 58453
Even with a very full V2 design, I see almost 5:1 compression of the bitstream with winzip (577K after
compression for 2V6000)
Symon wrote:
> Austin,
> Glad you like the idea. Out of curiosity I tried WinZipping some
> bit files and got >90% compression on my admittedly only 10% full V2
> design. So, I await the first freebie port of WinZip to VHDL or the
> PPC. I won't be holding my breath!!
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58454Martin Euredjian wrote: > > So ... it sure sounds like I'm trying to swim upstream. > > Is there a constraint that could cause data paths to be aligned better or is > it futile to even try? > > Take a pipe consisting of four eight-bit registers (as a simple example). > Can one over-constrain? Set a low maximum delay for the nets? > > Take an FIR module, for example. Are we doomed to hand-placement of such a > beast? I am not sure we are talking the same language. I don't know of any location constraints that will make the auto placement work better if that is what you are looking for. But if you are willing to figure out how the key parts of your critical speed logic should be located for best routing, then you can use relative location constraints to tell the placer how to do this. Basically the relative location constraints work inside an area with specific (or general area) positioning for each part you specify. So in your four stage, 8 bit pipeline, you would put the bits for each register on successive rows in pairs, quads or octets depending on the part you are targeting. Then each register gets placed to a successive column. This will put the pipeline in a rectangle which can then be placed by the tool anywhere within the design and the short connects between CLBs can be used for the fast pipeline. This also minimizes (or should minimize) the use of the longer routing which will make it more available for other signals. I try not to do much of this since it is a PITA and a bit tedious. As you can see from Ray's design example, instantiation and location constraints can be very tedious. Some VHDL features like generate statements can help automate this process. Ray was doing this same thing with schematic heirarchical modules before HDLs were nearly mandated by the chip vendors. But if your design requires the speed advantages that this process can give, it can be the only way to go. But also keep in mind that it makes your designs hard to port between families much less vendors. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58455
slice some of everybody else' SUN - I used to be (in?)famous for that Andrew Bill Hanna wrote: >nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0307080518.712eca43@posting.google.com>... > > >>Hi. >> >>My company is working on a xc2v8000 design, I expect it to be almost >>fully utilized (85%). >> >>I feel that our computing power is not sufficient. >> >>I am using Sun Ultra-80 with 4 GB memory. >> >>fpga_editor and floorplanner take a lot of time. >>P&R flow takes a lot of time. >>I read in Xilinx docs that the recommendation for xc2v8000 is 3 GB >>memory. >> >> >>Do you have from your experience additional recommendations, such as >>graphic card type, Processor, memory, or a brand name computer that >>you successfully use? >> >> >>ThankX >>NAHUM >> >> > > I have a design using the XC2V6000 that uses 66% of the chip's >capacity (23,000 slices out of 33,792). > > I am using the P4 2GHz PC , Windows XP PRO, with 1GB DDR SDRAM. >It takes 5 hours to synthesize, and 1 hour to place and route. > > I am sure that you are OK with the SUN processor. I have had some >designs use 2GB of virtual memory. > >Bill Hanna > >Article: 58456
Dear all, Have you ever measured the signal level of your FPGA pin out using Oscilloscope ? At the clock speed of 50 MHz, I observed the signal is destroyed. The oscilloscope sales guy pretends that I need to use active probe which is quite expensive. He said it was a circuit loading issues. Is there any such away to overcome this problem without buying the active probe ? Thanks. Best regards, BasukiArticle: 58457
On Wed, 23 Jul 2003 21:31:07 -0700, Basuki Endah Priyanto wrote: > Dear all, > > Have you ever measured the signal level of your FPGA pin out using > Oscilloscope ? > > At the clock speed of 50 MHz, I observed the signal is destroyed. The > oscilloscope sales guy pretends that I need to use active probe which is > quite expensive. > > He said it was a circuit loading issues. > > Is there any such away to overcome this problem without buying the > active probe ? High impedance divider probes tend to have high input capacitance (10 pF or greater) and lousy transient response. Easiest thing is to build your own passive divider probe: Put a 453 (for 10/1) Ohm non inductive (non spiraled) resistor on the end of a 50 Ohm coax going into the 50 Ohm input of your Scope (Or a high impedance scope input with 50 Ohm terminator) This will give you a 500 Ohm input resistance 10/1 divider probe with < 1 PF of input capacitance and frequency response > 1 GHz. Keep input lead (signal end of resistor) and ground lead _very_ short... PCW > > Thanks. > > Best regards, > > BasukiArticle: 58458
On Wed, 23 Jul 2003 09:01:50 -0700, Peter Alfke <peter@xilinx.com> wrote: >Allan, I considered that obvious. All hell breaks loose everywhere when >routing delays exceed the clock period. Yes, of course. But what is obvious to an experienced FIFO designer isn't neccessarily obvious to a newbie, and sometimes these things need to be pointed out explicitly. I recall discussing this issue with some Agilent co-workers, and it took a while before everyone agreed that the destination clock period has no bearing on the skew requirement. This matters a lot if the two clocks are of very different frequencies - you can end up with an under- or overconstrained design if you are not careful. Best Regards, Allan. P.S. I'm about to change email addresses. My new one will be allan (dot) herriman (at) ctam (dot) com (dot) au (dot) invalid >Peter Alfke >=============================== >Allan Herriman wrote: >> >> On Tue, 22 Jul 2003 09:21:34 -0700, Peter Alfke <peter@xilinx.com> >> wrote: >> >> >Yes, you have to be paranoid. But there is no problem with crossing the >> >clock domain boundary using a Grey signal. >> >> To be more precise: there is no problem with crossing the clock domain >> boundary using a Gray signal, provided that the maximum routing skew >> is less than the period of the source clock. >> >> Regards, >> Allan.Article: 58459
Petey, I am curious. Are you sales? Are you Marketing? Are you Applications? Why are you vendors even on this board? Who believes all of your spew? Your answer was a non answer. Contact your sales person. Oh thank you so much for that piece of such valuable information. FPGAs are expensive. They are very complicated products that demand a high premium. Especially ones like V2 pro. The part has up to 4 PPCs, multiple 3.125 rocket IO, and a huge amount of ram and logic. It's state of the art chip technology. Do you think it is not worth $1500? Pricing goes by volume and time. If you buy 10 per year you will never get what you are talking about. It's all about how important you are, how many you buy, and what you can negotiate. Time is a factor, but if you are low volume you will never get the best prices. A sales person will just lie to you to get the socket. That's their job. Once they have the socket they have you in their wallet. As if you will design it out once you put it on the board. My advice, get the deal in writing. Decide what you need the pricing to be and make them sign up for your proposal. Negotiate. It's the American way. Be a tough negotiator. They are in the driver's seat though. The technology is hot. If you are Cisco you will get the best price. It goes downhill from there. Peter Alfke <peter@xilinx.com> wrote in message news:<3F1F1F1A.C5C50F9E@xilinx.com>... > Your question can best be answered by a Xilinx salesperson, or most > likely a Sales Representative. If they cannot get you the answer > dirctly, they contact the factory. > They will love to talk to you and give you a quote with "budgetary > figures". They really are your friend, because they have a vested > interest to make you succeed. That is the only way they will get paid. > Do you have such a sales contact? > > Peter Alfke, Xilinx Applications > ================================ > MS wrote: > > > > Hi, > > So we are looking to implement some functionality that we have done in > > NPUs in the past into a Xilinx Virtex2Pro family (small space and less > > power). > > > > These parts are quite expensive right now (up to $1500 a piece). Our > > build timeframe is starting next year, carrying out into 2006/2007. > > When you add up the cost of product- the budget is nearly consumed > > completely by the FPGAs. > > > > The question is how much do you usually expect FPGA prices to fall in > > a given year. For example, would a guess of a 15% drop in the first > > year followed by a 30% fall in the second year be a good stab? 20% a > > year? I just need to fill out some numbers to make some bean counter > > happy. Anyone take a look at what has historical been the price > > drops? > > > > Thanks, > > M ScottArticle: 58460
russelmann@hotmail.com (Rudolf Usselmann) wrote in message > I agree, the biggest problem is cost. > > If you add a Spartan FPGA, you can use my free USB 1.1 > IP core, all you need is a $0.50 USB transceiver from > Phillips and a USB connector. > However, the FPGA and the config eeprom will cost you > around $30 alone, without the flash. You can however > add some hw support for MP3, or even include a 8051 > compatible micro in the FPGA. actel made a forward announcement of "G4" - a 2nd next version of their flash FPGAs G4 should have embedded Flash (1MB+) unfortunatly it is not to be released ant time soon G3 (with better IO standard and onchip flash programmin charge pump is to be released Q2 2003) anttiArticle: 58461
I was thinking more in terms of any constraint (not necessarily placement constraints) that would help deal with some of the logic in a more efficient manner. For the pipeline example, if I could say that the interconnects are not to have a delay greater than 0.1ns (just an example) and, through some other constraint, specify that the bits of successive registers are to be aligned in a left-right/up-down/whatever sequence... this could save a lot of time and reduce the need to do it by hand. I think it's pretty clear that I'm looking for something that does not exist yet. Area and hand-placed (RLOC) constraints will have to do for now. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F1F425E.5B3D4C04@yahoo.com... > Martin Euredjian wrote: > > > > So ... it sure sounds like I'm trying to swim upstream. > > > > Is there a constraint that could cause data paths to be aligned better or is > > it futile to even try? > > > > Take a pipe consisting of four eight-bit registers (as a simple example). > > Can one over-constrain? Set a low maximum delay for the nets? > > > > Take an FIR module, for example. Are we doomed to hand-placement of such a > > beast? > > I am not sure we are talking the same language. I don't know of any > location constraints that will make the auto placement work better if > that is what you are looking for. But if you are willing to figure out > how the key parts of your critical speed logic should be located for > best routing, then you can use relative location constraints to tell the > placer how to do this. > > Basically the relative location constraints work inside an area with > specific (or general area) positioning for each part you specify. So in > your four stage, 8 bit pipeline, you would put the bits for each > register on successive rows in pairs, quads or octets depending on the > part you are targeting. Then each register gets placed to a successive > column. This will put the pipeline in a rectangle which can then be > placed by the tool anywhere within the design and the short connects > between CLBs can be used for the fast pipeline. This also minimizes (or > should minimize) the use of the longer routing which will make it more > available for other signals. > > I try not to do much of this since it is a PITA and a bit tedious. As > you can see from Ray's design example, instantiation and location > constraints can be very tedious. Some VHDL features like generate > statements can help automate this process. Ray was doing this same > thing with schematic heirarchical modules before HDLs were nearly > mandated by the chip vendors. > > But if your design requires the speed advantages that this process can > give, it can be the only way to go. But also keep in mind that it makes > your designs hard to port between families much less vendors. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58462
Got it, thanks for the example. This seems like an obvious advantage of VHDL. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Ray Andraka" <ray@andraka.com> wrote in message news:3F1F05EF.F7AB5E81@andraka.com... > Basically, the lowest level of your hierarchy, at least the parts you want to > place, are xilinx unisim primitives. Using the VHDL generate construct allows > you to describe the logic and placement for one bit, and then have that > replicated in a sort of step and repeat fashion to build up your bottom level > macros. Those macros can then be used in a larger design by putting RLOCs on > the macro. The following is the generate loop to make a registered adder. That > adder component can then be used in the next level up and placed by putting an > RLOC attribute on the component following the same format as inside the generate > loop. The adder is a reusable component that can then be used in many designs > without having to change anything. Likewise, the next level up might be a > filter generate macro or something like that that builds a placed component that > can then be used in a higher level design. > > L:for i in 0 to width-1 generate > constant rc_str : string := "R" & itoa( origin -(i/2)) & "C0" & ".S" & > itoa(slice mod 2); > constant xy_str : string := "x0y" & itoa((i/2)-origin) ; > constant rloc_str : string := pickstring(virtex,rc_str,xy_str); > signal l,s,qr,qs: STD_LOGIC; > attribute BEL of U1:label is bel_lut(i mod 2); > attribute BEL of U3:label is bel_xor(i mod 2); > attribute BEL of U4:label is bel_ff(i mod 2); > attribute RLOC of U1 : label is rloc_str; > attribute RLOC of U2 : label is rloc_str; > attribute RLOC of U3 : label is rloc_str; > attribute RLOC of U4 : label is rloc_str; > begin > U1: fmap_xor2 port map( > a=> ax(i), > b=> bx(i), > z=> l); > > U2: MUXCY port map ( > O => cy(i+1), > CI => cy(i), > DI => ax(i), > S => l ); > > U3: XORCY port map ( > O => s, > CI => cy(i), > LI => l ); > > U4: FDRE port map ( > Q => q(i), > D => s, > R => lcl_rst, > CE => lcl_ce, > C => clk ); > end generate L; > > > Martin Euredjian wrote: > > > "Ray Andraka" <ray@andraka.com> wrote: > > > > > The automatic placment algorithms, while better than in the past, still > > suck. I > > > do a large amount of explicit placement using a structural hierarchy. The > > > relative placements (in the form of RLOCs) are in the code, and these are > > built > > > up hierarchically. Some examples of the floorplans can be seen on the > > gallery > > > page of my website (thanks Phil Freidin for that idea). > > > > Could I bother you to provide an example of how to do this? Are you saying > > that you locate placement constraints within the HDL modules themselves? > > How exactly are they "built up hierarchically"? > > > > I searched Google for a post from Phil Freidin on the subject but failed to > > locate anything applicable. > > > > Thanks, > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 58463
What are the specs on the scope? What are the specs on the probe? How are you grounding your probe? How's grounding in general? What does the output topology look like (internal and external to the FPGA)? What are you driving? Transmission line? Terminated? How? 50MHz isn't that fast. Mangled signals means that something is wrong. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:N8auEQZUDHA.3356@exchnews1.main.ntu.edu.sg... Dear all, Have you ever measured the signal level of your FPGA pin out using Oscilloscope ? At the clock speed of 50 MHz, I observed the signal is destroyed. The oscilloscope sales guy pretends that I need to use active probe which is quite expensive. He said it was a circuit loading issues. Is there any such away to overcome this problem without buying the active probe ? Thanks. Best regards, BasukiArticle: 58464
Can you give me some fundamental idea about MIPS in FPGA manner. tks, san.sArticle: 58465
OK, I give up. So, I ran 20 passes of "Multi Pass Place & Route" via the GUI. I get the following report (excerpt): <snip> Level/ Design Timing Number Run NCD Cost [ncd] Score Score Unrouted Time Status ---------- ------ -------- -------- ----- ------------ 5_5_17 * 146 0 0 02:16 Complete 5_5_7 * 147 0 0 02:11 Complete 5_5_19 * 147 0 0 02:31 Complete 5_5_3 * 151 0 0 02:16 Complete 5_5_4 * 151 0 0 02:15 Complete <snip> How do I make use of this now? It looks like cost table 17 is the best run. Do I go and manually switch to this table and run the standard Place & Route tool (not multi)? I looked through as much of the documentation as I could imagine might describe this but I couldn't find a descripition of the process by which you make use of multi-pass, from start to finish. I don't really need this level of optimization for my design, but I wanted to learn how to do it just in case. Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 58466
Thank you very much Avrum. It works. Atif "Avrum" <avrum@REMOVEsympatico.ca> wrote in message news:<EbyTa.85$ys2.30264@news20.bellglobal.com>... > I think that what you are asking for is the "Ratsnest". When the ratsnest > option is turned on, the tool will display all the connections from a > selected cell (CLB or IOB), to all other cells connected by nets. > > For some reason (that I never understood) there are TWO mechanisms to turn > on ratsnest view, and both of them must be on to actually see the ratsnest. > The more obvious one is the icon in the toolbar, which identifies itself as > "Toggle Rubber Bands". It is an icon with one dot on the left connected to 4 > dots on the right by magenta lines. The less obvious one is done from the > menus > > Edit->Preferences... > Select the Ratsnest tab > Check the "Display nets connected to selected logic" > > With this option selected, and the Toggle Rubber Bands depressed, you will > see the ratsnest. > > Avrum > > > "Atif" <atif@kics.edu.pk> wrote in message > news:6a0a3f23.0307230041.79dc6b08@posting.google.com... > > Hello all, > > I'm using xsa100 (xc2s100) board with registered evaluation version of > > Xilinx ISE5. I'm a newbie to this. I'm following the instructions in > > the manual "Introduction to webpack 4.1 for FPGAs" downloaded from > > http://www.xess.com/appnotes/webpack-4_1-fpga.pdf. > > > > I've written a code in Verilog for leddec (7 segment display). Then I > > follow the steps written in the manual. For the step in manual "to > > constraining the Fit", I can not find "Edit implantation constraints > > (Constraint editor)" in the "User Constraints" process to assign the > > FPGA pins to my I/Os. But I find "Assign package pins" in the "User > > constraints" of ISE5. On clicking this, it says that there is no > > Implementation constraint file. I make a new one by Project<-New > > Sourse<-Implementation constraint file and add this to current > > project. Now "Assign package pins" works. I assign the I/O signals to > > the FPGA pins as written in the manual. > > > > Everthing is allright so far. But in the step of "viewing the chip", > > when I click "view/edit Placed design (Floor planner)", it shows me > > the CLB's and Inputs and output pads. > > But inpouts and outputs are not associated with CLB's. As I click CLB, > > it should show the I/Os associated with it in shape of arrows from CLB > > to all the I/Os. But This does not happen. > > > > Can anyone please help me telling me where is the error and how to > > remove it? > > > > One more question, at each step, ISE5 gives me the warning that its an > > evaluation version. Will this warning create a problem anywhere in the > > design on loading and testing it to FPGA? > > > > Sorry for bothering such a huge textl. > > > > Regards > > > > Atif Nadeem > > Research Associate > > Al-Khawarizmi Institute of Computer Science, > > University of Engineering & Tech., Lahore > > Pakistan, 54890Article: 58467
Stifler wrote: > Petey, > > I am curious. Are you sales? Are you Marketing? Are you Applications? Your rhetorical style needs some work. > Why are you vendors even on this board? Because they know the ins and outs of their products better than anybody else? And with the apparent exception of you, most of us are very glad they're here and participating. > Who believes all of your spew? The vendors in this NG are remarkably restrained when it comes to promotion, marketing "spew" and putting down the competitors. > Your answer was a non answer. Contact your sales person. Oh thank you > so much for that piece of such valuable information. Oh what, and "Pricing goes by volume and time" is rocket science hot off the presses? Get over yourself!Article: 58468
Hi everybody,
while I was trying to create a statemachine with registered outputs
which shouldn't be delayed by one clock cycle (as usual when just
putting a register behind the outputs of the FSM) I modified some
sourcecode from the XILINX ISE Language Templates for sythesis. As an
example I tried to recreate the stopwatch statemachine from the ISE 5
In depth tutorial.
Everything works fine insofar that the function is correct and
itentical to the original design and it also synthesizes fine with one
little exeption:
The XST-Synthesis Tool does not recognize my coding style as a FSM,
therefore it wont do the neccessary optimizations. For comparision
purposes I have added some XST-synthesis report snippets to outline
the differences:
While my coding style produces a register and some feedback logic
around it, for the original code (Produced by StateCAD) XST inferes a
FSM and applies all optimizations on it.
(When I comment out the enum_encoding attributes in my code then
register CS will become One-State-Hot encoded, but no OSH-FSM will be
created. Instead some clumsy binary FSM with an unreal OSH encoding
(all statebits zero!!! - not allowed for OSH encoding!!!) will be
generated.
So, what trick makes the XST-Synthesis tool recognize my coding style
to be a FSM working in the way I want (that is with registered outputs
but no delay by one clock cycle)?
All help is appreciated.
Thanks
Eilert
=========================================================================
* HDL Synthesis
*
=========================================================================
Synthesizing Unit <elis_statemachine>.
Related source file is
S:/ssy_laboratory_test/ssy_stopwatch/ELIS_Statemachine.vhd.
Found 1-bit register for signal <clockenableout>.
Found 1-bit register for signal <resetout>.
Found 3-bit register for signal <cs>.
Summary:
inferred 5 D-type flip-flop(s).
Unit <elis_statemachine> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 3
3-bit register : 1
1-bit register : 2
=========================================================================
=========================================================================
* HDL Synthesis
*
=========================================================================
Synthesizing Unit <stmach>.
Related source file is
S:/ssy_laboratory_test/ssy_stopwatch/STMACH.vhd.
Found finite state machine <FSM_0> for signal <sreg>.
-----------------------------------------------------------------------
| States | 6
|
| Transitions | 11
|
| Inputs | 1
|
| Outputs | 2
|
| Reset type | asynchronous
|
| Encoding | automatic
|
| State register | d flip-flops
|
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <stmach> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
=========================================================================
Optimizing FSM <FSM_0> with One-Hot encoding and d flip-flops.
Sourcecode of elis_statemachine.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ELIS_Statemachine is
Port ( Clock : in std_logic;
Reset : in std_logic;
StartStop : in std_logic;
ClockEnableOut : out std_logic;
ResetOut : out std_logic);
end ELIS_Statemachine;
architecture Behavioral of ELIS_Statemachine is
type STATE_TYPE is (Clear,Zero,Start,Counting,Stop,Stopped);
attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of STATE_TYPE: type is "000 101 010 001 011
100";
signal CS : STATE_TYPE;
signal NS : STATE_TYPE;
begin
SYNC_PROC: process (CLOCK, RESET)
begin
if (RESET='1') then
CS <= Clear;
elsif (CLOCK'event and CLOCK = '1') then
CS <= NS;
end if;
end process;
COMB_PROC: process (CS, StartStop)
begin
case CS is
when clear => NS <= Zero;
when Zero => If StartStop = '1' then
NS <= Start;
else
NS <= Zero;
end if;
when Start => If StartStop = '0' then
NS <= Counting;
else
NS <= Start;
end if;
when Counting => If StartStop = '1' then
NS <= Stop;
else
NS <= Counting;
end if;
when Stop => If StartStop = '0' then
NS <= Stopped;
else
NS <= Stop;
end if;
when Stopped => If StartStop = '1' then
NS <= Zero;
else
NS <= Stopped;
end if;
when others => NS <= Clear;
end case;
end process;
Sync_Output : process (Reset, Clock)
begin
if (RESET='1') then
ClockEnableOut <= '0';
ResetOut <= '1';
elsif (CLOCK'event and CLOCK = '1') then
case NS is
when clear => ClockEnableOut <= '0';
ResetOut <= '1';
when Zero => ClockEnableOut <= '0';
ResetOut <= '0';
when Start => ClockEnableOut <= '1';
ResetOut <= '0';
when Counting => ClockEnableOut <= '1';
ResetOut <= '0';
when Stop => ClockEnableOut <= '0';
ResetOut <= '0';
when Stopped => ClockEnableOut <= '0';
ResetOut <= '0';
when others => ClockEnableOut <= '0';
ResetOut <= '1';
end case;
end if;
end process;
end Behavioral;
Sourcecode of stmach.vhd :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY STMACH IS
PORT (CLK,RESET,strtstop: IN std_logic;
clkout,rst : OUT std_logic);
END;
ARCHITECTURE BEHAVIOR OF STMACH IS
SIGNAL sreg : std_logic_vector (2 DOWNTO 0);
SIGNAL next_sreg : std_logic_vector (2 DOWNTO 0);
CONSTANT clear : std_logic_vector (2 DOWNTO 0) :="000";
CONSTANT counting : std_logic_vector (2 DOWNTO 0) :="001";
CONSTANT start : std_logic_vector (2 DOWNTO 0) :="010";
CONSTANT stop : std_logic_vector (2 DOWNTO 0) :="011";
CONSTANT stopped : std_logic_vector (2 DOWNTO 0) :="100";
CONSTANT zero : std_logic_vector (2 DOWNTO 0) :="101";
BEGIN
PROCESS (CLK, RESET, next_sreg)
BEGIN
IF ( RESET='1' ) THEN
sreg <= clear;
ELSIF CLK='1' AND CLK'event THEN
sreg <= next_sreg;
END IF;
END PROCESS;
PROCESS (sreg,strtstop)
BEGIN
clkout <= '0'; rst <= '0';
next_sreg<=clear;
CASE sreg IS
WHEN clear =>
clkout<='0';
rst<='1';
IF TRUE THEN
next_sreg<=zero;
ELSE
next_sreg<=clear;
END IF;
WHEN counting =>
clkout<='1';
rst<='0';
IF NOT ( (( strtstop='0' ) ) OR (( strtstop='1' ) ) ) THEN
next_sreg<=counting;
END IF;
IF ( strtstop='0' ) THEN
next_sreg<=counting;
END IF;
IF ( strtstop='1' ) THEN
next_sreg<=stop;
END IF;
WHEN start =>
clkout<='1';
rst<='0';
IF NOT ( (( strtstop='1' ) ) OR (( strtstop='0' ) ) ) THEN
next_sreg<=start;
END IF;
IF ( strtstop='1' ) THEN
next_sreg<=start;
END IF;
IF ( strtstop='0' ) THEN
next_sreg<=counting;
END IF;
WHEN stop =>
clkout<='0';
rst<='0';
IF NOT ( (( strtstop='1' ) ) OR (( strtstop='0' ) ) ) THEN
next_sreg<=stop;
END IF;
IF ( strtstop='1' ) THEN
next_sreg<=stop;
END IF;
IF ( strtstop='0' ) THEN
next_sreg<=stopped;
END IF;
WHEN stopped =>
clkout<='0';
rst<='0';
IF NOT ( (( strtstop='0' ) ) OR (( strtstop='1' ) ) ) THEN
next_sreg<=stopped;
END IF;
IF ( strtstop='0' ) THEN
next_sreg<=stopped;
END IF;
IF ( strtstop='1' ) THEN
next_sreg<=start;
END IF;
WHEN zero =>
clkout<='0';
rst<='0';
IF NOT ( (( strtstop='0' ) ) OR (( strtstop='1' ) ) ) THEN
next_sreg<=zero;
END IF;
IF ( strtstop='0' ) THEN
next_sreg<=zero;
END IF;
IF ( strtstop='1' ) THEN
next_sreg<=start;
END IF;
WHEN OTHERS =>
END CASE;
END PROCESS;
END BEHAVIOR;
Article: 58469MS (wpiman@aol.com) wrote: : The question is how much do you usually expect FPGA prices to fall in : a given year. For example, would a guess of a 15% drop in the first : year followed by a 30% fall in the second year be a good stab? 20% a : year? I just need to fill out some numbers to make some bean counter : happy. Anyone take a look at what has historical been the price : drops? Any number you pick will be a wild guess. The long term cost to produce a popular chip is calculated by the size factored in with the failure rate. The costs of the chip is the production cost plus R&D plus whatever else they throw in. The early production cost of a new chip is related to its complexity, its process, its pin count, its R&D expense, its mareting expense, its tool development expenses adn a dew other factors. If the chip is popular, then the R&D costs get spread over more chips. As production gets better, the yield goes up and that makes it cheaper. If there are problems with the chip (yield, marketing, bad tools, ugly web page, whatever), then the price may not go down much at all. If you want to look at price graphs, look at Intel's PC processors and how they have dropped over time. You will find different parts have different curves which are related to issues like the device being migrated to Cu or rumors of it over heating in laptops. For any given FPGA, I expect you can find a price curve of an Intel CPU to match with a slight adjstment of scales. You just have to bet on a chip thats going to go down and not stay level. That is determined by other things you don't know and won't know until your far into production if its a new chip in a new family. About all you can do is get budget numbers from the sales rep who will be relaying numbers that come from the guesses from the factory about how they hope things will go. -tim http://web.abnormal.comArticle: 58470
Martin, MPPR is used when PAR fails to meet timing constraints by a small margin with the default cost table. Each cost table would serve as a seed for PAR algorithm and result in a different placement and routing. One of these results may meet your timing constraints, otherwise MPPR will indicate the best placement and routing it achieved with the given cost tables. In your case all these MPPR results meet your timing constraints, as the timing score is zero. Timing score is simply a summation in picoseconds of all timing violations. You can use any of these cost table as long as your timing constraints are met by PAR. The following solution record explains on how to interpret MPPR report http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=3749 -Vikram Martin Euredjian wrote: > OK, I give up. > > So, I ran 20 passes of "Multi Pass Place & Route" via the GUI. > > I get the following report (excerpt): > > <snip> > > Level/ Design Timing Number Run NCD > Cost [ncd] Score Score Unrouted Time Status > ---------- ------ -------- -------- ----- ------------ > 5_5_17 * 146 0 0 02:16 Complete > 5_5_7 * 147 0 0 02:11 Complete > 5_5_19 * 147 0 0 02:31 Complete > 5_5_3 * 151 0 0 02:16 Complete > 5_5_4 * 151 0 0 02:15 Complete > > <snip> > > How do I make use of this now? > > It looks like cost table 17 is the best run. Do I go and manually switch to > this table and run the standard Place & Route tool (not multi)? > > I looked through as much of the documentation as I could imagine might > describe this but I couldn't find a descripition of the process by which you > make use of multi-pass, from start to finish. > > I don't really need this level of optimization for my design, but I wanted > to learn how to do it just in case. > > Thanks, > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" -- ---------------------------------------------- Vikram Pasham Xilinx Design Services - Texas http://www.xilinx.com/xds/ Phone no. (Internal): (840)-0253 Phone no. (External): (972)-246-0253 ----------------------------------------------Article: 58471
John, Thank you. Greatly appreciated. The "$1500" price in the posting is clearly a red herring, designed to alarm and annoy. Actual prices start far lower, and rarely get to that price point for customers that buy more than one part. The reason why we don't talk prices here is rather simple: each customer has their own volume requirement, their own time scale for delivery, and their own level of support. All of these items must be factored into the equation by the distributor. If you build motherboards for PCs, then the price you pay for a uP is pretty well known, and is an easy matter. Unfortunately, FPGAs are sold in volumes of 1 to millions: hard to offer a price for such a large variation in quantities. FPGAs might be in the Gibson guitar, or the Mars Lander. For me to say that you can get a part for $20 is as bad as saying the part costs $1500. In fact, both are true at some point in time (for different parts!). Oh, the other reason why we don't tak prices is that Peter and I are engineers (but you knew that - thanks again). Generally speaking, FPGAs do follow the same curve as microprocessors for reduction in price over time (astute observation by engineer). Austin John Williams wrote: > Stifler wrote: > > Petey, > > > > I am curious. Are you sales? Are you Marketing? Are you Applications? > > Your rhetorical style needs some work. > > > Why are you vendors even on this board? > > Because they know the ins and outs of their products better than anybody > else? And with the apparent exception of you, most of us are very glad > they're here and participating. > > > Who believes all of your spew? > > The vendors in this NG are remarkably restrained when it comes to > promotion, marketing "spew" and putting down the competitors. > > > Your answer was a non answer. Contact your sales person. Oh thank you > > so much for that piece of such valuable information. > > Oh what, and "Pricing goes by volume and time" is rocket science hot off > the presses? Get over yourself!Article: 58472
Ray, We routinely get folks who say they can compress a particular bitfile by 5:1 or even 10:1. Too bad that doesn't hold true for all bitfiles. As I have said before, if there was a good way to guarantee compression, we would have done it years ago. Let's see, we have ~150,000 bitstreams that are being developed right now at this moment. Think about it: to remain a quality supplier we have to make every one of those 150,000 designers have a wonderful (downloading) FPGA experience. Just one flakey option bit in the bitgen, and the hotlines would meltdown. Austin Ray Andraka wrote: > Even with a very full V2 design, I see almost 5:1 compression of the bitstream with winzip (577K after > compression for 2V6000) > > Symon wrote: > > > Austin, > > Glad you like the idea. Out of curiosity I tried WinZipping some > > bit files and got >90% compression on my admittedly only 10% full V2 > > design. So, I await the first freebie port of WinZip to VHDL or the > > PPC. I won't be holding my breath!! > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 58473
Help,
I am looking for the free modelsim simulator and I cannot seem to find
the link for it in the Xilinx web site. Where is it?
Theron Hicks
Article: 58474Hi Martin "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:W7jTa.279$NK6.51@newssvr24.news.prodigy.com... > > I've found that meeting basic timing constraints (like PERIOD) does not > guarantee that good logic (meaning that the HDL is good) will work. That, > BTW, to me, is one of the most frustrating aspects of FPGA's: good code != > working device. > It must be frustrating however: Proven board + Proven tools + Synchronous Design + Good Code (functionally correct) + Static Timing Closure => working device. If I had a block which works sometimes, and then does'nt on the next route, and all timing constraints were met, I would have to ask if my design is 100% synchronous, and if so, what makes me believe that my code is good. Eric Pearson
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