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I'm design a FEC scheme using Reed-Solomon and FPGA Cyclone (Altera). The input clock is 2.048MHz and the output must be (205/188)*2.048MHz (~2.233191MHz). The problem is in the increase clock rate at the output. The internal PLL works only whit frequencies above 15MHz and the factor 205/188 can't be achieve too. I think increase rate is a commom problem in channel coding application but I do not have any success searching related topics on internet or on books. For example, in celular a initial bit rate of 4.8kbps is increased to ~70kbps at the end of coding process, and there are a lot of intermediary rates (9.6kbps,32kbps etc). Using a external PLL was the first idea but I'd like to implement all the scheme in fpga. My actual aproach is to use a digital NCO (derived from a sample clock of 200MHz) with the central frequency in 2.233191MHz and a loop control related with the input clock. In the loop control the input clock and output clocks are conected to counters, when the input counter is 188 the output counter is sampled and the count value expected is 205, if it is false a new numeric control is applied to the NCO to correct the frequency. I dont know if it can works well and if anybody have any suggestion or idea I'd appreciate. Thanks IvanArticle: 58401
Hi, I have already designed a 2-D edge detector in Simulink and converted it to VHDL code using System Generator. I was wondering that how to feed the image to the FPGA? In simulink, I just read the image from workspace and write the data to workspace. It is very easy to read the image and write the image, but if I implement the design onto FPGA, how to feed the image to FPGA? Any good idea is highly appreciated. ShawArticle: 58402
"Ivan" <ivansimoes@msn.com> wrote in message news:4746b99b.0307221230.53adc209@posting.google.com... > I'm design a FEC scheme using Reed-Solomon and FPGA Cyclone (Altera). > The input clock is 2.048MHz and the output must be (205/188)*2.048MHz > (~2.233191MHz). The problem is in the increase clock rate at the > output. The internal PLL works only whit frequencies above 15MHz and > the factor 205/188 can't be achieve too. I think increase rate is a > commom problem in channel coding application but I do not have any > success searching related topics on internet or on books. For example, > in celular a initial bit rate of 4.8kbps is increased to ~70kbps at > the end of coding process, and there are a lot of intermediary rates > (9.6kbps,32kbps etc). > > Using a external PLL was the first idea but I'd like to implement all > the scheme in fpga. My actual aproach is to use a digital NCO (derived > from a sample clock of 200MHz) with the central frequency in > 2.233191MHz and a loop control related with the input clock. In the > loop control the input clock and output clocks are conected to > counters, when the input counter is 188 the output counter is sampled > and the count value expected is 205, if it is false a new numeric > control is applied to the NCO to correct the frequency. > > I dont know if it can works well and if anybody have any suggestion or > idea I'd appreciate. > > Thanks > > Ivan Ivan, Do you mean 204/188? That's the normal RS code rate for DVB. You can use a digital PLL that will track the input clock such that the NCO vector spins at 204/188 * input_clk, as long as you don't mind the 5ns jitter of the output clock. If this is a DVB modulator, you may have successive stages that change the code rate (like a trellis coder) and it's best just to clock only the final stage at the required rate, and let each stage fetch data irregulary from the previous stage as it is required. Another method is to have a fixed output clock that runs faster than the required rate of 204/188*input_clock. When the input FIFO underflows, a null packet is transmitted while the input FIFO fills again. -KevinArticle: 58403
If one does a groups.google.com search in comp.arch.fpga for "directed route cst" there will be one hit from a guy named... Philip Freidin providing a little detail about the ability to include a manual route in the constraints file. Once manual routing has produced the desired results, the route can be "archived" with the caveat that there can be no changes to the locations of the source and destinations nor any additions or delations of the destinations without "tossing out" the previous manual routing efforts. I've found the directed routing to be extremely helpful. I only wish it was friendlier, perhaps allowing specification of a subset of the route so "don't care" elements aren't arbitrarily LOCed and new elements on the net don't "break" the previous effort. I am *very* happy the feature is there in a not-so-friendly state rather than not being there at all. - John_H [Apologies to the newsgroup archivers for keeping the whole post. Sometimes it's the only way the comments make sense.] "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F1D9D41.32259930@yahoo.com... > Philip Freidin wrote: > > > > On 22 Jul 2003 07:29:35 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote: > > >Hi Guys, > > > > > >In Xilinx FPGA editor when you have finished your design and you can > > >see the routed desing using Xilinx FPGA Editor. > > >In that area used by the wire is more than the area used by IOB. > > > > I don't know what you mean. > > > > >How > > >can I place the wire the way I wanted to. Is FPGA editor can be used > > >to accomplish this task. > > > > Yes. It is an editor. You need to change the operating mode from > > read-only to "read-write". > > > > File->Main Properties->Edit Mode. This is also available in the > > File->Open pop-up > > > > Doing manual routing is not easy. You will need to carefully read > > the documentation. Sometimes it is best to start by practicing on > > an empty design (vreated new in the FPGA editor), until you are > > competent at doing the manual routing commands. Then do it on > > your real design. > > > > >Secondly, how can I concerntrate the desing in one part of the chip > > >rather than to use automatically generated design. > > > > Yes. You need to constrain your design BEFORE you run place-and-route. > > You should probably use an Area Constraint. > > The real problem with manual editing a design is maintenance. I have > worked on two designs which required manual edits to the routing. One > was a very simple routing change to optimize a very short path where the > chip was muxing a clock. But every time a new P&R was done, it had to > be edited to get this small improvement in routing time. So we had to > document this change step by step so the next person to work on the > design could repeat the process. > > The other was a similar change for a clock multiplexor, but was more > extensive. This was done by someone else and a couple of years later > when we were reworking the design, we could not find any documentation > on the change. This led to a process of trying to trace the ownership > of the design back to the original designer who happened to be my second > level manager. Lets just say that this process was not conducive to my > career advancement at that point since I have been sprinkling my > exploration with some amount of criticism about the lack of > documentation. > > The odd thing was that no one ever produced any real documentation of > that hand routing. The second level manager gave a few of us a demo of > what needed to be changed and how to do it. It seems clear that some > companies make do with oral tradition rather than written > documentation. > > So be aware of how important documentation of hand editing can be. The > process may seem simple, but it can be difficult to convey exactly how > to do it. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58404
I've been thinking about this whole issue of constraints vs. manual routing lately. I've been fighting a module that likes to break when changes in unrelated logic modify routing (my interpretation of what's going on). I've been tempted to go and hand-route (and lock) that module, but the reality of things is that the code isn't finished. So, a manual route could be a painful excercise in futility. There's also the issue of maintainability that Rick Collins brought-up. The question I have is: How do pro's approach a non-trivial design where development might preclude you from locking manual routing and placement until the very end? I've found that meeting basic timing constraints (like PERIOD) does not guarantee that good logic (meaning that the HDL is good) will work. That, BTW, to me, is one of the most frustrating aspects of FPGA's: good code != working device. Do you start with area constraints to at least get a handle on automated routing? And, is there a way to make the routing tools be more intelligent about aligning data paths? It seems so basic ... but in looking at FloorPlanner I've seen some pretty bad examples of how not to align data paths, even when the tools are set to maximum effort. Eager to find new ways... -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "John_H" <johnhandwork@mail.com> wrote in message news:tLiTa.20$Fz4.3672@news-west.eli.net... > If one does a groups.google.com search in comp.arch.fpga for "directed route > cst" there will be one hit from a guy named... Philip Freidin providing a > little detail about the ability to include a manual route in the constraints > file. Once manual routing has produced the desired results, the route can > be "archived" with the caveat that there can be no changes to the locations > of the source and destinations nor any additions or delations of the > destinations without "tossing out" the previous manual routing efforts. > > I've found the directed routing to be extremely helpful. I only wish it was > friendlier, perhaps allowing specification of a subset of the route so > "don't care" elements aren't arbitrarily LOCed and new elements on the net > don't "break" the previous effort. I am *very* happy the feature is there > in a not-so-friendly state rather than not being there at all. > > - John_H > [Apologies to the newsgroup archivers for keeping the whole post. > Sometimes it's the only way the comments make sense.] > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F1D9D41.32259930@yahoo.com... > > Philip Freidin wrote: > > > > > > On 22 Jul 2003 07:29:35 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote: > > > >Hi Guys, > > > > > > > >In Xilinx FPGA editor when you have finished your design and you can > > > >see the routed desing using Xilinx FPGA Editor. > > > >In that area used by the wire is more than the area used by IOB. > > > > > > I don't know what you mean. > > > > > > >How > > > >can I place the wire the way I wanted to. Is FPGA editor can be used > > > >to accomplish this task. > > > > > > Yes. It is an editor. You need to change the operating mode from > > > read-only to "read-write". > > > > > > File->Main Properties->Edit Mode. This is also available in the > > > File->Open pop-up > > > > > > Doing manual routing is not easy. You will need to carefully read > > > the documentation. Sometimes it is best to start by practicing on > > > an empty design (vreated new in the FPGA editor), until you are > > > competent at doing the manual routing commands. Then do it on > > > your real design. > > > > > > >Secondly, how can I concerntrate the desing in one part of the chip > > > >rather than to use automatically generated design. > > > > > > Yes. You need to constrain your design BEFORE you run place-and-route. > > > You should probably use an Area Constraint. > > > > The real problem with manual editing a design is maintenance. I have > > worked on two designs which required manual edits to the routing. One > > was a very simple routing change to optimize a very short path where the > > chip was muxing a clock. But every time a new P&R was done, it had to > > be edited to get this small improvement in routing time. So we had to > > document this change step by step so the next person to work on the > > design could repeat the process. > > > > The other was a similar change for a clock multiplexor, but was more > > extensive. This was done by someone else and a couple of years later > > when we were reworking the design, we could not find any documentation > > on the change. This led to a process of trying to trace the ownership > > of the design back to the original designer who happened to be my second > > level manager. Lets just say that this process was not conducive to my > > career advancement at that point since I have been sprinkling my > > exploration with some amount of criticism about the lack of > > documentation. > > > > The odd thing was that no one ever produced any real documentation of > > that hand routing. The second level manager gave a few of us a demo of > > what needed to be changed and how to do it. It seems clear that some > > companies make do with oral tradition rather than written > > documentation. > > > > So be aware of how important documentation of hand editing can be. The > > process may seem simple, but it can be difficult to convey exactly how > > to do it. > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > >Article: 58405
"Vikram Pasham" <Vikram.Pasham@xilinx.com> wrote in message news:3F1B452B.DE8DC29E@xilinx.com... > > An alternate way to bring internal FPGA signals to IOBs (mainly for debugging or > track internals signal's behaviour) is to use "Add Probes" feature in FPGA > Editor. This is explained in the solution record > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=6616 > > This is a more elegant way as you don't need to add ports in RTL or re-run PAR. > This will not change timing of the oringal design. You can add probes in FPGA > Editor, save the NCD file and generate a new bitstream. Thanks, just tried it. Life is MUCH simplified this way. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 58406
Another related question. Is there a way to area-constrain the logic corresponding to an HDL module and then have the tools take an iterative approach to getting the best placement (say, timing and data-path alignment) within that area? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:W7jTa.279$NK6.51@newssvr24.news.prodigy.com... > I've been thinking about this whole issue of constraints vs. manual routing > lately. I've been fighting a module that likes to break when changes in > unrelated logic modify routing (my interpretation of what's going on). I've > been tempted to go and hand-route (and lock) that module, but the reality of > things is that the code isn't finished. So, a manual route could be a > painful excercise in futility. There's also the issue of maintainability > that Rick Collins brought-up. > > The question I have is: How do pro's approach a non-trivial design where > development might preclude you from locking manual routing and placement > until the very end? > > I've found that meeting basic timing constraints (like PERIOD) does not > guarantee that good logic (meaning that the HDL is good) will work. That, > BTW, to me, is one of the most frustrating aspects of FPGA's: good code != > working device. > > Do you start with area constraints to at least get a handle on automated > routing? And, is there a way to make the routing tools be more intelligent > about aligning data paths? It seems so basic ... but in looking at > FloorPlanner I've seen some pretty bad examples of how not to align data > paths, even when the tools are set to maximum effort. > > Eager to find new ways... > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > > > "John_H" <johnhandwork@mail.com> wrote in message > news:tLiTa.20$Fz4.3672@news-west.eli.net... > > If one does a groups.google.com search in comp.arch.fpga for "directed > route > > cst" there will be one hit from a guy named... Philip Freidin providing a > > little detail about the ability to include a manual route in the > constraints > > file. Once manual routing has produced the desired results, the route can > > be "archived" with the caveat that there can be no changes to the > locations > > of the source and destinations nor any additions or delations of the > > destinations without "tossing out" the previous manual routing efforts. > > > > I've found the directed routing to be extremely helpful. I only wish it > was > > friendlier, perhaps allowing specification of a subset of the route so > > "don't care" elements aren't arbitrarily LOCed and new elements on the net > > don't "break" the previous effort. I am *very* happy the feature is there > > in a not-so-friendly state rather than not being there at all. > > > > - John_H > > [Apologies to the newsgroup archivers for keeping the whole post. > > Sometimes it's the only way the comments make sense.] > > > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3F1D9D41.32259930@yahoo.com... > > > Philip Freidin wrote: > > > > > > > > On 22 Jul 2003 07:29:35 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote: > > > > >Hi Guys, > > > > > > > > > >In Xilinx FPGA editor when you have finished your design and you can > > > > >see the routed desing using Xilinx FPGA Editor. > > > > >In that area used by the wire is more than the area used by IOB. > > > > > > > > I don't know what you mean. > > > > > > > > >How > > > > >can I place the wire the way I wanted to. Is FPGA editor can be used > > > > >to accomplish this task. > > > > > > > > Yes. It is an editor. You need to change the operating mode from > > > > read-only to "read-write". > > > > > > > > File->Main Properties->Edit Mode. This is also available in the > > > > File->Open pop-up > > > > > > > > Doing manual routing is not easy. You will need to carefully read > > > > the documentation. Sometimes it is best to start by practicing on > > > > an empty design (vreated new in the FPGA editor), until you are > > > > competent at doing the manual routing commands. Then do it on > > > > your real design. > > > > > > > > >Secondly, how can I concerntrate the desing in one part of the chip > > > > >rather than to use automatically generated design. > > > > > > > > Yes. You need to constrain your design BEFORE you run place-and-route. > > > > You should probably use an Area Constraint. > > > > > > The real problem with manual editing a design is maintenance. I have > > > worked on two designs which required manual edits to the routing. One > > > was a very simple routing change to optimize a very short path where the > > > chip was muxing a clock. But every time a new P&R was done, it had to > > > be edited to get this small improvement in routing time. So we had to > > > document this change step by step so the next person to work on the > > > design could repeat the process. > > > > > > The other was a similar change for a clock multiplexor, but was more > > > extensive. This was done by someone else and a couple of years later > > > when we were reworking the design, we could not find any documentation > > > on the change. This led to a process of trying to trace the ownership > > > of the design back to the original designer who happened to be my second > > > level manager. Lets just say that this process was not conducive to my > > > career advancement at that point since I have been sprinkling my > > > exploration with some amount of criticism about the lack of > > > documentation. > > > > > > The odd thing was that no one ever produced any real documentation of > > > that hand routing. The second level manager gave a few of us a demo of > > > what needed to be changed and how to do it. It seems clear that some > > > companies make do with oral tradition rather than written > > > documentation. > > > > > > So be aware of how important documentation of hand editing can be. The > > > process may seem simple, but it can be difficult to convey exactly how > > > to do it. > > > > > > -- > > > > > > Rick "rickman" Collins > > > > > > rick.collins@XYarius.com > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design URL http://www.arius.com > > > 4 King Ave 301-682-7772 Voice > > > Frederick, MD 21701-3110 301-682-7666 FAX > > > > > >Article: 58407
Symon,
You are using the syn_direct_enable directive correctly.
As you noticed, you achieved the desired behavior on the
data_int2 Flip Flop, but data_int1 FF was not correct.
Synplify seems to be loosing the direct_enable when
it is evaluating the integer expression toggle=0 along with
the enable expression.
It is possible to work around this problem by placing a "syn_keep"
directive on toggle. The syn_keep directive creates an
optimization boundary and this prevents Synplify from optimizing
toggle together with enable and thus produces the results
you expected. Your test case with my modifications follows
below. I realize the RTL posted on this message is just a
test case, but I assume that a similar work around can be used
on your actual design. If you need assistance getting this
to work on your design please do not hesitate to contact me
or any of our Corporate Application Engineers at
support@synplicity.com.
Obviously this is a bug in Synplify and I have filed bug # 107936.
This will be fixed in a future release. Please let me know if the
work around will solve your problem in the short term and
how urgently you require a fix to be incorporated into the tool.
Best Regards,
Jim Robinson
jim@synplicity.com
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity direct_enable_test is
port (
signal res_n : in std_logic; -- General reset.
signal clock : in std_logic; -- clock 350MHz
signal toggle_in : in integer range 0 to 15; -- toggle value
signal data : out std_logic -- data
);
end direct_enable_test;
architecture direct_enable_test_arch of direct_enable_test is
signal enable : std_logic;
signal data_int1 : std_logic;
signal data_int2 : std_logic;
signal toggle : integer range 0 to 15; -- toggle value
attribute syn_direct_enable: boolean;
attribute syn_direct_enable of enable : signal is true;
attribute syn_keep: boolean; -- Workaround
attribute syn_keep of toggle : signal is true; -- Workaround
begin
data <= data_int1 or data_int2;
process (res_n, clock)
begin
if (res_n = '0') then
enable <= '0';
toggle <= 0;
elsif rising_edge (clock) then
enable <= not enable;
if enable = '1' then
toggle <= (toggle + 1) mod 16;
end if;
end if;
end process;
process (res_n, clock)
begin
if (res_n = '0') then
data_int1 <= '0';
elsif rising_edge (clock) then
if enable = '1' then
if toggle = 0 then
data_int1 <= not data_int1;
end if;
end if;
end if;
end process;
process (res_n, clock)
begin
if (res_n = '0') then
data_int2 <= '0';
elsif rising_edge (clock) then
if enable = '1' then
if toggle_in = 0 then
data_int2 <= not data_int2;
end if;
end if;
end if;
end process;
end direct_enable_test_arch;
Article: 58408Hi, "Internal Errors" are unexpected conditions reached in the software. In this case, the programmer has made a check in the assembler database (I think) to ensure that their counter does not exceed a particular value, probably to avoid using it to reference entries in an array which do not exist (which would itself cause some mysterious crash, or worse, incorrect results from the tool). In other words, they are bugs. The error message produced by IEs are not intended to be particularly useful to the user -- if we thought users could reach these conditions, we would have written code to handle the conditions more gracefully. For example, if you write bad VHDL, or specify an illegal constraint, etc. Quartus should give you a useful error. It is rare for a gross/systematic error to make it into the production tool -- the vast majority of bugs are detected by a combination of input conditions that are usually unique to a single design or user. Thus the reason tech support requests your design and project files is that without these, the programmer has little hope in replicating the behaviour you are seeing. There's not much I can do for you here -- your best bet is to provide the support team with the requested information. Regards, Paul Leventis Altera Corp. "spring" <spring555555@yahoo.com> wrote in message news:bfk4v2$4to$1@news.storm.ca... > Hi, all, > Does anyone know how to deal with the annoying "Internal Error" with > whatever Quartus II 3.0 or Max+plus II? I migrated a design from > Max+plus II to Quartus II, imported the assignment from .acf file, then > run compilation. The Quartus showed the "Interanl Error" with following > message: > “Internal Error: Sub-system: ASMDB, File: asmdb_mux.cpp, Line: 445 > ASMDB_MUX error: RAM_MUX::select : index out of range (index = 2048, > size = 2048) : last archgroup encountered: type = RAM_CONTENT_FLEX10KE > Quartus II Version 3.0 Build 199 06/26/2003 SJ Full Version” > And compilation was cancelled! > I was hoping that the new Quartus II 3.0 would probably be better than > Max+plus II. I am wrong. I would guess that the Quartus was designed by > the same people. Besides, every time I am looking for the mySupport on > the Altera website, the only thing they could do is asking my design and > all my project files, although I gave them all the detailed information, > steps, their software messages. > Any input would be appreciated. > spring >Article: 58409
Which is exactly why I avoid it like the plague.
rickman wrote:
> The real problem with manual editing a design is maintenance. I have
> worked on two designs which required manual edits to the routing. One
> was a very simple routing change to optimize a very short path where the
> chip was muxing a clock. But every time a new P&R was done, it had to
> be edited to get this small improvement in routing time. So we had to
> document this change step by step so the next person to work on the
> design could repeat the process.
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58410
The automatic placment algorithms, while better than in the past, still suck. I
do a large amount of explicit placement using a structural hierarchy. The
relative placements (in the form of RLOCs) are in the code, and these are built
up hierarchically. Some examples of the floorplans can be seen on the gallery
page of my website (thanks Phil Freidin for that idea).
Martin Euredjian wrote:
> I've been thinking about this whole issue of constraints vs. manual routing
> lately. I've been fighting a module that likes to break when changes in
> unrelated logic modify routing (my interpretation of what's going on). I've
> been tempted to go and hand-route (and lock) that module, but the reality of
> things is that the code isn't finished. So, a manual route could be a
> painful excercise in futility. There's also the issue of maintainability
> that Rick Collins brought-up.
>
> The question I have is: How do pro's approach a non-trivial design where
> development might preclude you from locking manual routing and placement
> until the very end?
>
> I've found that meeting basic timing constraints (like PERIOD) does not
> guarantee that good logic (meaning that the HDL is good) will work. That,
> BTW, to me, is one of the most frustrating aspects of FPGA's: good code !=
> working device.
>
> Do you start with area constraints to at least get a handle on automated
> routing? And, is there a way to make the routing tools be more intelligent
> about aligning data paths? It seems so basic ... but in looking at
> FloorPlanner I've seen some pretty bad examples of how not to align data
> paths, even when the tools are set to maximum effort.
>
> Eager to find new ways...
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_" = "martineu"
>
> "John_H" <johnhandwork@mail.com> wrote in message
> news:tLiTa.20$Fz4.3672@news-west.eli.net...
> > If one does a groups.google.com search in comp.arch.fpga for "directed
> route
> > cst" there will be one hit from a guy named... Philip Freidin providing a
> > little detail about the ability to include a manual route in the
> constraints
> > file. Once manual routing has produced the desired results, the route can
> > be "archived" with the caveat that there can be no changes to the
> locations
> > of the source and destinations nor any additions or delations of the
> > destinations without "tossing out" the previous manual routing efforts.
> >
> > I've found the directed routing to be extremely helpful. I only wish it
> was
> > friendlier, perhaps allowing specification of a subset of the route so
> > "don't care" elements aren't arbitrarily LOCed and new elements on the net
> > don't "break" the previous effort. I am *very* happy the feature is there
> > in a not-so-friendly state rather than not being there at all.
> >
> > - John_H
> > [Apologies to the newsgroup archivers for keeping the whole post.
> > Sometimes it's the only way the comments make sense.]
> >
> >
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:3F1D9D41.32259930@yahoo.com...
> > > Philip Freidin wrote:
> > > >
> > > > On 22 Jul 2003 07:29:35 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote:
> > > > >Hi Guys,
> > > > >
> > > > >In Xilinx FPGA editor when you have finished your design and you can
> > > > >see the routed desing using Xilinx FPGA Editor.
> > > > >In that area used by the wire is more than the area used by IOB.
> > > >
> > > > I don't know what you mean.
> > > >
> > > > >How
> > > > >can I place the wire the way I wanted to. Is FPGA editor can be used
> > > > >to accomplish this task.
> > > >
> > > > Yes. It is an editor. You need to change the operating mode from
> > > > read-only to "read-write".
> > > >
> > > > File->Main Properties->Edit Mode. This is also available in the
> > > > File->Open pop-up
> > > >
> > > > Doing manual routing is not easy. You will need to carefully read
> > > > the documentation. Sometimes it is best to start by practicing on
> > > > an empty design (vreated new in the FPGA editor), until you are
> > > > competent at doing the manual routing commands. Then do it on
> > > > your real design.
> > > >
> > > > >Secondly, how can I concerntrate the desing in one part of the chip
> > > > >rather than to use automatically generated design.
> > > >
> > > > Yes. You need to constrain your design BEFORE you run place-and-route.
> > > > You should probably use an Area Constraint.
> > >
> > > The real problem with manual editing a design is maintenance. I have
> > > worked on two designs which required manual edits to the routing. One
> > > was a very simple routing change to optimize a very short path where the
> > > chip was muxing a clock. But every time a new P&R was done, it had to
> > > be edited to get this small improvement in routing time. So we had to
> > > document this change step by step so the next person to work on the
> > > design could repeat the process.
> > >
> > > The other was a similar change for a clock multiplexor, but was more
> > > extensive. This was done by someone else and a couple of years later
> > > when we were reworking the design, we could not find any documentation
> > > on the change. This led to a process of trying to trace the ownership
> > > of the design back to the original designer who happened to be my second
> > > level manager. Lets just say that this process was not conducive to my
> > > career advancement at that point since I have been sprinkling my
> > > exploration with some amount of criticism about the lack of
> > > documentation.
> > >
> > > The odd thing was that no one ever produced any real documentation of
> > > that hand routing. The second level manager gave a few of us a demo of
> > > what needed to be changed and how to do it. It seems clear that some
> > > companies make do with oral tradition rather than written
> > > documentation.
> > >
> > > So be aware of how important documentation of hand editing can be. The
> > > process may seem simple, but it can be difficult to convey exactly how
> > > to do it.
> > >
> > > --
> > >
> > > Rick "rickman" Collins
> > >
> > > rick.collins@XYarius.com
> > > Ignore the reply address. To email me use the above address with the XY
> > > removed.
> > >
> > > Arius - A Signal Processing Solutions Company
> > > Specializing in DSP and FPGA design URL http://www.arius.com
> > > 4 King Ave 301-682-7772 Voice
> > > Frederick, MD 21701-3110 301-682-7666 FAX
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58411
how deep?
One trick if your read/write rates are enough different is to synchronize the
read or write pulse of the slower side with the higher speed side's clock and
just maintain a population count on that side. In this case, you don't quite
have enough of a differential to do it straight, however if you can accumulate
and write two words at a time at half the write clock it is possible. If you
can do that, you can also jsut resync the write data to the read clock using
something like the flancter circuit and then operate a synchronous fifo at the
read clock rate. For shallow fifos, I've also used a shift register as a
population counter, nice because it is glitchless and is already decoded for
each count. Not real good for more than a handful of words deep though. For a
deeper fifo, you can also couple a small async one to a larger sync one to make
the pointers easier to manage.
Barry Brown wrote:
> A few more details I should have mentioned:
> write clock is 40 MHz
> read clock is 75 MHz
> I only need the "number of words in FIFO" count on the read clock side
>
> Here is what I have been thinking -
> Gray counters for read and write addresses. Re-clock the gray write address
> with the read clock, then convert it back to binary. Subtract the read
> address from the re-clocked write address (both in binary), to get the
> number of words in the FIFO. It seems that if I re-clock the write address
> while it's in gray code, I should only have a one count ambiguity.
>
> Anyone see a flaw, or have a better idea?
>
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3F1C5BFC.493D4F68@xilinx.com...
> > Synchronous FIFOs are effectively synchronous state machines.
> > Asynchronous operation is much trickier, since you must accomodate any
> > conceivable phase difference between the two clocks.
> > Clock speed is important.
> > One method performs the simple subtraction of the two binary counters,
> > but performs it continuously, and throws out any "non-fitting" results,
> > assuming they are the result of one counter just changing during the
> > capture. Clever but not really kosher...
> >
> > The design depend on the clock frequencies involves, and on free-running
> > or not free-running clock behavior.
> > There is no simple standard recipe.
> > Peter Alfke
> > =========
> > Barry Brown wrote:
> > >
> > > I have designed a synchronous FIFO in the past, but now I need one with
> > > asynchronous read and write clocks. It will be in a Virtex2, and I need
> to
> > > keep a count of the number of words in the FIFO. I do not need the empty
> and
> > > full indicators. I have the Xilinx app notes (175, 131), which say that
> it
> > > is not possible to have a reliable count of the number of words. Any
> ideas
> > > or example code would be much appreciated.
> > >
> > > TIA
> > > Barry Brown
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58412On Tue, 22 Jul 2003 09:21:34 -0700, Peter Alfke <peter@xilinx.com> wrote: >Yes, you have to be paranoid. But there is no problem with crossing the >clock domain boundary using a Grey signal. To be more precise: there is no problem with crossing the clock domain boundary using a Gray signal, provided that the maximum routing skew is less than the period of the source clock. Regards, Allan.Article: 58413
"louis lin" <n2684172@ms17.hinet.net> news:bfflob$mbb@netnews.hinet.net... > > [ chop an example of `ifdef that would be trivial in the > > traditional C programming world, but strains the capabilities > > of Xilinx's Verilog tools] > > > > > I had to "touch" the test.v to force ISE to re-scan the relationship > > > among test.v, mode0_proc.v, and mode1_proc.v. However, I have to "touch" > > > so many files in different directories if these files all contained such > > > "ifdef"... Is there any other way to solve it? > > > > I gave up on letting ISE itself deal with `ifdef. Now I run > > all my Verilog through Icarus first (iverilog -E) using a Makefile, > > and only then sic ISE on the preprocessed output. I agree the > > real problem is in the dependency generator, the synthesizer > > itself probably gets things right. > > > > - Larry > > > What is "iverilog"? > I'd like to process the design using Makefile, but how? > Is there any reference or example? Thank you! > > I couldn't believe the bad performance of dependency gnerator of ISE. > I found the some files got the correct definition in `ifdef statement, > but some files got the old definition if I forgot to "touch" them... > > I built a makefile to "touch" corresponding files when header file was modified. However, this problm existed from ISE 4.2i to ISE 5.2. Can I report this problem to Xilinx? I applied the WebCase last week, and Xilinx replied that it will take one business day to process my applicaion. I It had been at least 5 business days already...Article: 58414
hi folks, I'm trying to convert a .bit file into an MCS file suitable for putting into a configuration PROM. I can do this just fine with the GUI, via the following path of steps Prepare Configuration Files -> PROM file -> Choose target (Serial PROM, MCS format etc) -> Add Device XC18V04 -> Add File (download.bit) -> Finish I can then download this file to the PROM, and it will configure the FPGA and so on. However, I want to automate this procedure into an iMPACT batch file. The doco is a bit obtuse on the subject - there are plenty of batch mode examples for configuring devices, but none I could find for generating PROM files. I've got this far: $ impact -batch >setmode -pff >setsubmode -pffserial >addpromdevice -p 1 -name xc18v04 However, if I now try to use assignfile, and give it the input bitfile: >assignfile -p 1 -file download.bit it bombs with a fatal error. I'm figuring I'm close, just need to (a) assign a bit file that goes into the prom file (b) generate the file There's the 'generate' command but that also bombs, presumably because I haven't properly assigned a bitfile yet. Can anyone point me in the right direction? Thanks, JohnArticle: 58415
Just remember nyquist - if you forget - metastability!!!!!!!!!! Andrew Paule Peter Alfke wrote: >You can use any type counter you can imagine, as long as read and write >counter sequences are identical. >In my suggestion, there is no Grey counter in the read domain, but there >are binary counters in both domains. That's why you "obviously"have to >use these. I have tried to simplify this design as much as possible. >As Albert Einstein once said: >Everything should be made as simple as possible, but not any simpler... > >Peter Alfke >==================== >Kevin Neilson wrote: > > >>"Peter Alfke" <peter@xilinx.com> wrote in message >>news:3F1C845E.49CD7A06@xilinx.com... >> >> >> >>>Obviously, you need to use the binary counters for addressing the >>>dual-port RAM. >>> >>>Peter Alfke, Xilinx >>>================= >>> >>> >>Why couldn't one address the RAM with Gray pointers? >>-Kevin >> >>Article: 58416
There are some papers available answering nearly all asynch FIFO questions: http://www.sunburst-design.com/papers/ Regards Ronald Barry Brown wrote: > I have designed a synchronous FIFO in the past, but now I need one with > asynchronous read and write clocks. It will be in a Virtex2, and I need to > keep a count of the number of words in the FIFO. I do not need the empty and > full indicators. I have the Xilinx app notes (175, 131), which say that it > is not possible to have a reliable count of the number of words. Any ideas > or example code would be much appreciated. > > TIA > Barry Brown > >Article: 58417
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F1D945B.FA696337@yahoo.com>... > "bijesh v.m." wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F1BEFFC.61ECA2DA@yahoo.com>... > > > "bijesh v.m." wrote: > > > > > > > > Hi all, > > > > > > > > Am new to fpga. I would like to know about QuickSwitch devices and > > > > whether they are ideal to interface fpga (3.3v) with devices with > > > > different (5v)logic levels.Please share your knowledge on the > > > > following questions. > > > > > > > > 1. Is it a good practice to use Quickswitch to interface (3.3v) > > > > spartan IIE fpga and (5v) logic devices? > > > > > > That is one way of dealing with 5 volt signals. Or you can use a 5 volt > > > tolerant FPGA in the first place. I am finding that the Altera ACEX > > > EP1K family is a good choice also and saves board space if you have a > > > lot of 5 volt signals to interface. > > > > > > > > > > 2. Is it a commonly used approch to use Quickswitch devices with > > > > fpga? If not so what are its disadvantages? > > > > > > The disadvantage is the extra board space. > > > > > > > 3. Is it a recent technology? > > > > > > No, series pass switches have been used for voltage shifting for years. > > > > > > > > > > From what I read and understood is that,Quickswitches operation is in > > > > effctive to connecting a small resistance in series between the two > > > > logoc levels. > > > > > > Not exactly. They are a variable resistance where the resistance > > > increases as the input voltage gets close to the Vdd voltage. This is > > > because a high input voltage reduces the drive voltage which turns off > > > the series pass transistor. So at lower voltage levels the switch is > > > low resistance and has nearly no delay. > > > > > > > I read about Quickswitch devices from the site > > > > http://www.idt.com/products/pages/Bus_Switches-QS316245.html. > > > > > > > > 4. At frequencies (say 50MHZ) whether the quickswitch devices will > > > > introduce significat delay? > > > > > > The delay is less than a nanoSecond. These switches are almost like a > > > wire. > > > > > > > > > > 5.I think bidirectional data flow capability of the quickswitch device > > > > is a very good feature( no need of additional data direction control > > > > signals)compared to other Transceiver chips (like 74LVX4245).Whats > > > > your thinking? > > > > > > It all depends on your application. For example, if you were adding a > > > bunch of IO ports to control 5 volt signals from a 3 volt device then > > > you could do better with a register since you can use a lot fewer pins > > > on the FPGA. Adding extra registers could share the data bus and would > > > only require adding control signals. > > > > > > Also keep in mind that the quick switch will not let the 3 volt device > > > *drive* to 5 volts if that is needed. To get a signal to 5 volts you > > > will need your low voltage driver to be open collector (drain) and a > > > pullup to 5 volts on the output side of the switch. This will be a bit > > > slower than a 5 volt, direct drive, totem pole output. > > > > > > -- > > > > > Hi Rick, > > I was planning to use Quickswitch to interface a 5v TTL > > microcontroller with Spartan IIE fpga in my design. From your replay > > what I understood is that I shoud select a open drain o/p pin in my > > fpga to tranfer a 5V I/P to the microcontroller. > > You wrote to point 5: > > "To get a signal to 5 volts you will need your low voltage driver to > > be open collector (drain) and a pullup to 5 volts on the output side > > of the switch" > > > > 1. This I think brings a contraint to my design and I would like to > > avoid this. Please suggest a good approch. > > If the 5 volt device uses TTL voltage levels (Vlow < 0.8 volts and Vhi > > 2.0 volts), then a 3.3 volt TTL level device driving a quick switch > powered from around 4.2 volts (as indicated in the IDT appnotes) will do > the job. But if you are driving a signal that needs to go above 3.3 > volts, this approach will not let you do that without the more complex > arrangement I described. > > > 2. I would like to know ( our comments :) ) why this issue was not > > mensioned in the Quickswitch site. I was misleaded or misunderstood by > > the block diagrams in the document which shows interfacing 3.3V CPU > > and 5V accessory devices ( application note > > http://www.idt.com/docs/AN_11.pdf"). > > The quickswitch appnote discusses interfacing between 5 volt TTL devices > and 3.3 volt TTL devices that are not 5 volt tolerant. This is useful > when the issue is protection from too high signal voltages. The > Quickswitch (or any other similar series pass switch) will not allow one > side to drive the other side above about 0.8 volts below the Vdd voltage > on the switch. But if you need to interface to a signal level that is > above that voltage (such as true 5 volt CMOS levels with a spec'd Vhi of > 3.5 volts or even 4.0 volts) then you must use a true voltage converter > or modify the design as I described. A quickswitch is not a signal > level converter. It is just a high voltage clamp. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX Hi Markus, Hi Rick, :) Both of You gave me good info on the subject. The bitter thing for me is that some of the pins in my microcontroller is "Schmitt Trigger input with CMOS levels" ( VIH Minimum of 3.5v ; the controller has TTL and CMOS input outputs). So I think it will not be suitable for me to use quickswitch.Thanks to both of you for the help. regards BijeshArticle: 58418
I am creating a new design in Quartus using VHDL. It has been a long time since I have used VHDL and so I am relearning a lot of the issues with the language. I have found a couple of cases where the Quartus compiler either flagged an error that had nothing to do with the problem in my source code or did not flag an error and produced wrong logic. The problem I am having now is that my design is not being synthesized fully or large parts are being optimized away. I have checked the generated equations as best I can and compared to my source and can not find a reason that this should be happening. I have a ticket open with support, but they have not even asked me for my code yet and I doubt that we will get much going until that happens. I started this post about 10 hours ago and had to leave before I finished. When I got back I continued working on the problem before I completed the message. I finally found the problem. Seems that if you have a mismatch in the size of the vectors in an assignment or comparison, the software does not complain, it just produces some bad logic. Mainly it takes out all the subsequent logic. Trying to sort through a design at the equation level and figure out what part is missing and what part remains is not a simple task. Anyway, if anyone else sees a similar problem where logic is not being synthesized in Quartus 3.0, look for a mismatched SLV size. When I hear back from Altera support, I'll see if they already know about this bug. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58419
Hello all, I'm using xsa100 (xc2s100) board with registered evaluation version of Xilinx ISE5. I'm a newbie to this. I'm following the instructions in the manual "Introduction to webpack 4.1 for FPGAs" downloaded from http://www.xess.com/appnotes/webpack-4_1-fpga.pdf. I've written a code in Verilog for leddec (7 segment display). Then I follow the steps written in the manual. For the step in manual "to constraining the Fit", I can not find "Edit implantation constraints (Constraint editor)" in the "User Constraints" process to assign the FPGA pins to my I/Os. But I find "Assign package pins" in the "User constraints" of ISE5. On clicking this, it says that there is no Implementation constraint file. I make a new one by Project<-New Sourse<-Implementation constraint file and add this to current project. Now "Assign package pins" works. I assign the I/O signals to the FPGA pins as written in the manual. Everthing is allright so far. But in the step of "viewing the chip", when I click "view/edit Placed design (Floor planner)", it shows me the CLB's and Inputs and output pads. But inpouts and outputs are not associated with CLB's. As I click CLB, it should show the I/Os associated with it in shape of arrows from CLB to all the I/Os. But This does not happen. Can anyone please help me telling me where is the error and how to remove it? One more question, at each step, ISE5 gives me the warning that its an evaluation version. Will this warning create a problem anywhere in the design on loading and testing it to FPGA? Sorry for bothering such a huge textl. Regards Atif Nadeem Research Associate Al-Khawarizmi Institute of Computer Science, University of Engineering & Tech., Lahore Pakistan, 54890Article: 58420
On Wed, 23 Jul 2003 04:01:10 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >I am creating a new design in Quartus using VHDL. It has been a long >time since I have used VHDL and so I am relearning a lot of the issues >with the language. I have found a couple of cases where the Quartus >compiler either flagged an error that had nothing to do with the problem >in my source code or did not flag an error and produced wrong logic. > >The problem I am having now is that my design is not being synthesized >fully or large parts are being optimized away. I have checked the >generated equations as best I can and compared to my source and can not >find a reason that this should be happening. > >I have a ticket open with support, but they have not even asked me for >my code yet and I doubt that we will get much going until that happens. > >I started this post about 10 hours ago and had to leave before I >finished. When I got back I continued working on the problem before I >completed the message. I finally found the problem. Seems that if you >have a mismatch in the size of the vectors in an assignment or >comparison, the software does not complain, it just produces some bad >logic. Mainly it takes out all the subsequent logic. Trying to sort >through a design at the equation level and figure out what part is >missing and what part remains is not a simple task. Your simulator would have picked up the error straight away during either compilation or elaboration. Did you simulate your design? Allan.Article: 58421
John, Try: promgen -help Cheers, Aurash John Williams wrote: > hi folks, > > I'm trying to convert a .bit file into an MCS file suitable for putting > into a configuration PROM. I can do this just fine with the GUI, via > the following path of steps > > Prepare Configuration Files -> > PROM file -> > Choose target (Serial PROM, MCS format etc) -> > Add Device XC18V04 -> > Add File (download.bit) -> Finish > > I can then download this file to the PROM, and it will configure the > FPGA and so on. > > However, I want to automate this procedure into an iMPACT batch file. > The doco is a bit obtuse on the subject - there are plenty of batch mode > examples for configuring devices, but none I could find for generating > PROM files. > > I've got this far: > > $ impact -batch > >setmode -pff > >setsubmode -pffserial > >addpromdevice -p 1 -name xc18v04 > > However, if I now try to use assignfile, and give it the input bitfile: > >assignfile -p 1 -file download.bit > > it bombs with a fatal error. > > I'm figuring I'm close, just need to > > (a) assign a bit file that goes into the prom file > (b) generate the file > > There's the 'generate' command but that also bombs, presumably because I > haven't properly assigned a bitfile yet. > > Can anyone point me in the right direction? > > Thanks, > > John -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 58422
Hi,
I am currently working on getting Linux booting on an Insight Virtex II
Pro reference board and have a boot loader coming in off SystemACE
setting up and booting Linux ok. The kernel itself is being debugged and
in particular I am having problems with the memory management side.
The trouble seems to be in a few quirks with the way this board is
designed which mean I have to enable cacheing very early on for all of
SDRAM in head_4xx.S as I set up TLB entries for our hardware and before
enabling the MMU, which seems to be running ok now.
Switching back to real mode causes a lot of problems at the moment -
start_kernel turns off the MMU to setup exception handlers and so on[0].
When this happens it does the usual rfi trick to switch IR|DR off in the
MSR and jump to the next instruction which generates a Machine Check.
This seems to be due to the way in which SDRAM is wired on the board and
I have heard mention that the early boards had tied byte enables which
meant that turning on the I and D caches early on was necessary and
indeed this proves successful in part with the rev. 3 board.
Having found this forum generally useful in the past I am wondering if
there happens to be someone here who is familiar with this board issue.
Jon.
[0] This can be handled differently as is the case with NetBSD but that
cures the symptom rather than addressing the cause of the problem.
Article: 58423Working with the Floorplanner tonight (5.2, latest service pack) I had the pleasant experience of having the software mangle my extensive UCF file for no good reason. All floorplanning constraints being used are area constraints except for hard locations for such things as multipliers and SelectRAM. Thankfully a culture of frequent backups saved the day (night) with a bit of work. This leads me to ask: Are there any undocumented gotcha's I should look out for? Also, is there a way to have Floorplanner write more sensible area constraints? Wildcards are allowed in the instance specification, but it doesn't seem to know how to use them. So, if I want to allocate an area to the "input_fifo*" instance I get 100 lines of "INST" specifications instead of a simple: INST "input_fifo*" AREA_GROUP = "grp_input_fifo"; Is there a way to convince it to do it right? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 58424
"Ray Andraka" <ray@andraka.com> wrote: > The automatic placment algorithms, while better than in the past, still suck. I > do a large amount of explicit placement using a structural hierarchy. The > relative placements (in the form of RLOCs) are in the code, and these are built > up hierarchically. Some examples of the floorplans can be seen on the gallery > page of my website (thanks Phil Freidin for that idea). Could I bother you to provide an example of how to do this? Are you saying that you locate placement constraints within the HDL modules themselves? How exactly are they "built up hierarchically"? I searched Google for a post from Phil Freidin on the subject but failed to locate anything applicable. Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
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