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John wrote: > > Hey Rickman, > > In article <3F0AE7CC.68F9D9D0@yahoo.com>, spamgoeshere4@yahoo.com > says... > > I need to vent a little steam. So at risk of making myself look stupid > > (or more stupid) I will do it here. > > > > I have been trying to get the Quartus 3.0 software and a license since > > last Thursday. I tried three times over the weekend to download it, but > > the slow modem link I have to use would not complete the entire transfer > > without a problem. I think I have that licked as my brother tells me he > > has downloaded it for me. > > You might want to look into a *great* utility called "wget". > > It's probably comes standard on every modern FreeBSD/Linux > implementation, but not many people in the Windows world know about > it... > > See this for a command-line vanilla Windows version: > > http://space.tin.it/computer/hherold/ > > and see this for a Visual Basic GUI wrap-around: > > http://www.jensroesner.de/wgetgui/ > > If you use the plain-vanilla command-line version, just launch like > this: > > wget -c <url> > > -c tells it to continue if a download is aborted...this way if your > modem drops, when you re-connect, just re-issue wget -c <url> and it'll > continue where the file was chopped off. Yes, I very much should use a program like that. In the past I have preferred not to add more and more utilities to do a job. Often it can cause problems which are hard to pinpoint. But I think this is one case where it is well worth the effort. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57901
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3F0AE7CC.68F9D9D0@yahoo.com... > > > I have been trying to get the Quartus 3.0 software and a license since > > last Thursday. I tried three times over the weekend to download it, but > > the slow modem link I have to use would not complete the entire transfer > > without a problem. I think I have that licked as my brother tells me he > > has downloaded it for me. > > Get a download manager like Gozilla or something. The can resume a aboarded > download. My concern is that once installed, I will have no way to control it if I don't want to use it for some files. I remember Netscape adding something like this (or I added some download, I can't remember which). There were times I did not want it to pop up and could not find a way to turn it off. It also showed ads while running. Anyone know of a review of download utilities that would help me pick one? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57902
Sure, I have an architecture for the design_unit entity. Otherwise the compiler wouldn't compile it. Thanks. Liang "z.karim" <z.karim@comcast.net> wrote in message news:7eVOa.14181$OZ2.2551@rwcrnsc54... > Hi, > > There doesn't seem to be an architecture associated with > your DESIGN_UNIT entity. > > > "Liang Yang" <yangliang_mr@hotmail.com> wrote in message > news:befnvc$4bc$1@news.asu.edu... > > Hi , > > > > Thanks for your reply. > > > > I even tried to initialize this inout port to all 0, but it still shows > "UU" > > when I start simulation. During pre-synthesis simulation, > > the initial value of DATA is also "UU", but it changes to correct value > > after assignment take effect in the test bench. > > > > I try to figure out which one is driving this DATA port when its value > > is changed. But I don't know how to do this in Active HDL. The break point > > is located in the lsi_10k library and I can't trace it until the program > > control > > comes back to my program. > > > > Thanks. > > > > Liang > > > > > > Here is my code: > > --design.vhd > > library lsi_10k; > > use lsi_10k.all; > > ... > > entity DESIGN_UNIT is > > > > port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...); > > > > end DESIGN_UNIT; > > > > --testbench.vhd > > entity test_bench is > > end entity test_bench; > > > > architecture behav of test_bench is > > signal DATA: std_logic_vector(7 downto 0); > > signal Clock: bit :='0'; > > ... > > begin > > DUT: entity DESIGN_UNIT > > port map(DATA, ctl_data, ctl_op, Reset, Clock); > > > > simulation: process is > > begin > > clock <= '0'; > > wait for 20 ns; > > > > DATA <= "00000001"; > > Clock <= '1'; > > wait for 20 ns; -- DATA port will become "XX" at 20+1 ns > > > > wait; > > end process; > > end architecture behav; > > > > "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message > > news:3F0AF3F7.3010105@flukenetworks.com... > > > Mike wrote: > > > > > > > I declared a std_logic_vector(7 downto 0) (inout type) entity port > > > > in my VHDL program. In the testbench, I will try > > > > to assign some value to this port. But after synthesis > > > > using Synopsys Design Compiler, I found this port wouldn't > > > > accept the value from signal assignment in the test bench > > > > and the value of this port becomes "XX". > > > > > > > > > Post your code. Your output enable logic is likely the problem. > > > > > > -- Mike Treseler > > > > > > > > >Article: 57903
> ISE is just the GUI front end for the tools, it's not the important part > of the Xilinx tool suite. As you may have read in one of my prior posts, we use the Alliance tool set. Preaching about what the tools are is no value to me. We have been using them for years. So this is no value. > was rewritten for the 5.x release. The 6.x release is going to be 64 bit > as well as supporting native Linux, so that means that every important I would rather them stay focused on making a better product under MS than remove resources to work on LINUX and possibly add more problems for themselves. Just my preference. I guess all the major tool people are porting their code anyway so we will see. Nothing to do with the original posting, but fun to talk about. > I'm not talking for Xilinx, but I do talk to them all the time. I'm sure most of us do. > moment to drop Mac support. The same thing goes for Xilinx and Spartans. > No one is doing new designs with the original Spartan family, so it's not > worth Xilinx spending any money putting in support for Spartans in their > new tool sets. If the code were structured, supporting the older devices would not be a problem. > The old tools are completely adequate for doing anything > that you need to do with a Spartan. Agree, but again, they drive different and have their own bugs that you need to remember. > Just because there is a new better > faster tool set available doesn't mean that the old stuff has suddenly > vanished from the face of the earth. No value. > Disk space is cheap, you can have as > many versions of the tools as you want on a system, all you have to do to > switch between one rev and another is change an environment variable. Again, does not help the original problem. > All software has bugs and x.0 software has lots of bugs. Disagree. > Xilinx is > actually better than most but whenever they add a new family or do a major > rewrite there are bugs. I did an Altera Stratix design last year and every > piece of software in their design chain was broken, starting with the > Verilog models which wouldn't even compile. I've never had that level of > problems with Xilinx but I've certainly encountered my share of bugs in > their stuff over the years. Have used Altera for seven years or so and have had good results. > My point is that the support for an old part in a new tool wouldn't be any > better than the initial beta release of a new part. If they don't address known bugs that would be the case. > The difference being > is that with a new part lots of people are using it so that the software > bugs get found and fixed. With the obsolete part there will be hardly > anyone using it so the bugs aren't going to get found, the fixes aren't > going to get made, and the software quality will be beta forever. No value. > With the > tool set that existed at the end of the parts mainstream life the software > was mature. You benefit from the years of cumulative bug fixes that had been > applied, that's the stuff you want to be using if you have to make a > change to an old part. Thanks to Xilinx, this is the way you have to operate. So again, your not saying anything of value. > As I said before my experience with Altera has been much worse then with > Xilinx. I would have to say my experience has been a wash between the two. > The kind of bugs that I encountered with the Altera tool set > indicated that they hadn't done any QA at all. Sounds like some of the problems I find with Xilinx. Even you yourself just posted about all the bugs you seem to find in the Xilinx tools. It's bad when they know the bugs are there and don't have the resources to address them on a major release.Article: 57904
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F0C25FB.7BC1C0C9@yahoo.com... > Falk Brunner wrote: > > > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > > news:3F0AE7CC.68F9D9D0@yahoo.com... > > > > > I have been trying to get the Quartus 3.0 software and a license since > > > last Thursday. I tried three times over the weekend to download it, but > > > the slow modem link I have to use would not complete the entire transfer > > > without a problem. I think I have that licked as my brother tells me he > > > has downloaded it for me. > > > > Get a download manager like Gozilla or something. The can resume a aboarded > > download. > > My concern is that once installed, I will have no way to control it if I > don't want to use it for some files. I remember Netscape adding > something like this (or I added some download, I can't remember which). > There were times I did not want it to pop up and could not find a way to > turn it off. It also showed ads while running. > > Anyone know of a review of download utilities that would help me pick > one? I've tried two or three and now use Download Accelerator Plus. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 57905
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<bef5qm$bq9$1@news.tu-darmstadt.de>...
> Udayan <udayan@jhu.edu> wrote:
> : Hi,
>
> : I am having trouble with the GCLK feature in my design.
>
> : Basically my code is a 4 way handshaking protocol between my PC and
> : the FPGA on one hand and another 4 way handshaking with an
> : asynchronous chip on the other.
>
> : I am providing a clock to the system through the GCLK0 pin using an
> : oscilltor.
>
> : I further require edge tests on three lines that I receive from the
> : computer and the chip - which means they are inferred as clock
> : signals.
>
> : A total of 4 clocks.
>
> : However when I try to implement the design the engine complains that
> : my design is too large
>
> : Number of GCLKs: 6 out of 4 150%
> : Number of GCLKIOBs: 1 out of 4 25%
>
> : I cannot understand why this is so. I take the input from my CLKIOB
>
> Look at the synthesis report (*.syr) and at the graphical representation of
> your circuit ("View RTL Schematics"). It will give you a glimpse of what is
> going on. Then rethink the way you wrote your HDL implementation. In the
> synthesis report, the "Clock information" might be the most important
> thingto look at.
>
> Bye
SO I checked my design and removed the extra BUFG that was getting
tagged to my divided clock output. However, since I would like to
buffer my divided clock and the Synthesis engine automatically
attaches a BUFG to the GCLKIOB pin input I am still left with one
extra GCLK in my design being used up. Is there some way to get around
that? Would a divide using the clk_dll still use up the extra GCLK
resource?
Also when I do an edge test with my signal lines that arrive at
regular IOBs and pass them through a BUFG the MAP report gives a
warning that:
WARNING:NgdBuild:483 - Attribute "LOC" on "c_req" is on the wrong type
of
object. Please see the "Attributes, Constraints, and Carry Logic"
section of
the Libraries Guide for more information on this attribute.
What does this mean? I have tried looking up the Libraries Guide but
without success.
Thanks
Article: 57906Udayan <udayan@jhu.edu> wrote: ... : SO I checked my design and removed the extra BUFG that was getting : tagged to my divided clock output. However, since I would like to : buffer my divided clock and the Synthesis engine automatically : attaches a BUFG to the GCLKIOB pin input I am still left with one : extra GCLK in my design being used up. Is there some way to get around : that? Can't you use a Clock Enable and the original clock instead of the divided clock? : Would a divide using the clk_dll still use up the extra GCLK : resource? The DLL output will use a GCLK too, to my knowledge. : Also when I do an edge test with my signal lines that arrive at : regular IOBs and pass them through a BUFG the MAP report gives a : warning that: : WARNING:NgdBuild:483 - Attribute "LOC" on "c_req" is on the wrong type : of : object. Please see the "Attributes, Constraints, and Carry Logic" : section of : the Libraries Guide for more information on this attribute. : What does this mean? I have tried looking up the Libraries Guide but : without success. Perhaps you have an Output pin on a dedicated input or such. Recheck with the data sheet. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57907
Leon Heller wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F0C25FB.7BC1C0C9@yahoo.com... > > Falk Brunner wrote: > > > > > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > > > news:3F0AE7CC.68F9D9D0@yahoo.com... > > > > > > > I have been trying to get the Quartus 3.0 software and a license since > > > > last Thursday. I tried three times over the weekend to download it, > but > > > > the slow modem link I have to use would not complete the entire > transfer > > > > without a problem. I think I have that licked as my brother tells me > he > > > > has downloaded it for me. > > > > > > Get a download manager like Gozilla or something. The can resume a > aboarded > > > download. > > > > My concern is that once installed, I will have no way to control it if I > > don't want to use it for some files. I remember Netscape adding > > something like this (or I added some download, I can't remember which). > > There were times I did not want it to pop up and could not find a way to > > turn it off. It also showed ads while running. > > > > Anyone know of a review of download utilities that would help me pick > > one? > > I've tried two or three and now use Download Accelerator Plus. Thanks, I'll look at it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57908
Hi, I have been using Quartus II 2.0 for all my synthesis and fitting needs for the APEX20KE device I have on my prototype board. I hear that Quartus is not an efficient synthesizer compared to Synplicity's Synplify. Now, I have had trouble trying to fit my design on the FPGA and I have tried various methods to achieve successful fits (Logiclock, design change, etc.). Would there be a discernible advantage (in terms of achieving the required performance and fitting the design on the device) to using Synplify for synthesis and then using Quartus II 2.0 for placement and routing ? Can this process really solve my fitting problems ? Thanks, PrashantArticle: 57909
Udayan, Maybe you should try a different approach, like: state machine, with the running CLK some times faster than you fastest input signal, and be careful to add 2 (3) registers in the pipe for the inputs. only an idea... (depending how fast you want/need to sample) Aurash Udayan wrote: > Hi, > > I am having trouble with the GCLK feature in my design. > > Basically my code is a 4 way handshaking protocol between my PC and > the FPGA on one hand and another 4 way handshaking with an > asynchronous chip on the other. > > I am providing a clock to the system through the GCLK0 pin using an > oscilltor. > > I further require edge tests on three lines that I receive from the > computer and the chip - which means they are inferred as clock > signals. > > A total of 4 clocks. > > However when I try to implement the design the engine complains that > my design is too large > > Number of GCLKs: 6 out of 4 150% > Number of GCLKIOBs: 1 out of 4 25% > > I cannot understand why this is so. I take the input from my CLKIOB > and pass it through a clock divide routine that I wrote and use that > signal as my global clock. The rest of the three lines go through > BUFGs befor entering the design. > I would loke to pass my divided clock through a BUFG so that it does > not suffer from skew. > > To see what the problem might be I implemented another design which > has only one clock - the global clock that I divide and pass through a > BUFG but still the engine reports > > Number of GCLKs: 3 out of 4 75% > Number of GCLKIOBs: 1 out of 4 25% > > I was not clear on how this inference is taking place - possibly > because of IOB placements that are hardwired and result from clock > test or bad clock management. > > Could someone advice on how to remedy the situation. Would a Clkdll > help? I am not very clear on how it will solve the problem with the > multiple clock lines or even how it broadly works. > > Thanks > > Udayan --Article: 57910
Hi Fellows, How can I synthesize multiple file one by one using xilinx compiler in MAKEFILE script. I have done using only one file but when I enter multiple files in "VHDL= ....." field thenI get the following error. make: *** No rule to make target `VIR3.vhd,VIR3_1.vhd,VIR3_2.vhd Rgds MACEIArticle: 57911
Hello everybody, I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of calculation of a signal to be used in second architecture. Can any one tell how to defined signal so that it is globally visible to other architectures. Regards KhanArticle: 57912
Yes ALLAN I am Sure I am using different bits E.g This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7 process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int) begin if RISING_EDGE(CLK_2X) then if SR_IVCS_V3_int = '0' then if SR_IWR_int = '0' then if SR_ADDR_IO_int = "001100" then LED_V3_int <= SR_DATA_IO_int(13 downto 7); end if; end if; end if; end if; end process P_SRAM2LED;Article: 57913
Muhammad Khan wrote:
> I want to use the signal defined in one architecture in VHDL to
> another architecture. I have two architecture in the same .vhd file
> and I am using Component mapping. I required the result of calculation
> of a signal to be used in second architecture. Can any one tell how to
> defined signal so that it is globally visible to other architectures.
Hello Muhammad,
this is a common question.
The clean way for handling this is to feed the signal through
the port maps.
Regards,
Mario
--
----------------------------------------------------------------------
Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
Mario.Trams@wooden-technology.de
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------
Article: 57914Sorry I meant LONG division not LOG hope this helps "Mario Trams" <mtr@informatik.tu-chemnitz.de> wrote in message news:bea7c6$g5a$3@anderson.hrz.tu-chemnitz.de... > Replace_latter8717_with_manorsway wrote: > > > remember log division from schoool, now try that in base 2! > > Yes. > And then develop a hardware design that can do that... > > When this is done, it's a small step to describe it in VHDL. > > Regards, > Mario > > > > > "Ketan" <ketone007sa@yahoo.com> wrote in message > > news:cf47f3cc.0307042130.1eec1888@posting.google.com... > >> hello there > >> i am relatively new to VHDL..this might sound simple > >> any ideas how to carry out division (floating point) in VHDL?? > > -- > ---------------------------------------------------------------------- > Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de > Mario.Trams@wooden-technology.de > Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr > Dept. of Computer Science Tel.: (+49) 371 531 1660 > Chair of Computer Architecture Fax.: (+49) 371 531 1818 > ----------------------------------------------------------------------Article: 57915
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<behcjc$stq$1@news.tu-darmstadt.de>... > Udayan <udayan@jhu.edu> wrote: > ... > : SO I checked my design and removed the extra BUFG that was getting > : tagged to my divided clock output. However, since I would like to > : buffer my divided clock and the Synthesis engine automatically > : attaches a BUFG to the GCLKIOB pin input I am still left with one > : extra GCLK in my design being used up. Is there some way to get around > : that? > > Can't you use a Clock Enable and the original clock instead of the divided > clock? > > : Would a divide using the clk_dll still use up the extra GCLK > : resource? > > The DLL output will use a GCLK too, to my knowledge. > > : Also when I do an edge test with my signal lines that arrive at > : regular IOBs and pass them through a BUFG the MAP report gives a > : warning that: > > : WARNING:NgdBuild:483 - Attribute "LOC" on "c_req" is on the wrong type > : of > : object. Please see the "Attributes, Constraints, and Carry Logic" > : section of > : the Libraries Guide for more information on this attribute. > > : What does this mean? I have tried looking up the Libraries Guide but > : without success. > > Perhaps you have an Output pin on a dedicated input or such. Recheck with > the data sheet. > > Bye Hi Uwe, I sorted the GCLK problem out. Apparently if you use a clkdll it does not put a BUFG in front but an IBUFG and only the locked signal passes through a BUFG. That way the synthesizer does not infer a GCLK item for the input. Still having trouble with the IOB warnings though....SOmehow the synthesiser has now concluded that they are GCLKIOBs but since they are not on the pins assigned for GCLKIOBs they are probably causing the trouble. If you feel inspired and find an answer to my present query drop me a line. Thanks UdayanArticle: 57916
"Mancini Stéphane" <stephane.mancini@inpg.fr> wrote in message news:<pan.2003.07.09.11.21.27.470621@inpg.fr>... > Hi, > I've just had a look at marshall's (avnet) web site and it seems that > the Xilinx Virtex II XC2VP100 is $11512. > Did I miss something or lost some zeroes ? Is it that kind of price ? > Thanks a lot for your comments > > Stéphane Hi Stephane, No error there, thats a pretty normal price for a one off of the top of the range Virtex II Pro at the fastest speed grade. The good news is that the prices come down rapidly over a short time (we use XC2V6000's which have come down from £5k to £1k over a few months) Drop a speed grade or increase the volumes a bit and the prices plummet, too. MelArticle: 57917
Liang Yang wrote:
> I even tried to initialize this inout port to all 0, but it still shows "UU"
> when I start simulation. During pre-synthesis simulation,
> the initial value of DATA is also "UU", but it changes to correct value
> after assignment take effect in the test bench.
Initialization has no effect for synthesis code.
A bidirectional interface requires signals and controls
for access and data direction. See the example below.
> I try to figure out which one is driving this DATA port when its value
> is changed. But I don't know how to do this in Active HDL. The break point
> is located in the lsi_10k library and I can't trace it until the program
> control
Tracing code is not very effective at solving system level problems.
-- Mike Treseler
-------------------------------------------------------------------------------
-- Testbench Example for bidirectional port.
-- oe_demo.vhd
-- Wed Jul 9 12:13:53 2003 Mike Treseler
-------------------------------------------------------------------------------
---- Modelsim commands
-- 1. TEXT ASSERTIONS:
-- vsim -c test_oe_demo -do "run -all; exit"
-- 2. DEBUG WAVES
-- vsim test_oe_demo -do "add wave *;add wave /test_oe_demo/simulation/*;run -all"
-- Note: By specifying the process name, you get the variables ^^^^
-------------------------------------------------------------------------------
library ieee; -----------------------------------------------------------------
use ieee.std_logic_1164.all;
package oe_demo_package is
-- Shared constants go here:
subtype reg is std_logic_vector (7 downto 0);
constant dummy_reg : reg := x"3e";
constant dummy_dat : reg := x"81";
constant active : std_ulogic := '1';
constant clk_period : time := 40 ns;
constant rst_period : time := 2*clk_period;
constant sim_limit : time := 100 us;
end package oe_demo_package;
library ieee; -----------------------------------------------------------------
use ieee.std_logic_1164.all;
use work.oe_demo_package.all;
-- Simplified Device Under Test
entity oe_demo is
port
( reset : in std_ulogic;
clock : in std_ulogic;
data : inout std_logic_vector (7 downto 0);
ready : out std_ulogic;
oe : in std_ulogic );
end oe_demo;
architecture synth of oe_demo is
begin
bidir : process (clock, reset) is
begin -- process bidir
clked : if reset = active then
data <= (others => 'Z');
ready <= not active;
elsif rising_edge(clock) then
enable : if oe = active then
data <= dummy_reg;
ready <= active;
else
data <= (others => 'Z');
ready <= not active;
end if enable;
end if clked;
end process bidir;
end architecture synth;
library ieee; -----------------------------------------------------------------
use ieee.std_logic_1164.all;
use work.oe_demo_package.all;
-- Testbench
entity test_oe_demo is
end entity test_oe_demo;
architecture sim of test_oe_demo is
-- Testbench wires go here
signal reset_sim : std_ulogic; -- [in]
signal clock_sim : std_ulogic; -- [in]
signal data_sim : std_logic_vector (7 downto 0); -- [inout]
signal ready_sim : std_ulogic; -- [in]
signal oe_sim : std_ulogic; -- [in]
signal we_sim : std_ulogic;
shared variable done_sim : boolean := false;
begin
-- Device under test instance
oe_demo_1 : entity work.oe_demo
port map (reset => reset_sim, -- [in]
clock => clock_sim, -- [in]
data => data_sim, -- [inout]
ready => ready_sim, -- [out]
oe => oe_sim); -- [in]
-- clock and reset generator
tb_clk : process is
begin
done : if now > sim_limit or done_sim then
wait;
end if done;
rst : if now < rst_period then
reset_sim <= active;
else
reset_sim <= not active;
end if rst;
clock_sim <= '0';
wait for clk_period/2;
clock_sim <= '1';
wait for clk_period/2;
end process tb_clk;
simulation : process (clock_sim, reset_sim) is
type op_t is (idle, get, put);
type script_t is array (1 to 9) of op_t;
constant script : script_t :=
(1 => idle,
2 => get,
3 => idle,
4 => idle,
5 => put,
others => idle);
variable step : natural;
variable op_now : op_t;
begin -- process bidir
clked : if reset_sim = active then
report("reset " & std_ulogic'image(reset_sim));
step := 1;
oe_sim <= not active;
we_sim <= not active;
data_sim <= (others => 'Z');
oe_sim <= not active;
elsif rising_edge(clock_sim) then
done_sim := step > script'length;
enable : if not done_sim then
op_now := script(step);
report("op " & op_t'image(op_now) );
stim: case op_now is
when idle =>
we_sim <= not active;
oe_sim <= not active;
data_sim <= (reg'range => 'Z');
when get =>
we_sim <= not active;
oe_sim <= active;
data_sim <= (reg'range => 'Z');
when put =>
we_sim <= active;
oe_sim <= not active;
data_sim <= dummy_dat;
when others =>
oe_sim <= not active;
data_sim <= (reg'range => 'Z');
end case stim;
ck_write: if we_sim = active then
report(time'image(now)&
" Should have no Error assertions below " &
" ###### Write test ######");
assert data_sim = dummy_dat;
end if ck_write;
ck_read: if ready_sim = active then
report(time'image(now)&
" Should have no Error assertions below " &
" ###### Read test ######");
assert data_sim = dummy_dat;
-- assert data_sim = dummy_reg; -- uncomment to force error
end if ck_read;
step := step + 1; -- step counter
end if enable;
end if clked;
end process simulation;
end architecture sim;
-------------------------------------------------------------------------------
Liang Yang wrote:
> Hi ,
>
> Thanks for your reply.
>
> I even tried to initialize this inout port to all 0, but it still shows "UU"
> when I start simulation. During pre-synthesis simulation,
> the initial value of DATA is also "UU", but it changes to correct value
> after assignment take effect in the test bench.
>
> I try to figure out which one is driving this DATA port when its value
> is changed. But I don't know how to do this in Active HDL. The break point
> is located in the lsi_10k library and I can't trace it until the program
> control
> comes back to my program.
>
> Thanks.
>
> Liang
>
>
> Here is my code:
> --design.vhd
> library lsi_10k;
> use lsi_10k.all;
> ...
> entity DESIGN_UNIT is
>
> port( DATA : inout std_logic_vector (7 downto 0) := "ZZZZZZZZ"; ...);
>
> end DESIGN_UNIT;
>
> --testbench.vhd
> entity test_bench is
> end entity test_bench;
>
> architecture behav of test_bench is
> signal DATA: std_logic_vector(7 downto 0);
> signal Clock: bit :='0';
> ...
> begin
> DUT: entity DESIGN_UNIT
> port map(DATA, ctl_data, ctl_op, Reset, Clock);
>
> simulation: process is
> begin
> clock <= '0';
> wait for 20 ns;
>
> DATA <= "00000001";
> Clock <= '1';
> wait for 20 ns; -- DATA port will become "XX" at 20+1 ns
>
> wait;
> end process;
> end architecture behav;
>
> "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
> news:3F0AF3F7.3010105@flukenetworks.com...
>
>>Mike wrote:
>>
>>
>>>I declared a std_logic_vector(7 downto 0) (inout type) entity port
>>>in my VHDL program. In the testbench, I will try
>>>to assign some value to this port. But after synthesis
>>>using Synopsys Design Compiler, I found this port wouldn't
>>>accept the value from signal assignment in the test bench
>>>and the value of this port becomes "XX".
>>
>>
>>Post your code. Your output enable logic is likely the problem.
>>
>> -- Mike Treseler
>>
>
>
>
Article: 57918Hi Khan, If you declare a signal in a package and you include the package then the signal can be globally used by all architectures that reference that package. This is for simulation only and will not work for synthesis. Jon kalimuddin@hotmail.com (Muhammad Khan) wrote in message news:<7d350237.0307090951.775cbfe9@posting.google.com>... > Hello everybody, > > I want to use the signal defined in one architecture in VHDL to > another architecture. I have two architecture in the same .vhd file > and I am using Component mapping. I required the result of calculation > of a signal to be used in second architecture. Can any one tell how to > defined signal so that it is globally visible to other architectures. > > Regards > > KhanArticle: 57919
Prashant wrote: > I have been using Quartus II 2.0 for all my synthesis and fitting > needs for the APEX20KE device I have on my prototype board. I hear > that Quartus is not an efficient synthesizer compared to Synplicity's > Synplify. That used to be true, but the recent releases are much improved. However, I have not run any benchmarks. > Now, I have had trouble trying to fit my design on the FPGA > and I have tried various methods to achieve successful fits > (Logiclock, design change, etc.). > > Would there be a discernible advantage (in terms of achieving the > required performance and fitting the design on the device) to using > Synplify for synthesis and then using Quartus II 2.0 for placement and > routing ? Can this process really solve my fitting problems ? It might. That used to be the only option. You are in a good position to call an FAE from Mentor or Synplify and let him prove to you that their brand is better than Q. I expect that you could get lots of help with your demo synthesis runs. Let us know how it comes out. -- Mike TreselerArticle: 57920
"Replace_latter8717_with_manorsway" <david@latter8717.freeserve.co.uk> wrote in message news:behtt2$j78$1@newsg1.svr.pol.co.uk... > Sorry I meant LONG division not LOG For a few seconds I considered that you meant subtracting logs to do division. But then I figured it out. I don't think subtracting logs and then antilog is likely to be a very good way in FPGA. -- glenArticle: 57921
The JEDEC standard name for "Jam" is "STAPL". If you download the very latest Altera STAPL interpreter, it will support JEDEC standard STAPL files without issue Earlier versions only supported Altera proprietary formats. Antti Lukats wrote: >christoph.grundner@agfa.com (Christoph Grundner) wrote in message news:<8a172a75.0307030527.40c28b2d@posting.google.com>... > > >>Hi there >> >>i'm currently trying to configure Alteras JAM Player for a Mitsubishi >>M16 Controller to program multi vendor device JTAG chains. Input files >>are either *.jam (JAM file) or *.jbc (JAM-ByteCode file). >>Is there a (preferably free) Xilinx tool to produce either one of >>these file types? Where can i download the tool? >> >> > >impact generates JAM files, well called STAPL but it is the same thing. >there are some problems though most of the files generates will not >work with non-patched JAM player :( > >antti > >Article: 57922
If you are programming the Spartan2 device after the xc18v01 has been configured then the initiation of the boundary-scan configuration of the Spartan2 (program -p 2) also initiates configuration of the Spartan2 from the xc18v01and results in a configuration data conflict within the Spartan2. There are several ways to work around this problem either one of which should work (a) erase the PROM before configuring the Spartan2 (b) set the mode pins on the Spartan2 device to boundary-scan mode (c) set the preference (Edit->Preferences) to Use HIGHZ instead of BYPASS (d) generate an mcs file from the bit file and configure the PROM only Jimy wrote: >HI, > I have a Avnet Spartan2 board, if I download the the .mcs (prom >file) comming with the board to it, it seems everything is OK. Then I >build my design, went through the implementation flow, and I run a >script to run impact.exe, > >setMode -bscan >setCable -p lpt1 >addDevice -p 1 -part xc18v01 >addDevice -p 2 -file download.bit >program -p 2 >quit > > > but what I see is at the end of its running is like this, > > >'2':Programming device...done. >INFO:iMPACT:579 - '2': Completed downloading bit file to device. >INFO:iMPACT:580 - '2':Checking done pin ....done. >'2': Programming terminated, Done did not go high. >---------------------------------------------------------------------- >---------------------------------------------------------------------- >Done. > > > > Do you know what might be the problem? Note that I have the same P4 >download cable, JTAG cable and power supply. > >Thanks, >Jim > > > > >Article: 57923
In the 'sixties, the Wang calculators ( with Nixie-tube read-out) did just that. I think they used a very efficient algorithm for log and antilog Peter Alfke ============ Glen Herrmannsfeldt wrote: > > "Replace_latter8717_with_manorsway" <david@latter8717.freeserve.co.uk> wrote > in message news:behtt2$j78$1@newsg1.svr.pol.co.uk... > > Sorry I meant LONG division not LOG > > For a few seconds I considered that you meant subtracting logs to do > division. But then I figured it out. I don't think subtracting logs and > then antilog is likely to be a very good way in FPGA. > > -- glenArticle: 57924
Hi,
I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm
developing under Xilinx ISE 5. I'm wondering what would be the simplest JTAG
cable I could build (or buy if real cheap) to download my code in the PROM.
Is any JTAG cable supposed to do the job? The fact is I already a very
simple JTAG interface (with a 74HC244 buffer for parallel port)...I tried it
but it didn't work.
Thanks
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