Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, Please check VHDL FAQ. Xilinix Webpack with Modelsim, SympanyEDA are few to name. HTH, Ajeetha http://www.noveldv.com a <a@a.com> wrote in message news:<beukeb$aql1@noticias.madritel.es>... > adarsh arora escribió: > > can u tell me from where i will get free downloadable softwares for > > VHDL/verilog simulation and synthesis , SPICE ,IC Station...... with > > free licences. > > waiting for ur help > http://ghdl.free.frArticle: 58101
rickman wrote: > > Alan Fitch wrote: > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3F0F337C.27A8ED76@yahoo.com... > > <snip> > > > -- VERSION 1 > > > -- These lines work correctly > > > -- Data (15 downto 8) <= (others => '0') WHEN (ReadScratchReg = > > '1') > > > -- ELSE (others => 'Z'); > > > -- Data (7 downto 0) <= ScratchReg WHEN (ReadScratchReg = '1') > > > -- ELSE (others => 'Z'); > > > > > > -- VERSION 2 > > > -- This line fails by disabling the tristate buffers > > > -- Data <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > > > ScratchReg WHEN (ReadScratchReg = '1') > > > -- ELSE (others => 'Z'); > > > -- The difference seems to be the use of the type cast. > > > -- Using a type cast with the (others => aggregate seems to fail in > > > other cases as well. > > > > > > -- VERSION 3 > > > -- This version produces open drain outputs > > > Data <= DataOut WHEN (ReadScratchReg = '1') > > > ELSE (others => 'Z'); > > > -- This seems to work ok > > > -- DataOut <= "00000000" & ScratchReg; > > > -- This produces no register and open drain drivers > > > DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > > > ScratchReg; > > > > > > > Hallo Rick, > > just out of curiosity, have you tried using a named > > subtype? > > E.g. > > > > architecture... > > subtype vec8 is std_logic_vector(7 downto 0); > > begin > > > > ... > > > > -- VERSION 3 > > -- This version produces open drain outputs > > Data <= DataOut WHEN (ReadScratchReg = '1') > > ELSE (others => 'Z'); > > -- This seems to work ok > > -- DataOut <= "00000000" & ScratchReg; > > -- This produces no register and open drain drivers > > DataOut <= Vec8'(others => '0') & ScratchReg; > > > > I wondered if Quartus is getting confused by the (15 downto 8) slice? > > > > The reason I'm asking is that by using STD_LOGIC_VECTOR(15 downto 8) > > you create an anonymous subtype, and I know that anonymous subtypes > > are not always allowed where named subtypes are allowed. For instance, > > it's illegal to declare a function returning an anonymous subtype, > > but it's OK with a named subtype. > > > > regards > > > > Alan > > Alan, yes, that worked. Is this a bug that I should report to Altera? > Or is this to be expected in VHDL? To answer my own question, I heard back from Altera today that it is invalid syntax under VHDL, but not providing an error message is an Altera bug. So they should be telling me to not use this syntax and I need to use a named type here. The actual illegal syntax is the range in the type cast. Is that what you meant be anonymous subtype? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58102
Jun wrote: > But I don't see any difference between > sampling data with a 9.5 ns delayed memory clock and with a 2.5 ns > delayed DQS? If the data is coming every 5 ns, and timing uncertainty is larger than 5 ns, there is no position for the sampling clock that can collect the data. The DQS, however, will have a delay that mostly tracks the data delay. Once the data is sampled into TWO flipflops by both edges of DQS, it is now coming every 10 ns, twice as wide and half as fast, and the sampling clock can collect the data as long as the accumulated timing uncertainty is smaller than 10 ns, twice as long as in the case of not using the DQS as a clock. -- Phil HaysArticle: 58103
I was thinking in using a external SPI memory to store the CPLD program. The problem is that I am afraid that also the CPLD programming algorithm can not suit in a PIC, am I correct? anyone have tryed? Thanks in advanced, Javier ben@ben.com (Ben Jackson) wrote in message news:<P0EQa.61426$H17.19423@sccrnsc02>... > In article <c10cd8da.0307140345.f0999e@posting.google.com>, > javid <javodv@yahoo.es> wrote: > > > >I was wondering if it is possible to program a PLD/CPLD via a PIC > >(without connecting external memory). The PIC I am using has a > >internal RAM of 768 bytes and 16k of flash. I have seen some app.notes > >from Altera/Xilinx/Lattice but I think that I need a more powerful > >micro for doing the CPLD reprograming with it. Is there any new small > >CPLD easy to reprogram?. I would appreciate any suggestion or link. > > You could probably bit-bang JTAG with a PIC. I'm not at a computer > with a Xilinx dev env, but I bet the files are pretty big relative to > PIC flash size. And obviously you'd want at least 2 of them, since > otherwise you'd just leave the CPLD flashed permanently...Article: 58104
Hi,
I'm making a pcb with a xilinx FPGA. I will obviously put a JTAG header
on my board. I simply want to know what is the standard pinout for the
header. Looking a the specs for the Parallel IV cable from xilinx I found
the following pinout:
14 NC 13 GND
12 NC 11 GND
10 TDI 9 GND
8 TDO 7 GND
6 TCK 5 GND
4 TMS 3 GND
2 Vref 1 GND
However, my evaluation board from burchED doesn't feature the same pinout:
1 TDI 2 TDO
3 TCK 4 TMS
5 NC 6 NC
7 GND 8 VCC
9 NC 10 NC
Conclusion, I don't know what to use. The pinout from xilinx seems space
wasteful. What would you put on your board?
thanks,
Gabriel
Article: 58105In article <c10cd8da.0307142116.cdcdfe5@posting.google.com>, javid <javodv@yahoo.es> wrote: >I was thinking in using a external SPI memory to store the CPLD >program. The problem is that I am afraid that also the CPLD >programming algorithm can not suit in a PIC Why not? The "host" (PIC in this case) drives the clock and data lines. When I looked at my Parallel Cable III with a 'scope the Impact software wasn't even driving a constant speed clock. I don't think the JTAG clock restrictions can be very stringent. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 58106
In article <8DMQa.38230$O55.885629@wagner.videotron.net>, ..:: Gabster ::.. <gabsterblue@hotmail.com> wrote: > > Conclusion, I don't know what to use. The pinout from xilinx seems space >wasteful. What would you put on your board? If you buy the leads from Xilinx you get individual "flying leads", not a single connector. There doesn't appear to be a target standard. I think the reason is that on non-development boards it may not be practical or desirable to even have all of the connections be in the same area of the board (longer JTAG chain) much less be pins at all. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 58107
Hi all.
I was actually thinking about digital PLLs recently when I was doing
investigation on analog PLLs.
Can someone describe the basic parts and operation of a DPLL?
Essentially these are the components I figured would be needed and this
is how the operation might work, I'd appreciate comments....
1. Phase / Frequency Detector
Standard two-DFF version, UP/DOWN outputs are used to control a
Numerically Controlled Oscillator block.
Input one to the PFD is the signal to be locked onto and input two is
the current output(or an ouput controlled by the DPLL), thus UP/DOWN
tries to drive the error down. UP/DOWN may have to be sychronized,
comments?
A lock signal could be the NAND(UP,DOWN) signals. Thus the output is
true when UP and DOWN are both zero.
Though I wonder, since this is a digital system, will 100% lock ever be
achieved, thus will the lock signal ever light?.
2. NCO
This block is essentially a mod-N counter which, at the end of it's
count, re-loads a count value from a register (perhaps double-buffered).
The register("error counter") is setup to increment or decrement it's
current value depending on the UP/DOWN signal from the Phase/Frequency
detector block.
The mod-N counter is set to count down from the current value, thus, a
smaller value in the counter means a higher frequency. This operation
(should?) emulate a VCO.
If the counter is configured to count down, I would guess that the
"error counter" would have to numerically increment the value it stores
when DOWN is true and numerically decrement with UP is true. I reason
this because there is an inverse relationship between the value stored
in the register and the output frequency (since we're controlling
"time" in terms of clock cycles).
3. Gain
The "error" register could be setup to increment by more than decimal 1,
perhaps by a power of 2 or something. Maybe even a "coarse" and fine
UP/DOWN could be used to get a faster lock.
My guess is that the setup I described emulates a P/I controller since
we could control how much the "error register" changes for an UP/DOWN
"event", thus this control the "P". And since the "error register" has
memory and stores a value even when the system is locked, we have "I".
I'd appreciate any comments on my scheme, what kinds of input clocks I
might need, if there are pitfalls and so on. I haven't actually built
this, but it's just an idea I've been toying with.
Thanks everyone.
-- Jay.
In article <AcIQa.2165$eP6.325075@news20.bellglobal.com>,
look_at_bottom_of@email.com says...
> Thanks for all of the responses, it's a great place to get going from.
> Having further looked into this analog design it seems as though the analog
> phase lock loop IC was being implemented in a circuit that essential is a
> frequency lock loop more than anything else. The input signal goes through
> this phase lock loop chip and then through a very heavy analog filter which
> converts the differential output of the IC to a single ended DC voltage that
> then is used to steer a VCO, the VCO output then gets divided down and the
> resulting waveform is used to drive the main circuitry (off of which the
> reference or input signal is derived).
>
> This being the case if you try to create a digital version of this, your
> output waveform is essentially a rock solid wave and since it is driving the
> circuit that your reference or input signal is derived from nothing moves,
> i.e when you turn it on it is locked almost instantly. If you ideally want
> your system frequency to wander slightly (say +/- 200 Hz around a frequency
> of say 25000 Hz) according to certain conditions such as temperature,
> current, etc. how is that analog type lag created in the digital domain.
> Would it just be a delay from input to output or something similar. In
> essence what I'm looking for is to create an oscillator that maintains it's
> peak amplitude, as temperatures increase (due to circuit current) the tuned
> circuits' peak value changes, and the circuit frequency naturally wants to
> move to the peak.
>
> Does this make sense? It's an interesting problem, and I don't think that
> the answer is very easy. I'm approaching it from a few angles at present.
>
> Once again thanks for the responses.
>
> Jason
>
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3F134720.D19A8BCA@andraka.com...
> > Mine used a barrel shift in the feedback to get a gain that increased with
> the
> > size of the error. Had to do that to get a quick lock and still be able
> to
> > chase the reference. The reference was derived from a quad encoder on the
> > mechanical media path. The PLL had to adjust a process to keep a certain
> number
> > of events between encoder pulses. All in all, it was a pretty nasty
> problem
> > because of the dynamics and limited resolution of the encoder.
> >
> > Kevin Neilson wrote:
> >
> > > My all-digital PLL was similar and worked very well. My reference clock
> and
> > > system clock were pretty stable so I didn't do a lot of analysis. I
> just
Article: 58108brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0307140822.7db7cb86@posting.google.com>... > gilad_coh@walla.co.il (Gilad Cohen) wrote in message news:<8f9a8978.0307120946.10624a6a@posting.google.com>... > > brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0307111552.189961b8@posting.google.com>... > > I've noticed something else. When I start hanging peripherals and > other things on my CPU core and don't apply any constraints other than > minimum clock, the system clock frequency goes down significantly. The > CPU is the bottleneck, not the peripherals so I'm wondering why this > is so. The only thing I can recommend at this time is to open the static timing analyzer and examine the failing paths. You probably need to apply multi-cycle and false-paths somewhere in the peripherals or in their interface to the CPU. Gilad.Article: 58109
<snip>
> > > The reason I'm asking is that by using STD_LOGIC_VECTOR(15
downto 8)
> > > you create an anonymous subtype, and I know that anonymous
subtypes
> > > are not always allowed where named subtypes are allowed. For
instance,
> > > it's illegal to declare a function returning an anonymous
subtype,
> > > but it's OK with a named subtype.
> > >
> > > regards
> > >
> > > Alan
> >
> > Alan, yes, that worked. Is this a bug that I should report to
Altera?
> > Or is this to be expected in VHDL?
>
> To answer my own question, I heard back from Altera today that it is
> invalid syntax under VHDL, but not providing an error message is an
> Altera bug. So they should be telling me to not use this syntax and
I
> need to use a named type here.
>
> The actual illegal syntax is the range in the type cast. Is that
what
> you meant be anonymous subtype?
>
Hallo Rick, yes basically. If you have a type, you can constrain it.
In
the case above, the type is STD_LOGIC_VECTOR, which is an
unconstrained
array type. To constrain arrays, you limit the range of the index.
So
subtype Vec8 is std_logic_vector(7 downto 0);
is a subtype, but of course it has a name "vec8".
If you write
signal s: std_logic_vector(7 downto 0);
what happens is that the compiler treats it as though you'd said
subtype i_have_no_name is std_logic_vector(7 downto 0);
signal s : i_have_no_name;
In other words the constraint creates an un-named subtype of
the type std_logic_vector.
The same is true with integer subtypes as well, e.g.
variable v : integer range 0 to 255;
creates an anonymous integer subtype.
In certain places in the language reference manual is refers
to a "type mark", and if you look that up it means
the name of a type or subtype. So for instance, the return type
of a function can be
return typemark;
which allows
return std_logic_vector --(Ok, must be constrained when returned)
return vec8 --(ok, assuming vec8 above)
return std_logic_vector(7 downto 0) -- won't work, not the name of
a
-- type or subtype!
The nice thing about VHDL is that all this is written down
somewhere :-)
regards
Alan
--
Alan Fitch
Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
Article: 58110
Hay Try this .............
DLLRST <= not RST_V3;
STAT_V3(0) <= LOCKED;
C_BUFG_CLK_0 : IBUFG
port map (
O => CLK_0_INDLL,
I => CLK_0
);
C_BUFG_CLK_0_OUTDLL : BUFG
port map (
O => CLK_0_DESKEW,
I => CLK_0_OUTDLL
);
C_BUFG_CLK_0_2XOUTDLL : BUFG
port map (
O => CLK_2X,
I => CLK_0_2XOUTDLL
);
C_CLKDLL : CLKDLL
port map (
CLKIN => CLK_0_INDLL,
CLKFB => CLK_0_DESKEW,
RST => DLLRST,
CLK0 => CLK_0_OUTDLL,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => CLK_0_2XOUTDLL,
CLKDV => open,
LOCKED => LOCKED
);
Rgds
Muhammad Khan
Stephen wrote in message
news:<63d01b4.0307132323.7b58a4f1@posting.google.com>...
> Hi Everyone,
> I have got the following problem when I use following CLKDLL
> configuration in Xilinx ISE 5.1.
>
> // input of clock source
>
> IBUFG ibufg_lclk(
> .I (lclk),
> .O (lclk_ibufg));
>
> BUFG in_bufg_lclk(
> .I (lclk_ibufg),
> .O (lclk_bufg));
>
> CLKDLL dll_lclk(
> .CLKIN (lclk_bufg),
> .CLKFB (clk),
> .RST (dllrst),
> .CLK0 (lclk0),
> .CLK2X (lclk2x0),
> .LOCKED (locked_lclk));
>
> BUFG bufg_lclk(
> .I (lclk0),
> .O (clk));
> BUFG bufg_lclk2x(
> .I (lclk2x0),
> .O (clk2x));
>
> IBUFG ibufg0(
> .I (ramclki[0]),
> .O (ramclki_ibufg[0]));
>
> CLKDLL dll0(
> .CLKIN (lclk_bufg),
> .CLKFB (ramclki_ibufg[0]),
> .RST (dllrst),
> .CLK2X (ramclko[0]),
> .LOCKED (locked_ramclk[0]));
>
> IBUFG ibufg1(
> .I (ramclki[1]),
> .O (ramclki_ibufg[1]));
>
>
> CLKDLL dll1(
> .CLKIN (lclk_bufg),
> .CLKFB (ramclki_ibufg[1]),
> .RST (dllrst),
> .CLK2X (ramclko[1]),
> .LOCKED (locked_ramclk[1]));
>
> I have got the following errors. And I have set the enviroment
> variable to 1.
> ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
> is driving
> a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
> driven by
> a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
> error, set
> environment variable XIL_MAP_ALLOW_ANY_DLL_INPUT.
> ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
> is driving
> a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
> driven by
> a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
> error, set
> environment variable XIL_MAP_ALLOW_ANY_DLL_INPUT.
> ERROR:LIT:179 - BUFG symbol "in_bufg_lclk" (output signal=lclk_bufg)
> is driving
> a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being
> driven by
> a BUFG, the BUFG must also be driven by a CLKDLL. To by-pass this
> error, set
> environment variable XIL_MAP_ALLOW_ANY_DLL_INPUT.
> Errors found during logical drc.
>
> Anyone have idea about it? Thanks.
Article: 58111
Hi,
I am a student at the University of Rostock, Germany and Currently working
on a project that is about Partial Reconfiguration.
I'm using a Virtex-E 100 for the project.
Now I have some problems with the bus macros:
My design has 20 interconnection bits, ten from left to right and ten from
right to left.
At first I tried to use three bus macros per direction, but the PAR-Tool
from the Xilinx Webpack was not able to route the design completely. I had a
look at the placed and routed design with the fpga-editor from Xilinx. There
I saw that only the odd output signals are connected at the left side and
the even output signals are connected at the right side.
I post the instantiation of two working bus macros.
bm3: bm_4b_ve
port map (
LI(3) => gnd_p, -- dummy data
LI(2) => req_to_bm,
LI(1) => gnd_p, -- dummy data
LI(0) => read_to_bm,
--
LT(3) => vcc_p, -- tri-state the left side...
LT(2) => gnd_p, -- enable the left side...
LT(1) => vcc_p, -- tri-state the left side..
LT(0) => gnd_p, -- enable the left side...
-- ----------------------
RI => gnd_reconf, -- dummy data
RT => vcc_reconf, -- tri-state
-- ----------------------
O(3) => open_signal_bm3(1), -- going to RM
O(2) => req_from_bm, -- open!
O(1) => open_signal_bm3(0), -- going to RM
O(0) => read_from_bm -- open!
);
bm4: bm_4b_ve
port map (
LI => gnd_per, -- dummy data
LT => vcc_per, -- tri-state
-- ----------------------
RI(2) => gnd_r, -- dummy data
RI(3) => ack_to_bm,
RI(0) => gnd_r, -- dummy data
RI(1) => rdy_to_bm,
--
RT(2) => vcc_r, -- tri-state the right side...
RT(3) => gnd_r, -- enable the right side...
RT(0) => vcc_r, -- tri-state the right side...
RT(1) => gnd_r, -- enable the right side...
-- ----------------------
O(2) => open_signal_bm4(1), -- open!
O(3) => ack_from_bm, -- going to PM
O(0) => open_signal_bm4(0), -- open!
O(1) => rdy_from_bm -- going to PM
);
When I connect the other signals the PAR-Tool doesn't route this signals.
Now my question, is that the normal behaviour? When I have a look at the
Xilinx application note that does not seem to be normal.
What are your experiences with the bus macros and the routing?
Marco
Article: 58112Hi mates I am getting following error while doing NGDBUILD using command line. I used -aul switch as suggested in error but this action simply doesn't assigned any pin to SR_IRD as seen in *.par file. How tom remove this error . My UCF file entry is something like this NET "SR_IRD" LOC = "P10" ; Error :-------------------- /VIR3/VIR3_top/VIR3_top.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "VIR3.ucf" ... ERROR:NgdBuild:755 - Line 75 in 'VIR3.ucf': Could not find net(s) 'SR_IRD' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "VIR3.ucf". Rgds MACEI'SArticle: 58113
javid wrote: > I was thinking in using a external SPI memory to store the CPLD > program. The problem is that I am afraid that also the CPLD > programming algorithm can not suit in a PIC, am I correct? anyone have > tryed? There is actually no complex programming algorithm for programmable logic devices (... that could not be implemented in a micro controller). Most of these devices have a very simple serial programming interface where you just have to shift in some commands/addresses/data. Just check the data sheet or the appropriate documentation of your desired device. Though, your internal storage capacity of the micro controller might be too small and you would need some external memory (as you mentioned above). Again, you have to check the data sheet in order to find out how big the configuration stream is. Then you will see whether it fits in the micro or how much external memory is required. Regards, MarioArticle: 58114
Hi fellows I want to compile multiple *.vhd files one by one using Makefile and I have done for single file but not for multiple . I want to generate one *.rbt files after compiling all *.vhd at the same time one by one using make file. Any help would be highly appreciated. cheers Macei'Article: 58115
Hello, I am planing to use the PIC18F258 (1.5kbytes of SRAM and 32Kbytes of FLASH). Xilinx (app.note 058) and Altera (An111) seem to use external memories with the 8051. I was wondering if with just about 1k of internal SRAM and 20Kbytes of internal flash would be enough for implementing the code of those app. notes. Anyone have tried it? how much program code and RAM woull i need?. Thanks a lot and best regards, Javier del Valle ben@ben.com (Ben Jackson) wrote in message news:<ACMQa.56387$sY2.27288@rwcrnsc51.ops.asp.att.net>... > In article <c10cd8da.0307142116.cdcdfe5@posting.google.com>, > javid <javodv@yahoo.es> wrote: > >I was thinking in using a external SPI memory to store the CPLD > >program. The problem is that I am afraid that also the CPLD > >programming algorithm can not suit in a PIC > > Why not? The "host" (PIC in this case) drives the clock and data lines. > When I looked at my Parallel Cable III with a 'scope the Impact software > wasn't even driving a constant speed clock. I don't think the JTAG clock > restrictions can be very stringent.Article: 58116
Hello, I have read the docs, but still unclear if the JTAG boundary scan could be used during configuration, i.e. 1) small microcontroller connected to JTAG and selectmap pins 2) Xilinx Spartan II/Virtex 3) Parallel flash connected to FPGA microcontroller used Boundary scan to fetch from Flash then writes the configuration using selectmap as per xilinx docu this doesnt sound like not possible but I wonder if anyones has experience with that, or knows for sure if this approuch could work or not I think using boundary scan during JTAG configuration is not allowed but during selectmap? anttiArticle: 58117
Go to www.gaisler.com and download the latest Leon version. Have a look at the makefile in ./leon to get an idea of "How to write a Makefile for VHDL/Verilog". Our Makefiles (and others, I assume) are a bit complicated to understand, but those are a good starting point. Ronald MACEI'S wrote: > Hi fellows > I want to compile multiple *.vhd files one by one using Makefile and I > have done for single file but not for multiple . I want to generate > one *.rbt files after compiling all *.vhd at the same time one by one > using make file. > > Any help would be highly appreciated. > > cheers > > Macei'Article: 58118
"Thomas Fuchs" <thomasfuchs77@t-online.de> skrev i melding news:bep5ud$spu$04$1@news.t-online.com... > Hallo, > > I'm just making my first steps in FPGA programming. So, I bought myself > a development board with a SpartanIIE. My first try was to use the DLL. > It works pretty well except the additional CLK2X180 output in the > CLKDLLE macro. What I figured out so far is that in the FPGA Editor the > so called CLK2X180 output doesn't exit at the DLL. There is just another > output called CLK2X90. Not the same like the Libraries Guide says. Is > there maybe a bug? I'm using the 5.1 Webpack with Service Pack 3. > Another small question. When I connect to the FPGA via Boundary Scan the > device found is a xcv200e although the print on my IC says it is a > xc2s200e. So, its reading a work device ID. Can that happen? This may not answer your queston, but.. The CLK2X90 output in the fpga editor is a typo bug. It's the same as the CLK2X180. Ive read that on the xilinx webpage (or maybe I got it confirmed by voice? Dont remember exactly.) Make sure the LOCKED output is high, orelse you wont get a proper 2x clock (you may have a 1x clock present, but not locked)Article: 58119
Antti Lukats wrote: > > Hello, > > I have read the docs, but still unclear if the JTAG boundary scan could > be used during configuration, i.e. > > 1) small microcontroller connected to JTAG and selectmap pins > 2) Xilinx Spartan II/Virtex > 3) Parallel flash connected to FPGA > > microcontroller used Boundary scan to fetch from Flash > then writes the configuration using selectmap > > as per xilinx docu this doesnt sound like not possible but I wonder > if anyones has experience with that, or knows for sure if this > approuch could work or not > > I think using boundary scan during JTAG configuration is not allowed > but during selectmap? > > antti None of this sounds hard to me. The step of reading the Flash by driving the JTAG pins seems a bit complex and will be very slow, but it should work. But where are you going to store the configuration data while in the JTAG Flash read mode? It will be much more expensive to have that much RAM available. It would be better to hang the Flash off the MCU rather than on the FPGA. Then you can program each byte as you read it and don't need all that RAM storage. I have recently taken a look at NAND flash and it does not need the large number of address lines and is much cheaper than NOR Flash. You only need about 12 or 14 signals to connect to it and control it through the 8 bit data port. It is easy to do this through a pair of 8 bit ports on an MCU. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58120
"..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message news:8DMQa.38230$O55.885629@wagner.videotron.net... > Hi, > > I'm making a pcb with a xilinx FPGA. I will obviously put a JTAG header > on my board. I simply want to know what is the standard pinout for the > header. Looking a the specs for the Parallel IV cable from xilinx I found > the following pinout: > > 14 NC 13 GND > 12 NC 11 GND > 10 TDI 9 GND > 8 TDO 7 GND > 6 TCK 5 GND > 4 TMS 3 GND > 2 Vref 1 GND > > However, my evaluation board from burchED doesn't feature the same pinout: > > 1 TDI 2 TDO > 3 TCK 4 TMS > 5 NC 6 NC > 7 GND 8 VCC > 9 NC 10 NC > > Conclusion, I don't know what to use. The pinout from xilinx seems space > wasteful. What would you put on your board? I use a 6-way header (single row) with connections matching the Xilinx cable flying leads (I use the old Parallel Cable III): VCC GND TCK TDO TDI TMS There is less chance of getting them mixed up with this scheme. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 58121
Hi all,
When I try to follow the steps to make a bitstream of ML300 Embbedded
reference system in
Virtex-II Pro Development Kit, I get the following error during Mapping:
ERROR:Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement
for
your design exceeds the resources available in the device.
I'm using ISE 5.2i (SP3). The synthesis tool I use is XST. The following is
part of the synthesis report:
Number of Slices: 3366 out of 5440 61%
Number of Slice Flip Flops: 3176 out of 10880 29%
Number of 4 input LUTs: 3920 out of 10880 36%
The following is part of the Mapping report:
Logic Utilization:
Number of Slice Flip Flops: 6,265 out of 9,856 63%
Number of 4 input LUTs: 7,420 out of 9,856 75%
Logic Distribution:
Number of occupied Slices: 4,957 out of 4,928
100% (OVERMAPPED)
Number of Slices containing only related logic: 3,346 out of 4,957
67%
Number of Slices containing unrelated logic: 1,611 out of 4,957
32%
*See NOTES below for an explanation of the effects of unrelated
logic
Total Number 4 input LUTs: 8,072 out of 9,856 81%
Number used as logic: 7,420
Number used as a route-thru: 275
Number used for Dual Port RAMs: 176
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 201
I would like to ask how could I solve the *OVERMAPPED* problem?
There is pre-built bitstream file in the reference design. How come I
can't create one myself ?!
Thanks in advance.
tk
Article: 58122I know that respective regulars of this newsgroup don't like to give decisive answers to A vs. X type of questions, but... This last visit of the Xilinx representative was a shocker ! A bit of the background. We are as pure Altera shop as it goes. As such we don't follow Xilinx products very closely. When we occasionally did the check we typically found out that for our applications there are no big differences between offerings of Xilinx and Altera so there was no reason to step out of the comfort zone of established routine. We believed that this situation will last forever - it's what the competition is invented for, isn't it ? I have to mention that up until recently we never faced the project that was very multiplication-intensive on its FPGA side. The project we are trying to achieve now is exactly like this- very multiply (MAC) intensive almost 100% FIR filtering. As usual, initially we figured out a possible Altera solution. It was a bit pricey and required two (or four smaller) chips but we thought that it is the state of the art and so be it. But here come a representatives from Xilinx and showed as their Virtex-II Pro parts... As I mentioned above it was a shock: about three time as many multipliers as in similar size/similar price Stratix chip. Two and a half times more multipliers than in significantly bigger Startix chip ! XC2P30 - 136 18x18 Dedicated multipliers EP1S30 - 48 18x18 Embedded multipliers (the price of the parts is similar to XC2P30) EP1S40 - 56 18x18 Embedded multipliers I suppose that Startix parts are a bit faster, but it doesn't make a difference for our application. Doing the computational part of the design in the distinct (faster) clock domain doesn't make much sense when the main (data acquisition) clock already runs at 190MHz. And for 190MHz VirtexII-Pro is o.k. For us as far as Stratix unable to run calculation at 380MHz its speed advantage doesn't care. Since I have no experience with Xilinx in general and with Virtex-II Pro in particular I am afraid I missed something. It's almost too good to be true. IMHO if there is no catch (availability ?) here the XC2P parts draws Stratix into irrelevance for nearly all DSP-intensive applications.Article: 58123
The size of the PROM recommended for each Spartan model is shown here: http://www.xilinx.com/isp/compfpgatables/prom_spartan.htm Why can't I use a 4Mb PROM with my Spartan IIE FPGA. Right now, on a 2Mb (the recommended one), the PROM is 89% full but the FPGA is far from being completly exploited. thanks, GabrielArticle: 58124
Hello folks, Just a few quick questions regarding filters and actual designs on FPGAs: What are the largest interpolation/decimation factors you have used/seen used? What is the largest number of independant data channels you have used through one filter or N instances of the same filter where the number of channels = N? What is the largest bit-width input data samples you have used/seen used? Thanks for your time, Ken -- To reply by email, please remove the _MENOWANTSPAM from my email address.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z