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Threads Starting Nov 1999
18565: 99/11/01: <aoui0r93809@asadszlkjaslkjz.net>: Inkjets 4 you!
18567: 99/11/01: Luigi Funes: 16 bit counter in Abel
18586: 99/11/02: Roman Pollak: Re: 16 bit counter in Abel
18590: 99/11/02: Ray Andraka: Re: 16 bit counter in Abel
18616: 99/11/03: Luigi Funes: Re: 16 bit counter in Abel
18568: 99/11/01: <304830983@098340938.org>: *Latest Inkjetz for Sale*
18569: 99/11/01: Rick Filipkiewicz: Virtex hardware debugging - help needed
18573: 99/11/01: project: Roots of development of FPGA's
18582: 99/11/01: cmsmith1: Looking for a few more discontinued Xilinx chips.
18584: 99/11/02: anup kumar raghavan: XNF file formats ???
18585: 99/11/02: Ray Andraka: Re: XNF file formats ???
18589: 99/11/02: <gallant@nm.hsd.utc.com>: Input metastability
18598: 99/11/02: Peter Alfke: Re: Input metastability
18620: 99/11/03: Greg Neff: Re: Input metastability
18622: 99/11/03: Ray Andraka: Re: Input metastability
18638: 99/11/04: Greg Neff: Re: Input metastability
18645: 99/11/04: rk: Re: Input metastability
18630: 99/11/04: Rickman: Re: Input metastability
18639: 99/11/04: Greg Neff: Re: Input metastability
18642: 99/11/04: Bob Perlman: Re: Input metastability
18651: 99/11/05: Greg Neff: Re: Input metastability
18658: 99/11/05: Rickman: Re: Input metastability
18662: 99/11/05: Greg Neff: Re: Input metastability
18670: 99/11/06: Rickman: Re: Input metastability
18674: 99/11/07: <kayrock@my-deja.com>: Re: Input metastability
18677: 99/11/07: Hal Murray: Re: Input metastability
18683: 99/11/07: rk: Re: Input metastability
18686: 99/11/07: Bob Perlman: Re: Input metastability
18688: 99/11/07: Ray Andraka: Re: Input metastability
18699: 99/11/08: Hal Murray: Re: Input metastability
18591: 99/11/02: Thomas Hedler: Optimizing Logic Cells
18594: 99/11/02: Wenyi Feng: Re: Optimizing Logic Cells
18599: 99/11/02: Norm Ebsary: Job Posting
18600: 99/11/02: Warland, Tim [CRK:E930:EXCH]: WEB reconfigurable FPGA, How?
18612: 99/11/03: Andreas Doering: Re: WEB reconfigurable FPGA, How?
18618: 99/11/03: Eric Pearson: Re: WEB reconfigurable FPGA, How?
18601: 99/11/02: k1492799: logic fault simulation
18603: 99/11/03: <sheilasu@my-deja.com>: software microprocessor model needed
18604: 99/11/03: Child K.L. Sun: High Speed Enough!?
18613: 99/11/03: Ray Andraka: Re: High Speed Enough!?
18632: 99/11/04: Child K.L. Sun: Re: High Speed Enough!?
18641: 99/11/04: Peter Alfke: Re: High Speed Enough!?
18643: 99/11/04: Ray Andraka: Re: High Speed Enough!?
18605: 99/11/03: Kwong Chan: Xlinx FPGA
18609: 99/11/03: Peter C: Re: Xlinx FPGA
18649: 99/11/05: Kwong Chan: Re: Xlinx FPGA
18653: 99/11/05: Peter: Re: Xlinx FPGA
18614: 99/11/03: Ray Andraka: Re: Xlinx FPGA
18621: 99/11/03: Richard Erlacher: Re: Xlinx FPGA
18623: 99/11/03: Ray Andraka: Re: Xlinx FPGA
18668: 99/11/06: Kwong Chan: Re: Xlinx FPGA
18669: 99/11/05: Ray Andraka: Re: Xlinx FPGA
18610: 99/11/03: <lordxiphias@altern.org>: LX.MP3z: NO PORN, NO POP-UPS, NO BROKEN LINKS (Just MP3z!!)
18611: 99/11/03: project: Why DSP in a FPGA?
18615: 99/11/03: Ray Andraka: Re: Why DSP in a FPGA?
18672: 99/11/06: Ahmad A.: Re: Why DSP in a FPGA?
18673: 99/11/06: Ray Andraka: Re: Why DSP in a FPGA?
18678: 99/11/07: Hal Murray: Re: Why DSP in a FPGA?
18682: 99/11/07: rk: Re: Why DSP in a FPGA?
18617: 99/11/03: giuseppe giachella: Fpga Compiler Altera Edition & Leonardo Spectrum
18633: 99/11/04: Brian Drummond: Re: Fpga Compiler Altera Edition & Leonardo Spectrum
18619: 99/11/03: Norm Ebsary: NEBS PC
18624: 99/11/04: YUN SONG HYUN: looking for XNF Grammar
18687: 99/11/08: anup kumar raghavan: Re: looking for XNF Grammar
18625: 99/11/04: L Horvath: How to connect a Xilinx Virtex FPGA to a TI DSP ?
18804: 99/11/16: Joel Kolstad: Re: How to connect a Xilinx Virtex FPGA to a TI DSP ?
18626: 99/11/04: Ilia Oussorov: which is the maximum freqency?
18627: 99/11/04: fliser3: Re: which is the maximum freqency?
18636: 99/11/04: Andy Peters: Re: which is the maximum freqency?
18628: 99/11/04: Josef Fleischmann: Simulation of FPGA design. Please Help!
18629: 99/11/04: Harald Simmler: Re: Simulation of FPGA design. Please Help!
18635: 99/11/04: Andy Peters: Re: Simulation of FPGA design. Please Help!
18640: 99/11/04: Brian Philofsky: Re: Simulation of FPGA design. Please Help!
18667: 99/11/05: Rick Filipkiewicz: Re: Simulation of FPGA design. Please Help!
18719: 99/11/09: Brian Philofsky: Re: Simulation of FPGA design. Please Help!
18729: 99/11/10: Rick Filipkiewicz: Re: Simulation of FPGA design. Please Help!
18750: 99/11/11: <eml@riverside-machines.com.NOSPAM>: Re: Simulation of FPGA design. Please Help!
18753: 99/11/11: Ray Andraka: Re: Simulation of FPGA design. Please Help!
18631: 99/11/04: <brainsite@altern.org>: FREE XXX-PICS!! Without membership!!
18634: 99/11/04: Kavadias Stamatis: PCI Pamette Error
18637: 99/11/04: project: Price of FPGA
18644: 99/11/04: Ray Andraka: Re: Price of FPGA
18660: 99/11/05: Rickman: Re: Price of FPGA
18676: 99/11/07: <kayrock@my-deja.com>: Re: Price of FPGA
18646: 99/11/04: Steve Gross: Tuesday night
18647: 99/11/04: Andy Peters: Xilinx M2.1i SP2?
18650: 99/11/04: Ray Andraka: Re: Xilinx M2.1i SP2?
18659: 99/11/05: Rickman: Re: Xilinx M2.1i SP2?
18664: 99/11/05: Andy Peters: Re: Xilinx M2.1i SP2?
18652: 99/11/05: Greg Neff: Re: Xilinx M2.1i SP2?
18656: 99/11/05: <dfrevele@li.net>: Re: Xilinx M2.1i SP2?
18805: 99/11/16: Joel Kolstad: Re: Xilinx M2.1i SP2?
18837: 99/11/18: <dfrevele@li.net>: Re: Xilinx M2.1i SP2?
18661: 99/11/05: peter dudley: Re: Xilinx M2.1i SP2?
18666: 99/11/05: Andy Peters: Re: Xilinx M2.1i SP2?
18648: 99/11/05: Alexander Sherstuk: Analog FPGA ?!
18654: 99/11/05: Joerg RiTTer: Re: Analog FPGA ?!
18665: 99/11/05: Reiner Huober: Re: Analog FPGA ?!
18693: 99/11/08: Number Cruncher: Re: Analog FPGA ?!
18655: 99/11/05: =?iso-2022-jp?B?GyRCQFZMWjUxQ0sbKEI=?=: =?iso-2022-jp?B?GyRCJUElYyVzJTkbKEI=?=
18657: 99/11/05: david garnett: AMCC 5933 Woes
18663: 99/11/05: Dan: Re: AMCC 5933 Woes
18712: 99/11/09: <deroberts@my-deja.com>: Re: AMCC 5933 Woes
18671: 99/11/06: Anton Erasmus: Frequency Division in Altera AHDL ?
18714: 99/11/09: <jessiek@polbox.com>: Re: Frequency Division in Altera AHDL ?
18727: 99/11/10: <jessiek@polbox.com>: Re: Frequency Division in Altera AHDL ?
18679: 99/11/07: Mike: I've gotta buncha FPGA chips, but.....
18680: 99/11/07: Child K.L. Sun: FPGA's interface ....
18681: 99/11/07: Child K.L. Sun: ROM or SRAM !?
18684: 99/11/07: Ray Andraka: Re: ROM or SRAM !?
18685: 99/11/07: rk: Re: ROM or SRAM !?
18691: 99/11/08: Child K.L. Sun: Re: ROM or SRAM !?
18694: 99/11/08: rk: Re: ROM or SRAM !?
18696: 99/11/08: Ray Andraka: Re: ROM or SRAM !?
18703: 99/11/08: rk: Re: ROM or SRAM !? - who really cares?
18689: 99/11/08: Austin Franklin: Downloading Xilinx FPGA with just .bit file???
18690: 99/11/07: Ray Andraka: Re: Downloading Xilinx FPGA with just .bit file???
18697: 99/11/08: Austin Franklin: Re: Downloading Xilinx FPGA with just .bit file???
18700: 99/11/08: Rick Filipkiewicz: Re: Downloading Xilinx FPGA with just .bit file???
18692: 99/11/08: Number Cruncher: LATTICE SEMICONDUCTOR INTRODUCES THE PLD OF ANALOG CHIPS
18695: 99/11/08: Mark Harvey: R: StateCAD versus Viewdraw
18698: 99/11/08: Don Husby: OrcaLut from VHDL?
18701: 99/11/08: Chris: Need a good Pullup for a VHDL Test Bench
18704: 99/11/08: peter dudley: Re: Need a good Pullup for a VHDL Test Bench
18705: 99/11/09: Allan Herriman: Re: Need a good Pullup for a VHDL Test Bench
18717: 99/11/09: Chris: Re: Need a good Pullup for a VHDL Test Bench
18702: 99/11/08: <tgallati@hotmail.com>: Altera Releases First in New Line of PLDs
18706: 99/11/08: Adam J. Elbirt: Re: PLD Quesiton
18707: 99/11/08: Michael Ayton: PLD Quesiton
18708: 99/11/08: Michael Ayton: Reverse Engineering a 16L8
18709: 99/11/09: Leslie Yip (/ Loui): Problems in Viewlogic's Workview office
18710: 99/11/09: Alan Fitch: Re: Problems in Viewlogic's Workview office
18713: 99/11/09: Michael Schmid: Re: Problems in Viewlogic's Workview office
18715: 99/11/09: Srikanth Gurrapu: Sample Rate Conversion.
18720: 99/11/09: martin griffith: Re: Sample Rate Conversion.
18721: 99/11/09: Bill Groves: Re: Sample Rate Conversion.
18718: 99/11/09: Graham Seaman: orcad synthesis for simplepld
18733: 99/11/10: <wq998@my-deja.com>: Re: orcad synthesis for simplepld
18734: 99/11/10: Ray Andraka: Re: orcad synthesis for simplepld
18740: 99/11/11: Graham Seaman: Re: orcad synthesis for simplepld
18747: 99/11/11: Greg Neff: Re: orcad synthesis for simplepld
18772: 99/11/13: Graham Seaman: Re: orcad synthesis for simplepld
18894: 99/11/20: Tom Meagher: Re: orcad synthesis for simplepld
18722: 99/11/09: Brian Boorman: test
18723: 99/11/09: Arnold Beland: CAN tools reccomendations?
18726: 99/11/10: Don McKenzie: Re: CAN tools reccomendations?
18728: 99/11/10: Steve Lovell: Re: CAN tools reccomendations?
18730: 99/11/10: Ted Wood: Re: CAN tools reccomendations?
18731: 99/11/10: Steve Letkeman: Re: CAN tools reccomendations?
18732: 99/11/10: Tom Burgess: Re: CAN tools reccomendations?
18736: 99/11/10: Bruce L: Re: CAN tools reccomendations?
18724: 99/11/10: anup kumar raghavan: where can I find fitter algorithms
18725: 99/11/10: G.S. Vigneault: Re: where can I find fitter algorithms
18735: 99/11/10: <ozfbgs@hotmail.com>: ## Information Auction - Sell What You Know -Buy What You Dont ## 3845
18737: 99/11/11: <fidonews2@my-deja.com>: FS: New Altera Max+Plus II full VHDL $1K
18769: 99/11/13: Tony: Re: New Altera Max+Plus II full VHDL $1K
18738: 99/11/11: Rick Filipkiewicz: Re: Altera Files vho and sdo too big
18874: 99/11/19: Edwin Grigorian: Re: Altera Files vho and sdo too big
18877: 99/11/19: Ying C.: Re: Altera Files vho and sdo too big
18739: 99/11/11: Andreas Barthel: looking for Xilinx/Actel Board
18745: 99/11/11: <xiaocong9313@my-deja.com>: Re: looking for Xilinx/Actel Board
18746: 99/11/11: Steven K. Knapp: Re: looking for Xilinx/Actel Board
18771: 99/11/13: Markus Wannemacher: Re: looking for Xilinx/Actel Board
18741: 99/11/11: Theron Hicks: fast programmable divider using xilinx xc4002xl
18743: 99/11/11: Ray Andraka: Re: fast programmable divider using xilinx xc4002xl
18749: 99/11/11: Peter Alfke: Re: fast programmable divider using xilinx xc4002xl
18752: 99/11/11: Ray Andraka: Re: fast programmable divider using xilinx xc4002xl
18742: 99/11/11: Euripides Sotiriades: read back Altera
18751: 99/11/11: Richard Damon: Re: read back Altera
18744: 99/11/11: giuseppe giachella: Altera Files vho and sdo too big
18748: 99/11/11: Greg Neff: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18756: 99/11/12: Olav Gundersen: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18757: 99/11/12: Paul Butler: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18785: 99/11/15: B. Joshua Rosen: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18796: 99/11/16: Jason T. Wright: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18759: 99/11/12: Rick Filipkiewicz: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18763: 99/11/12: <malino@primenet.com>: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18778: 99/11/14: John Doe: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
18885: 99/11/20: <arafeeq@my-deja.com>: Synplify vs. FPGA Compiler II (v3.3)
18890: 99/11/19: Bruce Nepple: Re: Synplify vs. FPGA Compiler II (v3.3)
19189: 99/12/04: Rickman: Re: Synplify vs. FPGA Compiler II (v3.3)
19195: 99/12/05: Greg Neff: Re: Synplify vs. FPGA Compiler II (v3.3)
19196: 99/12/04: rk: Re: Synplify vs. FPGA Compiler II (v3.3)
19220: 99/12/06: Bruce Nepple: Re: Synplify vs. FPGA Compiler II (v3.3)
18754: 99/11/12: Steven Derrien: FPGA density evolution
18755: 99/11/12: anup kumar raghavan: What are the steps involved in the developement of a CAD tool
18765: 99/11/13: thi: Re: What are the steps involved in the developement of a CAD tool
18758: 99/11/12: Ray Andraka: Re: Pin locking problem in Altera fpga
18760: 99/11/12: Artur Leung: ROM Magafunction for Altera MAX7000 Series
18761: 99/11/12: giuseppe giachella: Pin locking problem in Altera fpga
18762: 99/11/12: Norm Ebsary: Career Opportunity
18764: 99/11/13: Uday Godbole: WHERE can I find xc9536_v2.bsd??!
18786: 99/11/16: Paul Taylor: Re: WHERE can I find xc9536_v2.bsd??!
18792: 99/11/16: Klaus Falser: Re: WHERE can I find xc9536_v2.bsd??!
18893: 99/11/20: h.f.: Re: WHERE can I find xc9536_v2.bsd??!
18766: 99/11/13: Rob Barris: How many bits in an FPGA bitstream?
18768: 99/11/13: Alexander Sherstuk: Re: How many bits in an FPGA bitstream?
18770: 99/11/13: John Larkin: Re: How many bits in an FPGA bitstream?
18774: 99/11/14: Richard Dungan: Re: How many bits in an FPGA bitstream?
18832: 99/11/18: Peter: Re: How many bits in an FPGA bitstream?
18835: 99/11/18: Ray Andraka: Re: How many bits in an FPGA bitstream?
18773: 99/11/13: Peter Alfke: Re: How many bits in an FPGA bitstream?
18871: 99/11/19: Luis Yanes: Re: How many bits in an FPGA bitstream?
18886: 99/11/19: John Larkin: Re: How many bits in an FPGA bitstream?
18775: 99/11/14: Jaap H. Mol: Altera NOT-gate push back
18788: 99/11/16: Hal Murray: Re: Altera NOT-gate push back
18776: 99/11/14: <a_maier@my-deja.com>: configure_flex10k30e_jtag_jam
18787: 99/11/16: Steve Rencontre: Re: configure_flex10k30e_jtag_jam
18917: 99/11/22: Michael Stanton: Re: configure_flex10k30e_jtag_jam
18948: 99/11/22: <a_maier@my-deja.com>: Re: configure_flex10k30e_jtag_jam
18777: 99/11/14: George: test
18779: 99/11/15: drl3: Altera programming leads
18780: 99/11/15: Nicolas Matringe: Re: Altera programming leads
18781: 99/11/15: Maciej Bartkowiak: Need advice on interfacing SDRAM modules
18784: 99/11/15: Joseph H Allen: Re: Need advice on interfacing SDRAM modules
18844: 99/11/18: Maciej Bartkowiak: Re: Need advice on interfacing SDRAM modules
18845: 99/11/18: Rickman: Re: Need advice on interfacing SDRAM modules
18848: 99/11/18: Andy Peters: Re: Need advice on interfacing SDRAM modules
18851: 99/11/18: Ray Andraka: Re: Need advice on interfacing SDRAM modules
18859: 99/11/19: Rick Filipkiewicz: Re: Need advice on interfacing SDRAM modules
18876: 99/11/19: Andy Peters: Re: Need advice on interfacing SDRAM modules
18791: 99/11/16: <mar@tcelectronic.com>: Re: Need advice on interfacing SDRAM modules
18846: 99/11/18: Stefan Ludwig: Re: Need advice on interfacing SDRAM modules
18903: 99/11/20: Tom Davidson: Re: Need advice on interfacing SDRAM modules
18908: 99/11/20: Rickman: Re: Need advice on interfacing SDRAM modules
18912: 99/11/21: Joseph H Allen: Re: Need advice on interfacing SDRAM modules
18925: 99/11/22: Rickman: Re: Need advice on interfacing SDRAM modules
18782: 99/11/15: Utku Ozcan: Xilinx m2.1i Service Pack #2 installation problems
18783: 99/11/15: Armin Mueller: Strongest/Fastest Logic Reduction?
18789: 99/11/15: John Doe: Lattice LXOR2 Question
18790: 99/11/16: Craig Humphrey: OLD programming Software
18793: 99/11/16: alco: How to use GSR-net in Virtex?
18794: 99/11/16: alco: What happens to power-on-reset when external signals control the GSR
18795: 99/11/16: Andy Peters: Re: How to use GSR-net in Virtex?
18826: 99/11/18: Austin Franklin: Re: How to use GSR-net in Virtex?
18828: 99/11/18: Allan Herriman: Re: How to use GSR-net in Virtex?
18829: 99/11/18: Nicolas Matringe: Re: How to use GSR-net in Virtex?
18833: 99/11/18: Ray Andraka: Re: How to use GSR-net in Virtex?
18855: 99/11/19: Hal Murray: Re: How to use GSR-net in Virtex?
18989: 99/11/23: Dragon: Re: How to use GSR-net in Virtex?
19001: 99/11/23: Ray Andraka: Re: How to use GSR-net in Virtex?
19006: 99/11/24: Hal Murray: Re: How to use GSR-net in Virtex?
18869: 99/11/19: Austin Franklin: Re: How to use GSR-net in Virtex?
18831: 99/11/18: Utku Ozcan: How to use multiple resets?
18834: 99/11/18: Ray Andraka: Re: How to use multiple resets?
18860: 99/11/19: <eml@riverside-machines.com.NOSPAM>: Re: How to use multiple resets?
18864: 99/11/19: Ray Andraka: Re: How to use multiple resets?
18868: 99/11/19: Austin Franklin: Re: How to use multiple resets?
18838: 99/11/18: Brian Boorman: Re: How to use multiple resets?
18952: 99/11/22: Keith Jasinski, Jr.: Re: How to use multiple resets?
18988: 99/11/23: Dragon: Re: How to use multiple resets?
19003: 99/11/23: Ray Andraka: Re: How to use multiple resets?
19013: 99/11/24: Allan Herriman: Re: How to use multiple resets?
18841: 99/11/18: Andy Peters: Re: How to use GSR-net in Virtex?
18854: 99/11/19: Austin Franklin: Re: How to use GSR-net in Virtex?
18865: 99/11/19: Ray Andraka: Re: How to use GSR-net in Virtex?
18867: 99/11/19: Austin Franklin: Re: How to use GSR-net in Virtex?
18873: 99/11/19: Andy Peters: Re: How to use GSR-net in Virtex?
18889: 99/11/19: Ray Andraka: Re: How to use GSR-net in Virtex?
18861: 99/11/19: <eml@riverside-machines.com.NOSPAM>: Re: How to use GSR-net in Virtex?
18863: 99/11/19: Austin Franklin: Re: How to use GSR-net in Virtex?
18875: 99/11/19: Andy Peters: Re: How to use GSR-net in Virtex?
18797: 99/11/16: Joseph Su: Q: implementing TCP/IP on PLD
18798: 99/11/17: martin griffith: Re: Q: implementing TCP/IP on PLD
18803: 99/11/17: Richard Erlacher: Re: Q: implementing TCP/IP on PLD
18799: 99/11/17: Dirk Bruere: Re: implementing TCP/IP on PLD
18800: 99/11/17: David Emrich: Re: implementing TCP/IP on PLD
18801: 99/11/17: Dirk Bruere: Re: implementing TCP/IP on PLD
18810: 99/11/17: Austin Franklin: Re: implementing TCP/IP on PLD
18821: 99/11/17: Dirk Bruere: Re: implementing TCP/IP on PLD
18921: 99/11/22: #YEO WEE KWONG#: Most micros (PIC/8051 etc) have TCP/IP stacks freely available.
18809: 99/11/17: Austin Franklin: Re: implementing TCP/IP on PLD
18813: 99/11/17: Jamie Lokier: Re: implementing TCP/IP on PLD
18818: 99/11/17: Joseph Su: Re: implementing TCP/IP on PLD
18820: 99/11/17: Dirk Bruere: Re: implementing TCP/IP on PLD
18825: 99/11/18: glen herrmannsfeldt: Re: implementing TCP/IP on PLD
18852: 99/11/19: Jamie Lokier: Re: implementing TCP/IP on PLD
18856: 99/11/18: Joel Kolstad: Re: implementing TCP/IP on PLD
18858: 99/11/19: Jamie Lokier: Re: implementing TCP/IP on PLD
18866: 99/11/19: Ray Andraka: Re: implementing TCP/IP on PLD
18998: 99/11/23: glen herrmannsfeldt: Re: implementing TCP/IP on PLD
18892: 99/11/19: <email@inter.net>: Re: implementing TCP/IP on PLD
18897: 99/11/20: Dirk Bruere: Re: implementing TCP/IP on PLD
18971: 99/11/23: Joseph C. Su: Re: implementing TCP/IP on PLD
18973: 99/11/23: Dirk Bruere: Re: implementing TCP/IP on PLD
19004: 99/11/23: Donald Gillies: Re: implementing TCP/IP on PLD
19026: 99/11/25: Mark Summerfield: Re: implementing TCP/IP on PLD
19027: 99/11/24: Dirk Bruere: Re: implementing TCP/IP on PLD
19036: 99/11/25: Mark Summerfield: Re: implementing TCP/IP on PLD
19053: 99/11/26: Dirk Bruere: Re: implementing TCP/IP on PLD
19055: 99/11/26: #YEO WEE KWONG#: implementing TCP/IP on PLD
19037: 99/11/25: glen herrmannsfeldt: Re: implementing TCP/IP on PLD
19077: 99/11/27: Peter: Re: implementing TCP/IP on PLD
19092: 99/11/28: marius: Re: implementing TCP/IP on PLD
19054: 99/11/26: #YEO WEE KWONG#: XTP
18974: 99/11/23: Kirill 'Big K' Katsnelson: Re: implementing TCP/IP on PLD
18975: 99/11/23: Hal Murray: Re: implementing TCP/IP on PLD
19022: 99/11/24: Armin Mueller: Re: implementing TCP/IP on PLD
18922: 99/11/22: #YEO WEE KWONG#: implementing TCP/IP on PLD
18819: 99/11/17: Joseph Su: Re: implementing TCP/IP on PLD
18811: 99/11/17: ken ryan: Re: Q: implementing TCP/IP on PLD
18802: 99/11/16: Michal: Orcad 7.0 to Altera MAX?
18806: 99/11/17: Bonio Lopez: COM1-FPGA communication
18814: 99/11/17: Carlhermann Schlehaus: Re: COM1-FPGA communication
18816: 99/11/17: John Larkin: Re: COM1-FPGA communication
18817: 99/11/17: Andy Peters: Re: COM1-FPGA communication
18827: 99/11/18: Richard Erlacher: Re: COM1-FPGA communication
18807: 99/11/17: John F Gostomski: FPGA to ASIC conversion
18824: 99/11/18: Jason T. Wright: Re: FPGA to ASIC conversion
18808: 99/11/17: James Birmingham: viewing fpga config
18812: 99/11/17: Steven Derrien: Foundation configuration
18815: 99/11/17: Rickman: Why not Lucent ORCA FGPAs?
18822: 99/11/17: Rickman: Re: Why not Lucent ORCA FGPAs?
18878: 99/11/19: Don Husby: Re: Why not Lucent ORCA FGPAs?
18879: 99/11/19: Don Husby: Re: Why not Lucent ORCA FGPAs?
18899: 99/11/20: Rickman: Re: Why not Lucent ORCA FGPAs?
18905: 99/11/21: Hal Murray: Re: Why not Lucent ORCA FGPAs?
18907: 99/11/20: Rickman: Re: Why not Lucent ORCA FGPAs?
18934: 99/11/22: Don Husby: Re: Why not Lucent ORCA FGPAs?
18944: 99/11/22: Ray Andraka: Re: Why not Lucent ORCA FGPAs?
18946: 99/11/22: Joseph H Allen: Re: Why not Lucent ORCA FGPAs?
18955: 99/11/22: Greg Neff: VHDL vs. schematic entry
18957: 99/11/22: Mike Treseler: Re: VHDL vs. schematic entry
18959: 99/11/22: Ray Andraka: Re: VHDL vs. schematic entry
18960: 99/11/23: <pladow@gocougs.wsu.edu>: Re: VHDL vs. schematic entry
19009: 99/11/24: Steve Rencontre: Re: VHDL vs. schematic entry
18976: 99/11/22: John Larkin: Re: VHDL vs. schematic entry
18983: 99/11/23: Ray Andraka: Re: VHDL vs. schematic entry
18990: 99/11/23: Greg Neff: Re: VHDL vs. schematic entry
18993: 99/11/23: rk: Re: VHDL vs. schematic entry
18999: 99/11/23: John Larkin: Re: VHDL vs. schematic entry
19017: 99/11/24: Greg Neff: Re: VHDL vs. schematic entry
19025: 99/11/24: John Larkin: Re: VHDL vs. schematic entry
19031: 99/11/25: Greg Neff: Re: VHDL vs. schematic entry
19032: 99/11/24: John Larkin: Re: VHDL vs. schematic entry
19047: 99/11/25: rk: Re: VHDL vs. schematic entry
19049: 99/11/25: Greg Neff: Re: VHDL vs. schematic entry
18992: 99/11/23: Mike Treseler: Re: VHDL vs. schematic entry
19095: 99/11/29: Dave Decker: Re: VHDL vs. schematic entry
19098: 99/11/29: Ray Andraka: Re: VHDL vs. schematic entry
18979: 99/11/23: rk: Re: VHDL vs. schematic entry
18987: 99/11/23: Robert Sefton: Re: VHDL vs. schematic entry
19000: 99/11/23: Ray Andraka: Re: VHDL vs. schematic entry
19005: 99/11/23: Bob Perlman: Re: VHDL vs. schematic entry
19007: 99/11/24: Jonathan Bromley: Re: VHDL vs. schematic entry
19020: 99/11/24: David G. Koontz: Re: VHDL vs. schematic entry
19024: 99/11/24: Rickman: Re: VHDL vs. schematic entry
19088: 99/11/28: <eml@riverside-machines.com.NOSPAM>: Re: VHDL vs. schematic entry
19113: 99/11/29: Stuart Clubb: Re: VHDL vs. schematic entry
19118: 99/11/30: Brian Drummond: Re: VHDL vs. schematic entry
19008: 99/11/23: <malino@primenet.com>: Re: VHDL vs. schematic entry
19079: 99/11/27: Rickman: Re: VHDL vs. schematic entry
19100: 99/11/29: Greg Neff: Re: VHDL vs. schematic entry
19106: 99/11/29: Keith Jasinski, Jr.: Re: VHDL vs. schematic entry
19115: 99/11/29: Ray Andraka: Re: VHDL vs. schematic entry
18913: 99/11/21: Robert Sefton: Re: Why not Lucent ORCA FGPAs?
18915: 99/11/21: Adam J. Elbirt: Re: Why not Lucent ORCA FGPAs?
18918: 99/11/21: Ray Andraka: Re: Why not Lucent ORCA FGPAs?
18923: 99/11/22: Rickman: Re: Why not Lucent ORCA FGPAs?
18932: 99/11/22: <a@z.com>: Re: Why not Lucent ORCA FGPAs?
18991: 99/11/23: Dragon: Re: Why not Lucent ORCA FGPAs?
19002: 99/11/23: Ray Andraka: Re: Why not Lucent ORCA FGPAs?
18924: 99/11/22: Rickman: Re: Why not Lucent ORCA FGPAs?
18939: 99/11/22: Robert Sefton: Re: Why not Lucent ORCA FGPAs?
18935: 99/11/22: Don Husby: Re: Why not Lucent ORCA FGPAs?
18823: 99/11/17: John Eaton: Actel FPGA prices
18836: 99/11/18: John Devereux: Re: Actel FPGA prices
18839: 99/11/18: Andy Peters: Re: Actel FPGA prices
18830: 99/11/18: ischoi(etri.re.kr): How can I specify the fanout constraints at FPGA compiler II & M1
18840: 99/11/18: myself: analog capabilities?
18849: 99/11/18: Ray Andraka: Re: analog capabilities?
18842: 99/11/18: Bonio Lopez: Not complett multipier LUT in FPGA
18843: 99/11/18: Bonio Lopez: Re: Not complett multipier LUT in FPGA
18850: 99/11/18: Ray Andraka: Re: Not complett multipier LUT in FPGA
18847: 99/11/18: <figluufg@which.net>: ROLLER GARAGE DOORS
18853: 99/11/19: OC team: HDL coders wanted
18857: 99/11/19: Paul Oh: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
18910: 99/11/21: Assaf Sarfati: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
18962: 99/11/23: <fuzzyyt@my-deja.com>: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
18950: 99/11/22: <a_maier@my-deja.com>: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
18862: 99/11/19: Matthias Fuchs: who to reset one-hot-fsm ?
18870: 99/11/19: Tom McLaughlin: Re: Programming Virtex device via JTAG
18927: 99/11/22: Michael Schmid: Re: Programming Virtex device via JTAG
18996: 99/11/23: Tom McLaughlin: Re: Programming Virtex device via JTAG
19038: 99/11/25: Michael Schmid: Re: Programming Virtex device via JTAG
19062: 99/11/26: Malachy Devlin: Programming Virtex device via JTAG
19041: 99/11/25: Bill Blyth: Re: Programming Virtex device via JTAG
19058: 99/11/26: Michael Schmid: Re: Programming Virtex device via JTAG
19059: 99/11/26: Rick Filipkiewicz: Re: Programming Virtex device via JTAG
19063: 99/11/26: Bill Blyth: Re: Programming Virtex device via JTAG
19086: 99/11/28: <eml@riverside-machines.com.NOSPAM>: Re: Programming Virtex device via JTAG
18872: 99/11/19: <info@r-and-d.de>: ARM7TDMI compatible synthesisable Module available
18880: 99/11/19: Jamie Sanderson: Virtex: Getting flip-flops into the pads
18881: 99/11/19: B. Joshua Rosen: Re: Virtex: Getting flip-flops into the pads
18882: 99/11/19: Bob Perlman: Re: Virtex: Getting flip-flops into the pads
18883: 99/11/19: Simon Goble: Re: Virtex: Getting flip-flops into the pads
18884: 99/11/19: Simon Goble: Re: Virtex: Getting flip-flops into the pads
18895: 99/11/20: <a@z.com>: Re: Virtex: Getting flip-flops into the pads
18904: 99/11/20: <simon_bacon@my-deja.com>: Re: Virtex: Getting flip-flops into the pads
18931: 99/11/22: John F Gostomski: Re: Virtex: Getting flip-flops into the pads
18936: 99/11/22: Jamie Sanderson: Re: Virtex: Getting flip-flops into the pads
18951: 99/11/22: Magnus Homann: Re: Virtex: Getting flip-flops into the pads
19080: 99/11/27: <rafeeqs@excite.com>: Re: Virtex: Getting flip-flops into the pads
19084: 99/11/28: Magnus Homann: Re: Virtex: Getting flip-flops into the pads
18972: 99/11/23: <simon_bacon@my-deja.com>: Re: Virtex: Getting flip-flops into the pads
18887: 99/11/20: Andrew M. Dyer: FPGA Compiler II Altera Edition vs. FPGA Express Xilinx
18888: 99/11/20: Austin Franklin: Xilinx FPGA Editor...does it really work?
18896: 99/11/20: <a@z.com>: Re: Xilinx FPGA Editor...does it really work?
18900: 99/11/20: Austin Franklin: Re: Xilinx FPGA Editor...does it really work
19378: 99/12/17: Ray Andraka: Re: Xilinx FPGA Editor...does it really work?
18898: 99/11/20: Rickman: Re: Xilinx FPGA Editor...does it really work?
18901: 99/11/20: Austin Franklin: Re: Xilinx FPGA Editor...does it really work?
18902: 99/11/20: Austin Franklin: Re: Xilinx FPGA Editor...does it really work?
18906: 99/11/20: Rickman: Re: Xilinx FPGA Editor...does it really work?
18891: 99/11/19: Bruce Nepple: Maybe this will help Xilinx Service Pack Downloads
18909: 99/11/21: <arafeeq@my-deja.com>: Synplify vs. FPGA Compiler II (v3.3)
18911: 99/11/21: Jonathon Hill: Brand New MUSIC
18914: 99/11/21: Erich Wagner: Altera JAM
18930: 99/11/22: Steve Rencontre: Re: Altera JAM
18937: 99/11/22: Bernard Esteban: Re: Altera JAM
18949: 99/11/22: <a_maier@my-deja.com>: Re: Altera JAM
18981: 99/11/23: <deroberts@my-deja.com>: Re: Altera JAM
18916: 99/11/21: Christof Paar: CHES 2000
18919: 99/11/22: Anthony Ellis - LogicWorks: PADS Experience?
18928: 99/11/22: Chiuj: Re: PADS Experience?
18933: 99/11/22: Theron Hicks: Re: PADS Experience?
18943: 99/11/22: Joseph H Allen: Re: PADS Experience?
18940: 99/11/22: John Larkin: Re: PADS Experience?
18947: 99/11/22: Tom Burgess: Re: PADS Experience?
19087: 99/11/28: <eml@riverside-machines.com.NOSPAM>: Re: PADS Experience?
18920: 99/11/22: Minhee Cho: IWDRS 2000 Final Call for Papers
18926: 99/11/22: Filip S. Balan: Trouble with ATMEL's AT40K20
18938: 99/11/22: Andy Peters: Re: Trouble with ATMEL's AT40K20
18982: 99/11/23: Filip S. Balan: Re: Trouble with ATMEL's AT40K20
18984: 99/11/23: Andy Peters: Re: Trouble with ATMEL's AT40K20
19011: 99/11/24: Filip S. Balan: Re: Trouble with ATMEL's AT40K20
19019: 99/11/24: Werner Dreher: Re: Trouble with ATMEL's AT40K20
19023: 99/11/24: Filip S. Balan: Re: Trouble with ATMEL's AT40K20
19021: 99/11/24: Andy Peters: Re: Trouble with ATMEL's AT40K20
19040: 99/11/25: Filip S. Balan: Re: Trouble with ATMEL's AT40K20
18929: 99/11/22: Duck Foot: Hierarchical Scan Insertion
19016: 99/11/24: Ravi Chandra Anantha: Re: Hierarchical Scan Insertion
18941: 99/11/22: <ritchie99_uk@my-deja.com>: Filter Coeficent and output quantisation
18942: 99/11/22: <ritchie99_uk@my-deja.com>: Filter Coefficient and Output Quantisation
18945: 99/11/22: Joseph H Allen: Re: Filter Coefficient and Output Quantisation
18953: 99/11/22: Austin Franklin: Xilinx changed the pinout of the download cable?
18954: 99/11/22: Michael G Wrighton: Virtex FIFO w/ Block RAM
18995: 99/11/23: Brian Philofsky: Re: Virtex FIFO w/ Block RAM
18997: 99/11/23: <kulak@my-deja.com>: Re: Virtex FIFO w/ Block RAM
18956: 99/11/22: Greg Neff: VHDL vs. schematic entry
18958: 99/11/23: Allan Herriman: Re: VHDL vs. schematic entry
18969: 99/11/23: Allan Herriman: Re: VHDL vs. schematic entry
18970: 99/11/23: Austin Franklin: Re: VHDL vs. schematic entry
18963: 99/11/23: <fuzzyyt@my-deja.com>: Re: VHDL vs. schematic entry
18965: 99/11/22: Ray Andraka: Re: VHDL vs. schematic entry
18977: 99/11/22: Phil Hays: Re: VHDL vs. schematic entry
18964: 99/11/23: <phil_jackson@my-deja.com>: Re: VHDL vs. schematic entry
18966: 99/11/23: Greg Neff: Re: VHDL vs. schematic entry
18978: 99/11/22: Phil Hays: Re: VHDL vs. schematic entry
18967: 99/11/22: John Doe: Re: VHDL vs. schematic entry
19033: 99/11/25: Robert Sefton: Re: VHDL vs. schematic entry
18994: 99/11/23: Jason T. Wright: Re: VHDL vs. schematic entry
18961: 99/11/22: Ray Andraka: Virtex mapper won't pack register with F5 combinatorial
18968: 99/11/22: John Doe: Leonardo Spectrum Printing Problem
19089: 99/11/28: <eml@riverside-machines.com.NOSPAM>: Re: Leonardo Spectrum Printing Problem
19190: 99/12/04: Ptarmigan: Re: Leonardo Spectrum Printing Problem
18980: 99/11/22: Haneef D. Mohammed: VHDL Simili from Symphony EDA adds support for Xilinx libraries
18985: 99/11/23: Edward Wallington: Anybody using Lucent OR3TP12?
19010: 99/11/24: Bryan Williams: Re: Anybody using Lucent OR3TP12?
19028: 99/11/24: Bruce Nepple: Re: Anybody using Lucent OR3TP12?
19046: 99/11/25: Edward Wallington: Lucent: OR3TP12, Some work arounds that we have found.
19083: 99/11/28: Bryan Williams: Re: Lucent: OR3TP12, Some work arounds that we have found.
19108: 99/11/29: Eric Crabill: Re: Anybody using Lucent OR3TP12?
19144: 99/12/01: Bruce Nepple: Re: backup fifo's
19159: 99/12/02: Eric Crabill: Re: backup fifo's
19185: 99/12/03: Rickman: Re: backup fifo's
19194: 99/12/04: Eric Crabill: Re: backup fifo's
19198: 99/12/05: Rickman: Re: backup fifo's
19214: 99/12/06: Eric Crabill: Re: backup fifo's
19221: 99/12/06: Bruce Nepple: Re: backup fifo's
19238: 99/12/07: Bruce Nepple: Re: backup fifo's(2)
19271: 99/12/09: Eric Crabill: Re: backup fifo's(2)
18986: 99/11/23: Jens Lauer: Hyperstones RiscDSP Eva Kit seems buggy
19012: 99/11/24: Bonio Lopez: Non-dedicated clock
19050: 99/11/25: Utku Ozcan: Re: Non-dedicated clock
19014: 99/11/24: Guido Pohl: MACH445 - parallel port programming cable
19015: 99/11/24: Guido Pohl: Re: MACH445 - parallel port programming cable
19103: 99/11/29: Stefan Wimmer: Re: MACH445 - parallel port programming cable
19018: 99/11/24: log: Obselete processor substitutes
19029: 99/11/25: jim granville: Re: Obselete processor substitutes
19030: 99/11/24: Franck Thierry: UTOPIA Interface on FPGA
19069: 99/11/26: Amal Khailtash: Re: UTOPIA Interface on FPGA
19034: 99/11/24: Volker Kalms: ALTERA EPC2 Configuration Help needed!
19136: 99/12/01: Edwin Grigorian: Re: ALTERA EPC2 Configuration Help needed!
19143: 99/12/01: Edwin Grigorian: Re: ALTERA EPC2 Configuration Help needed!
19035: 99/11/24: Volker Kalms: Configuration of ALTERA EPC2LC20 Please help!
19075: 99/11/27: <martin@the-thompsons.freeserve.co.uk>: Re: Configuration of ALTERA EPC2LC20 Please help!
19112: 99/11/29: Ying C.: Re: Configuration of ALTERA EPC2LC20 Please help!
19039: 99/11/25: Andy Pimentel: Ph.D. student position: Comp. Arch. Modelling & Simulation (Amsterdam)
19042: 99/11/25: Mark Harvey: R: How to use multiple resets?
19043: 99/11/25: Mariotto: CIC Filters in FPGA
19081: 99/11/28: Dave Decker: Re: CIC Filters in FPGA
19379: 99/12/17: Ray Andraka: Re: CIC Filters in FPGA
19616: 00/01/04: Morgan Colmer: Re: CIC Filters in FPGA
19085: 99/11/28: Antonio Garcia: Re: CIC Filters in FPGA
19044: 99/11/25: Bonio Lopez: async latch implementation in Leonardo
19048: 99/11/25: Bonio Lopez: Re: async latch implementation in Leonardo
19051: 99/11/25: Bonio Lopez: Re: async latch implementation in Leonardo
19090: 99/11/28: <eml@riverside-machines.com.NOSPAM>: Re: async latch implementation in Leonardo
19045: 99/11/25: Gordon Hollingworth: LOC's RLOC's and Virtex
19094: 99/11/29: Ray Andraka: Re: LOC's RLOC's and Virtex
19052: 99/11/25: <arafeeq@my-deja.com>: Xilinx Virtex design (xcv-800) into production
19101: 99/11/29: John F Gostomski: Re: Xilinx Virtex design (xcv-800) into production
19056: 99/11/25: Luigi: Analog
19057: 99/11/26: Mark Summerfield: Re: Analog
19065: 99/11/26: myself: Re: Analog
19068: 99/11/26: Jonathan Bromley: Re: Analog
19060: 99/11/26: Bonio Lopez: How one can use level sensitive latches
19061: 99/11/26: Ahmad A.: HDL editor?
19067: 99/11/26: Bob Perlman: Re: HDL editor?
19070: 99/11/26: Rick Filipkiewicz: Re: HDL editor?
19097: 99/11/29: <deroberts@my-deja.com>: Re: HDL editor?
19107: 99/11/29: B. Joshua Rosen: Re: HDL editor?
19141: 99/12/02: <rajesh52@hotmail.com>: Re: HDL editor?
19337: 99/12/14: <kulak@my-deja.com>: Re: HDL editor?
19064: 99/11/26: rk: slightly OT ...
19066: 99/11/26: Marco Sanvido: Re: HDL Editor
19071: 99/11/26: Austin Franklin: Xilinx FPGA Editor guessing games solved!
19073: 99/11/27: Rickman: Re: Xilinx FPGA Editor guessing games solved!
19074: 99/11/27: Austin Franklin: Re: Xilinx FPGA Editor guessing games solved!
19078: 99/11/27: Rickman: Re: Xilinx FPGA Editor guessing games solved!
19082: 99/11/28: Austin Franklin: Re: Xilinx FPGA Editor guessing games solved!
19111: 99/11/29: Steve Dewey: Re: Xilinx FPGA Editor guessing games solved!
19125: 99/11/30: Ray Andraka: Re: Xilinx FPGA Editor guessing games solved!
19072: 99/11/27: Mahboob Ahmed: Siemens HSCX development tools.
19076: 99/11/28: Chung Yew Liang: Great way to get a new hardware and its free
19091: 99/11/29: <ipreuse@my-deja.com>: Announcement: Opportunities at Intellectual Property Reuse/System-On-A-Chip Start Up Company
19093: 99/11/29: <fidonews2@my-deja.com>: FS: New Altera MAX+Plus II 9.01 $1000
19096: 99/11/29: Pat: ClearLogic Vs. Altera
19110: 99/11/29: Scott I. Chase: Re: ClearLogic Vs. Altera
19168: 99/12/03: ycp: ghd
19099: 99/11/29: George: FPGA vs DSP vs PENTIUM MMX
19102: 99/11/29: Ray Andraka: Re: FPGA vs DSP vs PENTIUM MMX
19104: 99/11/29: Steven Derrien: Re: FPGA vs DSP vs PENTIUM MMX
19114: 99/11/29: Ray Andraka: Re: FPGA vs DSP vs PENTIUM MMX
19116: 99/11/30: Steven Derrien: Re: FPGA vs DSP vs PENTIUM MMX
19119: 99/11/30: Ray Andraka: Re: FPGA vs DSP vs PENTIUM MMX
19120: 99/11/30: Steven Derrien: Re: FPGA vs DSP vs PENTIUM MMX
19122: 99/11/30: Arrigo Benedetti: Re: FPGA vs DSP vs PENTIUM MMX
19124: 99/11/30: Ray Andraka: Re: FPGA vs DSP vs PENTIUM MMX
19128: 99/12/01: Steven Derrien: Re: FPGA vs DSP vs PENTIUM MMX
19133: 99/12/01: Ray Andraka: Re: FPGA vs DSP vs PENTIUM MMX
19137: 99/12/01: Steven Derrien: Re: FPGA vs DSP vs PENTIUM MMX
19149: 99/12/02: Jonathan Bromley: Re: FPGA vs DSP vs PENTIUM MMX
19109: 99/11/29: <tronsmith@my-deja.com>: Re: FPGA vs DSP vs PENTIUM MMX
19127: 99/12/01: George: Re: FPGA vs DSP vs PENTIUM MMX
19138: 99/12/01: Joel Kolstad: Re: FPGA vs DSP vs PENTIUM MMX
19105: 99/11/29: Milliwave: Using Altera to pipeline a CLA adder
19117: 99/11/30: Steven Derrien: AGP based FPGA board
19121: 99/11/30: <ipreuse@my-deja.com>: IP Reuse/System-On-A-Chip Start Up Company
19123: 99/11/30: <sonic@sega.net>: Free classified ads
19126: 99/11/30: Rune Baeverrud: Here are the BEST and MOST IMPORTANT books on VHDL
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