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Hi,
this is a very interesting matter. Still I haven't understood the way
you reach different speed grades in the same FPGA family. For example I
am involved in a project using the FPGA XC4025E-4. What is the physical
difference with XC4025E-3 and -2 ? Are they implemented using a
different technology ?
Thanks.
Regards,
Davide
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Davide Falchieri
Physics Department, Bologna University
40127,Viale Berti Pichat 6/2, Bologna(ITALY)
TEL:+39-051-2095077, FAX:+39-051-2095297
URL:http://sunvlsi4.bo.infn.it/~davide
mailto:davide.falchieri@bo.infn.it
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 19376
Peter Alfke wrote:
> [ explanation on former physicalrelationship to speed grade ]
> You have to look up the
> individual parameters. Maybe the logic gets much faster, but the interconnect
> less so. Or it's ( more rarely) the other way around. But you can be assured
> that no parameter in a better speed grade is ever slower than it was in the
> slower speed grade. So we guarantee monotonicity, but that's all.
> Don't equate a -2 in one family with a -2 in another family, although in the
> XC4000 series, this is pretty close.
> I think this reasoning holds for our competitors as well. We are all in the
> same boat.
Note that within the same family some timing parameters depend on the
chip size, namely those associated with routing along a chip dimension
(or half ..)
Especially in the XILINX 4k family the usage of the long lines
(e.g. for tristate busses) gets slower in larger devices.
(This is obvious).
In ALTERA FLEX 10K devices nearly all routing uses wires of chip
dimension,
thus if you integrate two smaller designs into a larger device
you have to go to a better, say more expensive speed grade.
Otherwise your design will be propably much slower.
In XILINX 4k devices most routing resources have a fixed size and do not
depend in speed from the chip size.
If you want to know pin2pin delays you must specify the distance of the
pins.
Andreas
(having applied FLEX 10k and XC4kXV)
-----------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 19377http://members.home.nl/stoelie http://members.home.nl/stoelie a good page for all !Article: 19378
a@z.com wrote: > Hi Austin, > > First use File/Main Properties to turn the Edit Mode to Read Write (it is Read > Only by default). > > Then zoom in to your CLB (Ctrl-Right Click - and by the way zoom out is > Shift-Ctrl-Right Click!) and select your CLB pin. Then find your net in the > All Nets List (you can sort them by name) and Shith-Click to select it (if you > just Click the pin will be deselected). Press the add button and wait. Then > wait some more and when you least expect it your pin will be connected to that > net. Of course, you must first configure the CLB pin and then add it to the > net, otherwise it will just give you an error. You can also add multiple pins > to a net this way (using Shift-Click). > > Now for the CLB equation problem. Select the CLB, press the editblock button > and in the Block Editor window the F= toolbar button. Edit Feqn and Geqn and > press the Save Changes and Closes Window toolbar button. It works for me. > For the equations you need to call the pins A1 - A4, not F1 to F4. Also, you need to check the check box on the LUT to set it as a LUT before it will accept the equations. > By the way, what I have described is valid for the M2.1i FPGA Editor, the > M1.5i EPIC Design Editor, of NeoCAD origin, although similar is a different > beast (which never realy worked). The M2.1i version is a complete rewrite and > crashes less. I agree that the user interface is a bit strange. > Less is a relative term. It still crashes way more than any of the XACT tools ever did. > Catalin Baetoniu > > Austin Franklin wrote: > > > I have a Virtex design, I just wanted to add a damn pin to, and for the > > life of me, even following the documentation..I just can't get it to work. > > I want to add the SR pin of a CLB to an existing net...and it asks me for > > the name of the net...and I type it, and it says it already exists...which > > is true...but duh, it's what I want. > > > > Also, I tried editing the equations in the CLB, and I can put in 0 or 1, > > but not F4 ANYTHING but 0 or 1. > > > > Is this tool just sadly broken, or just too obtuse for a somewhat > > intelligent 12 year Xilinx veteran to use? I never had this kind of > > difficulty with the non-NeoCAD based editor... The answer is yes. The editor is a little obtuse, especially for those of us who have used XDE in past lives. Then again, XDE was no model of user friendliness either. I think we've probably forgotten the learning curve that went with XDE. On the other hand, XDE didn't crash the way the 2.1 editor still does. Frankly, I've been getting quite frustrated with the M2.1 tools for 'expert mode' design, especially for Virtex. I hate spending my time chasing tool problems. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19379
CIC is just a rearrangement of the equation for a boxcar filter to get a recursive implementation. A boxcar is an FIR filter with all the coefficients set to unity (sometimes called a moving average filter). Hogenauer's paper introduces the filters and goes into considerable discussion on errors caused by truncation. I found it a somewhat less than easy read. Marvin Frerking's DSP in Communications text (kluwer) has a much more readable discussion on CIC filters. These work pretty well in FPGAs if the sinc spectral response suits your application. They are really handy for high order interpolation and decimation. If you cascade several, you do need to watch the wordsize. You have to be extremely careful about truncating or your integrator will overflow. Dave Decker wrote: > Eugene B. Hogenauer's paper, 'An Economical Class of Digital Filters > for Decimation and Interpolation' was published in: > IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. > ASSP-29, NO. 2, April 1981. > > The Cascaded Integrator-Comb (CIC) filters work well in FPGAs whenever > you have to interpolate or decimate 2's compliment signals while > lowpass filtering them at the same time. The filters give the response > of FIR filters with all the coefficients set to 1. These are also > called 'box car' filters because their impulse response looks like a > rectangular box car. This type of filter requires no real > multiplication, which makes them relatively small and well suited for > FPGAs. > > The CIC implementation avoids the use of long shift register delay > lines you might think would be necessary for such a filter. This > efficiency is compounded because of the decimation/interpolation > especially when the CIC stages are cascaded. > > The architecture consists of accumulators, subtractors, and a small > number of pipeline delays. A 'must have' addition to your DSP bag of > tricks. > > Dave Decker > Diablo Research Co. LLC > > On Thu, 25 Nov 1999 10:57:12 GMT, "Mariotto" <mariotto@libero.it> > wrote: > > >Where I could find information on realizations of CIC filters supposed from > >E.B. Hogenauer in FPGA? > >Thank you. > > > >Claudio Casagrande > > > >e-mail:mariotto@libero.it > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19380
Hi friends, where can i find JEDEC standarts? with best regards, * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 19381
jeffrey j cook wrote: > Well I'm looking for the XCV50E,150E or 300E. This is simply for a small > project and I only require about 24-48 of them. > > > Jeffrey J. Cook > University of Illinois Computer Engineering Student > jjcook@uiuc.edu > According to my Avnet rep the only parts available now are the XCV300E & XCV1500E.Article: 19382
Søren Lambæk wrote in message ...
>Hi
>
<snip>
>My question is can someone point me in the right direction on how to
include
>the FPGA code in the C source kode of
>the microcontroller SW.
>
>Regards
>Søren Lambæk
I did this by:
1) Making a motorola s-record file for you Xilinx data using the prom
formatter program
2) Running that s-rec file thru a utility that converts it to a 'C' data
structure... I found a program that does this on http://www.wotsit.org/ in
a file called srec (see attached, also). It's source code, so you'll need a
'C' compiler for your PC...
3) Include that file in your microcontroller software and write a routine to
bit-bash the Spartan's configuration port... I found it helpful to be able
to compare my design with the signals from the Xilinx parallel cable...
Good Luck,
John
begin 666 srec.zip
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Article: 19383Bonio Lopez wrote in message <034f2f50.5d2a433f@usw-ex0102-009.remarq.com>... >Hi friends, >where can i find JEDEC standarts? Would you believe: http://www.jedec.org/ -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu The secret of Slurm is on a need-to-know basis.Article: 19384
Davide Falchieri wrote: > Hi, > this is a very interesting matter. Still I haven't understood the way > you reach different speed grades in the same FPGA family. For example I > am involved in a project using the FPGA XC4025E-4. What is the physical > difference with XC4025E-3 and -2 ? Are they implemented using a > different technology ? > There is no "physical difference" between devices with the same designation ( and made at the same time ) but different speed designators. Speed grades are created by testing the packaged devives and "binning" them, i.e. depending on the test results, feeding them into separate containers. It's just a selection process. Modern processing has a very narrow spread, which means that there is not much speed difference between the fastest and the slowest parts in a manufacturing run. This creates an interesting problem: Our industry often has no yield to the slowest spec, all parts are faster. But there are orders for slow parts. So everybody solves this problem by down-binning, i.e. marking a fast part as slow, and selling it at the usually lower price of a slow part. To the buyer, this may look like a bargain, getting a Porsche for the price of a VW. But it can get the design in trouble if "dirty asynchronous tricks" were used. Always assume that the part you buy tomorrow may be faster than the one you bought yesterday. That's why we are advocating synchronous design methods... Peter Alfke, Xilinx ApplicationsArticle: 19385
Gurus, I am encountering some difficulties with inserting global buffers on internal clocks in my FPGA design. My current flow is Synplify for synthesis, then Altera MaxPlusII to target a Flex10K FPGA. It appears that Synplify will NOT automatically insert a global buffer onto an internal clock, for my Flex10K, even if it finds the internal clock. (IT DOES seem to do this for Xilinx FPGA's, though! The Xilinx global buffer gets embedded right into the output EDIF. Not so for Flex10K.) Is there a way to make Synplify do this automatically for all target devices? (A Flex10K has 4 global buffers that may be used for internal signals.) Of course, this global buffer insertion can be done manually in MaxPlusII, but it is quite cumbersome, for a couple reasons. First, the (MaxPlusII internal) name of the net is not known until you get through the fitter, and the .rpt file is output, stating the (names of the) inferred clocks. Only then can you insert a statement in the <design>.acf file, inserting a global buffer onto some oddly-named net like "core~239~7." Then, you have to re-run maxPlusII just so it recognizes your global buffer! Secondly, of course this MaxPlusII name will change if you go back through the flow and resynthesize. Then you have to repeat the process to find the *new* MaxPlusII name for your internal clock! Then modify your .acf file, and re-run again! Any ideas? Can I get Synplify to insert the buffer manually, for Flex10K? And if not, is there a way to refer to my internal clock by the same name every time through the flow, in MaxPlusII. Thanks for any ideas. Matt GavinArticle: 19386
Hi there,
I have some problem simulating XDW components for Virtex-FPGAs.
I am synthesizing my design with Synopsys Behavioral Compiler and
Synopsys Design Compiler.
Simulating behavioral- and rt-level (behavioral-compiler-"schedule"d)
works well. Even the backannotated vhdl-output from xilinx's
design-manager works correctly, but the simulation of the
synopsys-"compile"d rt-level-code produces messages like
Warning: vhdlsim,105:
/TB_E/BSPMULT_INST/MUL_NS_UNS_106_MUL_51/MU04/LA0_11/A_LUTI/COMPONENT
was
not instanced because it is unbound.
where
A_LUTI : DWLUT2 port map( I0 => A(23), I1 => B0, O => SUM_4_port);
and DWLUT2 is
component DWLUT2
port( I0, I1 : in std_logic; O : out std_logic);
end component;
Unfortunately this component is not available in all our SYNOPSYS and
XILINX directory trees.
When forcing the use of normal DW-components instead of XDW-components
all simulation-levels work without problems.
Has anyone advice?
Greetings
Mark
Article: 19387I had a boss several years ago that had a big sign hung in his office that read "SPEED KILLS". He had been burned by several projects which started failing new production runs of old designs because of those very same asynchronous dirty tricks. Peter Alfke wrote: > Davide Falchieri wrote: > > > Hi, > > this is a very interesting matter. Still I haven't understood the way > > you reach different speed grades in the same FPGA family. For example I > > am involved in a project using the FPGA XC4025E-4. What is the physical > > difference with XC4025E-3 and -2 ? Are they implemented using a > > different technology ? > > > > There is no "physical difference" between devices with the same > designation ( and made at the same time ) but different speed designators. > Speed grades are created by testing the packaged devives and "binning" > them, i.e. depending on the test results, feeding them into separate > containers. It's just a selection process. > Modern processing has a very narrow spread, which means that there is not > much speed difference between the fastest and the slowest parts in a > manufacturing run. This creates an interesting problem: > Our industry often has no yield to the slowest spec, all parts are faster. > But there are orders for slow parts. So everybody solves this problem by > down-binning, i.e. marking a fast part as slow, and selling it at the > usually lower price of a slow part. > To the buyer, this may look like a bargain, getting a Porsche for the > price of a VW. But it can get the design in trouble if "dirty asynchronous > tricks" were used. > Always assume that the part you buy tomorrow may be faster than the one > you bought yesterday. That's why we are advocating synchronous design > methods... > > Peter Alfke, Xilinx Applications -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19388
Is anyone else running Altera's Quartus 99.10 SP1 under Windows NT 4.0 SP4 and having miserable problems? If I try tweaking any design options I consistently get internal errors during compiles . Tech Support doesn't say much except that "it" will be fixed in the next release? I reverted back to 99.06 SP 2 and am having none of the problems I had using 99.10. Just curious.Article: 19389
> Is anyone else running Altera's Quartus 99.10 SP1 under Windows NT 4.0 SP4 > and having miserable problems? If I try tweaking any design options I > consistently get internal errors during compiles . Tech Support doesn't say > much except that "it" will be fixed in the next release? > > I reverted back to 99.06 SP 2 and am having none of the problems I had using > 99.10. I just took a crap, and it spelt Q U A R T U S. No, all joking aside here, I have had ENDLESS problems with it crashing using 99.10 SP1 under NT 4.0 SP4. I turfed the SP1 and went back to old 99.10. I only had 2 crashes today....a new record. Trust me my friend...those internal errors arn't going anywhere fast.... My other tip for you....I was talking with Tech support, and they said the best thing is to run the tool with TCL scripts. I figured that was the route I was going to have to take anyway - that Timing Wizard does not nearly constrain the stuff I need, etc. If your problems were "solved" using 99.06 SP2, then I might have to give that a try. Thanks for the tip. Regards, XanatosArticle: 19390
thanks bill. spyng > ---------- > From: Bill Blyth[SMTP:bb@alphadata.co.uk] > Posted At: Thursday, December 16, 1999 6:09 PM > Posted To: comp.arch.fpga > Conversation: Virtex boards > Subject: Re: Virtex boards > > The RC1000-PP and ADC-RC1000 are identical. The board was designed by > Alpha Data for Embedded Solutions to support their Handel-C compiler > and is sold by both companies. > > Alpha Data specialise in design of hardware and produce the ADM-XRC > mezzanine card which also supports Virtex from V400 to V1000 and > Virtex- > e. > > In article > <0CF260C495FED111A6610000F866308D07D13C9D@mail3.ntu.edu.sg>, > Oh Sheau Pyng <ASSPOh@ntu.edu.sg> wrote: > > hi, > > "Rc1000-pp" from embedded system look actually the same board as > the > > one in Alpha Data "ADC-RC1000", even the technical brief is > idenitical. > > > > Any one know whats the different ? Is the design from Alpha Data > or > > Embedded System? > > I have order one "ADC-RC000" with a xcv1000 from Alpha Data, which > > have not arrived yet. > > > > spyng > > > > > ---------- > > > From: unknown@bits.bris.ac.uk (Address not > > > verified)[SMTP:unknown@bits.bris.ac.uk] on behalf of Tim > > > Tyler[SMTP:tt@cryogen.com] > > > Reply To: tt@cryogen.com > > > Posted At: Wednesday, December 15, 1999 3:05 AM > > > Posted To: comp.arch.fpga > > > Conversation: Virtex boards > > > Subject: Re: Virtex boards > > > > > > Daryl Bradley <dwb105@nospam.ohm.york.ac.uk> wrote: > > > > > > [snip 3 VCC boards] > > > > > > : We have just ordered a PCI based XCV1000 board form embedded > > > solutions - > > > : have heard this is pretty good but no hands on experience yet > > > > > > Embedded Solutions' RC1000-PP board - suitable for Virtex: > > > http://www.embeddedsol.com/tech_info_3.htm > > > > > > Embedded Solutions' "Special Offer to universities": > > > http://www.embeddedsol.com/programs/academic/uni_offer.htm > > > > > > ``In partnership with the Xilinx University Program, Xilinx are > > > supplying a limited number of the Virtex XCV1000 parts free of > > > charge as a donation for suitable teaching/research projects. > > > > > > ESL is mounting these devices on the RC1000-PP reconfigurable > > > computing PCI board enabling this top end version of the > > > RC1000-PP to be offered at a very substantial discount on the > > > standard university discounted price.'' > > > -- > > > __________ > > > |im |yler The Mandala Centre http://www.mandala.co.uk/ > > > tt@cryogen.com > > > > > > It is a miracle whenever curiosity survives a formal education. > > > > > > > > > -- > ----------------------------- > Alpha Data Parallel Systems Ltd. > http://www.alphadata.co.uk > ----------------------------- > > > Sent via Deja.com http://www.deja.com/ > Before you buy. >Article: 19391
There is a recent discussion on the computer chess club internet forum about
the feasibility of creating a chess chip using FPGA. Now, a chess chip
*must* have very fast access to large amounts of shared memory, and also be
able to execute an instruction set (much like a general purpose CPU -- but
the instruction set is {of course} specialized for chess).
My question:
Is it a good idea to attempt this with an FPGA, or should a general purpose
CPU be fabricated or should it be done with something else entirely?
--
C-FAQ: http://www.eskimo.com/~scs/C-faq/top.html
"The C-FAQ Book" ISBN 0-201-84519-9
C.A.P. Newsgroup http://www.dejanews.com/~c_a_p
C.A.P. FAQ: ftp://38.168.214.175/pub/Chess%20Analysis%20Project%20FAQ.htm
Article: 19392
The chess processor as you describe would be sensible in an FPGA. Current
offerings have extraordinary logic densities, and some of the newer FPGAs have
over 500K of on-chip RAM which can be arranged as a very wide memory. Some of
the newest parts have several million 'marketing' gates available too. FPGAs
have long been used as prototyping platforms for custom silicon.
If I were doing such I design in an FPGA however, I would look deeper to see
what algorithmic changes could be done to take advantage of the parallelism
offered by the FPGA architecture. Usually that means moving away from a
traditional GP CPU architecture which is limited by the inherently serial
instruction stream. If you are trying to mimic the behavior of a CPU, you would
possibly do better with a fast CPU, as you will get be able to run those at a
higher clock rate. The FPGA gains an advantage over CPUs when you can take
advantage of parallelism to get much more done in a clock cycle than you can
with a CPU.
That said, I wouldn't recommend that someone without a sound footing in
synchronous digital logic design take on such a project. Ideally the designer
for something like this is very familiar with the FPGA architecture and tools
(knows what does and doesn't map efficiently in the FPGA architecture), and is
conversant in computer architecture and design and possibly has some pipelined
signal processing background (for exposure to hardware efficient algorithms,
which are usually different than ones optimized for software).
Dann Corbit wrote:
> There is a recent discussion on the computer chess club internet forum about
> the feasibility of creating a chess chip using FPGA. Now, a chess chip
> *must* have very fast access to large amounts of shared memory, and also be
> able to execute an instruction set (much like a general purpose CPU -- but
> the instruction set is {of course} specialized for chess).
>
> My question:
> Is it a good idea to attempt this with an FPGA, or should a general purpose
> CPU be fabricated or should it be done with something else entirely?
> --
> C-FAQ: http://www.eskimo.com/~scs/C-faq/top.html
> "The C-FAQ Book" ISBN 0-201-84519-9
> C.A.P. Newsgroup http://www.dejanews.com/~c_a_p
> C.A.P. FAQ: ftp://38.168.214.175/pub/Chess%20Analysis%20Project%20FAQ.htm
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 19393"Ray Andraka" <randraka@ids.net> wrote in message news:385B1DEE.7517AAC7@ids.net... > The chess processor as you describe would be sensible in an FPGA. Current > offerings have extraordinary logic densities, and some of the newer FPGAs have > over 500K of on-chip RAM which can be arranged as a very wide memory. Some of > the newest parts have several million 'marketing' gates available too. FPGAs > have long been used as prototyping platforms for custom silicon. I am curious about the memory. Chess programs need to access at least tens of megabytes of memory. This is used for the hash tables, since the same areas are repeatedly searched. Without a hash table, the calculations must be performed over and over. Some programs can even access gigabytes of ram when implemented on a mainframe architecture. Is very fast external ram access possible from FPGA's? > If I were doing such I design in an FPGA however, I would look deeper to see > what algorithmic changes could be done to take advantage of the parallelism > offered by the FPGA architecture. Usually that means moving away from a > traditional GP CPU architecture which is limited by the inherently serial > instruction stream. If you are trying to mimic the behavior of a CPU, you would > possibly do better with a fast CPU, as you will get be able to run those at a > higher clock rate. The FPGA gains an advantage over CPUs when you can take > advantage of parallelism to get much more done in a clock cycle than you can > with a CPU. The ability to do many things at once may be a huge advantage. I don't really know anything about FPGA's, but I do know that in chess, there are a large number of similar calcutions that take place at the same time. The more things that can be done in parallel, the better. > That said, I wouldn't recommend that someone without a sound footing in > synchronous digital logic design take on such a project. Ideally the designer > for something like this is very familiar with the FPGA architecture and tools > (knows what does and doesn't map efficiently in the FPGA architecture), and is > conversant in computer architecture and design and possibly has some pipelined > signal processing background (for exposure to hardware efficient algorithms, > which are usually different than ones optimized for software). I am just curious about feasibility, since someone raised the question. I would not try such a thing by myself. Supposing that someone decided to do the project (however) what would a rough ball-park guestimate be for design costs, the costs of creating the actual masks, and production be for a part like that? -- C-FAQ: http://www.eskimo.com/~scs/C-faq/top.html "The C-FAQ Book" ISBN 0-201-84519-9 C.A.P. Newsgroup http://www.dejanews.com/~c_a_p C.A.P. FAQ: ftp://38.168.214.175/pub/Chess%20Analysis%20Project%20FAQ.htmArticle: 19394
Dann With today's technology an FPGA can easily evaluate, for instance, the (one-level) threats to all pieces on the board _in parallel_ at, say, 50MHz to 100MHz, depending on the metric used to quantify 'threat'. This is probably equivalent to mucho conventional MIPs if FPGA-friendly algorithms exist. Driving a bunch of DIMMs from an FPGA is pretty straightforward. However, the big win comes from using on-chip resources in as parallel a mode as your imagination can conjure, as Ray noted. Typically on-chip memory is a bunch of small blocks of a few KBytes each, with memory widths from 8 bits to 200+ bits, together with zillions of really small memories in the 16x1 range. Logic densities can be huge - thousands of primitive operations in parallel at the rated clock speed. Using the available density is one place where the designer's ingenuity comes in. Could you post a few examples of the sort of primitives you would like to see a Chess Machine execute. As for the cost, much of the design work can be done with a student edition of a manufacturer's toolset, at a cost of around $100. Of course, building a real board would be $2000++, plus whatever your time costs. Professional help in this area is expensive. Depending on the design, it may be possible to use a manufacturer's evaluation board. There are no charges for mask sets; there are no masks. An FPGA is typically configured at power-on from a processor or from a comms link of some sort. Hope this helps...Article: 19395
Dann Corbit wrote: > "Ray Andraka" <randraka@ids.net> wrote in message > news:385B1DEE.7517AAC7@ids.net... > > The chess processor as you describe would be sensible in an FPGA. Current > > offerings have extraordinary logic densities, and some of the newer FPGAs > have > > over 500K of on-chip RAM which can be arranged as a very wide memory. > Some of > > the newest parts have several million 'marketing' gates available too. > FPGAs > > have long been used as prototyping platforms for custom silicon. > > I am curious about the memory. Chess programs need to access at least tens > of megabytes of memory. This is used for the hash tables, since the same > areas are repeatedly searched. Without a hash table, the calculations must > be performed over and over. Some programs can even access gigabytes of ram > when implemented on a mainframe architecture. Is very fast external ram > access possible from FPGA's? This is conventional CPU thinking. With the high degree of parallelism in the FPGA and the large amount of resources in some of the more recent devices, it may very well be that it is more advantageous to recompute the values rather than fetching them. There may even be a better approach to the algorithm that just isn't practical on a conventional CPU. Early computer chess did not use the huge memories. I suspect the large memory is more used to speed up the processing rather than a necessity to solving the problem. > > > > If I were doing such I design in an FPGA however, I would look deeper to > see > > what algorithmic changes could be done to take advantage of the > parallelism > > offered by the FPGA architecture. Usually that means moving away from a > > traditional GP CPU architecture which is limited by the inherently serial > > instruction stream. If you are trying to mimic the behavior of a CPU, you > would > > possibly do better with a fast CPU, as you will get be able to run those > at a > > higher clock rate. The FPGA gains an advantage over CPUs when you can > take > > advantage of parallelism to get much more done in a clock cycle than you > can > > with a CPU. > > The ability to do many things at once may be a huge advantage. I don't > really know anything about FPGA's, but I do know that in chess, there are a > large number of similar calcutions that take place at the same time. The > more things that can be done in parallel, the better. Think of it as a medium for creating a custom logic circuit. A conventional CPU is specific hardware optimized to perform a wide variety of tasks, none especially well. Instead we can build a circuit the specifically addresses the chess algorithms at hand. Now, I don't really know much about the algorithms used for chess. I suspect one would look ahead at all the possibilities for at least a few moves ahead and assign some metric to each to determine the one with the best likely cost/benefit ratio. The FPGA might be used to search all the possible paths in parallel. > > That said, I wouldn't recommend that someone without a sound footing in > > synchronous digital logic design take on such a project. Ideally the > designer > > for something like this is very familiar with the FPGA architecture and > tools > > (knows what does and doesn't map efficiently in the FPGA architecture), > and is > > conversant in computer architecture and design and possibly has some > pipelined > > signal processing background (for exposure to hardware efficient > algorithms, > > which are usually different than ones optimized for software). > I am just curious about feasibility, since someone raised the question. I > would not try such a thing by myself. > > Supposing that someone decided to do the project (however) what would a > rough ball-park guestimate be for design costs, the costs of creating the > actual masks, and production be for a part like that? The nice thing about FPGAs is that there is essentially no NRE or fabrication costs. The parts are pretty much commodity items, purchased as generic components. The user develops a program consisting of a compiled digital logic design, which is then used to field customize the part. Some FPGAs are programmed once during the product manufacturer (one time programmables include Actel and Quicklogic). Others, including the Xilinx line, have thousands of registers that are loaded up by a bitstream each time the device is powered up. The bitstream is typically stored in an external EPROM memory, or in some cases supplied by an attached CPU. Part costs range from under $5 for small arrays to well over $1000 for the newest largest fastest parts. The design effort for the logic circuit you are looking at is not trivial. For the project you describe, the bottom end would probably be anywhere from 12 weeks to well over a year of effort depending on the actual complexity of the design, the experience of the designer with the algorithms, FPGA devices and tools. > -- > C-FAQ: http://www.eskimo.com/~scs/C-faq/top.html > "The C-FAQ Book" ISBN 0-201-84519-9 > C.A.P. Newsgroup http://www.dejanews.com/~c_a_p > C.A.P. FAQ: ftp://38.168.214.175/pub/Chess%20Analysis%20Project%20FAQ.htm -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19396
On Sat, 18 Dec 1999 01:24:39 -0700, "Simon Bacon" <simon@tile.demon.co.uk.notreally> wrote: >Dann > >snip >Could you post a few examples of the sort of primitives you >would like to see a Chess Machine execute. > >snip The partition between the work done by the micro or DSP and the work done by the FPGA, is usually best made giving the micro the more complex algorithmic jobs and giving the FPGA the compute intensive, but algorithmicly simple, repetitive, flow through tasks. Chess programs have to: Generate a tree of all possible moves from the current position for a depth of a few generations, the more the better. Prune that tree so that stupid moves are not investigated, giving time for more interesting moves to be probed to more generations. As each new possible future board position is postulated it must be evaluated. It seems that one first task the FPGA could do is to evaluate a board position and return its merit. If that's not enough work, perhaps the FPGA could also generate a list of every possible next half move and return that list. The micro would be used for the more complex task of pruning the tree and sending the next position to be evaluated to the FPGA(s). The micro would need access to big memory. The FPGA would just run a subroutine, without need to reference the history or progress of the overall algorithm. Why not ask around on some the chess news groups like: rec.games.chess.computer to see what part of computer programs use the most time, and then see if the FPGA's power could help speed up one of those bottlenecks. Dave Decker there is only one 'h' in my email adrArticle: 19397
In article <385bc858.108486125@news.slip.net>, mushh@slip.net (Dave Decker) wrote: > On Sat, 18 Dec 1999 01:24:39 -0700, "Simon Bacon" > <simon@tile.demon.co.uk.notreally> wrote: > Why not ask around on some the chess news groups like: > rec.games.chess.computer > to see what part of computer programs use the most time, and then see > if the FPGA's power could help speed up one of those bottlenecks. Actually this came from CCC which is like rec.games.chess.computer but with a much better signal to noise ratio. (http://www.icdchess.com/ , and you have to join up but it's free.) Over on CCC there are plently of people who understand chess programs and their bottlenecks. But not many who know about FPGAs. And the ones that do know a bit about FPGAs seem to be badly out of date. From the answers here it seems FPGAs would do the job much better than some people on CCC (including me) thought it could be done. Thanks for the help. There is also someone who knows someone who probably knows FPGAs and doesn't know computer chess. We are trying to understand each other enough to see if we can do a joint project :-) Computer chess consists of a tree search which is easiest done serially. But there are service subroutines you need to call at every node in the tree that could have a lot of internal parallelism. Most notable are the static evaluator for end-node positions, and the move generate and sort. Both of those could eat huge numbers of gates to work faster and better, especially the evaluator. The tree search engine though would probably run on a simple general purpose CPU that you would build in the FPGA somewhere so it would have very fast access to the special purpose parts. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19398
Peter Alfke ha scritto nel messaggio <385A7561.F990F364@xilinx.com>... >To the buyer, this may look like a bargain, getting a Porsche for the >price of a VW. But it can get the design in trouble if "dirty asynchronous >tricks" were used. >Always assume that the part you buy tomorrow may be faster than the one >you bought yesterday. That's why we are advocating synchronous design >methods... > >Peter Alfke, Xilinx Applications > Peter, can you explain what are the "dirty asynchronous tricks" to avoid, please? The manufacturers specify only the max. delays. I have always to assume that the min. delay, theorically, could be zero? If several signals follow similar paths, like in a bus, how have I to assume the timing relationships between these signals at the end of path? Each signal could have a different delay on the same device? And generally, how much real is the timing analysis and simulation? I belive these are important misunderstood questions. Thank you. LuigiArticle: 19399
Hi, i use MAX+plus II 9.3 7/23/1999 (1999.07). I can program the EPF10K10LC84-4 direcly out of Max+plus. And all works correct! Then I try to program the EPF10K10LC84-4 with JAM.EXE (16Bit Dos) on the same Hardware (Computer and Byteblaster). But it does not work! The following lines are from the dosbox ----------- Jam (Stapl) Player Version 2.12 Copywrite (C) 1997-1999 Altera Corporation Device #1 IDCODE is 010100DD DONE Exit code = 0 ... Success ----------- If i take off the cable from the ByteBlaster then i get the following lines: ----------- Jam (Stapl) Player Version 2.12 Copywrite (C) 1997-1999 Altera Corporation Device #1 IDCODE is FFFFFFFF DONE Exit code = 0 ... Success ---------- The ExitCode ist always 0. But the EPF10K10LC84-4 ist not working. This Error is so clear, that i think that must be an User Error. Which option is not correkt in MAX+plus or JAM.EXE? thanks -- Thomas Bornhaupt Bernard Humblot Str 8a 67434 Neustadt adW Tel: +49 (06321) 482260 eMail: Thomas@Bornhaupt.de
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