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I'm designing a board with a backend FPGA. I would like to download the firmware to the FPGA, and control the function of the FPGA through the Web. I know that internet reconfigurability is fairly new, but embedded web servers are a couple years old. Does anyone have any experience with these subsystems. I'm looking for the hardware requirements right now. I'd like a small processor ie 68HC16 with some boot flash and RAM. Are there any available? Are there reference designs? Any feedback/ pointers would be appreciated Tim Warland -- Observe everything; admire nothing. My opinions != Nortel's opinion.Article: 18601
Hello, Do anybody have informations on generation of vhdl code using FPGA in logic fault suimulation? Currently, I am using Xlinix Foundation 2.1i on my project. If yes, pls e-mail me. My e-mail address is sckey@visto.com Regards, KeyArticle: 18602
SwiftView by Northern Development Group, Inc. will view and print hpgl drawings very well. Sorry, I have no contact info for this company. Barry Brown rk wrote in message <38176FB4.3C287AC7@NOSPAM.erols.com>... > >i could do .hgl (hp graphics language) output but not sure how readable >that would be. usually when i import an .hgl into word it makes a mess. >Article: 18603
Hi, We need to obtain some software microprocessor model to do VHDL simulation for an ASIC's microprocessor interface. For now we hope to simulate Intel 196 and Motorola MC68332. The model need not be fancy since we are mostly concerned about its bus timing. I'd really appreciate any idea to help us obtain a relatively cheap and effective solution. Sheila Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18604
Dear Guys,
I am now trying to implement the following block diagram:
+-------+ (2) +-------+ (10)
o--|1:2 S/P|=====|Encoder|======o
/ +-------+ +-------+ \\
/ +-------+ (3) +-------+ (10) \\
155Mbps------o o--|1:3 S/P|=====|Encoder|======o o=== Parallel Output
+-------+ +-------+
+-------+ (4) +-------+ (10)
o--|1:2 S/P|=====|Encoder|======o
+-------+ +-------+
^ ^
| |
| |
Selector Selector
where S/P = Serial to Parallel converter, Encoder can be implemented by
simple logic gates(may be less than 4 levels).
I want to know if I can implement the above subsystem all in FPGA.
Can it be so ?? Thanks.
Child
Article: 18605Hi, Does the Xlinx FPGA compiler really compile any 5-bit Boolean function into one CLB?Article: 18606
James Yeh wrote: > > I was wondering if somebody could tell me the trade offs of using one > over the other. > > I have a design in Viewdraw currently (a SDRAM controller with a fairly > complex FSM, which I have implemented by hand). > > The issues I have are > > a) I'm positive that StateCAD will do a better job in optimizing my FSM > (speed or space) and I know I can put gates and components down from the > Xilinx library. But what about its simulation environment? I > incorporate a Micron VHDL model in my viewdraw design for simulation, > and I was wondering if StateCAD does a good job of taking VHDL and > allowing it to interact with real Schematics. > > b) I was wondering if there were a lot of people who used StateCAD > because, granted I've only been doing stuff with FPGA's for about a > year, I just don't hear that much about the software (that actually > could be a good thing :) ) > > c) Reliability. I have Service Pack 5, and well Viewdraw and what not > is not the most stable software in the world, and was wondering if > Statecad was any better at not crashing (I'm guessing not...blame it all > on Bill anyway.....). I have my own opinion about how to do FPGA design and I am not sure that anything other than schematic is the way to go. I have used VHDL for state machine design which has its pros and cons. Likewise I looked at using StateCad (or something similar) and found that it also had pros and cons. Basically, I found that the higher the level of abstraction, the less control over the hardware you had. An HDL gives you less control and a graphical editor gives you the least control over the final logic produced. The state editor I used was not obvious in how to use it to produce fairly optimized logic. It was one that produced VHDL from the diagram. I never could figure out exactly what VHDL would be produced. So I gave up on that. I also had significant problems using VHDL for state machine design. I needed to produce a FSM that would run at a fairly good clip so it could not have more than two or three levels of logic. Being a sparse machine (not a lot of transisitions into each state) it should have been easy to implement as a One-hot encoded machine. But the VHDL compiliers (I ended up trying three different ones) were very dense about this and I often ended up with 10 levels of logic or more. Each compilier had its own way of telling it that one hot encoding was in use. This required that the code be optimized or each compilier in very different ways. The entire process was very tedious and definately took more time than it would have to simply design the FSM using the techniques I learned in college (paper and pencil, yes, I'm that old) and drawing the schematic. If you don't need to optimize for space or speed, then I am sure that either VHDL or a state editor is faster debugging your conceptual design. But I just don't know that this is the best way to produce a completed design. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18607
On Tue, 02 Nov 1999 23:50:55 -0500, Rickman <spamgoeshere4@yahoo.com> wrote: > >Basically, I found that the higher the level of abstraction, the less >control over the hardware you had. An HDL gives you less control and a >graphical editor gives you the least control over the final logic >produced. > >The state editor I used was not obvious in how to use it to produce >fairly optimized logic. It was one that produced VHDL from the diagram. >I never could figure out exactly what VHDL would be produced. So I gave >up on that. I think that the point about higher levels of abstraction giving us less and less control is a good one. Let me add this observation: shoving a design through a long tool chain reminds me of the old game of "telephone" that kids played at parties. One person would whisper a message to the next, and that person to the next, and so on, until the message had gone to everyone. Then the first person and the last would compare initial and final messages, which rarely had anything in common. That's what I imagine when I think of trying to pass a design description through, say, StateCAD, then Synplicity, then Xilinx M2.1. It seems as though each interface is an opportunity for confusion and sin. I did once evaluate StateCAD for a month. The tool seemed well-written and the support was very good, but at the end of the month I was left with the question, "Why am I doing this?" There may be a good answer, but it wasn't apparent to me. Despite being a schematic diehard, I'm pretty happy with Synplicity, but see no need to pile other stuff on top of it. As I once told a vendor, I'm not sure I can survive another productivity improvement. Take care, Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 18608
In article <3818798e.610866647@mindmeld.idcomm.com>, edick@hotmail.com wrote: > I've had to wrtestle with this problem from time to time myself, and > have not found anything that works better than either PCX or BMP > format, so long as your intended audience uses Win9x, which provides > handlers for those formats. > > Several schematic/PCB packages have HPGL viewers, i.e. allow > importation of HPGL drawings, but I've not found a schematic capture > package for Windows that satisfies my requirements, so I still use a > 10-year old DOS-based one (OrCAD), which, by the way, doesn't import > HPGL, but their PCB package does. It's not perfect, by any means, > however, as text often gets muddled to where it can't be read. > > If you find a solution, please share it with me. The PCB package I use can output HPGL files. I do that, and convert the HPGL to GIF. The result is adequate. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18609
Kwong Chan wrote: > > Hi, > > Does the Xlinx FPGA compiler really compile > any 5-bit Boolean function into one CLB? Yes (at least for those families that have 5-input CLBs). -- Peter CrightonArticle: 18610
LX.MP3z *********** New upcoming MP3-site without porn, pop-ups or porn!! With own private server => NO BROKEN LINKS ACCESS FOR EVERYONE!!! Free downloads... Check It Out: http://dowload.at/LX.MP3zArticle: 18611
Why implement a DSP in a FPGA? Advantages of FPGA versus another systems. * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 18612
"Warland, Tim [CRK:E930:EXCH]" wrote:
>
> I'm designing a board with a backend FPGA. I would like
> to download the firmware to the FPGA, and control the
> function of the FPGA through the Web.
>
> I know that internet reconfigurability is fairly new, but
> embedded web servers are a couple years old. Does
> anyone have any experience with these subsystems.
I am doing exactly this rigth now with our router prototype
(3 xc40150xv, 1 xc40250xv). In total I need to configure
14 MBit.
My "host" system is a single board computer with i386EX processor,
10 MBit Ethernet, 16MByte RAM which runs Linux.
On top of this I have a program written in Gforth
which does the configuring, BSCAN and a small http-deamon.
It just handle some "form"-urls which are translated
into the different operations.
The configuration data is loaded through the normal NFS, and the program
generates HTML-source to report the board's status.
Currently we are developing some applets (for the browser)
to present the results prettier.
If you are interested in more details, please contact me.
Some more details can be found on our project pages.
Andreas
-----------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck Germany
Tel.: +49 451 500-3741, Fax: -3687
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 18613Current FPGAs are capable of 155Mbit/sec performance if you are careful with the design. With the information shown here, this should be an easy fit to an FPGA. Depending on the complexity of the encoder, you may even get away with a slower speed grade part. Child K.L. Sun wrote: > Dear Guys, > > I am now trying to implement the following block diagram: > > +-------+ (2) +-------+ (10) > o--|1:2 S/P|=====|Encoder|======o > / +-------+ +-------+ \\ > / +-------+ (3) +-------+ (10) \\ > 155Mbps------o o--|1:3 S/P|=====|Encoder|======o o=== Parallel Output > +-------+ +-------+ > +-------+ (4) +-------+ (10) > o--|1:2 S/P|=====|Encoder|======o > +-------+ +-------+ > ^ ^ > | | > | | > Selector Selector > > where S/P = Serial to Parallel converter, Encoder can be implemented by > simple logic gates(may be less than 4 levels). > > I want to know if I can implement the above subsystem all in FPGA. > Can it be so ?? Thanks. > > Child > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18614
Not always. Depends on logic around it and how the tool partitions the logic. Kwong Chan wrote: > Hi, > > Does the Xlinx FPGA compiler really compile > any 5-bit Boolean function into one CLB? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18615
FPGAs allow you build a processing pipeline customized to the process you need to do. Using low level parallelism, you get potentially huge processing gains over a microprocessor based DSP system. If for example you needed to add a list of numbers you need to do at least log2(n)-1 additions. In an FPGA you can construct a tree of adders so all the additions are performed at the same time. In a microprocessor, there is usually only one adder so you need to do the additions one at a time. As an example of the FPGA's processing power, look at the "FPGAs make a radar signal processor on a chip a reality" paper on my website. In that case, the FPGA is performing over 10 billion multiplies per second on a 130 MHz clock (that's more than 80 multiplies per clock cycle). The processor is a pair of 256 tap complex matched filters, a pair of quadrature phase detect demodulators and doppler pulse pair averagers. Thats about than 2 orders of magnitude more performance than you will get out of the fastest DSP microprocessors today. An ASIC solution can outperform an FPGA, but involves a significant NRE cost and any flexibility has to be in the design. The FPGA solution can approach the performance of an ASIC based system without giving up the flexibility and low volume economy. project wrote: > Why implement a DSP in a FPGA? Advantages of FPGA versus > another systems. > > * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is Beautiful -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18616
Thanks all for the advices. I resolved this problem setting the compiler strategy to Delay; in this way the counter uses correctly 16 macrocells of 4 GLBs. Strangely, in this project, if the compiler strategy is set to Area, it wastes more macrocells and the counter results slower. I hope this can be useful for other peoples. Regards. LuigiArticle: 18617
I'm trying to synthetize a design on an Altera Flex 10KA250 . I've tried to use two different tools 1)Leonardo Spectrum (on a WinNT4.0 PC Pentium II, 128 MB Ram) 2)Fpga Compiler II Altera Edition (on a Solaris 2.5.1, 512 MB Ram) Leonardo crashed after a few hours. Fpga Compiler created an "implementation" of a state machine (about 200 states,1/4 of my design), after more than 2 hours. In Fpga Compiler, creating an implementation is only the 1st step toward synthesys (the 2nd is the "optimization"). So, I'm expecting too long compilation times using Fpga Compiler. That's way I decided to synthetize my design using Design Compiler (even if its area and delay estimates aren't correct), simulating the design after place and route (using the .vho generated by Maxplus2), in order to debug it. Any suggestion about possible workarounds ? Is there anyone who encountered (and solved) these problems ? Is there any user of Fpga Compiler II Altera Ed., who may help me? What about other tools (they say Synplify requires less Ram) ? G. Giachella Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18618
Hi Tim.... Try http://www.brightstareng.com/index.html, I've used their product, the IP-engine which is basically a cpu + rtos + web server + FPGA. Eric Pearson Warland, Tim [CRK:E930:EXCH] wrote in message <381F4A25.858EF16D@americasm01.nt.com>... >I'm designing a board with a backend FPGA. I would like >to download the firmware to the FPGA, and control the >function of the FPGA through the Web. > >I know that internet reconfigurability is fairly new, but >embedded web servers are a couple years old. Does >anyone have any experience with these subsystems. > >I'm looking for the hardware requirements right now. >I'd like a small processor ie 68HC16 with some boot >flash and RAM. Are there any available? Are there >reference designs? > >Any feedback/ pointers would be appreciated > >Tim Warland >-- >Observe everything; admire nothing. > >My opinions != Nortel's opinion.Article: 18619
Hello,
I am trying to find a listing of Bellcore NEBS 3 compliant Wintel PCs. We
are looking for a telecommunications carrier class grade Windows NT
platform, is there any website that is a central portal for this type of
product- or any other information available on what manufacturers have this
grade of product available.
Thanks,
Norm
Norm Ebsary
-->
DTI Networks
6601 Lyons Road, Suite E1
Coconut Creek, Florida
33073-3636
Email: norm@dticorp.com
WWW: www.dtinetworks.com
Tel: 954-247-4116
Fax: 954-247-4050
The best approach for next generation network solutions
-->
Over the Top!
Article: 18620In article <7vmc8l$ju8$1@nnrp1.deja.com>, gallant@nm.hsd.utc.com wrote: > Hello, > > I have a general FPGA design question. I have many asynchronous inputs > to my Actel 42MX device. Is the general practice to cascade 2 flip- > flops for each input in order to reduce the probability of > metastability? How can I calculate this probability? > > Where could I find more information about this subject (I searched the > Actel web site but couldn't find anything)? > > Thanks in advance, > > Josh Gallant > > Sent via Deja.com http://www.deja.com/ > Before you buy. > We work with Xilinx parts, but I can offer some advice that will probably apply to Actel parts as well: 1) Standard practice is to use two registers to reduce the probability of metastability. To quantify the probability, you need to get characterization data from Actel. Once you have this, and the clock frequency, then you can work out the probability. Contact an Actel applications engineer to find out how to do this. Since Actel plays in the hi-rel arena, I am sure that they will have this information. 2) Don't use standard routing resources for your register clocks! This is a mistake that I have seen more times than I care to count. You won't reduce the probability of metastability if you have a hold time violation between registers. Low skew global clock nets are a must for multi-stage registers of any kind, including counters, state machines, pipelines, etc. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18621
I'm new at this, but I've been trying t olearn what I can by reading the literature. I'd say it's possible, but the software won't always do it by itself. Though it doesn't always do it by iteself, I have read that it's possible to generate any logic function of 5 variables, since it uses a 32-bit lookup table. If necessary, you can force it to do that. That means doing a lot more work yourself, though. Dick On Wed, 03 Nov 1999 08:10:52 -0500, Ray Andraka <randraka@ids.net> wrote: >Not always. Depends on logic around it and how the tool partitions the >logic. > >Kwong Chan wrote: > >> Hi, >> >> Does the Xlinx FPGA compiler really compile >> any 5-bit Boolean function into one CLB? > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 18622
Also, you should keep the route between the resynchronizers as short as possible (measured in time) because the propagation delay eats into your metastability resolution window. Greg Neff wrote: > In article <7vmc8l$ju8$1@nnrp1.deja.com>, > gallant@nm.hsd.utc.com wrote: > > Hello, > > > > I have a general FPGA design question. I have many asynchronous > inputs > > to my Actel 42MX device. Is the general practice to cascade 2 flip- > > flops for each input in order to reduce the probability of > > metastability? How can I calculate this probability? > > > > Where could I find more information about this subject (I searched the > > Actel web site but couldn't find anything)? > > > > Thanks in advance, > > > > Josh Gallant > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > > > We work with Xilinx parts, but I can offer some advice that will > probably apply to Actel parts as well: > > 1) Standard practice is to use two registers to reduce the probability > of metastability. To quantify the probability, you need to get > characterization data from Actel. Once you have this, and the clock > frequency, then you can work out the probability. Contact an Actel > applications engineer to find out how to do this. Since Actel plays in > the hi-rel arena, I am sure that they will have this information. > > 2) Don't use standard routing resources for your register clocks! This > is a mistake that I have seen more times than I care to count. You > won't reduce the probability of metastability if you have a hold time > violation between registers. Low skew global clock nets are a must for > multi-stage registers of any kind, including counters, state machines, > pipelines, etc. > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18623
Yes this is correct. You can put any 5 input boolean function into one Xilinx 4K CLB. The tools don't always do that (in fact there is a switch that will disable 5 input functions). If you know what you want, then you can specify it using Fmaps and Hmaps. The 4K structure is a pair of 4 input look-up tables (LUTs) followed by a 3 input LUT. Each LUT can be programmed for any boolean function of the number of inputs to that LUT. For a 5 input function, the 3 LUT is programmed as a multiplexer to select from one of the two 4-LUTs. 4 bits of your input go to both 4 LUTs and the 5th bit controls the 3LUT mux. You can get selected functions of up to 9 inputs in a single CLB, but be careful doing that as it can congest the routing. Richard Erlacher wrote: > I'm new at this, but I've been trying t olearn what I can by reading > the literature. > > I'd say it's possible, but the software won't always do it by itself. > > Though it doesn't always do it by iteself, I have read that it's > possible to generate any logic function of 5 variables, since it uses > a 32-bit lookup table. If necessary, you can force it to do that. > > That means doing a lot more work yourself, though. > > Dick > > On Wed, 03 Nov 1999 08:10:52 -0500, Ray Andraka <randraka@ids.net> > wrote: > > >Not always. Depends on logic around it and how the tool partitions the > >logic. > > > >Kwong Chan wrote: > > > >> Hi, > >> > >> Does the Xlinx FPGA compiler really compile > >> any 5-bit Boolean function into one CLB? > > > > > > > >-- > >-Ray Andraka, P.E. > >President, the Andraka Consulting Group, Inc. > >401/884-7930 Fax 401/884-7950 > >email randraka@ids.net > >http://users.ids.net/~randraka > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18624
Hi there! I am about to make XNF Reader. If you have XNF grammar, could you email me? -- Yun song hyun --
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