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Threads Starting Feb 2000
20210: 00/02/01: Swapnajit Mittra: Verilog PLI website
20215: 00/02/01: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Count 1's algorithm...
20225: 00/02/01: Mike Treseler: Re: Count 1's algorithm...
20227: 00/02/01: B. Joshua Rosen: Re: Count 1's algorithm...
20230: 00/02/01: Ray Andraka: Re: Count 1's algorithm...
20303: 00/02/04: Dragon: Re: Count 1's algorithm...
20350: 00/02/07: <a@z.com>: Re: Count 1's algorithm...
20231: 00/02/01: John L. Smith: Re: Count 1's algorithm...
20250: 00/02/02: Nick Macias: Re: Count 1's algorithm...
20254: 00/02/02: Peter Alfke: Re: Count 1's algorithm...
20266: 00/02/03: Peter Alfke: Re: Count 1's algorithm...
20285: 00/02/03: Donald Gillies: Re: Count 1's algorithm...
20288: 00/02/04: Ray Andraka: Re: Count 1's algorithm...
20216: 00/02/01: Jamil Khaib: part time
20260: 00/02/02: funky jim: Re: part time
20264: 00/02/03: Matt Billenstein: Re: part time
20218: 00/02/01: Larry Eisner: PCI core in public domain
20226: 00/02/01: Steen Larsen: Re: PCI core in public domain
20239: 00/02/02: <rob_dickinson@my-deja.com>: Re: PCI core in public domain
20219: 00/02/01: Keith Wootten: Xilinx Tools
20229: 00/02/01: Ray Andraka: Re: Xilinx Tools
20233: 00/02/01: Keith Jasinski, Jr.: Re: Tools and how little guy is treated (was Xilinx Tools)
20236: 00/02/02: Kirk Saban: Re: Tools and how little guy is treated (was Xilinx Tools)
20243: 00/02/02: Keith Jasinski, Jr.: Re: Tools and how little guy is treated (was Xilinx Tools)
20249: 00/02/02: Richard Dungan: Re: Tools and how little guy is treated (was Xilinx Tools)
20298: 00/02/04: David Hawke: Re: Xilinx Tools
20301: 00/02/04: Keith Jasinski, Jr.: Re: Xilinx Tools
20306: 00/02/04: Andy Peters: Re: Xilinx Tools
20300: 00/02/04: Keith Wootten: Re: Xilinx Tools
20314: 00/02/04: David Hawke: Re: Xilinx Tools
20220: 00/02/01: Steven Sanders: Xilinx Foundation 2.1: VHDL to MACRO error
20224: 00/02/01: David Dye: Re: Xilinx Foundation 2.1: VHDL to MACRO error
20234: 00/02/01: John Janusson: Xilinx Virtex Decoupling Cap Guidelines
20279: 00/02/03: Tom Burgess: Re: Xilinx Virtex Decoupling Cap Guidelines
20282: 00/02/03: Rickman: Re: Xilinx Virtex Decoupling Cap Guidelines
20291: 00/02/04: Allan Herriman: Re: Xilinx Virtex Decoupling Cap Guidelines
20308: 00/02/04: Rickman: Re: Xilinx Virtex Decoupling Cap Guidelines
20292: 00/02/04: Andreas Heiner: Re: Xilinx Virtex Decoupling Cap Guidelines
20309: 00/02/04: Rickman: Re: Xilinx Virtex Decoupling Cap Guidelines
20311: 00/02/04: Andreas Heiner: Re: Xilinx Virtex Decoupling Cap Guidelines
20331: 00/02/05: Rickman: Re: Xilinx Virtex Decoupling Cap Guidelines
20349: 00/02/07: Andreas Heiner: Re: Xilinx Virtex Decoupling Cap Guidelines
20286: 00/02/03: Bob Perlman: Re: Xilinx Virtex Decoupling Cap Guidelines
20457: 00/02/11: peter dudley: Re: Xilinx Virtex Decoupling Cap Guidelines
20468: 00/02/11: Andreas Heiner: Re: Xilinx Virtex Decoupling Cap Guidelines
20570: 00/02/15: peter dudley: Re: Xilinx Virtex Decoupling Cap Guidelines
20235: 00/02/02: David T Le: Which is the best HDL book ?
20318: 00/02/04: <elynum@my-deja.com>: Re: Which is the best HDL book ?
20337: 00/02/06: Victor the Cleaner: Re: Which is the best HDL book ?
20238: 00/02/02: Jamie Honan: Foundation 1.5 VHDL compiler command line
20242: 00/02/02: Rune Baeverrud: FreeCore.com has been restored
20247: 00/02/02: Björn Lindegren: XC9536 and Abel
20251: 00/02/02: Andy Peters: Re: XC9536 and Abel
20252: 00/02/02: Dave Vanden Bout: Re: XC9536 and Abel
20248: 00/02/02: <anoriaki@comp.ufscar.br>: FPGA x DPGA x TSFPGA
20256: 00/02/02: Veselic Mladen: Foundation
20259: 00/02/02: funky jim: Re: Foundation
20257: 00/02/02: Mikhail Matusov: Visualizing EDIF netlist for Xilinx
20265: 00/02/03: Allan Herriman: Re: Visualizing EDIF netlist for Xilinx
20270: 00/02/03: Rémi SEGLIE: Re: Visualizing EDIF netlist for Xilinx
20274: 00/02/03: Ernest Jamro: Re: Visualizing EDIF netlist for Xilinx
20277: 00/02/03: Rémi SEGLIE: Re: Visualizing EDIF netlist for Xilinx
20305: 00/02/04: Andy Peters: Re: Visualizing EDIF netlist for Xilinx
20281: 00/02/03: Mikhail Matusov: Re: Visualizing EDIF netlist for Xilinx
20258: 00/02/02: funky jim: Can hobbyist buy altera in uk?
20262: 00/02/03: Tim Tyler: Re: Can hobbyist buy altera in uk?
20275: 00/02/03: Stewart, Nial [HAL02:HH00:EXCH]: Re: Can hobbyist buy altera in uk?
20287: 00/02/04: funky jim: Re: Can hobbyist buy altera in uk?
20377: 00/02/08: Stewart, Nial [HAL02:HH00:EXCH]: Re: Can hobbyist buy altera in uk?
20408: 00/02/09: Leon Heller: Re: Can hobbyist buy altera in uk?
20261: 00/02/03: Irit: Looking for a small, fast CPU core for FPGA
20344: 00/02/07: Wiggo Olufsen: Re: Looking for a small, fast CPU core for FPGA
20684: 00/02/17: David Jacobowitz: Re: Looking for a small, fast CPU core for FPGA
20685: 00/02/17: Nicholas C. Weaver: Re: Looking for a small, fast CPU core for FPGA
20840: 00/02/23: Jamie Lokier: Re: Looking for a small, fast CPU core for FPGA
20841: 00/02/23: Nicholas C. Weaver: Re: Looking for a small, fast CPU core for FPGA
20899: 00/02/25: Jamie Lokier: Re: Looking for a small, fast CPU core for FPGA
20267: 00/02/03: Volker Nicolai: Crossing clock domain boundaries in digital ASICs
20268: 00/02/03: Jamil Khaib: please help me
20269: 00/02/03: Klee: wrong ID from XC9536
20280: 00/02/03: Klee: capacitor !
20271: 00/02/03: Nicolas Matringe: Spartan 2 & Foundation
20289: 00/02/04: Ray Andraka: Re: Spartan 2 & Foundation
20294: 00/02/04: Jean-Paul GOGLIO: Re: Spartan 2 & Foundation
20295: 00/02/04: Jean-Paul GOGLIO: Re: Spartan 2 & Foundation
20296: 00/02/04: Jean-Paul GOGLIO: Re: Spartan 2 & Foundation
20302: 00/02/04: Ray Andraka: Re: Spartan 2 & Foundation
20312: 00/02/04: David Dye: Re: Spartan 2 & Foundation
20322: 00/02/04: Ray Andraka: Re: Spartan 2 & Foundation
20338: 00/02/06: David Dye: Re: Spartan 2 & Foundation
20272: 00/02/03: <eml@riverside-machines.com.NOSPAM>: Renoir problem: several engineers sharing a common setup?
20273: 00/02/03: David Jones: Re: Renoir problem: several engineers sharing a common setup?
20283: 00/02/03: <eml@riverside-machines.com.NOSPAM>: Re: Renoir problem: several engineers sharing a common setup?
20284: 00/02/03: Phil Cole: Re: Renoir problem: several engineers sharing a common setup?
20299: 00/02/04: <eml@riverside-machines.com.NOSPAM>: Re: Renoir problem: several engineers sharing a common setup?
20319: 00/02/04: Phil Cole: Re: Renoir problem: several engineers sharing a common setup?
20276: 00/02/03: Holger Kleinert: VHDL and Xilinx Books for beginners
20278: 00/02/03: Dave Vanden Bout: Re: VHDL and Xilinx Books for beginners
20430: 00/02/10: Don Golding: Re: VHDL and Xilinx Books for beginners
20445: 00/02/10: Andy Peters: Re: VHDL and Xilinx Books for beginners
20293: 00/02/04: <boniolopez@my-deja.com>: PMUX primitive in Sinplify
20327: 00/02/04: Ken McElvain: Re: PMUX primitive in Sinplify
20297: 00/02/04: Joel BRUNEAU: RECHERCHE
20304: 00/02/04: Georgi Beloev: OE in hierachial ABEL design
20307: 00/02/04: Mikhail Matusov: Conditional compilation in VHDL?
20310: 00/02/04: <eml@riverside-machines.com.NOSPAM>: Re: Conditional compilation in VHDL?
20326: 00/02/04: A person: Re: Conditional compilation in VHDL?
20313: 00/02/04: Mike Treseler: Re: Conditional compilation in VHDL?
20316: 00/02/04: Mikhail Matusov: Re: Conditional compilation in VHDL?
20317: 00/02/04: Mike Treseler: Re: Conditional compilation in VHDL?
20323: 00/02/04: Ray Andraka: Re: Conditional compilation in VHDL?
20333: 00/02/05: Clyde R. Shappee: Re: Conditional compilation in VHDL?
20358: 00/02/07: <mench@mench.com>: Re: Conditional compilation in VHDL?
20366: 00/02/07: Mikhail Matusov: Re: Conditional compilation in VHDL?
20367: 00/02/07: Mike Treseler: Re: Conditional compilation in VHDL?
20382: 00/02/08: <a@z.com>: Re: Conditional compilation in VHDL?
20386: 00/02/08: Mikhail Matusov: Re: Conditional compilation in VHDL?
20320: 00/02/04: Srinivasan Venkataramanan: Re: Conditional compilation in VHDL?
20324: 00/02/05: David Jones: Re: Conditional compilation in VHDL?
20325: 00/02/05: Ray Andraka: Re: Conditional compilation in VHDL?
20315: 00/02/04: jakab tanko: Re: Conditional compilation in VHDL?
20321: 00/02/04: Ray Andraka: Xilinx "WebCD" gripes
20328: 00/02/05: John Larkin: Re: Xilinx "WebCD" gripes
20329: 00/02/05: rk: Re: Xilinx "WebCD" gripes
20334: 00/02/05: Ray Andraka: Re: Xilinx "WebCD" gripes
20343: 00/02/06: Hal Murray: Re: Xilinx "WebCD" gripes
20346: 00/02/06: rk: Re: Xilinx "WebCD" gripes
20347: 00/02/07: Uwe Bonnes: Re: Xilinx "WebCD" gripes
20351: 00/02/07: rk: Re: Xilinx "WebCD" gripes
20354: 00/02/07: Ray Andraka: Re: Xilinx "WebCD" gripes
20355: 00/02/07: Ray Andraka: Re: Xilinx "WebCD" gripes
20330: 00/02/05: Rickman: Re: Xilinx "WebCD" gripes
20332: 00/02/05: rk: Re: Xilinx "WebCD" gripes
20405: 00/02/09: Domagoj: Re: Xilinx "WebCD" gripes
20406: 00/02/08: Joel Kolstad: Re: Xilinx "WebCD" gripes
20335: 00/02/06: <whitmoreg@my-deja.com>: Alternate to Altera Flex family
20336: 00/02/06: Carlhermann Schlehaus: Re: Alternate to Altera Flex family
20390: 00/02/08: Scott I. Chase: Re: Alternate to Altera Flex family
20339: 00/02/06: George: Availability of Virtex E Series
20341: 00/02/06: George: Re: Availability of Virtex E Series
20340: 00/02/06: George: FG1156 package for non-E XCV1000
20342: 00/02/06: Christof Paar: CFP --- CHES 200
20345: 00/02/07: T.Koyama: Where SpartanXL CS280 Pin Locatin
20348: 00/02/07: Phil Endecott: Linux Xilinx Download program
20435: 00/02/10: Roman Pollak: Re: Linux Xilinx Download program
20353: 00/02/07: Kai Troester: Why does Virtex has no EPROM support like XC4000
20407: 00/02/08: Joel Kolstad: Re: Why does Virtex has no EPROM support like XC4000
20411: 00/02/09: Ray Andraka: Re: Why does Virtex has no EPROM support like XC4000
20356: 00/02/07: Austin Franklin: How to get Synplicity to NOT use Global Clock for Virtex...
20357: 00/02/07: Austin Franklin: Re: How to get Synplicity to NOT use Global Clock for Virtex...
20370: 00/02/08: Ken McElvain: Re: How to get Synplicity to NOT use Global Clock for Virtex...
20359: 00/02/07: <m.beard@vertex-solutions.co.uk>: ASIC Opportunities
20360: 00/02/07: Nicolas Matringe: Floating license & Foundation Express
20362: 00/02/07: Nicolas Matringe: Re: Floating license & Foundation Express : Ooops
20365: 00/02/07: Paul Mondello: FLASH-based reconfigurability
20380: 00/02/08: Etienne Racine: Re: FLASH-based reconfigurability
20462: 00/02/10: Rickman: Re: FLASH-based reconfigurability
20368: 00/02/07: Mark Enwright: Cool website... Engineering Salary Survey
20372: 00/02/08: Tanthanuch.SAWIT: Xilinx board
20394: 00/02/09: Tanthanuch.SAWIT: Re: Xilinx board
20470: 00/02/11: Leon Heller: Re: Xilinx board
20373: 00/02/08: Jose: EDIF info
20424: 00/02/09: Sébastien Buschini: Re: EDIF info
20425: 00/02/10: Jose: RE: EDIF info
20374: 00/02/08: Jean-Paul GOGLIO: Timing constraint on a DLL output
20375: 00/02/08: Jean-Paul GOGLIO: Re: Timing constraint on a DLL output
20376: 00/02/08: Jean-Paul GOGLIO: Re: Timing constraint on a DLL output
20378: 00/02/08: Jean-Paul GOGLIO: Re: Timing constraint on a DLL output
20448: 00/02/10: Kate Meilicke: Re: Timing constraint on a DLL output
20615: 00/02/16: Kate Meilicke: Re: Timing constraint on a DLL output
20379: 00/02/08: Kai Troester: FPGA express: No clockbuf for rst
20381: 00/02/08: Pete Little: Re: FPGA express: No clockbuf for rst
20387: 00/02/08: Kai Troester: Re: FPGA express: No clockbuf for rst
20389: 00/02/08: Pete Little: Re: FPGA express: No clockbuf for rst
20388: 00/02/08: anurag: MP3 & Wavelet on FPGA
20471: 00/02/11: Mark Harvey: Re: MP3 & Wavelet on FPGA
20391: 00/02/08: qaz: PC Card - generally 3.3V signaling on laptops?
20393: 00/02/08: Ewan D. Milne: XC3000 series w/Foundation Student Edition?
20402: 00/02/08: Andy Peters: Re: XC3000 series w/Foundation Student Edition?
20409: 00/02/09: Andrew Dow: Lattice isp programming problems
20420: 00/02/09: Mikeandmax: Re: Lattice isp programming problems
20662: 00/02/17: <kapp_harald@my-deja.com>: Re: Lattice isp programming problems
20410: 00/02/09: Steven Derrien: Mapped design file
20412: 00/02/09: Marc Reinert: Viterbi Dec. in VHDL (on Xilinx XC4000)
20432: 00/02/10: Edwin Naroska: Re: Viterbi Dec. in VHDL (on Xilinx XC4000)
20475: 00/02/11: Marc Reinert: Re: Viterbi Dec. in VHDL (on Xilinx XC4000)
20414: 00/02/09: Jon Huppenthal: Reconfigurable Computing Jobs
20417: 00/02/09: <fpgaer@my-deja.com>: launching a FPGA cores start-up
20419: 00/02/09: David Kessner: Re: launching a FPGA cores start-up
20426: 00/02/10: <fpgaer@my-deja.com>: Re: launching a FPGA cores start-up
20520: 00/02/13: Ray Andraka: Re: launching a FPGA cores start-up
20539: 00/02/14: <fpgaer@my-deja.com>: Re: launching a FPGA cores start-up
20544: 00/02/14: Ray Andraka: Re: launching a FPGA cores start-up
20576: 00/02/15: <fpgaer@my-deja.com>: Re: launching a FPGA cores start-up
20579: 00/02/15: Ray Andraka: Re: launching a FPGA cores start-up
20580: 00/02/15: Rickman: Re: launching a FPGA cores start-up
20620: 00/02/16: <fpgaer@my-deja.com>: Re: launching a FPGA cores start-up
20661: 00/02/17: Ray Andraka: Re: launching a FPGA cores start-up
20706: 00/02/18: <news@fkchong.freeuk.com>: Re: launching a FPGA cores start-up
20418: 00/02/09: Bob - Commtech Services: 12+ month contract-NJ
20421: 00/02/09: Sergio A. Cuenca Asensi: RECONFIGURABLE board for image processign
20683: 00/02/17: <mrauf@nova-eng.com>: Re: RECONFIGURABLE board for image processign
20690: 00/02/17: Ray Andraka: Re: RECONFIGURABLE board for image processign
20702: 00/02/18: <smcc_adps@my-deja.com>: Re: RECONFIGURABLE board for image processign
20423: 00/02/09: Andy Peters: Spartan and timing analyzer: clock nets using non-dedicated resources
20427: 00/02/10: Allan Herriman: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20434: 00/02/10: Mark Harvey: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20443: 00/02/10: Peter Alfke: Re: Spartan and timing analyzer: clock nets using non-dedicated
20446: 00/02/10: Andy Peters: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20449: 00/02/10: Tom Burgess: Re: Spartan and timing analyzer: clock nets using non-dedicated
20450: 00/02/10: Peter Alfke: Re: Spartan and timing analyzer: clock nets using non-dedicated
20454: 00/02/10: Tom Burgess: Re: Spartan and timing analyzer: clock nets using non-dedicated
20488: 00/02/11: Andy Peters: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20712: 00/02/18: Rickman: Re: Spartan and timing analyzer: clock nets using non-dedicated
20740: 00/02/20: Ray Andraka: Re: Spartan and timing analyzer: clock nets using non-dedicated
20777: 00/02/21: Tom Burgess: Re: Spartan and timing analyzer: clock nets using non-dedicated
20489: 00/02/11: Andy Peters: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20496: 00/02/11: Magnus Homann: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20500: 00/02/11: Andy Peters: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20784: 00/02/22: <rob_dickinson@my-deja.com>: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20781: 00/02/22: Greg Neff: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20925: 00/02/28: Andy Peters: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20933: 00/02/28: Rickman: Re: Spartan and timing analyzer: clock nets using non-dedicated
20428: 00/02/10: Nicolas Matringe: Spartan/Foundation Latch reset problem
20429: 00/02/10: Botond Kardos: SRAM part question
20444: 00/02/10: Tom Burgess: Re: SRAM part question
20431: 00/02/10: Nikolay: Data conversion tools
20436: 00/02/10: <boniolopez@my-deja.com>: links about partitioning.
20437: 00/02/10: anurag: FPGA IP complexity
20455: 00/02/10: Mike DeBruin: Re: FPGA IP complexity
20521: 00/02/13: Ray Andraka: Re: FPGA IP complexity
20438: 00/02/10: Leon Heller: Altera - pcpu symbol in mega_lpm library
20439: 00/02/10: Pradeep Rao: Simulation problem
20456: 00/02/10: Mike DeBruin: Re: Simulation problem
20472: 00/02/11: Alan Fitch: Re: Simulation problem
20480: 00/02/11: <a@z.com>: Re: Simulation problem
20440: 00/02/10: Mary Frantz: Altera vs Cypress?
20459: 00/02/11: Clyde R. Shappee: Re: Altera vs Cypress?
20464: 00/02/11: Geoffrey G. Rochat: Re: Altera vs Cypress?
20494: 00/02/11: Carlhermann Schlehaus: Re: Altera vs Cypress?
20587: 00/02/15: <charles_elias@my-deja.com>: Re: Altera vs Cypress?
20441: 00/02/10: <bjorn_lindegren@my-deja.com>: Xilinx error message
20447: 00/02/10: Andy Peters: Re: Xilinx error message
20473: 00/02/11: Alan Fitch: Re: Xilinx error message
20481: 00/02/11: <a@z.com>: Re: Xilinx error message
20442: 00/02/10: <bjorn_lindegren@my-deja.com>: Xilinx error message
20469: 00/02/11: Klaus Falser: Re: Xilinx error message
20451: 00/02/10: Tom McLaughlin: Master/Serial mode for Virtex
20460: 00/02/10: Rickman: Re: Master/Serial mode for Virtex
20482: 00/02/11: <a@z.com>: Re: Master/Serial mode for Virtex
20487: 00/02/11: Tom McLaughlin: Re: Master/Serial mode for Virtex
20495: 00/02/11: <a@z.com>: Re: Master/Serial mode for Virtex
20497: 00/02/11: Tom McLaughlin: Re: Master/Serial mode for Virtex
20508: 00/02/13: Hal Murray: Re: Master/Serial mode for Virtex
20591: 00/02/15: Mike Peattie: Re: Master/Serial mode for Virtex
20710: 00/02/18: Rickman: Re: Master/Serial mode for Virtex
20499: 00/02/11: Peter Alfke: Re: Master/Serial mode for Virtex
20452: 00/02/10: Mark Luscombe: Xilinx Virtex Reset
20461: 00/02/10: Rickman: Re: Xilinx Virtex Reset
20484: 00/02/11: <a@z.com>: Re: Xilinx Virtex Reset
20522: 00/02/13: Ray Andraka: Re: Xilinx Virtex Reset
20551: 00/02/14: Mark Luscombe: Re: Xilinx Virtex Reset
20564: 00/02/14: Ray Andraka: Re: Xilinx Virtex Reset
20569: 00/02/15: Hal Murray: Re: Xilinx Virtex Reset
20585: 00/02/15: Magnus Homann: Re: Xilinx Virtex Reset
20623: 00/02/16: Rick Filipkiewicz: Re: Xilinx Virtex Reset
20630: 00/02/16: Peter Alfke: Re: Xilinx Virtex Reset
20681: 00/02/17: Mark Luscombe: Re: Xilinx Virtex Reset
20636: 00/02/16: Mark Luscombe: Re: Xilinx Virtex Reset
20656: 00/02/16: Rickman: Re: Xilinx Virtex Reset
20453: 00/02/10: <erika_uk@my-deja.com>: quantiser + ....
20458: 00/02/10: TeikMing Goh: ROL VHDL operator.. need help!
20463: 00/02/11: Domagoj: Re: ROL VHDL operator.. need help!
20474: 00/02/11: Alan Fitch: Re: ROL VHDL operator.. need help!
20485: 00/02/11: <a@z.com>: Re: ROL VHDL operator.. need help!
20465: 00/02/11: George: RLOC_RANGE property.
20677: 00/02/17: Steve Gross: Re: RLOC_RANGE property.
20466: 00/02/11: George: RLOC_RANGE property.
20503: 00/02/12: Philip Freidin: Re: RLOC_RANGE property.
20504: 00/02/12: George: Re: RLOC_RANGE property.
20467: 00/02/11: George: RLOC_RANGE property.
20476: 00/02/11: Manan: HELP ! Problems in mapping
20479: 00/02/11: David Hawke: Re: HELP ! Problems in mapping
20477: 00/02/11: Hans Holm: XILINX JTAG ID
20478: 00/02/11: John Breslin: re: Looking for a small, fast CPU core for FPGA
20483: 00/02/11: jean-marc: Processing a sdf file
20486: 00/02/11: <elynum@my-deja.com>: xilinx
20490: 00/02/11: Andy Peters: Re: xilinx
20509: 00/02/13: Hal Murray: Re: xilinx
20491: 00/02/11: Jason T. Wright: Re: xilinx
20493: 00/02/11: <elynum@my-deja.com>: Re: xilinx
20501: 00/02/11: Andy Peters: Re: xilinx
20512: 00/02/12: John Larkin: Re: xilinx
20515: 00/02/13: Peter Alfke: Re: xilinx
20527: 00/02/13: John Larkin: Re: xilinx
20530: 00/02/14: Peter Alfke: Re: xilinx
20532: 00/02/13: John Larkin: Re: xilinx
20764: 00/02/21: Hal Murray: Re: xilinx
20767: 00/02/21: <rob_dickinson@my-deja.com>: Re: xilinx
20529: 00/02/13: <imclaren@california.com>: Re: xilinx
20572: 00/02/14: rodger: Re: xilinx
20604: 00/02/16: <elynum@my-deja.com>: Re: xilinx
20692: 00/02/17: rodger: Re: xilinx
20492: 00/02/11: <elynum@my-deja.com>: fpga
20891: 00/02/25: Steven K. Knapp: Re: fpga
20498: 00/02/11: Magnus Homann: A FPGA hickup
20502: 00/02/11: Andy Peters: Re: A FPGA hickup
20506: 00/02/12: Magnus Homann: Re: A FPGA hickup
20523: 00/02/13: Ray Andraka: Re: A FPGA hickup
20510: 00/02/13: Hal Murray: Re: A FPGA hickup
20526: 00/02/13: Magnus Homann: Re: A FPGA hickup
20763: 00/02/21: Hal Murray: Re: A FPGA hickup
20888: 00/02/25: Tim Tyler: Re: A FPGA hickup
20578: 00/02/15: Magnus Homann: Re: A FPGA hickup
20624: 00/02/16: Rick Filipkiewicz: Re: A FPGA hickup
20505: 00/02/12: TS Kutty: Problem in Wildforce synthesis.
20507: 00/02/12: Andy Peters: Re: Problem in Wildforce synthesis.
20516: 00/02/13: TS Kutty: Re: Problem in Wildforce synthesis.
20534: 00/02/14: Keith R. Williams: Re: Problem in Wildforce synthesis.
20517: 00/02/13: TS Kutty: Re: Problem in Wildforce synthesis.
20550: 00/02/14: Andy Peters: Re: Problem in Wildforce synthesis.
20511: 00/02/12: annoob: [NEED HELP] Carry Select Adder?
20524: 00/02/13: Ray Andraka: Re: [NEED HELP] Carry Select Adder?
20525: 00/02/13: rk: Re: [NEED HELP] Carry Select Adder?
20652: 00/02/16: glen herrmannsfeldt: Re: [NEED HELP] Carry Select Adder?
20513: 00/02/12: Asher C. Martin: Where can I get PLCC sockets for Xilinx 4005e???
20514: 00/02/12: Asher C. Martin: How do you program the Xilinx 4005e?
20518: 00/02/13: Asher C. Martin: Re: How do you program the Xilinx 4005e?
20519: 00/02/13: Jamil Khatib: FPGA verification
20528: 00/02/13: Bob Perlman: Xilinx M2.1 Floorplanner Question
20695: 00/02/18: Ray Andraka: Re: Xilinx M2.1 Floorplanner Question
20739: 00/02/20: Bob Perlman: Re: Xilinx M2.1 Floorplanner Question
20742: 00/02/20: Ray Andraka: Re: Xilinx M2.1 Floorplanner Question
20531: 00/02/13: TeikMing Goh: Logiblox Model failed in functional simulation by vhdldbx
20533: 00/02/13: Neill Clift: Using a programable logic device to search a huge number field
20696: 00/02/18: Ray Andraka: Re: Using a programable logic device to search a huge number field
20697: 00/02/18: Ray Andraka: Re: Using a programable logic device to search a huge number field
20535: 00/02/14: Jamil Khatib: LUT & VHDL
20545: 00/02/14: Ray Andraka: Re: LUT & VHDL
20566: 00/02/15: raja: Re: LUT & VHDL
20536: 00/02/13: Jesse Newcomb: QuickLogic FPGA programmers for sale
20537: 00/02/14: TS Kutty: Wildforce Board
20541: 00/02/14: Jonas Thor: Re: Wildforce Board
20538: 00/02/13: Jesse Newcomb: HP 16500B logic analyzer for sale
20540: 00/02/14: Don Golding: Public Domain Micro Processor Project
20560: 00/02/14: Ben Franchuk: Re: Public Domain Micro Processor Project
20542: 00/02/14: Mathew Wojko: Multiple GND & VCC Instances
20547: 00/02/14: Rickman: Re: Multiple GND & VCC Instances
20592: 00/02/15: Greg Neff: Re: Multiple GND & VCC Instances
20543: 00/02/14: <flavioas@my-deja.com>: CIC Question
20546: 00/02/14: Ray Andraka: Re: CIC Question
20632: 00/02/16: <flavioas@my-deja.com>: Re: CIC Question
20638: 00/02/16: Ray Andraka: Re: CIC Question
20548: 00/02/14: <ritchie99_uk@my-deja.com>: MULTIRATE DESIGN
20556: 00/02/14: <erika_uk@my-deja.com>: Re: MULTIRATE DESIGN
20577: 00/02/15: Ray Andraka: Re: MULTIRATE DESIGN
20549: 00/02/14: Ptarmigan: Verilog DRC?
20552: 00/02/14: Joshua Lamorie: FPGA Network stack
20553: 00/02/14: Paul Urbanus: Post-synthesis simulation in Foundation Express
20557: 00/02/14: Andy Peters: Re: Post-synthesis simulation in Foundation Express
20559: 00/02/14: <a@z.com>: Re: Post-synthesis simulation in Foundation Express
20561: 00/02/14: Andy Peters: Re: Post-synthesis simulation in Foundation Express
20554: 00/02/14: Yuyuan Lu: Altera: how to convert .tdf to .gdf?
20555: 00/02/14: Andy Peters: FPGA Express/XC4KXLA annoyance
20601: 00/02/15: John Fielden: Re: FPGA Express/XC4KXLA annoyance
20639: 00/02/16: Andy Peters: Re: FPGA Express/XC4KXLA annoyance
20558: 00/02/14: <sweazle@my-deja.com>: Advice please
20563: 00/02/14: Gary Spivey: Re: Advice please
20565: 00/02/14: Gary Spivey: Re: Advice please
20567: 00/02/14: Andy Peters: Re: Advice please
20568: 00/02/15: Ray Andraka: Re: Advice please
20581: 00/02/15: Dragon: Re: Advice please
20655: 00/02/16: Rickman: Re: Advice please
20583: 00/02/15: PaulTB: Re: Advice please
20562: 00/02/14: J.R.: Is EDIF format adopted by all FPGA manufacturers???
20588: 00/02/15: George: Re: Is EDIF format adopted by all FPGA manufacturers???
20571: 00/02/15: RSche42109: decoder
20573: 00/02/15: <gerizamir@my-deja.com>: BCH Implementation
20574: 00/02/15: Benoît HAMON: clock
20575: 00/02/15: Nicolas Matringe: Re: clock
20589: 00/02/15: Andy Peters: Re: clock
20610: 00/02/16: <jball99653@aol.com>: Re: clock
20612: 00/02/16: <rob_dickinson@my-deja.com>: Re: clock
21709: 00/03/29: <larell@airmail.net>: Re: clock
20621: 00/02/16: Dominique SZYMIK: Re: clock
20711: 00/02/18: Sprow: Re: clock
20582: 00/02/15: <gazit@my-deja.com>: Xilinx - implementing macros
20584: 00/02/15: Matt Gavin: 100% slice utilization in Virtex FPGA
20600: 00/02/15: Kamal Chaudhary: Re: 100% slice utilization in Virtex FPGA
20606: 00/02/16: <gazit@my-deja.com>: Re: 100% slice utilization in Virtex FPGA
20626: 00/02/16: Rick Filipkiewicz: Re: 100% slice utilization in Virtex FPGA
20667: 00/02/17: <gazit@my-deja.com>: Re: 100% slice utilization in Virtex FPGA
20617: 00/02/16: Ray Andraka: Re: 100% slice utilization in Virtex FPGA
20627: 00/02/16: <jeffreyzuelch@my-deja.com>: Re: 100% slice utilization in Virtex FPGA
20628: 00/02/16: <jeffreyzuelch@my-deja.com>: Re: 100% slice utilization in Virtex FPGA
20629: 00/02/16: <jeffreyzuelch@my-deja.com>: Re: 100% slice utilization in Virtex FPGA
20586: 00/02/15: Magnus Homann: Using SRL16 for synching asynch inputs?
20594: 00/02/15: TalentLab: Product Validation Engineers Needed!
20595: 00/02/15: Mark Hillers: coregen-bug produces bad blockram > 16 bit
20608: 00/02/16: P Little: Re: coregen-bug produces bad blockram > 16 bit
20609: 00/02/16: Matthias Brucke: Re: coregen-bug produces bad blockram > 16 bit
20613: 00/02/16: Mark Hillers: Re: coregen-bug produces bad blockram > 16 bit
20635: 00/02/16: <fjz001@email.mot.com>: Re: coregen-bug produces bad blockram > 16 bit
20682: 00/02/17: Mark Hillers: Re: coregen-bug produces bad blockram > 16 bit
20689: 00/02/17: Ray Andraka: Re: coregen-bug produces bad blockram > 16 bit
20708: 00/02/18: Matthias Brucke: Re: coregen-bug produces bad blockram > 16 bit
20709: 00/02/18: Mark Hillers: Re: coregen-bug produces bad blockram > 16 bit
20596: 00/02/15: Don Husby: Virtex size: Row,Col or Col,Row ?
20598: 00/02/15: Peter Alfke: Re: Virtex size: Row,Col or Col,Row ?
20597: 00/02/15: Matt Billenstein: Simulating Virtex
20599: 00/02/15: <karthikeyan@my-deja.com>: The definitive site for ASIC jobs!
20602: 00/02/16: funky jim: synopsys, vhdl, verilog specs free?
20603: 00/02/16: <rajesh52@hotmail.com>: Verilog FAQ
20605: 00/02/16: Matt Billenstein: Simulating Virtex
20607: 00/02/16: Jean-Paul GOGLIO: Re: Simulating Virtex
20611: 00/02/16: Pradeep Rao: multiplier
20616: 00/02/16: Don McCarley: Re: multiplier
20619: 00/02/16: Ray Andraka: Re: multiplier
20691: 00/02/18: Mathew Wojko: Re: multiplier
20694: 00/02/18: Ray Andraka: Re: multiplier
20699: 00/02/18: Mathew Wojko: Re: multiplier
20741: 00/02/20: Ray Andraka: Re: multiplier
20757: 00/02/21: Mark Summerfield: Re: multiplier
20765: 00/02/21: Andrew Ince: Re: multiplier
20769: 00/02/21: Ray Andraka: Re: multiplier
20672: 00/02/17: Keith Jasinski, Jr.: Re: multiplier
20688: 00/02/17: Ray Andraka: Re: multiplier
20707: 00/02/18: Don Husby: Re: multiplier
20614: 00/02/16: Tim Forcer: Using JTAG on XC4k
20855: 00/02/24: Tim Forcer: Re: Using JTAG on XC4k
20896: 00/02/25: Alain Cloet: Re: Using JTAG on XC4k
20622: 00/02/16: Theron Hicks: loading FPGA from PROM's? file type?
20625: 00/02/16: Richard Dempster: Choosing the correct size FPGA
20647: 00/02/16: Peter Alfke: Re: Choosing the correct size FPGA
20651: 00/02/16: Ben Franchuk: Re: Choosing the correct size FPGA
20658: 00/02/17: Ray Andraka: Re: Choosing the correct size FPGA
20631: 00/02/16: <jlamorie@engsoc.carleton.ca>: How to manage projects with Xilinx?
20634: 00/02/16: Dave Vanden Bout: Re: How to manage projects with Xilinx?
20669: 00/02/17: <jlamorie@engsoc.carleton.ca>: Re: How to manage projects with Xilinx?
20680: 00/02/17: Dave Vanden Bout: Re: How to manage projects with Xilinx?
20633: 00/02/16: Andy Krumel: Spartan-II Pricing - What gives?
20664: 00/02/17: Steven Derrien: Re: Spartan-II Pricing - What gives?
20673: 00/02/17: Keith Jasinski, Jr.: Re: Spartan-II Pricing - What gives?
20892: 00/02/25: Ulf Samuelsson: Re: Spartan-II Pricing - What gives?
20637: 00/02/16: Xanatos: Simple (?) Question about FPGA Test/Demo Boards....
20668: 00/02/17: <gazit@my-deja.com>: Re: Simple (?) Question about FPGA Test/Demo Boards....
20640: 00/02/16: Federico Silla: Logiblox and virtex
20663: 00/02/17: Steven Derrien: Re: Logiblox and virtex
20665: 00/02/17: P Little: Re: Logiblox and virtex
20717: 00/02/18: Alfred Rodriguez: Re: Logiblox and virtex
20641: 00/02/16: Joseph H Allen: Xilinx hold time problems...
20642: 00/02/16: Magnus Homann: Re: Xilinx hold time problems...
20643: 00/02/16: Joseph H Allen: Re: Xilinx hold time problems...
20649: 00/02/16: Magnus Homann: Re: Xilinx hold time problems...
20645: 00/02/16: Xanatos: Re: Xilinx hold time problems...
20657: 00/02/16: Rickman: Re: Xilinx hold time problems...
20659: 00/02/17: Bob Perlman: Re: Xilinx hold time problems...
20648: 00/02/16: Peter Alfke: Re: Xilinx hold time problems...
20653: 00/02/17: Bob Perlman: Re: Xilinx hold time problems...
20674: 00/02/17: Joseph H Allen: Re: Xilinx hold time problems...
20675: 00/02/17: Joseph H Allen: Re: Xilinx hold time problems...
20686: 00/02/17: Paul Urbanus: Re: Xilinx hold time problems...
20679: 00/02/17: Hernan Saab: Re: Xilinx hold time problems...
20687: 00/02/17: Ray Andraka: Re: Xilinx hold time problems...
20644: 00/02/16: Gary Spivey: Runtime Conditionals?
20654: 00/02/16: Andy Peters: Re: Runtime Conditionals?
20646: 00/02/16: Gary Spivey: Writing to STDOUT?
20650: 00/02/16: rudy munguia: Request for Info
20660: 00/02/17: Ray Andraka: Re: Request for Info
20666: 00/02/17: Riad BOURGUIBA: CLAy 31 datasheet
20671: 00/02/17: Ray Andraka: Re: CLAy 31 datasheet
20670: 00/02/17: Matt Billenstein: Suggested prototyping boards < $200
20678: 00/02/17: Sergio A. Cuenca Asensi: Re: Suggested prototyping boards < $200
20693: 00/02/17: John Rible: Re: Suggested prototyping boards < $200
20698: 00/02/18: Ray Andraka: Re: Suggested prototyping boards < $200
20713: 00/02/18: Tim Tyler: Re: Suggested prototyping boards < $200
20705: 00/02/18: Leon Heller: Re: Suggested prototyping boards < $200
20676: 00/02/17: <ahf@watson.ibm.com>: GLSVLSI-2000
20700: 00/02/18: Tim Tuan: protocol implementations
20701: 00/02/18: Felix Deutsch: Re: protocol implementations
20720: 00/02/19: stanislav shalunov: Re: protocol implementations
20703: 00/02/18: Jun Yang: Does testability measurement play an inportant role in DFT?
20704: 00/02/18: Steve Charlwood: Interfacing multiple clock domains via FIFOs in XCV300
20714: 00/02/18: Bill Kury: Advanced Digital Design book
20774: 00/02/21: <jlamorie@engsoc.carleton.ca>: Re: Advanced Digital Design book
20715: 00/02/18: Nestor: Generating a Higher Frequency Clock from a Lower One in FPGA
20726: 00/02/19: Peter Alfke: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20737: 00/02/20: Hal Murray: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20738: 00/02/20: Ray Andraka: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20745: 00/02/20: <nestor@ece.concordia.ca>: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20747: 00/02/20: Ray Andraka: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20762: 00/02/21: Hal Murray: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20778: 00/02/22: jim granville: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20783: 00/02/22: Mark Harvey: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20785: 00/02/22: Dominique SZYMIK: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20916: 00/02/27: =?koi8-r?B?88HXwSD2ydfBzs/XyT8gKFNhdmEgWnhpdmFub3ZpY2gp?=: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20716: 00/02/18: Nestor: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20718: 00/02/18: Ray Andraka: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20724: 00/02/19: <nestor@stansync.com>: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20721: 00/02/18: Peter Alfke: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20723: 00/02/19: <nestor@stansync.com>: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20719: 00/02/18: <ritchie99_uk@my-deja.com>: BEHAVIOURAL VHDL
20728: 00/02/19: Ray Andraka: Re: BEHAVIOURAL VHDL
20732: 00/02/19: J.R.: Re: BEHAVIOURAL VHDL
20736: 00/02/20: Ray Andraka: Re: BEHAVIOURAL VHDL
20771: 00/02/21: Andrew Ince: Re: BEHAVIOURAL VHDL
20773: 00/02/21: rk: Re: BEHAVIOURAL VHDL
21030: 00/03/03: <1209@my-deja.com>: Re: BEHAVIOURAL VHDL
21040: 00/03/03: Ray Andraka: Re: BEHAVIOURAL VHDL
20722: 00/02/18: Tim Tuan: Xilinx 9500 CPLD
20725: 00/02/19: Peter Alfke: Re: Xilinx 9500 CPLD
20727: 00/02/19: Keyvan Irani: x18 FIFO's in Virtex
20729: 00/02/19: Ray Andraka: Re: x18 FIFO's in Virtex
20743: 00/02/20: Peter Alfke: Re: x18 FIFO's in Virtex
20730: 00/02/19: Peter: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20731: 00/02/19: Ray Andraka: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20744: 00/02/20: Peter: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20746: 00/02/20: Ray Andraka: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20753: 00/02/20: Peter Alfke: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20779: 00/02/22: Austin Franklin: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20750: 00/02/20: Mark Harvey: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20754: 00/02/20: Ray Andraka: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20780: 00/02/22: Austin Franklin: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20995: 00/03/02: Peter: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20999: 00/03/02: Ray Andraka: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20733: 00/02/19: aaf: Lattice Download Cable
20799: 00/02/23: Fuzesi Arnold: Re: Lattice Download Cable
20734: 00/02/19: Pai Chou: Call for Participation: SIGDA Ph.D. Forum at DAC'2000
20735: 00/02/20: Ray Andraka: Distributed Arithmetic De-mystified
20772: 00/02/21: Jerry Avins: Re: Distributed Arithmetic De-mystified
20782: 00/02/22: Gilbert H. Herbeck: Re: Distributed Arithmetic De-mystified
20795: 00/02/22: Ray Andraka: Re: Distributed Arithmetic De-mystified
20802: 00/02/23: E. Robert Tisdale: Bit Serial Arithmetic De-mystified
20805: 00/02/23: Peter Alfke: Re: Bit Serial Arithmetic De-mystified
20807: 00/02/23: Herman: Re: Bit Serial Arithmetic De-mystified
20813: 00/02/23: Jerry Avins: Re: Bit Serial Arithmetic De-mystified
20971: 00/03/01: Andy Peters: Re: Bit Serial Arithmetic De-mystified
20809: 00/02/23: Ray Andraka: Re: Bit Serial Arithmetic De-mystified
20828: 00/02/23: E. Robert Tisdale: Re: Bit Serial Arithmetic De-mystified
20835: 00/02/23: Jerry Avins: Re: Bit Serial Arithmetic De-mystified
20849: 00/02/24: Ray Andraka: Re: Bit Serial Arithmetic De-mystified
20856: 00/02/24: Gary Cook: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
20994: 00/03/02: Andy Peters: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
20997: 00/03/02: Edward Lee: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
20832: 00/02/23: Crackpot: Re: Bit Serial Arithmetic De-mystified
20812: 00/02/23: Jerry Avins: Re: Bit Serial Arithmetic De-mystified
20825: 00/02/23: rk: Re: Bit Serial Arithmetic De-mystified
20826: 00/02/23: Jerry Avins: Re: Bit Serial Arithmetic De-mystified
20860: 00/02/24: russell shaw: Re: Bit Serial Arithmetic De-mystified
20862: 00/02/24: George Russell: Re: Bit Serial Arithmetic De-mystified
20870: 00/02/24: Jerry Avins: Re: Bit Serial Arithmetic De-mystified
20871: 00/02/24: E. Robert Tisdale: Re: Bit Serial Arithmetic De-mystified
20874: 00/02/24: Bob Cain: Re: Bit Serial Arithmetic De-mystified
20878: 00/02/24: rk: Re: Bit Serial Arithmetic De-mystified
20900: 00/02/26: Steven J. Ackerman: Re: Bit Serial Arithmetic De-mystified
20983: 00/03/02: jg.campbell: Re: Bit Serial Arithmetic De-mystified
20822: 00/02/23: Lasse Langwadt Christensen: Re: Bit Serial Arithmetic De-mystified
20834: 00/02/23: Crackpot: Re: Bit Serial Arithmetic De-mystified
20837: 00/02/23: Jerry Avins: Re: Bit Serial Arithmetic De-mystified
20748: 00/02/20: <dave_admin@my-deja.com>: Divider
20752: 00/02/20: Juliusz: Re: Divider
20755: 00/02/20: Ray Andraka: Re: Divider
20756: 00/02/20: Antonio =?iso-8859-1?Q?Mart=EDnez=20=C1lvarez?=: Re: Divider
21064: 00/03/05: Steve Brainard: Re: Divider
20760: 00/02/20: Swapnajit Mittra: Re: Divider
20749: 00/02/20: <dave_admin@my-deja.com>: Divider
20751: 00/02/20: Alain BROISIN: Spartan Config
20758: 00/02/20: <rotemg@mysticom.com>: Passing multi-cycle timing constrains from Synplify to M1
20761: 00/02/21: Ray Andraka: Re: Passing multi-cycle timing constrains from Synplify to M1
20766: 00/02/21: <gazit@my-deja.com>: Re: Passing multi-cycle timing constrains from Synplify to M1
20770: 00/02/21: Ray Andraka: Re: Passing multi-cycle timing constrains from Synplify to M1
20823: 00/02/23: <gazit@my-deja.com>: Re: Passing multi-cycle timing constrains from Synplify to M1
20759: 00/02/20: <rotemg@mysticom.com>: Passing multi-cycle timing constrains from Synplify to M1
20768: 00/02/21: info: GateVision - Netlist to Schematic Generation Tools
20775: 00/02/21: Jaime Andrés Aranguren Cardona: Installing Xilinx Foundation on PC
20820: 00/02/23: Nicolas Matringe: Re: Installing Xilinx Foundation on PC
20857: 00/02/24: Yacine EL KOLLI: Re: Installing Xilinx Foundation on PC
20829: 00/02/23: <a@z.com>: Re: Installing Xilinx Foundation on PC
20838: 00/02/23: David Hawke: Re: Installing Xilinx Foundation on PC
20776: 00/02/21: Andrew McCartney: JTAG Programmer & Windows 2000
20946: 00/02/29: Robert Binkley: Re: JTAG Programmer & Windows 2000
20988: 00/03/02: Edward Lee: Re: JTAG Programmer & Windows 2000
21056: 00/03/04: Kasper Pedersen: Re: JTAG Programmer & Windows 2000
21062: 00/03/05: Edward Lee: Re: JTAG Programmer & Windows 2000
21091: 00/03/06: Kasper Pedersen: Re: JTAG Programmer & Windows 2000
21063: 00/03/05: Alain Cloet: Re: JTAG Programmer & Windows 2000
21092: 00/03/06: Kasper Pedersen: Re: JTAG Programmer & Windows 2000
20786: 00/02/22: fred cezilly: Signal visualization debug
20787: 00/02/22: <bjorn_lindegren@my-deja.com>: CPLD communication->LabVIEW
20788: 00/02/22: Davide Falchieri: ASP: Addressable Scan Port
20789: 00/02/22: Holger Kleinert: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20790: 00/02/22: S Lam: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20797: 00/02/22: 2.1 Meter Observer: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20817: 00/02/23: Holger Kleinert: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20796: 00/02/22: 2.1 Meter Observer: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20816: 00/02/23: Holger Kleinert: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20819: 00/02/23: Frank Poppen: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20833: 00/02/23: seamus: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20843: 00/02/24: Takemoto,Satoru: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
21222: 00/03/10: lino: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20791: 00/02/22: Michal Smulski: Xilinx App 058
20792: 00/02/22: Fabrice Hoffmann: ALTERA BitBlaster
20815: 00/02/23: Andreas Heiner: Re: ALTERA BitBlaster
20821: 00/02/23: Fabrice Hoffmann: Re: ALTERA BitBlaster
20824: 00/02/23: Andreas Heiner: Re: ALTERA BitBlaster
20839: 00/02/23: Armin Mueller: Re: ALTERA BitBlaster
20793: 00/02/22: Rickman: MRP systems
20810: 00/02/22: Fred Marshall: Re: MRP systems
20851: 00/02/23: Rickman: Re: MRP systems
20852: 00/02/24: Herman: Re: MRP systems
20882: 00/02/25: Ralph Weir: Re: MRP systems
20893: 00/02/25: Rickman: Re: MRP systems
20865: 00/02/24: <rob_dickinson@my-deja.com>: Re: MRP systems
20905: 00/02/26: Rick Lyons: Re: MRP systems
20907: 00/02/26: Ray Andraka: Re: MRP systems
20910: 00/02/26: Rickman: Re: MRP systems
20794: 00/02/22: Thomas P. Myers: Re: IEC 1131-3 i NEED HELP
20798: 00/02/22: Matt Billenstein: Xilinx Logic Simulator Foundation 2.1i help
20800: 00/02/23: Fuzesi Arnold: Xchecker schematic?
20808: 00/02/23: Ray Andraka: Re: Xchecker schematic?
20830: 00/02/23: <a@z.com>: Re: Xchecker schematic?
20831: 00/02/23: Tom Burgess: Re: Xchecker schematic?
20850: 00/02/24: Ray Andraka: Re: Xchecker schematic?
20864: 00/02/24: <a@z.com>: Re: Xchecker schematic?
20867: 00/02/24: Etienne Racine: Virtex DLL & JTAG (was Re: Xchecker schematic?)
20858: 00/02/24: Fuzesi Arnold: Re: Xchecker schematic?
20844: 00/02/24: rfbrw: Re: Xchecker schematic?
20876: 00/02/25: <alex65536@my-deja.com>: Re: Xchecker schematic?
20801: 00/02/23: J.R.: Help!!!
20803: 00/02/22: Rickman: Re: Help!!!
20804: 00/02/23: Peter Alfke: Re: Help!!!
20811: 00/02/23: J.R.: Re: Help!!!
20806: 00/02/23: Greg Neff: FAA doc on FPGA/ASIC design/test
20814: 00/02/23: wannarat: Noise to RAM
20836: 00/02/23: Uwe Bonnes: Re: Noise to RAM
20818: 00/02/23: <ajit_madhekar@my-deja.com>: PCI problem
20842: 00/02/23: Bruce McArdle: Re: PCI problem
20827: 00/02/23: Radoslaw Gasiorek: IEC 1131-3 i NEED HELP
20848: 00/02/24: jim granville: Re: IEC 1131-3 i NEED HELP
20845: 00/02/23: Balaji Rangaswamy: test
20846: 00/02/23: Balaji Rangaswamy: PWM implementation in Flex 10K.
20869: 00/02/24: Carlhermann Schlehaus: Re: PWM implementation in Flex 10K.
20879: 00/02/25: Steve Rencontre: Re: PWM implementation in Flex 10K.
20847: 00/02/24: <usenet201@hotmail.com>: Interfacing Xilinx PCI32 Logicore with external Dual-Port sync. SRAM?
20853: 00/02/24: Kenneth Porter: Re: Required, 16 bit micro, with onchip protected eeprom/flash
20859: 00/02/24: Markus Michel: PCI 64 bit / 66 MHz
20861: 00/02/24: Steven Derrien: Re: PCI 64 bit / 66 MHz
20908: 00/02/26: peter dudley: Re: PCI 64 bit / 66 MHz
20919: 00/02/28: Malachy Devlin: PCI 64 bit / 66 MHz
20866: 00/02/24: Nicolas Matringe: Xilinx PCI pinout ?
20881: 00/02/25: Ken Schmidt: Re: Xilinx PCI pinout ?
20883: 00/02/25: Nicolas Matringe: Re: Xilinx PCI pinout ?
20886: 00/02/25: Andreas Heiner: Re: Xilinx PCI pinout ?
20887: 00/02/25: Nicolas Matringe: Re: Xilinx PCI pinout ?
20890: 00/02/25: David Hawke: Re: Xilinx PCI pinout ?
20968: 00/03/01: Holger Kleinert: Re: Xilinx PCI pinout ?
20978: 00/03/01: Steve Casselman: Re: Xilinx PCI pinout ?
20868: 00/02/24: Arrigo Benedetti: Automatic retiming in FPGA Express
20872: 00/02/24: Arrigo Benedetti: Re: Automatic retiming in FPGA Express
20875: 00/02/25: anup kumar raghavan: FPGA Express Synthesis Now Available Over The Internet
20880: 00/02/25: Ken Schmidt: $6 32 bit/33 MHz PCI Xilinx: Fact or Fiction?
20884: 00/02/25: PEDRO C. GUILLEM VALENTIN: DISTRIBUIDOR
20895: 00/02/25: Ewan D. Milne: Foundation 2.1i device support?
20898: 00/02/25: David Hawke: Re: Foundation 2.1i device support?
20903: 00/02/26: <imclaren@california.com>: Re: Foundation 2.1i device support?
20917: 00/02/28: Peter: Re: Foundation 2.1i device support?
20897: 00/02/25: Tom McLaughlin: Xilinx in system programmable proms and JTAG
20904: 00/02/26: =?koi8-r?B?88HXwSD2ydfBzs/XyT8gKFNhdmEgWnhpdmFub3ZpY2gp?=: ISP in the Field
20906: 00/02/26: <margaretatwork@my-deja.com>: IC Validation Engineers/Managers Wanted
20909: 00/02/27: Pradeep Rao: Galois Coefficients g0,g1,...
20926: 00/02/28: Umesh Chandra Gowda: Re: Galois Coefficients g0,g1,...
20913: 00/02/27: Austin Franklin: Xilinx 1802/4 SPROMs....anyone get them to actually work?
20914: 00/02/27: Austin Franklin: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work?
20931: 00/02/29: Austin Franklin: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work? - FIXED!!!
21025: 00/03/03: Austin Franklin: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work? - FIXED!!!
20915: 00/02/27: Jamil Khatib: clocked or not clocked?
20918: 00/02/28: JRei7227: Xilinx Abel Problems
20920: 00/02/28: Tom Burgess: Re: Xilinx Abel Problems
20945: 00/02/29: Dennis McCrohan: Re: Xilinx Abel Problems
20921: 00/02/28: myself: atmel fpga starter kit
20923: 00/02/28: Andy Peters: Re: atmel fpga starter kit
20924: 00/02/28: Peter Alfke: Re: atmel fpga starter kit
20929: 00/02/29: Wiggo Olufsen: Re: atmel fpga starter kit
20936: 00/02/29: myself: Re: atmel fpga starter kit
20922: 00/02/28: Antonio Joaquim A Esteves: PCI Core Problem
20987: 00/03/02: Rickman: Re: PCI Core Problem
21053: 00/03/04: mike johnson: Re: PCI Core Problem
21067: 00/03/05: Rickman: Re: PCI Core Problem
20927: 00/02/28: test: XABEL State Machines?
20943: 00/02/29: Dennis McCrohan: Re: XABEL State Machines?
20928: 00/02/28: Karl Olsen: Asynchronous flipflops in Cypress CPLDs with Warp VHDL
20938: 00/02/29: KJ: Re: Asynchronous flipflops in Cypress CPLDs with Warp VHDL
20951: 00/02/29: Karl Olsen: Re: Asynchronous flipflops in Cypress CPLDs with Warp VHDL
20930: 00/02/29: Greg Deych: Extremely fault tolerant strategies
20937: 00/02/29: Terje Mathisen: Re: Extremely fault tolerant strategies
20940: 00/02/29: Greg Deych: Re: Extremely fault tolerant strategies
20947: 00/02/29: Greg Neff: Re: Extremely fault tolerant strategies
20953: 00/02/29: Jan Mikkelsen: Re: Extremely fault tolerant strategies
21295: 00/03/15: Gary Watson: Re: Extremely fault tolerant strategies
20981: 00/03/01: Philip Koopman: Re: Extremely fault tolerant strategies
20985: 00/03/02: Daryl Bradley: Re: Extremely fault tolerant strategies
20989: 00/03/02: Mark W Brehob: Re: Extremely fault tolerant strategies
20992: 00/03/02: Brian Drummond: Re: Extremely fault tolerant strategies
21028: 00/03/03: <gdeych@my-deja.com>: Re: Extremely fault tolerant strategies
21198: 00/03/10: Mark Thorson: Re: Extremely fault tolerant strategies
21221: 00/03/10: Tom Burgess: Re: Extremely fault tolerant strategies
21226: 00/03/11: Ben Franchuk: Re: Extremely fault tolerant strategies
20932: 00/02/29: News: Foundation2.1i installation problem in Win98se
20934: 00/02/29: Jürgen Marquardt: Philips LA PM3585 disassembler software wanted
20977: 00/03/01: Peter: Re: Philips LA PM3585 disassembler software wanted
160917: 18/12/17: David Brown: Re: Philips LA PM3585 disassembler software wanted
160921: 18/12/19: David Brown: Re: Philips LA PM3585 disassembler software wanted
160918: 18/12/17: <frankcovending@gmail.com>: Re: Philips LA PM3585 disassembler software wanted
160920: 18/12/18: Nicolas Matringe: Re: Philips LA PM3585 disassembler software wanted
160922: 18/12/19: <frankcovending@gmail.com>: Re: Philips LA PM3585 disassembler software wanted
20935: 00/02/29: henry: Delay Lines using FPGA ??
20942: 00/02/29: Peter Alfke: Re: Delay Lines using FPGA ??
20944: 00/02/29: Mike Treseler: Re: Delay Lines using FPGA ??
20957: 00/02/29: Phil Hays: Re: Delay Lines using FPGA ??
21019: 00/03/03: henry: Re: Delay Lines using FPGA ??
20939: 00/02/29: Gareth Jones: FilterExpress version 3.0 now available
21070: 00/03/06: Hans Holm: Re: FilterExpress version 3.0 now available
20941: 00/02/29: <stang99@my-deja.com>: Book recommendations?
20948: 00/02/29: Domagoj: Re: Book recommendations?
20958: 00/03/01: Edwin Naroska: Re: Book recommendations?
21241: 00/03/12: Steven K. Knapp: Re: Book recommendations?
20949: 00/02/29: Rick Filipkiewicz: How to use the Xilinx FG676 package ?
20950: 00/02/29: Number Cruncher: Recommended VHDL titles wanted ...
20952: 00/02/29: Jonathan Bromley: Re: Recommended VHDL titles wanted ...
20954: 00/02/29: rk: Re: Recommended VHDL titles wanted ...
20973: 00/03/01: Number Cruncher: Re: Recommended VHDL titles wanted ...
20955: 00/02/29: <wamsi@my-deja.com>: Xilinx Tools Vs Altera tools
20960: 00/03/01: Georg Berliner: Re: Xilinx Tools Vs Altera tools
20961: 00/03/01: David Hawke: Re: Xilinx Tools Vs Altera tools
20963: 00/03/01: <wamsi@my-deja.com>: Re: Xilinx Tools Vs Altera tools
20974: 00/03/01: Jerry English: Re: Xilinx Tools Vs Altera tools
20976: 00/03/01: Ray Andraka: Re: Xilinx Tools Vs Altera tools
20982: 00/03/02: Bob Baman: Re: Xilinx Tools Vs Altera tools
20990: 00/03/02: Ray Andraka: Re: Xilinx Tools Vs Altera tools
21001: 00/03/02: David Bishop: Re: Xilinx Tools Vs Altera tools
20984: 00/03/02: David Hawke: Re: Xilinx Tools Vs Altera tools
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