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Magnus Homann wrote in message ...
>"Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> writes:
>
>> Had the Spartan-II been available six months ago when I started down this
>> route, I would've chosen it! OK, you just have to add that other voltage
>> regulator. That would make three power supplies on the board!
>
>Only three? Let me know when you have 5V, 3.3V, 2.5V, 2.05V, 1.8V and
>some +/- 12V...
Uncle :)
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20501
elynum@my-deja.com wrote in message <881odi$nc6$1@nnrp1.deja.com>...
>Thanks, guys!
>What would the benefits be to using a serial eeprom over an
>microprocessor or vice versa to program the fpgas?
Well, if your application doesn't have a local processor, you'll need an
SPROM (or a parallel EPROM and a small PLD) to configure your chip.
if you have a local CPU and your FPGA is not required to be alive before the
CPU, then using the CPU to configure the FPGA is a cool thing - it'll save
you the cost of a serial PROM (which, as someone has pointed out, might cost
more than the FPGA!).
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20502
Magnus Homann wrote in message ...
>
>Hello,
>
>One of the FPGA we are using (Xilinx, XCV300) sometimes has a small
>hickup. I would like to invite your opinion on where I should look
>first.
>
>The Design:
>
>A memory controller unit that fetches a packet from the SRAM, feeeds
>the apcket into a FIFO. The last byte of the packet is marked with a
>special bit. Ojn the others side of the FIFO a packet processor
>massages every byte, and puts them back into another FIFO, the last
>byte still marked. The memory controller then outputs the result to the
memory
>again.
>
>The problem:
>
>On _some_ boards, in _elevated temperature_, a problem occur _after a
>while_. The output data gets out of sync with the input data, i.e. it
>is stored in the buffer that belongs to the output buffer of the
>_next_ input packet. This out of synch then continues.
>
>Where to start looking? We suspect an erroneus flag in the FIFO, so
>that an extra packet delimiter is inserted in output FIFO.
>
>Some extra info:
>Synchronous design, all flops and FIFO on rising edge only.
>STA suggest 45 Mhz max freq., but we only run at 33 MHz.
>STA reports 96% covered by constraints.
>The packet processing half of the design can be with another, similar
>entity, and then the problem disappear.
>Simulation shows no problem, even after P&R and with SDF.
>
>What do you think? A problem with the part going out of spec? or is it
>our VHDL-code that hides some ugly stuff?
>
>Comments welcome!
I will assume that your FIFO and SRAM are both external to your FPGA.
Are these memory devices synchronous? Are you meeting their setup and hold
times? I use offset constraints when interfacing to memories like this -
that way, the memories' setup requirements are taken into account.
Do you think you might have a skew problem between the FPGA's clock and the
FIFO's clock?
These are just some thoughts!
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20503You might want to try the correct syntax: 'RLOC_RANGE=R1C1:R2C2' Certainly the syntax in the online docs could be a little clearer. Your lower case "r" and "c" are un-needed. Of course, it would have been nice for the Xilinx tools to have told you that, and issued some type of error message. Maybe it did. Did you check all the report files? But see their example in the UCF section: INST /archive/designs/MACRO4 RLOC_RANGE=R4C4:R10C10; Philip In article <8808l8$spo$1@news.qub.ac.uk>, George <g_roberts75@hotmail.com> wrote: >Hi Folks, > >I am using Foundation 2.1i-SP4 to target XC4000. I am having problems using >the 'RLOC_RANGE' property. I am using schematic design entry. I attach the >property 'RLOC_RANGE=Rr1Cc1:Rr2Cc2' to a symbol in order to place it between >Rows r1 and r2, and between Columns c1 and c2. However, when it maps, it >does not give what I expect. It seems that it is ignoring this directive. >Has anybody out there used this property? How did it work for you? > >I appreciate your help. > >Article: 20504
r1, r2 , c1 and c2 are just variables standing for real values... The syntax is right.Article: 20505
Hi,
I am a student of the University Of Cincinnati. This query is about
a problem in using the synthesis tools for the WILDFORCE board. This
board is made up of 4 FPGA's.
I get these errors in wildforce synthesis. I am using synopsys
tools for synthesis and M1 tools for routing and placement in to a
4036xl fpga.
ERROR:basnu:128 - output pad net "PAD_MboxSelect" drives multiple
buffers
ERROR:basnu:129 - output pad net "PAD_MboxSelect" has an illegal buffer
ERROR:basnu:130 - output pad net "PAD_MboxSelect" is not driven by an
output
ERROR:basnu:142 - output pad net "PAD_MboxSelect" has an illegal
connection
ERROR:basnu:142 - output pad net "U_IF/n1808" has an illegal connection
ERROR:basnu:142 - output pad net "U_IF/n1822" has an illegal connection
>>>>> Excess stuff deleted by Archive Owner
ERROR:basnu:142 - output pad net "U_IF/n1807" has an illegal connection
ERROR:basnu:142 - output pad net "U_IF/n1816" has an illegal connection
and sooon. PLease give me any pointers to information or anything that
would help.
Shrinath Kutty.
Article: 20506"Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> writes: > Magnus Homann wrote in message ... > > > >Hello, > > > >One of the FPGA we are using (Xilinx, XCV300) sometimes has a small > >hickup. I would like to invite your opinion on where I should look > >first. > > > >The Design: > > > >A memory controller unit that fetches a packet from the SRAM, feeeds > >the apcket into a FIFO. The last byte of the packet is marked with a > >special bit. Ojn the others side of the FIFO a packet processor > >massages every byte, and puts them back into another FIFO, the last > >byte still marked. The memory controller then outputs the result to the > memory > >again. > > > >The problem: > > > >On _some_ boards, in _elevated temperature_, a problem occur _after a > >while_. The output data gets out of sync with the input data, i.e. it > >is stored in the buffer that belongs to the output buffer of the > >_next_ input packet. This out of synch then continues. > > > >Where to start looking? We suspect an erroneus flag in the FIFO, so > >that an extra packet delimiter is inserted in output FIFO. > > > >Some extra info: > >Synchronous design, all flops and FIFO on rising edge only. > >STA suggest 45 Mhz max freq., but we only run at 33 MHz. > >STA reports 96% covered by constraints. > >The packet processing half of the design can be with another, similar > >entity, and then the problem disappear. > >Simulation shows no problem, even after P&R and with SDF. > > > >What do you think? A problem with the part going out of spec? or is it > >our VHDL-code that hides some ugly stuff? > > > >Comments welcome! > > I will assume that your FIFO and SRAM are both external to your FPGA. > > Are these memory devices synchronous? Are you meeting their setup and hold > times? I use offset constraints when interfacing to memories like this - > that way, the memories' setup requirements are taken into account. > > Do you think you might have a skew problem between the FPGA's clock and the > FIFO's clock? > > These are just some thoughts! Sorry, was a bit unclear. The FIFO is internal to the Virtex, but the SRAM is external. The reason the external interface isn't my first suspect, is that the error is not is so "symmetric". It doesn't write the data all over, but in a deterministic memory area. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 20507
TS Kutty wrote in message <38A51625.A87709CD@ececs.uc.edu>...
>Hi,
> I am a student of the University Of Cincinnati. This query is about
>a problem in using the synthesis tools for the WILDFORCE board. This
>board is made up of 4 FPGA's.
> I get these errors in wildforce synthesis. I am using synopsys
>tools for synthesis and M1 tools for routing and placement in to a
>4036xl fpga.
[snip errors]
sounds like your code isn't any good. did you do a simulation of your
source code before attempting to synthesize it?
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20508> You need then only four signals between boards (PRGM, DONE, CCLK and DIN). Peter already said it, but... Beware of signal integrity on CCLK. -- These are my opinions, not necessarily my employers.Article: 20509
> If you want to configure from a CPU, you'd use the slave parallel mode for > the first chip and slave serial for the second. Again, see the manual for > the exact interconnects. You can also configure from a CPU with the first chip in slave serial mode. It takes a few more lines of code as the CPU has to do the byte to bit conversion. That often saves a few pins on the FPGA and/or simplifies the data bus on the CPU. -- These are my opinions, not necessarily my employers.Article: 20510
> Where to start looking? We suspect an erroneus flag in the FIFO, so > that an extra packet delimiter is inserted in output FIFO. How about ripping the guts out of your FPGA design so you can focus on the external timings? Can you get a simpler case to fail in a similar way? How long does it take to fail? Can you get a logic analyzer to trigger when it doesn't work right? Try more heat/cold to make it fail more often. -- These are my opinions, not necessarily my employers.Article: 20511
I am a college student who is interested in computer architecture. However, I have some question about the Carry-Select Adder. Question 1: What is the carry-select adder in data path? Question 2: How we design an adder that uses MUXes and 1-Bit address that can run as fast as O(log n)? Thank you in advance for your help ANNOOB annoob@email.msn.comArticle: 20512
On Fri, 11 Feb 2000 15:41:36 GMT, elynum@my-deja.com wrote: |How would I go about programming 2 xilinx fpga's on a single board? |Would I need 2 separate EEPROM chips(ATMEl) or just one? How would |I go about doing it with a microprocessor 8051 or 860? What would I |need to do this? | | |Sent via Deja.com http://www.deja.com/ |Before you buy. Hi, we've done a few systems with one or two Xilinx fpga's which are loaded at powerup time by a CPU, generally an MC68332. We use a single eprom which holds the uP program and the config data for all the FPGAs. We use both fpga's in slave serial mode. The CPU needs N + 2 parallel port pins to program N fpga's: shared serial data DIN, shared clock CCLK, and one 'program' pin per chip. Works fine, and we can ship a customer a single eprom chip to upgrade his uP code and the fpga's. A 4013XL or an XCS20 Spartan configures in half a second maybe. JohnArticle: 20513
Hi, Can someone please tell me where I can get PLCC sockets for wire wrapping the Xilinx 4005e (85 pin). Please e-mail me directly... Take care, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin 805 West Oregon Street Urbana, IL 61801-3825 (217) 367-3877 martin2@acm.uiuc.edu http://fermi.isdn.uiuc.edu <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 20514
Hi, I need a schematic for how to connect the Xilinx DLC4 programmer to the XC4005e-4PC84C. After you program the XC4005e what pins must be connected? Does the chip function if only the Vcc and GND pins are connected? Please e-mail me directly... Take care, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin 805 West Oregon Street Urbana, IL 61801-3825 (217) 367-3877 martin2@acm.uiuc.edu http://fermi.isdn.uiuc.edu <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 20515
John Larkin wrote:Hi, > > we've done a few systems with one or two Xilinx fpga's which are > loaded at powerup time by a CPU, generally an MC68332. We use a single > eprom which holds the uP program and the config data for all the > FPGAs. We use both fpga's in slave serial mode. The CPU needs N + 2 > parallel port pins to program N fpga's: shared serial data DIN, shared > clock CCLK, and one 'program' pin per chip. Works fine, and we can > ship a customer a single eprom chip to upgrade his uP code and the > fpga's. A 4013XL or an XCS20 Spartan configures in half a second > maybe. > > John I suppose this works, but it is very peculiar. It seems to be optimized for individual reprogramming at arbitrary times. The more conventional method would daisy-chain the two FPGAs: interconnecting CCLKs, but have the first chip's Dout feed the next chip's Din, as describes in many places in the Xilinx data book. Configuration speed, in this application, is determined by the microprocessor. From the FPGA's point of view, you can run CCLK at 10 MHz, which configures two daisy-chained XC4013XLs ( each 393 632 bits ) in less than 80 ms. At slower CCLK rates it takes proportionally longer. I recommend reading pages 14-30 through 45 of the Xikinx 1999 data book. Peter Alfke, Xilinx ApplicationsArticle: 20516
Hi,
Thanks for reply.
The code that I am using is of the blank architecture. I am attaching
the code that I am using. It would be great if you give some pointers
regarding the mistakes that I am commitingin the code
Andy Peters wrote:
> TS Kutty wrote in message <38A51625.A87709CD@ececs.uc.edu>...
> >Hi,
> > I am a student of the University Of Cincinnati. This query is about
> >a problem in using the synthesis tools for the WILDFORCE board. This
> >board is made up of 4 FPGA's.
> > I get these errors in wildforce synthesis. I am using synopsys
> >tools for synthesis and M1 tools for routing and placement in to a
> >4036xl fpga.
>
> [snip errors]
>
> sounds like your code isn't any good. did you do a simulation of your
> source code before attempting to synthesize it?
>
> -- a
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "Money is property; it is not speech."
> -- Justice John Paul Stevens
>>>>> Huge pile of Copyrighted VHDL deleted by Archive Owner
Article: 20517
This is a multi-part message in MIME format.
--------------032FA2A9ABF2A538BB748C8C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Sir,
I did not simulate it. But it is a blank architecture that I am trying
to synthesise.
Please tell me if I can send the actual .vhd files I am using the .vhd files
given by wildforce to do my synthesis. I want to get the environment right
before I start synthesizing for my research.
For now I am attaching the pe1lca.vhd file. This is the logic core that is
the only part that we write. Aso I am sending you the pe1ifa.vhd, file that
is the interface file in which the errors are comming.
Shrinath Kutty
Andy Peters wrote:
> TS Kutty wrote in message <38A51625.A87709CD@ececs.uc.edu>...
> >Hi,
> > I am a student of the University Of Cincinnati. This query is about
> >a problem in using the synthesis tools for the WILDFORCE board. This
> >board is made up of 4 FPGA's.
> > I get these errors in wildforce synthesis. I am using synopsys
> >tools for synthesis and M1 tools for routing and placement in to a
> >4036xl fpga.
>
> [snip errors]
>
> sounds like your code isn't any good. did you do a simulation of your
> source code before attempting to synthesize it?
>
> -- a
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "Money is property; it is not speech."
> -- Justice John Paul Stevens
>>>>> Huge pile of Copyrighted VHDL deleted by Archive Owner
Article: 20518On Sat, 12 Feb 2000, Asher C. Martin wrote: > Hi, > > I need a schematic for how to connect the Xilinx DLC4 programmer to the > XC4005e-4PC84C. After you program the XC4005e what pins must be > connected? Does the chip function if only the Vcc and GND pins are > connected? According to Xilinx's page you can program the XC4005e... with the following setup... (see figure) http://toolbox.xilinx.com/docsan/2_1i/data/common/hug/fig11.htm or http://toolbox.xilinx.com/docsan/2_1i/data/common/hug/hug1_5.htm Take care, >Asher< <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> Asher C. Martin 805 West Oregon Street Urbana, IL 61801-3825 (217) 367-3877 martin2@acm.uiuc.edu http://fermi.isdn.uiuc.edu <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 20519
Hi, What is the best way to make a logic verification for FPGA designs. Does it depend on the size of the logic do I need to do formal verifications or so or is it enghough to use the simulation only because I can do reconfigure the FPGA in the debug stage? Thanks Jamil Khatib OpenIP Organization http://www.openip.org OpenIPCore Project http://www.openip.org/oc OpenCores Project http://www.opencores.orgArticle: 20520
Good luck. From what I've seen, people are not willing to pay much for FPGA based cores. Seems the silicon vendors have set the price expectations for cores well below the cost to develop, maintain and support such cores. Optimized FPGA cores are more difficult to design than comparable cores in ASICs, yet the market price for FPGA cores is orders of magnitude less than similar ASIC cores. fpgaer@my-deja.com wrote: > Hi, > > wld. appreciate if anyone cld. share their views on launching a co. > which delivers custom-made FPGA cores ? Wld. the effort be worth in > terms of time ( & money ) ...... specifically, is there a demanding > market for FPGA cores ??? > > Any comments wld. be highly appreciated !!! > > Thanks in advance........ > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20521
Check out some of the papers on my website. In particular, consider the radar on a chip paper from the Asilomar conference this past fall and the Radar simulator paper from MAPLD'98 (which is actually 8 older FPGAs, but the entire signal processing path is done in FPGAs). anurag wrote: > Hi, > > There's a lot of talk on IP for FPGAs - ( tons of articles can be found > on this at EET, EDTN, Optimagic....etc. sites). The > reconfigurable-silicon concept does look very powerful & attractive ! > The question is " What level of functional complexity can exactly be > achieved on the currently available FPGAs ? " > > The designs that I've come across so far are ,at best, complex > independent functional blocks ie; FIR/IIR filters, Veterbi > codecs....etc. I've yet to come across a full fledged system level > design on an FPGA - something like (say) a design where a FPGA can be > instantly reconfigured to be a MP3 codec in one mode and a soft modem in > another. Another ex. I cld. quote is a FPGA behaving as one of the > wireless air interface standards ie; GSM/TDMA/CDMA ( in other words - a > S/W radio ) depending on the core downloaded on it (an ASIC from > Motorola exactly does this ! ) > > What I'm trying to get at is that all this seems to be theoritically > possible but I haven't seen any working design yet ! Even the ref. > examples at the Xilinx site are mostly glue-logic designs. SO, can the > examples quoted above be realised on a FPGA ( assuming that the required > no. of gates are available ) ? > If not (since it's possible theoritically) what cld. be the primary > reason for this ? > > Any comments wld. be appreciated ! > > Thanks........Anurag > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20522
Not every flip flop in an FPGA design needs to be reset; You only need to reset select flip-flops to make sure that 'loops' in the logic reach a known state after some number of clock cycles. Data path will self clear, so there's no need to apply explicit resets. You may also want to reset the flip-flops closest to the outputs, and hold them reset for a number of clocks after reset is released. I know that this makes the ASIC guys blood curdle, but the fact of the matter is that it uses up resources in the FPGA and slows down your design. Rickman wrote: > Mark Luscombe wrote: > > > > Hi, > > > > I am trying to work out a satifactory method for resetting a > > synchronously design Virtex running at 74MHz. > > > > Now, the reset signal needs to be synchronised with the 74MHz clock > > and the propagation delay from this to the CLB and IOB DFFs needs to > > be less than 13ns to ensure that all registers within the device at > > reset on the sam clock edge. > > > > Xilinx seem to have been telling people not to use the GSR net, as it > > is too slow, but it does seem a pity not to use it, and use extra > > routing and CLB inputs for a global reset. > > > > It seems as though the STARTUP_VIRTEX component can accept a USER_CLK > > input, i.e. the 74MHz, so is this a good solution ? > > Also, this component has a GSR input for an external reset signal, > > does anybody know if this is also synchronised with the USER_CLK input > > ? > > The device is configured in 8-bit parallel with CCLK which is related > > to the 74MHz. > > > > What have other designers done in this situation. > > > > Cheers, Mark. > > This is a subject that is often discussed here. What you describe with > using a user clock for startup is one way to do it. That should work if > the GSR net is fast enough to operate within your clock cycle. > > Another way to use the GSR which does not depend on sychronized release > of the GSR is to make sure that all of the inputs to your various FSMs > or other sychronous logic are in a state that will not cause the > machines to make a state change. For example if the FSMs reset to an > IDLE state, then make sure that none of the inputs that let the machine > leave the IDLE state are asserted. Then even if the GSR is released on > different clock cycles for different FFs, it will not matter. > > Or use a couple of delay FFs to generate (from the GSR) a separate, > synchronized input to the FSMs which will delay state changes from this > initial state until it releases. This net will not need to go to all of > the FFs in your design and can be routed much faster. > > Another method which is similar to this last one is to have a separate, > external reset signal which is controlled by a micro or other logic. > This will only be released well after the config is complete and is > synchrnized to the clock. As in the last method, this reset will not > need to go to every FF in the FPGA and so can be routed more quickly. > > The GSR is nice in that it puts every FF into a known state and it is > asynch so it does it NOW! But releasing it can be a problem. A second, > more limited reset is a good way to get the FPGA started on the right > foot. > > I can't remember other ways that have been described, but I am sure > there are some. > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20523
Did you meet timing? (Stupid question perhaps, but worth asking). If you did, do you have signals crossing clock domains, and if you do have you done that crossing carefully so that you don't get hiccups there. Andy Peters wrote: > Magnus Homann wrote in message ... > > > >Hello, > > > >One of the FPGA we are using (Xilinx, XCV300) sometimes has a small > >hickup. I would like to invite your opinion on where I should look > >first. > > > >The Design: > > > >A memory controller unit that fetches a packet from the SRAM, feeeds > >the apcket into a FIFO. The last byte of the packet is marked with a > >special bit. Ojn the others side of the FIFO a packet processor > >massages every byte, and puts them back into another FIFO, the last > >byte still marked. The memory controller then outputs the result to the > memory > >again. > > > >The problem: > > > >On _some_ boards, in _elevated temperature_, a problem occur _after a > >while_. The output data gets out of sync with the input data, i.e. it > >is stored in the buffer that belongs to the output buffer of the > >_next_ input packet. This out of synch then continues. > > > >Where to start looking? We suspect an erroneus flag in the FIFO, so > >that an extra packet delimiter is inserted in output FIFO. > > > >Some extra info: > >Synchronous design, all flops and FIFO on rising edge only. > >STA suggest 45 Mhz max freq., but we only run at 33 MHz. > >STA reports 96% covered by constraints. > >The packet processing half of the design can be with another, similar > >entity, and then the problem disappear. > >Simulation shows no problem, even after P&R and with SDF. > > > >What do you think? A problem with the part going out of spec? or is it > >our VHDL-code that hides some ugly stuff? > > > >Comments welcome! > > I will assume that your FIFO and SRAM are both external to your FPGA. > > Are these memory devices synchronous? Are you meeting their setup and hold > times? I use offset constraints when interfacing to memories like this - > that way, the memories' setup requirements are taken into account. > > Do you think you might have a skew problem between the FPGA's clock and the > FIFO's clock? > > These are just some thoughts! > -- > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul Stevens -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20524
When you post your homework problems, you should put the post the figure too. Perhaps you ought to listen a little better in class and read your class notes or text. annoob wrote: > I am a college student who is interested in computer architecture. However, > I have some question about the Carry-Select Adder. > > Question 1: What is the carry-select adder in data path? > Question 2: How we design an adder that uses MUXes and 1-Bit address that > can run as fast as O(log n)? > > Thank you in advance for your help > > ANNOOB > annoob@email.msn.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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