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Authors (D)
D:
70630: 04/06/22: ROM instantiation question
70655: 04/06/22: Re: ROM instantiation question
D Brown:
41014: 02/03/19: Constraint File NET syntax
41060: 02/03/20: Re: Constraint File NET syntax
43580: 02/05/24: Xilinx Pull Ups/Dpwns
45077: 02/07/11: Deterministic Output?
45407: 02/07/22: Xilinx NGDBuild -sd option in Project Navigator?
45466: 02/07/24: Re: Xilinx NGDBuild -sd option in Project Navigator?
45475: 02/07/24: Gatelevel Simulation of Xilinx Block RAM
D Chiron:
6164: 97/04/21: palasm...
D Lee:
47610: 02/09/30: Re: design multiplier
61778: 03/10/10: Questions on Function Approximation (using FPGAs)
72219: 04/08/11: Re: ramdon noise generation
D Plunkett:
1165: 95/05/10: Lattice Ftp site ?
1409: 95/06/18: MACH110 Uk distributer ?
D Widel:
69006: 04/04/24: Help implementing a 74273 flip flop in a 9536 cpld
D Yuniskis:
146513: 10/03/21: Re: Finally, selling my old Xilinx/Viewlogic software package
D. Hibbs:
4665: 96/11/27: JEDEC file structure
D. Kruse:
71916: 04/08/03: nco and phase detector
D. Polo:
16107: 99/05/04: AHDL books
D. Rademaker VH233 4717:
5583: 97/02/26: Slew-rate control feature in XC4000E
D.A.Kopf:
41534: 02/04/01: Re: Data Compression in FPGAs
<d.cary@ieee.org>:
13220: 98/11/20: Re: Big-Endian vs Little-Endian
D.F. Spencer:
6838: 97/07/01: inexpensive Xilinx 3042A development
D.H. Chung:
8528: 98/01/06: Re: Design with EPM7128S
8569: 98/01/09: Re: ALTERA Global Signal
8637: 98/01/15: Re: Byteblaster
8648: 98/01/16: Re: Implementing Altera FIFOs without EABs
8668: 98/01/19: Re: FPGA core for ASIC?
8745: 98/01/24: Re: MAX+II software from Altera.
8828: 98/01/30: Re: ABEL to Altera-HDL? Group FAQ?
13343: 98/11/27: Re: Which parts are fastest for 3-state enables?
<D.J.Mulligan@gmail.com>:
128761: 08/02/05: Re: Loading the design from Compact Flash...
D2fabrizio:
37200: 01/12/03: Announce: TimingAnalyzer Program Update
41539: 02/04/01: Announce: TimingAnalyzer Program Update
42316: 02/04/20: Announce: non_overlapping_clocks script for TimingAnalyzer
42788: 02/05/02: new website for TimingAnalyzer
[D3]Asensoh.K.O:
868: 95/03/17: test
<188d77@compuserve.com>:
6966: 97/07/17: Get FREE PASSWORD TO 2000 SEX SITEs
<975d8@dfdfws.com>:
17404: 99/07/24: Sexy Stuff 59821
<d_cary@my-dejanews.com>:
14205: 99/01/20: Re: The development of a free FPGA synthesis tool
d_s_klein:
143358: 09/10/05: Re: Virtx 4 and FPGA programming
143851: 09/10/29: Re: error while opening hex file
143944: 09/11/04: Re: problem fpga aera optimization
144085: 09/11/10: Re: Dealing wiht multiple clock domain...cleanly?
144181: 09/11/17: Re: Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8
146018: 10/03/03: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146032: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146038: 10/03/04: Re: Ethernet development kit
146045: 10/03/04: Re: FPGA platform??
146333: 10/03/12: Re: Comparing FPGA with ASIC implementations
146334: 10/03/12: Re: Xilinx ISE Webpack Schematics
146385: 10/03/15: Re: Looking for a G.723.1 codec IP core for Xilinx FPGA
146404: 10/03/16: Re: ISE speed determined by console output?
146405: 10/03/16: Re: Looking for a G.723.1 codec IP core for Xilinx FPGA
146471: 10/03/19: Re: wishbone
146532: 10/03/22: Re: Quartus: rpm: Command not found.
146603: 10/03/23: Re: Quartus: rpm: Command not found.
146810: 10/03/29: Re: upgrading to ISE 11.x
146917: 10/04/01: Re: Predefined MACRO's in XST v11.5
147085: 10/04/13: Re: EDK BFM Simulation
147086: 10/04/13: Re: Microblaze Reset
147121: 10/04/14: Re: Quartus: rpm: Command not found.
147221: 10/04/19: Re: Need to run old 8051 firmware
147242: 10/04/20: Re: Developin tool for Xilinx XC2018
147416: 10/04/26: Re: ISE tools not detecting IOSTANDARD conflicts within bank
147451: 10/04/27: Re: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
147482: 10/04/28: Re: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
147789: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
147808: 10/05/25: Re: Xilinx Xact software for XC2018 Logic Cell Array
147809: 10/05/25: Re: Software bloat (Larkin was right)
147846: 10/05/26: Re: EDK BFM Simulation
148060: 10/06/17: Re: Why is Google so F****** dense about SPAM?
148155: 10/06/23: Re: Why is Google so F****** dense about SPAM?
148156: 10/06/23: Re: SDRAM capacity using Petalinux
148205: 10/06/28: Re: help with OVL on Actel tool
148222: 10/06/30: Re: Testbench
148245: 10/07/01: Re: Xilinx xapp175, empty + full flag really synchronous?
148294: 10/07/05: Re: software for xc3000
148337: 10/07/08: Re: Programming individual FPGAs in a daisy chain
148340: 10/07/08: Re: Programming individual FPGAs in a daisy chain
148378: 10/07/16: Re: Another Xilinx webpack download rant
148847: 10/09/02: Re: dct verilog
148908: 10/09/09: Re: We need an administrator for the group to fight spam
149012: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149024: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
149272: 10/10/13: Re: FPGAOptim0208r available
149273: 10/10/13: Re: pci didn't recognize pci express
149275: 10/10/13: Re: store data into fpga
149276: 10/10/13: Re: JTAG stops working!
149371: 10/10/19: Re: Old LOC constraint stuck somewhere
149381: 10/10/20: Re: Designing for Xilinx Spartan in 2010?
149382: 10/10/20: Re: Old LOC constraint stuck somewhere
149394: 10/10/21: Re: Xilinx: How to save all invalid constraints to a file?
149438: 10/10/25: Re: xilinx spartan3e clock domain crossing or synchronizing two clocks
149514: 10/11/01: Re: Xilinx ConstraintSystem:59
149543: 10/11/03: Re: Good Dev Board
149571: 10/11/05: Re: crazy error message
149572: 10/11/05: Re: PCI Parallel port detection in XILINX
149573: 10/11/05: Re: ucf impact to synplify pro
149602: 10/11/10: Re: Device 0 Unit 0:waiting for core to be armed, slow or stopped clock.
149615: 10/11/11: Re: Altera JTAG problem
149639: 10/11/12: Re: cool BGA pattern
149914: 10/12/01: Re: MicroBlaze Software Debugging print problem
150009: 10/12/06: Re: Linux on Microblaze
150010: 10/12/06: Re: Lattice XO2 video
150011: 10/12/06: Re: FPGA BOARD QUESTION
150022: 10/12/06: Re: Linux on Microblaze
150157: 10/12/21: Re: using a cordic on EDK
150247: 11/01/05: Re: I Give Up!
150248: 11/01/05: Re: I Give Up!
150325: 11/01/10: Re: FPGA to PHY/MAC chip
150327: 11/01/10: Re: Xilinx ML561 Schematics
150328: 11/01/10: Re: FPGA to PHY/MAC chip
150336: 11/01/10: Re: FPGA to PHY/MAC chip
150337: 11/01/10: Re: FPGA to PHY/MAC chip
150356: 11/01/11: Re: spartan 3 xc3s1000 not getting programmed
150365: 11/01/12: Re: spartan 3 xc3s1000 not getting programmed
150373: 11/01/12: Re: spartan 3 xc3s1000 not getting programmed
150476: 11/01/24: Re: Xilinx news
150531: 11/01/25: Re: tft lcd with xilinx fpga
<d_s_klein@yahoo.com>:
134695: 08/08/26: Re: Verification methods importance
135976: 08/10/24: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
<da_wils@hotmail.com>:
146693: 10/03/26: baud rates etc
DAB sounds worse than FM:
55870: 03/05/22: Re: fir distributed arithmetic
55915: 03/05/23: Re: fir distributed arithmetic
55974: 03/05/25: Re: fir distributed arithmetic
56000: 03/05/27: Re: fir distributed arithmetic
56682: 03/06/11: Re: Learning FPGAs
dadabuley@gmail.com:
124959: 07/10/12: Re: Graphical VHDL Viewer ?
124960: 07/10/12: Re: Unrouted nets (Xilinx FPGA Editor)
133734: 08/07/12: Re: multicyle and false path in FPGA Design
133735: 08/07/12: Re: Fixed point number hardware implementation
133736: 08/07/12: Strange ddr controller bugs.
133744: 08/07/12: Re: Strange ddr controller bugs.
133746: 08/07/12: Re: VHDL code for DDFS
133747: 08/07/12: Re: Strange ddr controller bugs.
133751: 08/07/12: Re: Using VHDL packages
133767: 08/07/14: Re: Strange ddr controller bugs.
133768: 08/07/14: Re: Mismatch simulation & post sythese results
133785: 08/07/14: Re: GTP simulation problems
daestrom:
108234: 06/09/07: Re: Please help me with (insert task here)
Daf:
119831: 07/05/27: Best way of moving paralell bits of data from over clock domains?
Dag Magne Ulvang:
6624: 97/06/06: flex10k100
Dagfinn Eidsvaag:
9934: 98/04/14: Interessted in some money ?
<dagmargoodboat@yahoo.com>:
93689: 05/12/28: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
<dahlback@gmail.com>:
161361: 19/05/07: Re: Replaceme EPROM by CPLD/FPGA
daica:
62707: 03/11/05: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
62714: 03/11/05: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
daica nguyen:
62636: 03/11/03: Re: Shannon Entropy for Black Holes
<dainis@safequipment.com>:
38153: 02/01/07: PDH MUX (E2,E3) VHLD cores
<dainis@saftehnika.com>:
42810: 02/05/03: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples
Daio:
27587: 00/11/29: FPGA Express warning
Daixun:
24716: 00/08/17: Multilinx cable problem
24927: 00/08/22: Chipscope problem
Daixun Zheng:
24138: 00/07/27: implementation problem of Foundation 2.1i
DAJ:
141087: 09/06/04: How to generate clocks of higher frequency?
141129: 09/06/08: refresh to refresh period
142316: 09/08/04: File I/O read in verilog
dajjou:
131348: 08/04/20: how we can prove that really the AES 256 is used to crypt the
132187: 08/05/16: frame format virtex 5
132429: 08/05/27: impact / encrypted bitstream
132431: 08/05/27: Re: impact / encrypted bitstream
132446: 08/05/27: Re: impact / encrypted bitstream
132465: 08/05/28: Re: impact / encrypted bitstream
134684: 08/08/26: Re: AES decryption (ASIC)
135489: 08/10/04: Bitstream configuration question (virtex 5).
136943: 08/12/15: JTAG / IMPACT / VIRTEX
136947: 08/12/15: Re: JTAG / IMPACT / VIRTEX
136949: 08/12/15: Re: JTAG / IMPACT / VIRTEX
137137: 08/12/27: JTAG USB interface
137272: 09/01/07: OpenOCD / FTDI2232 / JTAG/ Virtex
137810: 09/01/30: ebcrypted bitstream configuration modes (virtex5)
137816: 09/01/30: virtex 5 decryption
138071: 09/02/05: FPGA/altera / Configuration logic,decryptor
138281: 09/02/12: select map /virtex
138325: 09/02/16: Virtex 5 slave serial config
138371: 09/02/18: Re: Virtex 5 slave serial config
138372: 09/02/18: Re: Virtex 5 slave serial config
138378: 09/02/18: Re: Virtex 5 slave serial config
dakkumar:
107957: 06/09/03: Xilinx VSK (Video Starter Kit)
Daku:
145223: 10/02/01: Help Please - Xilinx message
145241: 10/02/02: Re: Help Please - Xilinx message
145251: 10/02/03: Re: Help Please - Xilinx message
145263: 10/02/04: Re: Help Please - Xilinx message
145424: 10/02/08: Xilinx ISE 11.1 crash - Visual Studio error
149731: 10/11/21: Network stack on Xilinx, Alterra ?
dal:
102118: 06/05/10: Re: [Newbie] 64-point complex FFT with 32 bit floating-point representation
Dal:
83400: 05/04/28: Re: dynamic size of ports
92889: 05/12/08: Re: Replace fast ethernet with VDSL2
dalai lamah:
85259: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
85904: 05/06/17: Re: AbusivepPricing information in marketing publications
86093: 05/06/21: Re: FPGAs: Where will they go?
87848: 05/08/02: Programmable frequency synthesizer with Xilinx DCM
88283: 05/08/14: Clock for serializer with a Spartan3
88357: 05/08/16: Re: Clock for serializer with a Spartan3
88358: 05/08/16: Re: Clock for serializer with a Spartan3
88359: 05/08/16: Re: Clock for serializer with a Spartan3
102353: 06/05/15: Re: getting good deals on small qty?
103297: 06/05/30: Re: fpga debug
103432: 06/06/01: Re: clockless arbiters on fpgas?
103720: 06/06/09: Re: Good free or paid merge software that edits two similar files?
116394: 07/03/08: Re: Spartan3AN - Roadmap
117154: 07/03/24: Re: Austin the Altera Mole
117928: 07/04/13: Order of the synchronous operations
117952: 07/04/14: Re: Order of the synchronous operations
117960: 07/04/14: Re: Order of the synchronous operations
117981: 07/04/15: Re: Order of the synchronous operations
118155: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118727: 07/05/02: Re: Xilinx software quality - how low can it go ?!
119480: 07/05/21: Re: Timing not met but working on board
120577: 07/06/11: Re: PBGA FPGA in hi-rel application
130533: 08/03/26: Re: VHDL document generation utilities
130626: 08/03/28: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130903: 08/04/04: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130972: 08/04/07: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
131537: 08/04/24: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131583: 08/04/25: Spartan3 "commercial" temperature range
131599: 08/04/25: Re: Spartan3 "commercial" temperature range
131601: 08/04/25: Re: Spartan3 "commercial" temperature range
134559: 08/08/18: Re: More work, less posts
134931: 08/09/07: Re: Best way to buy Xilinx FPGAs?
142222: 09/07/29: Re: Different behavior of FSM in same simulation
147118: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
149164: 10/10/05: Re: Why did Microsemi buy Actel?
151001: 11/02/28: Re: Nanosecond pulse generator using Spartan-3E
159744: 17/02/17: Re: cmos delay vs temperature
161125: 19/02/04: Re: Is it possible to implement Ethernet on bare metal FPGA, Without Use of any Hard or Soft core processor?
161499: 19/11/10: Re: FPGA config sizes
Dale:
100393: 06/04/07: Re: FSL to VHDL interface
100485: 06/04/10: Re: FSL to VHDL interface
103659: 06/06/07: Can ILMB and DLMB of Microblaze be 24kByte?
113540: 06/12/15: 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4
114279: 07/01/10: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114320: 07/01/11: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
116560: 07/03/12: 3.3V tolerant Virtex-4 JTAG Configuration
116584: 07/03/13: Re: 3.3V tolerant Virtex-4 JTAG Configuration
122426: 07/07/27: Can Xilinx and Altera be on the same JTAG chain for programming?
122454: 07/07/27: Can Altera and Xilinx Done signals be tied together? Has anyone done it?
128617: 08/01/31: Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9
128625: 08/01/31: Re: Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9
129998: 08/03/12: Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro?
130629: 08/03/28: Having trouble building an old Xilinx Spartan3 FPGA project I did on
130633: 08/03/28: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did
136225: 08/11/07: Setting FSM encoding in VHDL or in UCF for Xilinx
136232: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136237: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136243: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136245: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136246: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136250: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136259: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136768: 08/12/04: Project/File corruption problem with ISE 10.1
143307: 09/10/01: Why won't Xilinx use an FDR?
143696: 09/10/21: Can I use a crystal for the clock source for a Xilinx Spartan 3A
Dale E. Redford:
9526: 98/03/20: Re: Dual port
Dale Pontius:
8377: 97/12/11: Re: what is metastability time of a flip_flop
8393: 97/12/12: Re: what is metastability time of a flip_flop
8394: 97/12/12: Re: what is metastability time of a flip_flop
8356: 97/12/10: Re: what is metastability time of a flip_flop
8366: 97/12/10: Re: what is metastability time of a flip_flop
Dale Shuttleworth:
4818: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
<dale.prather@gmail.com>:
91599: 05/11/09: Re: Suggestions/Recommendations with CPLD's and Software
91645: 05/11/10: Re: Suggestions/Recommendations with CPLD's and Software
99802: 06/03/29: FSL to VHDL interface
99862: 06/03/30: Re: FSL to VHDL interface
99870: 06/03/30: Re: need your comments
100164: 06/04/04: Re: need your comments
100217: 06/04/05: Re: need your comments
100251: 06/04/05: Re: FSL to VHDL interface
100318: 06/04/06: Re: FSL to VHDL interface
<dale1@denton.quik.com>:
8806: 98/01/27: CHAOS on the net and jingle of COINS
Dali:
47293: 02/09/23: Re: Spartan II JTAG reconfiguration bug - workaround
47441: 02/09/25: Re: Unpredictable Place and Route
47442: 02/09/25: Re: Finding nets in hierarchy
47498: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47574: 02/09/29: Re: Does it need any protection circuit for Interfacing FPGA device
47609: 02/09/30: Re: Rounting of non-global IO pad to a GCLKIOB site.
47615: 02/10/01: Re: Rounting of non-global IO pad to a GCLKIOB site.
47684: 02/10/02: Re: Rounting of non-global IO pad to a GCLKIOB site.
48777: 02/10/24: Re: Silly Virtex 2 Pro question...
48810: 02/10/24: Re: Silly Virtex 2 Pro question...
49345: 02/11/10: Re: Back annotation initialization problem
49527: 02/11/13: Re: creating a fabric in an FPGA
Dalip K. Singh:
22975: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
22950: 00/06/05: Re: 3.3V I/O TO 5V LOGIC?
Dalton Marris:
72425: 04/08/18: Viewing internal nets during Quartus functional simulation
72427: 04/08/18: Re: Viewing internal nets during Quartus functional simulation
72457: 04/08/19: Re: Viewing internal nets during Quartus functional simulation
<damak.taheni@gmail.com>:
131653: 08/04/28: Re: Virtex4 FX PPC and Fsl
<damb.flaviano@libero.it>:
110128: 06/10/11: Simulink Co-simulation,parallel-door or platform cable USB
110134: 06/10/11: Re: Simulink Co-simulation,parallel-door or platform cable USB
damc4:
100800: 06/04/18: Re: FPGA + MAC board?
122024: 07/07/17: 8B/10B decoding after serial transmission problem?
Damian Busch:
<damicha@gmx.de>:
124032: 07/09/11: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
124052: 07/09/11: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
124105: 07/09/12: Re: Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
damidar:
85812: 05/06/16: re:Problem for xilinx!!!
85896: 05/06/17: re:Problem for xilinx!!!
85948: 05/06/18: re:Problem for xilinx!!!
86638: 05/07/01: re:Problem for xilinx!!!
86658: 05/07/02: re:Problem for xilinx!!!
86674: 05/07/03: Re: Problem for xilinx!!!
damien:
54808: 03/04/18: Altera Megawizard from Quartus 2.2 (qmegawiz.exe)
Damien:
45914: 02/08/10: I seek a FPFA developer
damir:
92388: 05/11/29: Slow FIFO using external SRAM
92390: 05/11/29: Cypress FX2 bandwidth problem
92393: 05/11/29: Re: Cypress FX2 bandwidth problem
92407: 05/11/29: Re: Cypress FX2 bandwidth problem
92419: 05/11/29: Re: Slow FIFO using external SRAM
92428: 05/11/29: Re: Cypress FX2 bandwidth problem
92547: 05/12/01: Re: Slow FIFO using external SRAM
92809: 05/12/07: VGA controller
92817: 05/12/07: Re: VGA controller
92864: 05/12/08: Re: VGA controller
93557: 05/12/24: Re: Cypress FX2 bandwidth problem
93561: 05/12/24: Re: Cypress FX2 bandwidth problem
Damir Danijel Zagar:
27153: 00/11/13: Re: Webpack 3.2WP3.x from Xilinx is useless
27841: 00/12/12: Xilinx CPLD capable of driving LEDs
27900: 00/12/14: Verilog or VHDL
27903: 00/12/14: Decoding output from incremental encoder...
27906: 00/12/14: Re: Decoding output from incremental encoder...
30458: 01/04/09: VHDL falling edge in Xilinx Foundation...
36648: 01/11/14: ASRC (asynchronus sample rate conversion)
37045: 01/11/29: Re: SpartanIIE
37052: 01/11/29: Re: SpartanIIE
38420: 02/01/14: Re: MSP430 + Xilinx via JTAG
38552: 02/01/17: Re: MSP430 + Xilinx via JTAG
42270: 02/04/19: Re: Programming for FPGA or ASIC
43911: 02/06/06: Xilinx JTAG verification failed
44064: 02/06/11: Re: Problems initialising an FPGA - SPARTAN II
Damir Smitlener:
881: 95/03/20: Re: Free Viewlogic design kits?
Damjan Lampret:
18149: 99/10/04: SDRAM&PCI controller
18542: 99/10/29: opencores.org announcement
19729: 00/01/10: Re: Versatile digital filter for signal processing systems
19730: 00/01/10: fastest 32 bit RISC
19752: 00/01/11: RISC in FPGA?
19786: 00/01/12: Re: PCI/USB project started
19828: 00/01/13: Re: fastest 32 bit RISC
19846: 00/01/14: Re: fastest 32 bit RISC
19859: 00/01/14: Re: fastest 32 bit RISC
Damn Yankee:
6894: 97/07/07: !!!Hello!!!
6913: 97/07/08: I Am Very Sorry!!!
damon:
10550: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10551: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10552: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10554: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10553: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10555: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10556: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10557: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10558: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10559: 98/05/29: PGCK pin and external clock assignment problem on XC4000A
10586: 98/06/03: Example of 8051 codes to configure Xilinx fpga
DaMunky89:
151062: 11/03/02: Problems with Xilinx SDK and LwIP
151127: 11/03/08: Re: Problems with Xilinx SDK and LwIP
151250: 11/03/17: Re: Problems with Xilinx SDK and LwIP
151332: 11/03/23: Problems connecting with Xilinx Spartan-6 FPGA
151362: 11/03/27: Re: Problems connecting with Xilinx Spartan-6 FPGA
dan:
11997: 98/09/23: Re: easier testing for PCI cards??
49369: 02/11/11: How much to build this? xvga to ntsc uhf broadcaster
81749: 05/03/30: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
81770: 05/03/31: Re: FPGA board--host PC, need 20-50 Mbps speed, USB2, PCI or 1394?
115005: 07/01/29: bram can't store elf
115060: 07/01/30: Re: bram can't store elf
Dan:
7096: 97/07/30: Make extra cash..it works.
7925: 97/10/30: Part checksum calculate program?
15347: 99/03/19: Bit Error Rate Test
18663: 99/11/05: Re: AMCC 5933 Woes
21864: 00/04/04: Re: Replication control in Xilinx P&R
22132: 00/04/26: How to Prevent theft of FPGA design
22143: 00/04/27: ? economical SPROM programmer for Xilinx
22241: 00/05/02: DCT vs. FFT Are these ideas correct ?
22242: 00/05/02: soldering quad flat packs
22744: 00/05/22: Web page for FPGA design jobs???
22753: 00/05/23: % use of schematic vs VHDL ???
23075: 00/06/13: Re: Altera vs Xilinx
23181: 00/06/16: Hand soldering a PQ208 - It looks tough to do.
23545: 00/06/29: PCI with Xilinx controller
23604: 00/07/02: division in FPGA - help !
23612: 00/07/02: How can I search this newsgroup archive?
24495: 00/08/11: PCI core needed for Xilinx
24541: 00/08/12: Virtex 2.5V part with 5V IO problems
24552: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24553: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24556: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24572: 00/08/14: Re: this is a reply test
24593: 00/08/14: Ben my laugh was real Thanks
24693: 00/08/17: Re: Xilinx Spartan II block RAM
24695: 00/08/17: When will SpartanII be in ditribution
24704: 00/08/17: Distributor attitude !!
25174: 00/08/29: Re: Spartan II vs. Virtex
25190: 00/08/30: That was a good read.
25293: 00/09/05: PCB design for Xilinx FPGAs
25587: 00/09/14: nice one Rick
25588: 00/09/14: Simon,Floating Inputs
25601: 00/09/15: Re: Simon,Floating Inputs
25619: 00/09/15: Simon , decoupling caps
25673: 00/09/17: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25739: 00/09/18: Info seems incomplete and unrealistic
25740: 00/09/18: They put the 'Free' in freelance.
25815: 00/09/21: Re: Safe voltage regulator for Xilinx XC2S150 part?
25822: 00/09/22: What a badly written advertisement EOM
26536: 00/10/19: DS2401 security from pirating an FPGA
26549: 00/10/20: Hay Ray -
26629: 00/10/23: How secure from pirates is a Quick Logic part ?
26631: 00/10/23: RS422 interfacing to a FPGA ?
26646: 00/10/23: Eric and Andy Thanks for help
26684: 00/10/25: Design theft story in EDN. New security ?
26678: 00/10/24: Thanks for the info David
26878: 00/11/02: Pwer supply for a XCV300. Recommendations please.
26885: 00/11/02: Need a PCB speaker driven by XCV100
26923: 00/11/03: Thanks to all for great input EOM
26924: 00/11/03: I2C bus driven by Xilinx
26965: 00/11/06: Re: ViewLogic ViewDraw questions
27010: 00/11/07: Re: Need help locking pins for Spartan XL
27653: 00/12/01: DLLs driving DLLs in Virtex.
27706: 00/12/04: Spartan II poor avaiablility. Strategic decision or technical problems ?
27786: 00/12/08: Mistake - I was trying to send elsewhere
28149: 00/12/23: VGA compatible design for a Xilinx FPGA needed.
28671: 01/01/20: How to be a more efficient productive FPGA designer ?
28694: 01/01/21: Re: UK parts
28697: 01/01/21: Firewire bus driven/received by Xilinx using LVDS
28786: 01/01/24: Encryption is supported in new Virtex II but.....
28799: 01/01/24: Re: Advice on FPGA board.
28810: 01/01/25: Re: Encryption is supported in new Virtex II but.....
28818: 01/01/25: Re: Encryption is supported in new Virtex II but.....
28819: 01/01/25: How does a flip chip differ from a BGA ?
28861: 01/01/26: Re: Advice on FPGA board.
28864: 01/01/26: Re: 6845
29065: 01/02/04: Re: Advice on FPGA board.
29067: 01/02/05: Re: Encryption is supported in new Virtex II but.....
29085: 01/02/05: Hey Jerry, he lives in Montreal. Still Canadian last time I checked.
29261: 01/02/11: FPGAs take wron road. SoC NO - on-the-fly reprogrammability YES
29533: 01/02/25: VDHL Book recomendation please. Xilinx designer.
30557: 01/04/16: PCMCIA implemented with Xilinx. Spec info needed.
30647: 01/04/20: Who make Xilinx Proto PCBs ? Spartan II on PCI bus.
35867: 01/10/21: To Christoph Hauze
37134: 01/11/30: PCI card - 2 layers versus four layers
40783: 02/03/15: PCI design in a Spartan II which crashes in some wintel PCs
40816: 02/03/15: Spartan II IOB tristate control FF use
40817: 02/03/15: To Falk Brunner
40818: 02/03/15: To Yury's post
40820: 02/03/15: Reply to Kevin
40822: 02/03/16: Re: Spartan II IOB tristate control FF use
40880: 02/03/17: Thanks to all for great tips
41198: 02/03/22: Ligthning strikes & EMI - SPARTAN II design in flight
43910: 02/06/06: Re: Spartan II Proto. Board
44721: 02/06/27: Who near London UK can burn a Xilinx SPROM ?
45332: 02/07/19: Theft protection of FPGA configuration data
46503: 02/09/01: In 2 clk domains. How to xfer data from 1 bus to the another ?
46957: 02/09/12: number of IOBs in Spartan IIE is fishy
47039: 02/09/15: 1.8V regulator needed for Spartan IIE
47051: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
47248: 02/09/21: Can a fpga replace external inverters in a crystal osc ?
47255: 02/09/21: Great feedback as always Ray . Thanks
47400: 02/09/24: virtex II pro development board
47401: 02/09/24: Re: ISE 5.1 Linux?
47650: 02/10/01: question on ISE 5.1 and SMP machines...
47844: 02/10/05: Re: question on ISE 5.1 and SMP machines...
51418: 03/01/13: Re: need pointers to FPGA software & download hardware
53503: 03/03/14: Re: What is the diff between FPGA and CPLD?
63441: 03/11/21: Re: Small PLD choices
63444: 03/11/21: Re: XC9500 design does not fit into Coolrunner
75898: 04/11/18: Pci timing tsu and tco
76377: 04/12/01: clocks switch
76474: 04/12/03: Pci problems
76487: 04/12/03: Re: Pci problems
76658: 04/12/08: Fpga prices
76849: 04/12/14: Pal programming
77380: 05/01/05: Best solution for pci target and backend interface
78200: 05/01/26: Pci fpga board schematic
78279: 05/01/27: Xilinx ISE 6.3i compxlib freeze
83411: 05/04/29: Lvds input problem urgent
94886: 06/01/18: Re: ISE8.1 on Linux, first impressions
94885: 06/01/18: Re: ISE8.1 on Linux, first impressions
105247: 06/07/18: Virtex 4 ACE Compact Flash configuration problem
105253: 06/07/18: Re: Virtex 4 ACE Compact Flash configuration problem
105291: 06/07/19: Re: Virtex 4 ACE Compact Flash configuration problem
105296: 06/07/19: Re: Virtex 4 ACE Compact Flash configuration problem
105299: 06/07/19: Re: Virtex 4 ACE Compact Flash configuration problem
119433: 07/05/18: Quartus 7.1 Simulations
Dan Alley:
3771: 96/07/29: Programmer for Cypress 7C382A - how to speed up production?
27173: 00/11/13: Conversion of Altera POF file for a new config device
29028: 01/02/02: virtex mapping failing after small change to source files
Dan Arik:
132313: 08/05/21: RS232 Interface
132362: 08/05/23: Simple PRNG problem -> clk not recognised as input
132363: 08/05/23: Re: Simple PRNG problem -> clk not recognised as input
132364: 08/05/23: Re: Simple PRNG problem -> clk not recognised as input
Dan Bartram:
1935: 95/09/22: Re: Is there a reprogramable XC17256D available?
2095: 95/10/13: Re: info needed...
2119: 95/10/17: Re: Programming AMD Mach Parts
2113: 95/10/17: Re: Bet you can't do these....
4299: 96/10/11: Info/opinions wanted for PCI interface in an FPGA
4324: 96/10/15: Re: Update on Atmel AT17C128 Problem
4400: 96/10/24: Re: Info/opinions wanted for PCI interface in an FPGA
4439: 96/10/29: Re: Info/opinions wanted for PCI interface in an FPGA
4780: 96/12/14: Re: Xilinx configuration PROM
4781: 96/12/14: Re: Xilinx configuration PROM
4810: 96/12/17: Re: Xilinx configuration PROM
Dan Benson:
38311: 02/01/11: Help with Older Programmer
Dan Blow:
2512: 95/12/21: Re-progromable VXI module
2579: 96/01/05: Need Re-programable VXI Module
2612: 96/01/10: Re: Need Re-programable VXI Module
Dan Braunstein:
66559: 04/02/22: ModelSim, Virtex DCM, and clk0 phase problem
Dan Briggs:
32374: 01/06/25: Date Code Problem?
Dan Connors:
30587: 01/04/18: MICRO-34 Call for Papers
31318: 01/05/18: MICRO-34 Call for Papers - Six weeks until submission June 22
Dan DeConinck:
63204: 03/11/17: Xilinx Design entry via Schematic Capture - What tool to use ?
63209: 03/11/17: using multilinx from ISE to download a bit file
64732: 04/01/12: Power plane assignments in a Xilinx PCI card
Dan DeConinck of PixelSmart:
74580: 04/10/14: Xilinx to Make Image Processing FPGA
74644: 04/10/15: SPARTANI II - PCI target logic - what code generates burst read ?
Dan Diekhoff:
4293: 96/10/11: JOB: US-IN. VHDL/ASIC Design. HW/SW Integration debug. FPGAs. - ddiekhof@notes.techni-source.com
Dan Dietrich:
15383: 99/03/21: Re: Bit Error Rate Test
Dan Dixon:
5697: 97/03/07: Re: Opinions on Cypress/PCI?
dan doberstein:
40501: 02/03/07: GATE ARRAY PROJECT
Dan Fabrizio:
37956: 01/12/27: Re: Where could I get a signal waveform editor?
43024: 02/05/09: Announce: TimingAnalyzer Program Update
43601: 02/05/26: automatically generate timing diagrams
43614: 02/05/27: request for vcd and Symphony 1.5 lst files
45558: 02/07/26: Announce: TimingAnalyzer Program Update
Dan Fraser:
2519: 95/12/23: Re: [q][Reverse Engineering Protection]
Dan Henry:
73163: 04/09/14: Re: EDK OPB Uart 16550
75956: 04/11/20: Re: nucleus
78035: 05/01/23: Re: What's difference of low/high level driver in Xilinx MicroBlaze?
78661: 05/02/04: Re: RoseRT + Threadx + Xilinx Microblaze
82702: 05/04/16: Re: EDK:input to microblaze
82884: 05/04/19: Re: EDK:input to microblaze
82885: 05/04/19: Re: EDK:input to microblaze
83636: 05/05/04: Re: embedded linux for v2pro PPC?
Dan Hicks:
56183: 03/05/29: Re: FIFO Controller
Dan Hollands:
87890: 05/08/03: Re: System Engineering in the R/D World
Dan Hopper:
1314: 95/05/31: FPGA primer text?
25144: 00/08/28: Re: run time doubled with Xilinx 3.1i upgrade
25171: 00/08/29: Re: run time doubled with Xilinx 3.1i upgrade
27885: 00/12/13: Re: question on initial states of FFs and GSR in Virtex
Dan K:
28961: 01/01/31: Xilinx fast carry counter question
29277: 01/02/12: Re: 8B/10B Encoding
73120: 04/09/14: Re: Need some help with some technical claims...
73657: 04/09/27: Re: VHDL inout used for non bidirectional uses
78099: 05/01/24: Re: 60Hz clock on XC9572
107076: 06/08/24: Modelsim XE problem with Xilinx ISE 8.1i and 8.2i
112759: 06/11/28: ModelSim Xilinx edition new bug?
123914: 07/09/06: VCCAUX too high on a Spartan 3 design
124122: 07/09/12: Re: Good VHDL reference?
124266: 07/09/17: Re: VCCAUX too high on a Spartan 3 design
124630: 07/09/28: Programming the ARM7 used to download our Xilinx FPGA
125184: 07/10/17: Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files
127053: 07/12/10: Re: Xilinx ise 9.2i clean up project files
129800: 08/03/05: could use some help with verilog/vhdl
130820: 08/04/02: ModelSim XE problems with a VHDL coregen in a Virtex 5
131245: 08/04/16: how do I test signals in a testbench that are 1 or 2 levels down in the UUT?
134778: 08/08/29: Xilinx Multipass PPR
Dan Kegel:
59979: 03/09/03: Re: [ann] Microblaze uClinux Demo released
Dan Koren:
82033: 05/04/05: Re: ISA vs. patent/trademark
Dan Kotlow:
27283: 00/11/17: Re: ANNOUNCE: Checksum and CRC Code/Article
27334: 00/11/18: Re: ANNOUNCE: Checksum and CRC Code/Article
27352: 00/11/19: Re: ANNOUNCE: Checksum and CRC Code/Article
27230: 00/11/16: Re: ANNOUNCE: Checksum and CRC Code/Article
Dan Kuechle:
6183: 97/04/23: Re: ISP CPLD from AMD or Cypress???
7683: 97/10/02: Re: bidirectional bus problem
11520: 98/08/20: half full flag in a xilinx async fifo?
12485: 98/10/13: gray code counter in a Xilinx fpga???
12546: 98/10/15: Re: gray code counter in a Xilinx fpga???
12879: 98/11/03: Xilinx bit file format question
15012: 99/03/03: combining multiple xilinx designs into one
19912: 00/01/17: Wanted: Xilinx XCV400-6FG676C for prototype
22121: 00/04/25: Xilinx Virtex problem (schematic)
22947: 00/06/05: Virtex-E and SCSI
23321: 00/06/22: dual processor PC for PPR - are they worth the extra cost?
24979: 00/08/23: run time doubled with Xilinx 3.1i upgrade
25032: 00/08/24: run time doubled with Xilinx 3.1i upgrade - Problem Fixed!!
25475: 00/09/12: Re: computing difference between Gray values?
26308: 00/10/11: Re: palasm
26649: 00/10/23: Re: RS422 interfacing to a FPGA ?
36300: 01/11/05: Xilinx DLL clock question
40998: 02/03/19: Re: FIFO general question
43966: 02/06/07: VirtexE LVDS problem / question
44433: 02/06/19: Xilinx Bel - how do I find the Bel nane?
44463: 02/06/20: Re: 5V tolerance
44802: 02/07/01: dammage to Virtex-E???
45103: 02/07/12: Re: Question: Xilinx schematic entry, constants, bit swapping
45738: 02/08/02: Re: changing Vcco
62136: 03/10/20: Subroutine in VHDL?
62238: 03/10/22: Any problems with Xilinx 6.1i ISE?
71141: 04/07/09: Spartan 3 termination question (DCI)
136100: 08/10/31: Re: classic Spartan-3 DDR2 and IOBs
137477: 09/01/19: Differential bidirectional in VHDL (Xilinx)
137518: 09/01/21: Re: Differential bidirectional in VHDL (Xilinx)
Dan L. Symes:
6146: 97/04/18: PCI bus Target VHDL solution by Lucent
Dan Linder:
478: 94/11/30: ASIC emulation (Quickturn, etc.)
524: 94/12/19: ASIC emulation summary
Dan McDonald:
100991: 06/04/23: Re: ISE 8.1i for Linux ?
101628: 06/05/03: Re: windrvr for Linux broken in 2.6.16
Dan Nenni:
1203: 95/05/13: GateField 100K FPGA
Dan Nilsen:
83219: 05/04/26: dynamic size of ports
83290: 05/04/27: Re: dynamic size of ports
83394: 05/04/28: Re: dynamic size of ports
Dan NITA:
81374: 05/03/22: Re: NIOS II power-on reset
82780: 05/04/18: Re: Multi-page schematics (.bdf) in Quartus II?
93813: 05/12/31: Timing problem in ModelSim, Post-Route Simulation.
93845: 06/01/02: Re: Timing problem in ModelSim, Post-Route Simulation.
93981: 06/01/04: Re: Timing problem in ModelSim, Post-Route Simulation.
96862: 06/02/12: Re: Simulation problem using CONV_INTEGER
Dan Notestein:
33721: 01/08/02: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
Dan Oomkes:
16244: 99/05/11: UART Design
Dan Oprisan:
35648: 01/10/12: max+plus2 under winNT
35882: 01/10/22: Re: Verilog vs. VHDL
39469: 02/02/11: Re: NT parallel port driver
39814: 02/02/20: Counter does not fit CPLD?
41336: 02/03/26: Re: Can't detect Altera MAX7000s using JTAG
41391: 02/03/27: Re: ByteblasterMV EPM7064S voltage problem
Dan Parent:
11823: 98/09/11: Cypress CPLD Jam Player
12040: 98/09/25: Cypress CPLDs
12051: 98/09/25: Re: Cypress CPLDs
Dan Prysby:
13989: 99/01/06: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14013: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14035: 99/01/08: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
Dan RADUT:
54929: 03/04/22: Re: help required in ISE 5.1 -----ERROR:NgdBuild:604 - logical block 'filtercore'
56700: 03/06/11: Re: ERROR:NgdBuild:755
58228: 03/07/17: Re: Digital Design with just one clock at one edge
Dan Rudolf:
29760: 01/03/08: Spartan II: POWERDOWN MODE WAS DELETED!!!
29765: 01/03/08: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
Dan Rymarz:
19199: 99/12/05: hobbyist friendly pld?
19262: 99/12/09: Re: JTAG programming problem with multiple Altera MAX7000A devices
19830: 00/01/13: Re: PCI Bus Problems with Burst Transfers
19836: 00/01/13: Re: Reliability of programming SRAM FPGAs
Dan Schaffer:
63228: 03/11/18: SPI 4.2 Core perceptions and Power
Dan Simpkins:
1657: 95/08/11: Re: VHDL/FPGAs/PLDs help
Dan Wawa:
155926: 13/10/16: Partnership Request
Dan Yang:
24437: 00/08/08: FPGA intro
<dan.costin@gmail.com>:
76573: 04/12/06: PAL programming
<dan.nilsen@gmail.com>:
83736: 05/05/05: quantization and rate control
<dan.walmsley@gmail.com>:
124869: 07/10/09: Starting FPGA
124896: 07/10/10: UK Supplier XILINX spartan 3 development board??
Dana Dorsett:
3464: 96/06/03: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
dana s withrow:
883: 95/03/20: Beyond Futurenet including PLD ?
<danberquet@my-deja.com>:
20180: 00/01/30: Re: Xilinx vs Altera
<dancedynamix@hotmail.com>:
101093: 06/04/25: clock multiplication
101101: 06/04/25: Re: clock multiplication
101107: 06/04/25: Re: clock multiplication
dand2k:
102644: 06/05/18: Re: FPGA Configuration Question
102648: 06/05/18: Re: Spartan 3 Readback
134984: 08/09/09: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
Danesh Tavana:
19462: 99/12/22: JOBS: Open Positions at Triscend: The Configurable System-on-Chip Company
DANFuboco:
55493: 03/05/10: Xilinx parts listed on ebay..
dang_hut@yahoo.com:
115747: 07/02/19: Need help with VHDL simulation with SPW in Linux
115880: 07/02/22: Need help to buy first FPGA board!
danger:
15398: 99/03/22: ALTERA Byteblaster configuration for DOS and LINUX
dani:
84342: 05/05/17: Jam Byte-Code Player for 8051
84379: 05/05/18: Re: Jam Byte-Code Player for 8051
84383: 05/05/18: Re: Jam Byte-Code Player for 8051
Dani Guzman:
39663: 02/02/15: FPGA choices and questions
danial gifani:
150289: 11/01/08: Design Ip core for FPGA
danialgifani:
150293: 11/01/08: IP core design for FPGA
Daniel:
45038: 02/07/10: FPGA/CPLD Decision help?
45649: 02/07/30: Impedance Measureing
45657: 02/07/30: Re: Impedance Measureing
68944: 04/04/22: Cable connection failed
73786: 04/09/29: FPGA for OCR processing
73793: 04/09/29: Re: FPGA for OCR processing
76713: 04/12/09: Seeking suggestions on prototyping board
76794: 04/12/12: Inconsistant compilations with quartus
77311: 05/01/04: ISE Toolflow : hardmacro, incremental or modular
77362: 05/01/05: Re: ISE Toolflow : hardmacro, incremental or modular
77655: 05/01/13: Re: MHS modify and then ...?
77691: 05/01/14: Re: MHS modify and then ...?
120390: 07/06/06: Re: data compression algorithms on FPGA
130094: 08/03/14: Help on Virtex-II Pro global clocks.
130159: 08/03/17: Re: Help on Virtex-II Pro global clocks.
130191: 08/03/17: Re: Help on Virtex-II Pro global clocks.
130238: 08/03/18: Re: Help on Virtex-II Pro global clocks.
daniel:
36757: 01/11/19: Re: how to limit the fanout in APEX20K400E
Daniel Leu:
72399: 04/08/17: Re: Spooling from FPGA to the PC
75448: 04/11/05: Re: chipscope pro problem (par)
77862: 05/01/18: Re: decrease slew rate - Actel Libero
87017: 05/07/12: Re: Announce: Impulse C-to-RTL Version 2 now available
87270: 05/07/20: Re: General-purpose STAPL Composer?
88986: 05/09/01: Re: bare die (non packaged) FPGA, CPLD, controllers ?
99513: 06/03/25: Re: false paths in Actel flow
103745: 06/06/09: Re: Requesting for an Actel Library
110345: 06/10/13: Re: more than 90% occupancy in an Actel FPGA
110441: 06/10/15: Re: Libero 7.2
110442: 06/10/15: Re: more than 90% occupancy in an Actel FPGA
Daniel =?iso-8859-1?Q?Ha=F1czewski?=:
27967: 00/12/18: JTAG protocol
32933: 01/07/12: Xilinx FPGA density estimation
33313: 01/07/23: Re: Homemade Xilinx parallel cable problem
33355: 01/07/24: Re: Homemade Xilinx parallel cable problem
33427: 01/07/26: Free VHDL cores - where?
Daniel =?ISO-8859-1?Q?Han=27czewski?=:
43672: 02/05/29: Xilinx Foundation schematic multi-sheet problem.
Daniel Alley:
5735: 97/03/11: How to tell number of or name of Viewlogic users on PC network under site license?
6151: 97/04/18: Re: Pentium Pro Worth it for Altera Max Plus?
9700: 98/03/31: Re: Digital PLL's or Manual Synching?
10226: 98/05/05: Re: 3.3V design conversion
Daniel Camozzato:
59930: 03/09/01: Partial Reconfiguration : 2 reconfig modules
60137: 03/09/05: Re: Partial Reconfiguration : 2 reconfig modules
60568: 03/09/16: Re: Partial Reconfiguration : 2 reconfig modules
Daniel Davies:
39287: 02/02/05: Development time query
Daniel Elftmann:
6779: 97/06/27: PCI
7312: 97/08/25: Re: ISP Stories
Daniel Engeler:
Daniel Feldman:
16209: 99/05/10: Divider core
Daniel Fichtner:
55740: 03/05/18: SID chip describtion
Daniel Figuerola Estrada:
17663: 99/08/21: microcontroller vs FPGA
17775: 99/09/02: Re: microcontroller vs FPGA
Daniel Finchelstein:
122401: 07/07/26: Re: EDK Simulation Problem
Daniel Florin:
82595: 05/04/14: free-ip
82686: 05/04/16: Re: free-ip
Daniel Forchheimer:
78333: 05/01/29: Attempts to run Quartus Web Edition in linux (wine)
Daniel Gowans:
69656: 04/05/17: Clock Generation from Asynchronous Data Stream
70019: 04/05/27: Re: Clock Generation from Asynchronous Data Stream
Daniel Hanczewski:
27232: 00/11/16: Basic question on PLD & FPGA
Daniel i Oscar Sanchez:
10118: 98/04/28: help:DfII netlist from extracted
Daniel J. Morelli:
5690: 97/03/07: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
6036: 97/04/07: Re: Motorola FPGAs (again)
32722: 01/07/05: Re: Best JTAG H/W, S/W for most meaningful debug info?
Daniel Johnson:
Daniel Jones:
6789: 97/06/27: Re: XCHECKER Download to Xilinx 9500 CPLDs
8297: 97/12/06: Re: M1 : UCF file problems
9189: 98/03/01: Re: Xilinx Info.
12720: 98/10/26: Re: State machines in VHDL/Verilog
Daniel K Elftmann:
9903: 98/04/12: Re: Xilinx routing optimization?
11386: 98/08/09: Re: Security [0/4]
11387: 98/08/09: Re: Security [1/4]
11388: 98/08/09: Re: Security [2/4]
11389: 98/08/09: Re: Security [3/4]
11390: 98/08/09: Re: Security [4/4]
11857: 98/09/15: Re: Design Security Question
12035: 98/09/25: Re: FPGA information
12036: 98/09/25: Re: Design Security Question
12057: 98/09/26: Re: Design Security Question
12062: 98/09/26: Re: Design Security Question
12096: 98/09/29: Re: Metastability
12188: 98/10/03: Re: Verilog Simulators
12251: 98/10/07: Re: interrupt controller design? (i.e. 82C59)
12252: 98/10/07: Re: Design security again - the Actel solution
Daniel K. Elftmann:
6842: 97/07/02: Re: Altera archiving
7568: 97/09/23: Re: Lattice Synario and ISPLSI1048
7567: 97/09/23: Re: I2C bus in an ALTERA FPGA (FLEX 10K50)
11654: 98/08/29: Re: CPLD/FPGA software
12551: 98/10/15: Re: 100 MHz FPGA
12552: 98/10/15: Re: PCI target code
12680: 98/10/23: Re: Xilinx may not support schematics for Virtex?????
13395: 98/11/30: Re: Which parts are fastest for 3-state enables?
13504: 98/12/06: Re: Which parts are fastest for 3-state enables?
13505: 98/12/06: Re: CPLD with extended temperature (almost mil temp range)
13781: 98/12/26: Re: Xilinx/CAST 16550 core
13833: 98/12/29: Re: Async Fifo Core or Macro for Xilinx FPGA
15100: 99/03/06: Re: experience with Xilinx 4K series I/Os
15426: 99/03/23: Re: FPGA vendor comparison
16543: 99/05/27: Re: Xilinx M1.5 Crash
18051: 99/09/26: Re: absolut Newbie
19286: 99/12/10: Re: Synopsys backannotation
Daniel Kho:
153724: 12/04/30: Re: CPU Design in Xilinx Spartan 3E
153741: 12/05/03: Re: Wow! No TestbenchWow!
156940: 14/07/31: Re: Generating a desired synthesizable binary pulse train on FPGA
157013: 14/08/26: Re: Bidirectional Pin FPGA (Parallel ADC)
157014: 14/08/26: Re: Bidirectional Pin FPGA (Parallel ADC)
158641: 16/02/23: Re: Where is a code example on how to use a floating multiplier on
158642: 16/02/23: Re: Source control and ip cores
158643: 16/02/23: Re: Source control and ip cores
158673: 16/03/05: Re: Where is a code example on how to use a floating multiplier on
158674: 16/03/05: Re: How to define a counter whose width is big enough to hold integer 27?
158676: 16/03/05: Re: How to define a counter whose width is big enough to hold integer 27?
158678: 16/03/05: Re: How to define a counter whose width is big enough to hold integer 27?
Daniel Koethe:
80888: 05/03/14: Re: BFM Simulation Trouble
87609: 05/07/27: Re: The new IOBUF in Spartan-3E
126155: 07/11/15: Re: EDK 9.1 Issues
127010: 07/12/08: Re: Xilinx EDK simulation
127728: 08/01/06: Re: MPMC On EDK
127733: 08/01/06: Re: MPMC On EDK
127889: 08/01/09: Re: Using DDR SDRAM as single data rate ..?
128702: 08/02/04: Re: A video tutorial: The Xilinx FPGA Editor
129168: 08/02/17: Re: Synthesis-Place-Route benchmark for i386-32bit
Daniel Kroening:
22222: 00/05/02: Re: which Conference Calendars on the web .... (FPL 2000)
Daniel Lang:
3340: 96/05/15: Re: Anyone use Orcad PLD tools ?
3341: 96/05/15: Re: Anyone use Orcad PLD tools ?
5237: 97/01/31: Re: Suggestions how wire wrap mount a Xilinx PG223
5633: 97/03/03: Re: JTAG config on ALTERA FLEX10K10: How?
6114: 97/04/12: Re: About the usage of Altera maxplus2
6322: 97/05/14: Re: HELP!!! can't work with ByteBlaster
8054: 97/11/11: Re: ALPHA AXP architecture
8413: 97/12/12: Re: bus design in Altera 10K, how to increase speed
8666: 98/01/19: Re: ASIC and PCB makers for Hobbyists wanted
8784: 98/01/26: Re: ALtera Devices.
9911: 98/04/12: Re: Effects of IC production
10336: 98/05/12: Re: Altera 3.3V and 5V
10740: 98/06/15: Re: AHDL vs. VHDL vs. Verilog HDl
11157: 98/07/21: Re: Shift Invarient Bit Transform
11601: 98/08/26: Re: PROM alternative
11612: 98/08/26: Re: How to design a PLL
12185: 98/10/03: Re: Orcad Capture error DSM0006 and DBO3203
13596: 98/12/10: Re: computer requirements for CAE systems
29176: 01/02/08: Re: can -(A+B) computed in one level of logic ?
29177: 01/02/08: Re: Altera, NON JTAG devices.
35341: 01/09/29: Re: How does Altera FLEX 10k communicate with PC?
35950: 01/10/24: Re: High-speed Logic, Military/Space Grade
41432: 02/03/27: Re: ByteblasterMV EPM7064S voltage problem
45160: 02/07/13: Re: Accurate Oscillator
48914: 02/10/26: Re: Virtex2 5V tolerant I/O ??
51152: 03/01/03: Re: BP programmer questions, prices, alternatives
57694: 03/07/03: Re: Regarding NRZ
60025: 03/09/03: Re: Thinking out loud about metastability
60112: 03/09/05: Re: Flex6K configuration PROM
60443: 03/09/12: Re: Crystal Input to FPGA
62678: 03/11/04: Re: help with 120MHz comparator
63335: 03/11/19: Re: Architecture desing using national serializer and deserialiser
85557: 05/06/10: Re: computer upgrade time.
88788: 05/08/28: Re: CPLD Jitter
88889: 05/08/30: Re: Array of slope A/Ds in FPGA?
89377: 05/09/13: Re: Migration Altera APEX20KE to ???
91551: 05/11/08: Re: which Altera CPLD?
96768: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
100553: 06/04/11: Re: very slow pull-up with CPLD design
104786: 06/07/06: Re: Chaos in FF metastability
Daniel Lapierre:
689: 95/02/07: USRT on actel
694: 95/02/08: USRT integration
708: 95/02/13: Small Computer integration.
daniel lapierre:
116: 94/08/17: ACTEL
Daniel Lee Moore:
1642: 95/08/09: Re: Clocking methods - which is prefered?
Daniel Leu:
150233: 11/01/04: Re: Actel Designer: how to compile VHDL top & EDIF submodule together?
Daniel Lewallen:
8557: 98/01/08: Timingg Question for Xilinx FPGA
Daniel Ley:
1482: 95/06/27: Test,don't bother reading this
Daniel Lopresti:
2210: 95/11/02: Re: Xilinx Configuration Memory Hacking
Daniel Mendes:
151836: 11/05/22: Re: Quadrature Modulation Tutorial
Daniel Morelli:
32595: 01/07/01: Intel 82380 DMA Controller in Xilinx 300
Daniel Nilsson:
25303: 00/09/06: sowtware/programmer
25330: 00/09/06: DRAM controller
25861: 00/09/23: dp ram
25932: 00/09/27: hdl
25938: 00/09/27: SV: hdl
26112: 00/10/04: pci host
26628: 00/10/23: SV: PCB's for re-casting the form factor of a QFP
27359: 00/11/19: xilinx xc9500
27483: 00/11/23: ide and dram controller
28755: 01/01/23: xilinx cpld
28994: 01/02/01: lcd driver for EG2401S
29198: 01/02/09: SV: counter
29247: 01/02/11: OT: SEIKO-EPSON LCD behaving strange.
29322: 01/02/14: SV: Programming a CPLD
30091: 01/03/23: what to do with I/O pins during powerup or during jtag programming
33884: 01/08/07: interfacing XILINX XC95 to PC parallell port
33934: 01/08/09: Re: interfacing XILINX XC95 to PC parallell port
34339: 01/08/22: protecting pins on xilinx xc95 cpld
34474: 01/08/27: new to fpga
34490: 01/08/28: Re: Polyphase adjustment to keep it working
34495: 01/08/28: IEEE 1149.1-1990
34669: 01/09/03: using non-standard eeprom to program xilinx fpga
36694: 01/11/16: jtag programming xilinx cpld
36743: 01/11/19: jtag programming xilinx xc9572 cpld
77005: 04/12/19: Re: RAM programming by JTAG (i need some serious help)
Daniel O'Connell:
29329: 01/02/14: Re: Duplicate definitions for timing specs (xilinx fnd)
Daniel O'Connor:
100993: 06/04/24: Re: ISE 8.1i for Linux ?
101482: 06/05/02: Re: ISE 8.1i for Linux ?
102960: 06/05/24: Re: getting good deals on small qty?
102962: 06/05/24: Re: windrvr for Linux broken in 2.6.16
103206: 06/05/29: Re: Superscalar Out-of-Order Processor on an FPGA
103783: 06/06/11: Re: Xilinx ISE S/W Install kernel version "mismatch"
103785: 06/06/11: Re: Altium Livedesign eval boards - can you add a configuration prom?
103832: 06/06/13: Re: Anyone with Xilinx SP305-board ?
103837: 06/06/13: Re: xc3sprog -- any updates?
105862: 06/08/02: Re: 100m JTAG cable
106063: 06/08/07: Re: 100m JTAG cable
106066: 06/08/07: Re: Xilinx USB Blaster FX2 firmware and CPLD replacement under GPL released
106133: 06/08/08: Re: Xilinx USB Blaster FX2 firmware and CPLD replacement under GPL released
106747: 06/08/18: Re: Open-source JTAG software?
106855: 06/08/21: Newbie frustration
106856: 06/08/21: Re: Anyone use XC3Sprog?
106949: 06/08/23: Re: Newbie frustration
106963: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
106977: 06/08/23: Re: Newbie frustration
107145: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107153: 06/08/25: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107278: 06/08/26: Re: Newbie frustration
107279: 06/08/26: Re: Quartus and source control (continued)
107280: 06/08/26: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107287: 06/08/26: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
108136: 06/09/06: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
114028: 07/01/03: Re: Xilinx ISE 8.2.3 - Re-Creating Projects
114589: 07/01/20: Re: ISE Simulator Error 222: SuSE 10.1 Linux
114714: 07/01/23: Re: Xilinx ISE 8.2
114856: 07/01/25: Re: Xilinx ISE 8.2
114953: 07/01/28: Re: Xilinx ISE 8.2
115052: 07/01/30: Re: USB 2.0 Streaming using FPGAs
115346: 07/02/08: Replacing/emulating an asynchronous FIFO
115392: 07/02/09: Re: Replacing/emulating an asynchronous FIFO
115403: 07/02/10: Re: Replacing/emulating an asynchronous FIFO
117315: 07/03/28: Re: Help with Xilinx Parallel Cable IV.
117400: 07/03/30: Re: Help with Xilinx Parallel Cable IV.
118500: 07/04/28: Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
127069: 07/12/11: Re: Xilinx ise 9.2i clean up project files
127394: 07/12/20: Xilinx Spartan 3 JTAG issues
127409: 07/12/21: Re: Xilinx Spartan 3 JTAG issues
Daniel Payne:
3404: 96/05/24: Re: *** The Great ESDA Shootout ***
3741: 96/07/23: Job posting
Daniel R. Crouse:
691: 95/02/07: Low cost Boundary Scan?
Daniel Roganti:
6348: 97/05/17: Q: Leonardo, any pros/cons using this ?
6513: 97/05/29: Re: Q: Leonardo, any pros/cons using this ?
Daniel S.:
54937: 03/04/22: Re: Webpack 5.2 Install problems?
56782: 03/06/15: Re: xilinx webpack programming
106586: 06/08/15: Re: Large Spartan3 vs. Small V5
106618: 06/08/16: Re: Large Spartan3 vs. Small V5
106657: 06/08/16: Re: Large Spartan3 vs. Small V5
106668: 06/08/16: Re: xilinx or altera?
106808: 06/08/19: Re: Warningmessage in ISE
107666: 06/08/30: Re: MGT Power supply
107736: 06/08/31: Re: MGT Power supply
108025: 06/09/04: Re: wiring resource utilization?
108134: 06/09/05: Re: Serial I/O Question
108239: 06/09/06: Re: Serial I/O Question
108379: 06/09/09: Re: how can I decrease the time cost when synthesis and implement
108404: 06/09/10: Re: ddr with multiple users
108483: 06/09/12: Re: ddr with multiple users
108542: 06/09/12: Re: ddr with multiple users
109594: 06/09/29: Re: state machine dead problem
111092: 06/10/28: Re: ISE 8.2 freeze
112025: 06/11/14: Re: Pipelining can reduce the slice usage
112422: 06/11/21: Re: PCMCIA interface
112424: 06/11/21: Re: I2C "READ" Setup/Hold Requirement
112565: 06/11/24: Re: pulse jitter due to clock
112910: 06/11/30: Re: Bus structures question (Spartan 3)
112944: 06/12/01: Re: Double buffering
113220: 06/12/08: Re: Clock phase shift
113572: 06/12/17: Re: FPGA : Async FIFO, Programmable full
113573: 06/12/17: Re: Frequency divider?
113585: 06/12/17: Re: FPGA : Async FIFO, Programmable full
113592: 06/12/17: Re: FPGA : Async FIFO, Programmable full
113595: 06/12/17: Re: what are your current SoC design for ?
113597: 06/12/17: Re: Frequency divider?
113610: 06/12/18: Re: FPGA : Async FIFO, Programmable full
113665: 06/12/19: Re: FPGA : Async FIFO, Programmable full
116059: 07/02/28: Re: Making a 32KB BRAM block, virtex-4
116068: 07/02/28: Re: How to implement pipeline in this case?
116158: 07/03/02: Re: Making a 32KB BRAM block, virtex-4
116160: 07/03/02: Re: How to implement pipeline in this case?
116202: 07/03/04: Re: xilinx block ram synthesis
116250: 07/03/05: Re: How to implement pipeline in this case?
116261: 07/03/05: Re: xilinx block ram synthesis
116271: 07/03/06: Re: Multiplication operation
116297: 07/03/06: Re: How to implement pipeline in this case?
116302: 07/03/06: Re: How to implement pipeline in this case?
116312: 07/03/07: Re: How to implement pipeline in this case?
116314: 07/03/07: Re: VHDL and Latch
116391: 07/03/08: Re: Introducing picosecond delay between two output signals
116393: 07/03/08: Re: FPGA Vs ASIC design and implementation
116395: 07/03/08: Re: Avnet Virtex-4 FX12 mini module
116399: 07/03/08: Re: Introducing picosecond delay between two output signals
116453: 07/03/09: Re: Routing problem of DCM
116459: 07/03/09: Re: FPGA Vs ASIC design and implementation
116494: 07/03/10: Re: ddr sdram controller
116501: 07/03/11: Re: Are FPGAs go enough for clock dstribution
116567: 07/03/13: Re: Heatsink on FPGA?
116615: 07/03/13: Re: VHDL and Latch
116616: 07/03/13: Re: xilinx block ram synthesis
116618: 07/03/13: Re: Addressing scheme in Block RAM
116620: 07/03/14: Re: faq
116627: 07/03/14: Re: Heatsink on FPGA?
116660: 07/03/14: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116711: 07/03/15: Re: Clearing fpga internal memory...
116748: 07/03/16: Re: How to use the DDR SDRAM instead of Block RAM?
116761: 07/03/16: Re: Clearing fpga internal memory...
116776: 07/03/17: Re: Xilinx Synthesis Attribute usage
116787: 07/03/18: Re: Xilinx ISE support for dual/quad core CPUs?
116789: 07/03/18: Re: Eval board advice
116792: 07/03/18: Re: Eval board advice
116814: 07/03/19: Re: How to use the DDR SDRAM instead of Block RAM?
116910: 07/03/20: Re: How to use the DDR SDRAM instead of Block RAM?
116932: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
116933: 07/03/21: Re: Xilinx ISE support for dual/quad core CPUs?
116977: 07/03/21: Re: Data width in Block ram
116981: 07/03/21: Re: Xilinx ISE support for dual/quad core CPUs?
116992: 07/03/21: Re: Off topic: what is the purpoe of XST?
117028: 07/03/22: Re: Virtex-II block RAM problem
117032: 07/03/22: Re: Data width in Block ram
117093: 07/03/22: Re: Virtex-II block RAM problem
117128: 07/03/23: Re: multiple clock domain issues
117177: 07/03/26: Re: Where is Open Source for FPGA development?
117210: 07/03/26: Re: Where is Open Source for FPGA development?
117236: 07/03/27: Re: Where is Open Source for FPGA development?
117257: 07/03/27: Re: Spartan 3E Not enough block ram.
117282: 07/03/27: Re: Lattice "Open IP" license is GPL-compatible?
117295: 07/03/27: Re: Where is Open Source for FPGA development?
117327: 07/03/28: Re: Where is Open Source for FPGA development?
117350: 07/03/28: Re: Confuse on Spartan speed
117351: 07/03/28: Re: Confuse on Spartan speed
117372: 07/03/29: Re: Where is Open Source for FPGA development?
117420: 07/03/30: Re: Where is Open Source for FPGA development?
117422: 07/03/30: Re: A suggestion for a new input interface for functions in VHDL:
117428: 07/03/30: Re: Spartan 3E Not enough block ram.
117433: 07/03/30: Re: RISC implementation questions
117464: 07/04/01: Re: A suggestion for a new input interface for functions in VHDL:
117466: 07/04/01: Re: How much time margin should I give to a SDRAM interface via FPGA?
117476: 07/04/02: Re: Help with a face recognition system
117567: 07/04/04: Re: Spartan 3E Not enough block ram.
117596: 07/04/04: Re: Implement IIR Filter on FPGA
117598: 07/04/04: Re: high number of multipliers / low cost
117633: 07/04/05: Re: Spartan 3E Not enough block ram.
117739: 07/04/09: Re: Clocking data into a shift register on positive AND negative
117780: 07/04/10: Re: Measuring the period of a signal
117782: 07/04/10: Re: VIrtex-4 FIFO16
117839: 07/04/11: Re: Spartan 3E Not enough block ram.
117885: 07/04/12: Re: Spartan 3E Not enough block ram.
117927: 07/04/13: Re: Spartan 3E Not enough block ram.
117930: 07/04/13: Re: Order of the synchronous operations
117953: 07/04/14: Re: Order of the synchronous operations
117961: 07/04/14: Re: Order of the synchronous operations
117970: 07/04/14: Re: Order of the synchronous operations
117973: 07/04/15: Re: How many RAM words can I implement in my Xilinx FPGA?
117978: 07/04/15: Re: Order of the synchronous operations
118031: 07/04/16: Re: Safety of bidirectional lines
118033: 07/04/16: Re: Why 166Mhz DDR?
118034: 07/04/16: Re: Why 166Mhz DDR?
118075: 07/04/17: Re: Spartan 3E Not enough block ram.
118077: 07/04/17: Re: Safety of bidirectional lines
118107: 07/04/17: Re: Safety of bidirectional lines
118108: 07/04/17: Re: Why 166Mhz DDR?
118383: 07/04/25: Re: Spartan 3E Not enough block ram.
118556: 07/04/29: Re: physical chip size
118730: 07/05/02: Re: Area constraint - trust Low Level Synthesis?
119125: 07/05/12: Re: how to choose the perfect fpga support
123265: 07/08/22: Re: Amount of wire and logic
123375: 07/08/25: Re: DDR/DDR2 controller - core
123446: 07/08/28: Re: MGT Link
123448: 07/08/28: Re: DDR controller - best device to perform
123684: 07/09/01: Re: comparison with embedded processor
123984: 07/09/09: Re: Quick question for an Altera wizard
124233: 07/09/15: Re: Virtex II pro design question
124449: 07/09/21: Re: Guess: what is the largest number of state machines in a current
Daniel Sears:
13810: 98/12/28: Re: smallest DCT algorithm?
Daniel Stevens:
33360: 01/07/24: IEEE1394
Daniel T. Schwager:
11665: 98/08/29: Spartan and VHDL-design "Problem"
11666: 98/08/29: Re: PROM alternative
Daniel Tschurr:
44589: 02/06/24: latch in Altera APEX20KE causes oscillations
Daniel V. Bailey:
13592: 98/12/10: CFP: Workshop On Cryptographic Hardware And Embedded Systems (CHES)
Daniel Wiklund:
15109: 99/03/07: Re: A few questions - beginner
Daniel Yap:
37926: 01/12/25: Lattice Filter Schematic?
38052: 02/01/03: Help on RAM-based Shift Registers
38127: 02/01/07: scalling ammulator problem
38478: 02/01/16: Altera Compiling Error..WHY?????
38594: 02/01/19: why Altera LPM_ROM can't drive out value?
40244: 02/03/03: thank you friends
daniel.kho:
153738: 12/05/03: Re: Wow! No TestbenchWow!
153739: 12/05/03: Re: Wow! No TestbenchWow!
daniel.larkin@gmail.com:
106612: 06/08/16: FPGA Memory Power
106637: 06/08/16: Re: FPGA Memory Power
106645: 06/08/16: Re: FPGA Memory Power
148473: 10/07/26: Embedded Multipliers in Altera Cyclone
148479: 10/07/27: Re: Embedded Multipliers in Altera Cyclone
<daniel.studer@ebv.com>:
119485: 07/05/21: Re: Cyclone FPGAs in Switzerland
<daniel_elftmann@my-deja.com>:
25118: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25119: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25120: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
Daniele Beccari:
284: 94/10/12: ALTERA EPLDs
<danielgutierrezcastro@hotmail.com>:
122888: 07/08/09: Reset and DCM
Danijel Sebalj:
25263: 00/09/03: Satecad
25283: 00/09/05: StateCAD ?
Daning Ren / 30066:
23861: 00/07/13: Functional Simulation for Xilinx PCI Example Ping
<daniveras@aol.com>:
91110: 05/10/29: Re: Physical interface for PCI express(PIPE) electrical information
94555: 06/01/13: Re: FPGA Journal Article
94550: 06/01/13: Re: PCI e clocking
dank:
115614: 07/02/14: Re: picoblaze assembler : kcpsm3.exe and wine/linux
danmarco:
136987: 08/12/17: xilinx: FSL - FSL_Has_Data vs FSL_S_Exists
Dann Corbit:
8630: 98/01/14: Re: Asynchronous square root.
19391: 99/12/17: Dumb question springing from a discussion about chess on a chip...
19393: 99/12/17: Re: Dumb question springing from a discussion about chess on a chip...
104822: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104871: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104948: 06/07/10: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105001: 06/07/11: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
Danny:
231: 94/09/29: Re: Exemplar CORE experiences?
Danny Kumamoto:
7450: 97/09/11: RFP: Reconfigurable Tool
Danny Niewzwaag:
29874: 01/03/14: VHDL capacity
29893: 01/03/15: International VHDL cooperation wanted
<dannymarcus@gmail.com>:
94480: 06/01/12: Newbe Startup Time Question
dano:
40444: 02/03/07: How can I install Xilinx ISE 4.1i under Linux?
40488: 02/03/08: Re: How can I install Xilinx ISE 4.1i under Linux?
<dano1@attglobal.net>:
44983: 02/07/08: Virtex-II PRO Channel alignment not working?
Dany:
43198: 02/05/16: XAPP173 BUG
Dany Comeau:
Dany XP:
36165: 01/10/31: Synthesis of picoJava II for FSOC
Danyao:
144438: 09/12/07: Rotating priority encoder and shifters in XST
144492: 09/12/10: Re: Rotating priority encoder and shifters in XST
danyxp:
55892: 03/05/22: FIFO with EABs in Altera MaxPlusII for Flex 10K
56737: 03/06/13: Altera Flex10K FIFOs
56993: 03/06/20: Virtex-E boards
DanyXP:
51637: 03/01/17: Synopsys tools for Linux
Dar Shan:
51259: 03/01/08: Small outline FPGA/PLD with differential LVPECL capability
Daragoth:
70887: 04/06/30: Compact FPGA Board?
70917: 04/07/01: Re: Compact FPGA Board?
71189: 04/07/11: Re: Compact FPGA Board?
71274: 04/07/13: Re: Compact FPGA Board?
71401: 04/07/16: Re: Compact FPGA Board?
71607: 04/07/24: Re: Compact FPGA Board?
71858: 04/08/02: Re: Compact FPGA Board?
71965: 04/08/04: Re: Compact FPGA Board?
72066: 04/08/06: Re: Compact FPGA Board?
72140: 04/08/09: Re: Compact FPGA Board?
72316: 04/08/14: Re: Compact FPGA Board?
73745: 04/09/28: Re: Looking for a Design for a Small FPGA Board
73883: 04/09/30: Re: Looking for a Design for a Small FPGA Board
73203: 04/09/15: Looking for a Design for a Small FPGA Board
73303: 04/09/18: Re: Looking for a Design for a Small FPGA Board
73565: 04/09/23: Re: Looking for a Design for a Small FPGA Board
74096: 04/10/03: Re: Looking for a Design for a Small FPGA Board
Darcio Prestes:
139909: 09/04/18: Atari VCS 2600 FPGA Cartridge
139916: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139921: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139923: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139925: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139973: 09/04/21: Re: Atari VCS 2600 FPGA Cartridge
Darien A. Gothia:
81514: 05/03/25: iMPACT Boundary-Scan Error
81539: 05/03/26: Re: iMPACT Boundary-Scan Error
Darin Johnson:
24903: 00/08/21: Re: Non-disclosures in job interviews, Round One
24949: 00/08/23: Re: Non-disclosures in job interviews, Round One
25009: 00/08/23: Re: Non-disclosures in job interviews, Round Two
25011: 00/08/23: Re: Non-disclosures in job interviews, Round Two
25584: 00/09/14: Re: hardware compatibility and patent infringement
25629: 00/09/15: Re: hardware compatibility and patent infringement
25630: 00/09/15: Re: hardware compatibility and patent infringement
25643: 00/09/16: Re: hardware compatibility and patent infringement
25745: 00/09/19: Re: hardware compatibility and patent infringement
56528: 03/06/07: Re: Logical analyzer via USB or printer port
Dario:
104796: 06/07/06: FPGA interpolated FIR implementation
109540: 06/09/28: Nios II dev board
<dario.gall@gmail.com>:
81418: 05/03/23: nallatech BallySHARC boot JTAG problem
Darius:
89758: 05/09/25: re:Xilinx ISE WebPACK-7.1i on NetBSD
90122: 05/10/05: re:Xilinx ISE WebPACK-7.1i on NetBSD
Darius Braziunas:
6236: 97/05/01: TEST
darkcyde:
8474: 97/12/19: FPGA Speeds ???
DarkDawn:
49636: 02/11/18: looking for a VHDL imlementation of MD5 Hash algorithm.
Darko8:
156680: 14/06/03: Re: Signal Integrity Failure on Custom FPGA board
Darol:
150686: 11/02/03: Re: Trivia: Where are you on the HDL Map?
153021: 11/11/15: Re: ASIC design job vs FPGA design job
Darol Klawetter:
127314: 07/12/17: Re: How to use a generic memory with Xilinx ?
135207: 08/09/19: Re: Is it hard to detect an ucf sytax error?
135891: 08/10/20: Re: external differential clock inputs
135902: 08/10/21: Re: Question on timing constraints
135934: 08/10/22: Re: Virtex 5 DSP.
138206: 09/02/09: Re: Learning backend stuff
141614: 09/06/30: Re: 720 Mhz IF Processing
147841: 10/05/26: Re: Advice on Xilinx Spelunking
148998: 10/09/20: Xilinx XST and a State Machine - A Mystery
149001: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149002: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149004: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149007: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149010: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149014: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149022: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
149057: 10/09/27: Re: Xilinx XST and a State Machine - A Mystery
149246: 10/10/11: Re: Calculating SFDR in FPGA
<darol.klawetter@gmail.com>:
154340: 12/10/08: Re: FPGA-Board for Ethernet
157788: 15/03/27: Re: Interpret a VHDL statement within a serial to paralell port
Darrell Gibson:
31062: 01/05/10: Leonardo/Modelsim/Xilinx post synthesis simulation (VHDL)
Darrell Grainger:
39192: 02/02/04: Re: JTAG Boundary Scan with the XDS510
Darrell Irvin:
6481: 97/05/27: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
darrell mcginnis:
23871: 00/07/13: Re: Timing Simulation for Alter FPGAs
24062: 00/07/25: Re: Spartan II Pin
34446: 01/08/24: Re: SmartMedia
Darrell Ray:
11378: 98/08/07: Re: PCI Core In FPGA
Darren File:
12207: 98/10/05: interrupt controller design? (i.e. 82C59)
Darren Gnanapragasam:
43715: 02/05/30: VIRTEX-E XCV405E Orcad schematic required
Darren Koh:
13163: 98/11/18: which programing
Darren Kuhn:
24737: 00/08/17: Re: Non-disclosures in job interviews, Round One
24793: 00/08/18: Re: Non-disclosures in job interviews, Round One
24794: 00/08/18: Re: NDA's outside the US.
24796: 00/08/18: Re: Non-disclosures in job interviews, Round One
Darren Wedgwood:
2424: 95/12/04: Re: NeoCAD and AT&T vs. Xilinx
Darren Zacher:
66989: 04/03/02: Re: synthesis error - left bound of range doesn't evaluate to a constant
<darren.redmond@gmail.com>:
111932: 06/11/13: Re: FPGA Debug Tool
111945: 06/11/13: Re: FPGA Debug Tool
<Darren@pmel.com>:
976: 95/04/06: Motorola Software Support
1392: 95/06/13: RE: Low cost CPLD/FPGA tools
<darrick>:
121283: 07/06/30: Xilinx programmer, many unknown devices...
121286: 07/06/30: Re: Xilinx programmer, many unknown devices...
121293: 07/06/30: Re: Xilinx programmer, many unknown devices...
121302: 07/07/01: Question about xilinx programmer
121305: 07/07/02: Re: Question about xilinx programmer
121316: 07/07/02: About the parallel port jtag programmer,
121357: 07/07/03: question about xilinx jtag
121360: 07/07/03: Re: question about xilinx jtag
121437: 07/07/04: Question about xilinx jtag programmer
121439: 07/07/04: Re: Question about xilinx jtag programmer
121445: 07/07/04: Unbuffered jtag programmer?
Darrin Nagy:
14872: 99/02/22: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
17596: 99/08/12: Re: NRZ Deserializing in Virtex
17685: 99/08/24: Re: input offset constraint to Xilinx IOB's
57305: 03/06/27: Offset and falling edge clocks
160224: 17/08/09: SystemVerilog and alternatives
Darron:
143359: 09/10/05: Re: Implement ARM cores on a FPGA chip?
143383: 09/10/07: Re: Implement ARM cores on a FPGA chip?
Darron May:
2754: 96/02/02: Re: Synplify from SYNPLICITY
Darryl Groom:
47749: 02/10/03: Goertzel algorithm tone detector
Darryl Jewiss:
18256: 99/10/11: Re: Can't detect Flex 10K Altera device through JTAG port
dartanian:
125580: 07/10/29: registers are not shown in waveform (xilinx microblaze)
126465: 07/11/23: can't read/load memory contents
126513: 07/11/26: Re: can't read/load memory contents
126548: 07/11/27: Re: can't read/load memory contents
Darxus:
7963: 97/11/03: I'm interested in FPGAs. How do I start ?
Daryl:
45597: 02/07/29: Re: How to implement efficient wide word comparator?
45604: 02/07/29: Re: Programming FLASH with Xilinx Parallel Cable III
45605: 02/07/29: Re: secure FPGA
45630: 02/07/30: Who can compare the synthesis tools for me ?
45683: 02/08/01: Re: about amplify/synplify
45795: 02/08/06: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45834: 02/08/07: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45965: 02/08/13: Re: changing width of array
45975: 02/08/13: "flip flop" and "register"
46130: 02/08/20: Re: "flip flop" and "register"
46257: 02/08/23: FPGA speed level
46352: 02/08/27: Re: FPGA speed level
47332: 02/09/24: Re: Unused pins in Apex20KE
49779: 02/11/21: "new" Xilinx IOB timing paramter "Tiotp"
Daryl Bradley:
14870: 99/02/22: Xilinx Virtex
14973: 99/03/01: Virtex development boards
15058: 99/03/04: virtex chips
15059: 99/03/04: Re: virtex chips
15157: 99/03/10: Nallatech Virtex boards
15569: 99/03/31: vcc virtex workbench
15937: 99/04/22: vcc vw cables
16253: 99/05/12: Virtex development boards
16845: 99/06/14: Re: Virtex Boards
16901: 99/06/16: Re: Which Virtex prototype board ?
16925: 99/06/17: Re: Virtex Boards
16927: 99/06/17: Re: Virtex Boards
16940: 99/06/18: Re: Virtex Boards
17703: 99/08/25: Re: Virtex dev boards
17712: 99/08/26: Re: Virtex dev boards
18220: 99/10/08: Preconfigured pull ups
18473: 99/10/26: generating power on initialisation
19311: 99/12/13: Re: Virtex boards
20985: 00/03/02: Re: Extremely fault tolerant strategies
21072: 00/03/06: Re: Xilinx Parallel Cable III and 3.3V
21312: 00/03/16: Re: Xilinx 6200 devices?
22218: 00/05/02: Re: A Question on Virtex Configuration
82986: 05/04/21: Re: CAM for FPGA ...
Daryl Lee Specter:
15578: 99/03/31: Re: vcc virtex workbench
DaS:
67395: 04/03/11: Re: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
67580: 04/03/15: Re: Anyone Had Spurious Reconguration Issues With Cyclone Devices?
dasari:
50730: 02/12/18: Is there any generic BIST architectures for Xilinx FPGAs for functional test?
50731: 02/12/18: LUT architecture!!
50767: 02/12/18: 16-bit LFSR
50769: 02/12/19: Re: Is there any generic BIST architectures for Xilinx FPGAs for functional test?
51006: 02/12/25: free fpga soft core
51029: 02/12/26: Re: free fpga soft core
51113: 03/01/02: Re: free fpga soft core
51114: 03/01/02: Re: Xilinx Gate Counts
55948: 03/05/24: Re: FPGA design: firmware or hardware?
58585: 03/07/27: Re: GL85 synthesizable code
dash82:
126715: 07/11/29: Pipelining of FPGA code
126774: 07/12/01: Re: Pipelining of FPGA code
datalines:
54078: 03/04/01: CPLD applications?
DATE 2001 University Booth:
28267: 01/01/04: CFP: DATE2001 University Booth
Datha:
63901: 03/12/08: USB basic doubts
<daughenbaugh@gmail.com>:
110082: 06/10/10: Re: longest webcase record
110120: 06/10/11: Re: longest webcase record
Davar Robdan:
51688: 03/01/19: A Request: VHDL Source of a 32bit Floating Point ALU
51762: 03/01/21: Re: A Request: VHDL Source of a 32bit Floating Point ALU - Still Looking!
dave:
65489: 04/01/30: Re: Good/Affordable Stater kits
66095: 04/02/12: Programmable clock, FPGA PLLs, and Actel PLL Core
66126: 04/02/12: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
66176: 04/02/13: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
68119: 04/03/26: Re: USB Traffic Generation for FPGA Test
68159: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
68302: 04/03/31: Re: USB Traffic Generation for FPGA Test
73607: 04/09/25: Re: How To Synchronize FPGAs
76072: 04/11/23: Re: Beginers Question ModelSim Signals
80880: 05/03/14: Re: FPGA Engineer w/clearance - where do you look for a job?
80906: 05/03/14: Re: Which HDL?
81089: 05/03/17: Newbie: Slow FPGAs
81095: 05/03/17: Re: Newbie: Slow FPGAs
81097: 05/03/17: Re: Newbie: Slow FPGAs
81098: 05/03/17: Re: Newbie: Slow FPGAs
81100: 05/03/17: Re: Newbie: Slow FPGAs
81104: 05/03/17: Re: Newbie: Slow FPGAs
81105: 05/03/17: Re: Newbie: Slow FPGAs
81239: 05/03/20: Re: Newbie: Slow FPGAs
82750: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82839: 05/04/18: Re: Tutorial on FPGAs
83054: 05/04/22: Re: Xilinx Impact in Linux 2.6.x
84574: 05/05/21: Re: VHDL vs. Schematic Capture
84577: 05/05/21: Re: VHDL vs. Schematic Capture
84735: 05/05/25: Re: VHDL vs. Schematic Capture
84764: 05/05/26: Re: VHDL vs. Schematic Capture
85122: 05/06/05: Re: keypad scanner
85227: 05/06/07: Re: keypad scanner
85260: 05/06/07: Re: XP for NIOS2
85262: 05/06/07: Re: XP for NIOS2
85949: 05/06/19: Ideal CPU for FPGA?
85964: 05/06/19: Re: Ideal CPU for FPGA?
85965: 05/06/19: Re: Ideal CPU for FPGA?
85966: 05/06/19: Re: Ideal CPU for FPGA?
86332: 05/06/25: Re: Ideal CPU for FPGA?
88027: 05/08/06: Re: Free 8 bit micro for fpga
108851: 06/09/18: Re: Writing VHDL, Software dummy!
121755: 07/07/12: Re: highly-parallel highspeed connection between two FPGA boards
146709: 10/03/26: Re: baud rates etc
Dave:
2442: 95/12/05: FPGA => ASIC (Summary)
3260: 96/05/05: Re: Simple Xilinx board
3367: 96/05/21: Re: Xilinx and Viewlogic
7646: 97/09/30: Circuit Board & FPGA Designers
23055: 00/06/12: Back annotated timing in FPGA Advantage
51043: 02/12/28: BP programmer questions, prices, alternatives
51180: 03/01/05: Re: BP programmer questions, prices, alternatives
51756: 03/01/21: Simulink to vhdl tools
53515: 03/03/14: Re: What is the diff between FPGA and CPLD?
54898: 03/04/21: Re: Webpack 5.2 Install problems?
55773: 03/05/19: Anyone used the CeSys USB2FPGA board
60353: 03/09/11: Webpack Vs. ISE
62449: 03/10/29: using extra eeprom space
63142: 03/11/16: ISE 6.1 with synplify : pin assignments
66648: 04/02/24: Re: Routing algorithm - help needed
68604: 04/04/09: Spartan-3 LC Development Kit from Insight with USB 2.0 Port
68639: 04/04/12: Re: Spartan-3 LC Development Kit from Insight with USB 2.0 Port
68653: 04/04/12: Is Xilinx Parallel Cable III OK For Memec V2Pro / Xilinx EDK?
69378: 04/05/09: Floating Point With Xilinx EDK (PPC)?
69406: 04/05/10: Re: Floating Point With Xilinx EDK (PPC)?
69483: 04/05/11: Re: Floating Point With Xilinx EDK (PPC)?
69522: 04/05/12: Re: Floating Point With Xilinx EDK (PPC)?
69648: 04/05/17: Low cost FPGA dev board with high speed i/f?
69786: 04/05/19: Xilinx EDK (PPC): Problems Porting to Memec 2VP4LC Board
71584: 04/07/22: Re: 32-channel PC-based logic analyzers
72123: 04/08/09: Re: What is the price of the micro-blaze, ... ?
72669: 04/08/27: Problems With Spartan 3 Starter Board
73743: 04/09/28: Re: what to do with the DCM locked signal?
74047: 04/10/02: Re: Removing set/reset logic for shift register (HDL ADVISOR )
73671: 04/09/27: what to do with the DCM locked signal?
76714: 04/12/09: Getting Started With Simple Sound Synthesis
76739: 04/12/09: Re: Getting Started With Simple Sound Synthesis
78400: 05/01/31: Asynchronous Inputs Question
78482: 05/02/01: Asynchronous Inputs Question
82654: 05/04/15: salary ballpark please guys
82696: 05/04/16: Re: salary ballpark please guys
82697: 05/04/16: Re: salary ballpark please guys
82698: 05/04/16: Re: salary ballpark please guys
82699: 05/04/16: Re: salary ballpark please guys
82701: 05/04/16: Re: salary ballpark please guys
82781: 05/04/18: Re: salary ballpark please guys
82946: 05/04/20: Cost of Altera DSP Builder
82997: 05/04/21: Do Synplify DSP and Accelchip support multiple clock domains?
83050: 05/04/22: Re: Do Synplify DSP and Accelchip support multiple clock domains?
83151: 05/04/25: Re: Do Synplify DSP and Accelchip support multiple clock domains?
84874: 05/05/31: What is a typical job scope when FPGAs are involved?
85142: 05/06/06: Re: FPGA : MAC FIR doubt--HELP ME PLEASE
86748: 05/07/05: fastest FPGA speed grade?
86804: 05/07/06: Re: fastest FPGA speed grade?
86925: 05/07/09: Re: Timespec for DCM outputs (Spartan 3) ?
88243: 05/08/12: freeware/reasonable-ware c compiler for picoblaze
88265: 05/08/13: Re: freeware/reasonable-ware c compiler for picoblaze
89428: 05/09/14: Re: FFT implementation in Xilinx Spartan 3 started kit
90949: 05/10/25: Re: a few questions
92633: 05/12/02: Re: Quick question, how do I supply +-5V?
93339: 05/12/20: Re: real-time compression algorithms on fpga
93467: 05/12/22: Re: Going insane - Xilinx VGA controller...
94168: 06/01/06: Chipscope Pro
94985: 06/01/20: Re: Quadrature Encoder ::
96534: 06/02/06: Re: Tefzel or Kynar for PCB mods ?
98158: 06/03/06: Re: processor bus tristate at two places
99282: 06/03/22: Those yellow markers .... (ISE8.1)
101129: 06/04/26: Spartan 3E Starter Board Question
101386: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101511: 06/05/02: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101516: 06/05/02: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101562: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101563: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101571: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101574: 06/05/03: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101639: 06/05/04: Phase alignment of DCMs on different boards/devices
101713: 06/05/05: Re: Phase alignment of DCMs on different boards/devices
102805: 06/05/21: Re: [Newbie] Suitable FPGA for my project
102939: 06/05/23: Re: Superscalar Out-of-Order Processor on an FPGA
102953: 06/05/23: Re: Verilog vs VHDL
102974: 06/05/24: Re: PCI 64/66 fpga eval boards
103442: 06/06/01: Re: Building custom ASIC solutions
103448: 06/06/02: Re: Building custom ASIC solutions
104817: 06/07/06: Re: debouncing a switch (in hardware)
105151: 06/07/14: Re: Where are you heading?
107940: 06/09/02: xilinx bootloader help...
107941: 06/09/02: gpio help...
107966: 06/09/03: Re: gpio help...
107972: 06/09/03: Re: FIR Implementation with System Generator 8.2
108546: 06/09/12: Re: EDK8.2: bidirectional signals when top-level is ISE
108627: 06/09/14: Re: XIlinx Spartan 2E stuck in configuration mode
109332: 06/09/24: Spartan 3 or 3E ?
118336: 07/04/24: Re: DONE problems
118337: 07/04/24: Re: DONE problems
119913: 07/05/29: Re: Looking for experiences with SUZAKU SZ010/SZ030
119943: 07/05/30: Re: Looking for experiences with SUZAKU SZ010/SZ030
125201: 07/10/17: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125247: 07/10/18: Re: VHDL trivia?
125748: 07/11/02: Re: Xilinx EDK and Windows Vista?
126005: 07/11/12: Re: Strange VHDL Error
126206: 07/11/16: Re: FPGA for hobby use
126293: 07/11/19: Re: Update to Xilinx ISE 9.2
126753: 07/11/30: Re: Traffic Light with counter
126972: 07/12/07: Re: converting verilog to vhdl
127598: 08/01/03: Re: round,fix and floor algortihms
127603: 08/01/03: Re: round,fix and floor algortihms
127606: 08/01/03: Re: round,fix and floor algortihms
127912: 08/01/10: Re: Synthesizing big RAMs
127913: 08/01/10: Re: Xilinx ISE 7.1 to 9.2 Width Mismatch
128136: 08/01/16: Re: Basic FPGA question about Reset
128960: 08/02/11: how to implement this...
129135: 08/02/15: Re: microblaze firmware + UART handshaking blues
129596: 08/02/28: Re: DSP newbie
129942: 08/03/11: Re: BRAM synthesis question
129945: 08/03/11: Re: Matlab, RS-232, Ethernet
130524: 08/03/26: Re: Serial Transmission w/o 8B/10B encoding
131265: 08/04/17: Survey: FPGA PCB layout
131285: 08/04/17: Re: Survey: FPGA PCB layout
131510: 08/04/23: Re: Verilog state machines, latches, syntax and a bet!
131711: 08/04/29: Hand-editing xilinx.sys
131890: 08/05/06: Re: warning from ISE 9.2
132119: 08/05/14: Re: xilinx beginner modelsim question
133076: 08/06/17: Cadence offers to buy Mentor Graphics for $1.45B
133179: 08/06/19: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
133187: 08/06/19: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
133190: 08/06/20: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
133224: 08/06/21: Re: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_?=
133458: 08/06/30: Re: arithmetic problem
133459: 08/06/30: Re: Missing the simplest things - Active HDL - Beginners Questions
133462: 08/06/30: Re: arithmetic problem
133774: 08/07/14: Re: Why cant XST sythesis this piece of code
133826: 08/07/16: Re: Fifo Simulation Error
134192: 08/07/30: ISE new file wizard
134255: 08/08/01: Re: ISE new file wizard
135225: 08/09/22: Re: SDRAM question
135418: 08/10/01: Asynchronous delay report shows delays longer that clock period - ok?
135851: 08/10/17: Re: Port mapping (combining components)
136080: 08/10/30: Re: ISE 9.2.03i problem
136484: 08/11/18: Re: opinion about various code generators
137371: 09/01/12: Re: ISE Simulator and State Machines
137372: 09/01/12: Re: what is the difference between two process model & one process
138523: 09/02/25: Re: Converting state machine encoding to std_logic_vector
140394: 09/05/12: XCF32P programming via JTAG
140427: 09/05/13: Re: XCF32P programming via JTAG
140437: 09/05/13: Re: XCF32P programming via JTAG
140768: 09/05/25: Re: When is it to generate transparent latch or usual combinational
141153: 09/06/09: Re: dsp with fpgas by Uwe Meyer-Baese
141414: 09/06/23: Re: index in arrays doesn't work
141620: 09/07/01: Re: pinout
141622: 09/07/01: Re: pinout
141657: 09/07/02: Re: Cheapest FPGA with decent PCI- e interface ?
141766: 09/07/07: Re: How to interpret polyphase coefficients generated in MATLAB
141820: 09/07/10: Re: pullup
142014: 09/07/21: Re: building a card reader into a virtex 2 or 5 based FPGA device.
142084: 09/07/23: Re: building a card reader into a virtex 2 or 5 based FPGA device.
144068: 09/11/10: How to script Xilinx ISE - xflow, batch file, tcl, ?
144576: 09/12/15: Re: multiprocessors MB and shared BRAM
146004: 10/03/03: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146084: 10/03/05: Re: Modelsim PE vs. Aldec Active-HDL (PE)
149030: 10/09/22: Xilinx dropping Modelsim XE
149861: 10/11/29: Re: Brain Cramps...
150137: 10/12/16: FPGA modules/cards with peripheral functions
150143: 10/12/18: Re: FPGA modules/cards with peripheral functions
150150: 10/12/20: Re: FPGA modules/cards with peripheral functions
150158: 10/12/21: Simple ISE Microblaze with GPIO and custom logic example?
150161: 10/12/22: Re: Simple ISE Microblaze with GPIO and custom logic example?
150180: 10/12/28: Microblaze GPIO interfaces to internal logic
150186: 10/12/29: Re: Error in Clock Divider!
154702: 12/12/20: Re: FPGA DSP basics: clock enable / new clock
156223: 14/01/18: Re: Math is hard
156569: 14/05/02: Re: Old Spartan-II demo board from Insight - seeking docs..
156747: 14/06/15: Re: 22V10 programmer
Dave Sharples:
11031: 98/07/13: PCB design @ half the cost
Dave Allen:
584: 95/01/11: Re: Backannotating Xilinx pinouts to ViewLogic symbols
1017: 95/04/14: Re: PPR problem
Dave Bancroft:
9511: 98/03/20: Re: Looking for space qualified FPGAs/ASICs
32211: 01/06/19: Altera EPC16 Question
32234: 01/06/20: Re: Gray counter STRUCTURAL (VHDL)
Dave Barry:
35101: 01/09/21: Altera 20KE Bus Switching
Dave Bartolomeo:
2120: 95/10/18: Re: Bet you can't do these....
Dave Bennett:
84: 94/08/11: Re: Proprietary Configuration Data
604: 95/01/17: Re: Motorola FPGA
Dave Blair:
7650: 97/09/30: Re: Xilinx license idiocy
7969: 97/11/04: 64 BIT PCI bridge in FPGA?
7972: 97/11/04: Help with 64 bit, 33MHz PCI bridge in FPGA?
7970: 97/11/04: Help with 64 bit 33MHz PCI bridge in singe FPGA?
7971: 97/11/04: Help with 64 bit, 33MHz PCI bridge in FPGA?
7973: 97/11/04: Help with 64 bit, 33MHz PCI bridge in FPGA?
7976: 97/11/04: Re: Help with 64 bit, 33MHz PCI bridge in FPGA?
7985: 97/11/05: Re: 64 BIT PCI bridge in FPGA?
Dave Blevins:
58194: 03/07/16: Re: Xilinx ECS Schematic Entry
Dave Brown:
30164: 01/03/26: Xilinx FPGA Config file sizes.
33049: 01/07/16: Xilinx .bit file format
33092: 01/07/17: MCS file format
35370: 01/10/01: CTL Register in Virtex-E Configuration
35733: 01/10/15: SpartanXL bidirectional buffers
35823: 01/10/18: Timing Constarint Error message
35825: 01/10/18: Re: Timing Constarint Error message
35838: 01/10/19: Re: Timing Constarint Error message
35892: 01/10/22: Xilinx Functrional Schematic, extra elemtents?
35913: 01/10/23: Bidirectional port is converted to input during synthesis
35915: 01/10/23: Re: Bidirectional port is converted to input during synthesis
35937: 01/10/24: Re: Bidirectional port is converted to input during synthesis
35938: 01/10/24: Re: Bidirectional port is converted to input during synthesis
35949: 01/10/24: SpartanXL Device Utilization Summary
35979: 01/10/25: Re: SpartanXL Device Utilization Summary
36168: 01/10/31: Xilinx CLB Pack Factor Percentage setting?
36290: 01/11/05: Xilinx ISE false timing errors?
36474: 01/11/09: Location constraint error message?
36494: 01/11/09: Re: Location constraint error message?
36504: 01/11/09: XIlinx SLOW configuration option
36506: 01/11/09: Re: XIlinx SLOW configuration option
36842: 01/11/21: read only version register usinga generic
36866: 01/11/22: Re: read only version register usinga generic
36881: 01/11/22: 3 Input LUTs in SpartanXL
39148: 02/02/01: Read Only Register
39866: 02/02/21: Using a CoreGen component
Dave Colson:
32179: 01/06/18: Flexlm license and windows 2000
32205: 01/06/19: Re: Flexlm license and windows 2000
32210: 01/06/19: Re: Flexlm license and windows 2000
32701: 01/07/05: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
32703: 01/07/05: Aldec Active-HDL 4.2 Windows 2000 Verilog back anno Xilinx problems
33091: 01/07/17: Re: PROBLEM!!!
33096: 01/07/17: Re: PROBLEM!!!
33998: 01/08/10: Re: Spartan-II serial configuration problem from ATMEL device
34005: 01/08/10: Re: Spartan-II serial configuration problem from ATMEL device
34359: 01/08/22: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34517: 01/08/28: test
34607: 01/08/30: Re: WebPack Con-Game
34626: 01/08/31: Re: WebPack Con-Game
34640: 01/08/31: Re: WebPack Con-Game
34792: 01/09/07: Spartan II use of GCK[0:3] pins as general inputs
34832: 01/09/10: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
46676: 02/09/05: Actel Libero
46707: 02/09/06: Actel Libero Platinum Model Sim slow
53929: 03/03/27: Mixed VHDL and Verilog with Xilinx ISE
53956: 03/03/28: Re: Mixed VHDL and Verilog with Xilinx ISE
59651: 03/08/25: Xilinx GLOBAL_LOGIC0 and 1 nets, why?
67760: 04/03/18: JDrive Xilinx
72575: 04/08/25: Re: Any experience with Actel Flash-FPGAs ?
78875: 05/02/09: ProAsic3 (PA3)
78945: 05/02/10: Re: ProAsic3 (PA3)
79023: 05/02/11: Re: ProAsic3 (PA3)
80102: 05/03/01: Re: FPGA tool benchmarks on Linux systems
82211: 05/04/08: XST -vlgincdir
82329: 05/04/11: Re: XST -vlgincdir
Dave Curbow:
17255: 99/07/14: Re: Alto in an FPGA (was CPU's directly executing HLL's)
Dave D'Aurelio:
12154: 98/10/01: Re: open drain output in Altera MAX7000S
12337: 98/10/09: Re: VHDL'93 in MaxPlus
12566: 98/10/16: Re: What's wrong at this Address decoder?
16448: 99/05/22: Re: JTAG: Altera & Xilinx
Dave Daurelio:
2509: 95/12/21: Re: Altera related Qs.
2677: 96/01/23: Re: PLD JDEC Files
Dave Dea:
6999: 97/07/21: Re: PCI burst transfers
Dave Decker:
5623: 97/03/03: Re:What kind of functions mostly implemented using FPGAs?
7726: 97/10/07: Re: bidirectional bus problem
13275: 98/11/23: Re: Combining busses Xilinx
14339: 99/01/26: Re: PLL in FPGA
14922: 99/02/25: Re: Xilinx ABEL?
15776: 99/04/13: Lowest power for DSP
18172: 99/10/05: Re: Multiplierless FIR filters in FPGAs
18178: 99/10/05: Re: Multiplierless FIR filters in FPGAs
19081: 99/11/28: Re: CIC Filters in FPGA
19095: 99/11/29: Re: VHDL vs. schematic entry
19205: 99/12/06: Re: Schematic Help Please....
19396: 99/12/18: Re: Dumb question springing from a discussion about chess on a chip...
19468: 99/12/23: Re: Dumb question springing from a discussion about chess on a chip...
19668: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
19917: 00/01/18: Re: Random Number Generator
dave decker:
2980: 96/03/08: Re: [NEWBIE] FPGA Project?
Dave Dunfield:
21934: 00/04/07: Re: Any free design of 8051 in the net?
Dave Farrance:
10326: 98/05/12: Re: Altera 3.3V and 5V
11311: 98/08/04: Re: VHDL std_logic_vector to integer
56544: 03/06/09: Info on Spartan-II PCI Development Kit
56561: 03/06/09: Re: Info on Spartan-II PCI Development Kit
56597: 03/06/10: Re: Shift registers
56609: 03/06/10: Re: Shift registers
56646: 03/06/10: Re: Shift registers
56661: 03/06/11: Re: Shift registers
56671: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
103474: 06/06/03: FPGA board for USB experiments?
103491: 06/06/04: Re: FPGA board for USB experiments?
103499: 06/06/04: Re: FPGA board for USB experiments?
103503: 06/06/04: Re: FPGA board for USB experiments?
103519: 06/06/05: Re: FPGA board for USB experiments?
103520: 06/06/05: Re: FPGA board for USB experiments?
103521: 06/06/05: Re: FPGA board for USB experiments?
103573: 06/06/06: Re: FPGA board for USB experiments?
103623: 06/06/07: Re: FPGA board for USB experiments?
103712: 06/06/09: Re: FPGA board for USB experiments?
135470: 08/10/03: Re: WEBPACK for linux
139646: 09/04/08: Re: Two stage synchroniser,how does it work?
139650: 09/04/08: Re: Two stage synchroniser,how does it work?
139652: 09/04/08: Re: Two stage synchroniser,how does it work?
139805: 09/04/14: Re: reset & analog circuits
140718: 09/05/22: Re: SPAM?
140727: 09/05/22: Re: SPAM?
141665: 09/07/02: Re: Sign up for Multimedia SoC project
142332: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142344: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142350: 09/08/05: Re: AES encryption of bitstream - is my design secure?
Dave Feustel:
30848: 01/05/01: Re: FPGA Prototyping Kits (Platforms)
30993: 01/05/08: Re: PCI bridge core
31035: 01/05/09: Nallatech Products
31146: 01/05/13: Avnet Virtex-E Development Kit
31147: 01/05/13: Re: C++ To Gates
31149: 01/05/13: Getting Started with FPGAs
31152: 01/05/13: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31313: 01/05/18: Re: Getting Started with FPGAs
31314: 01/05/18: Re: Getting Started with FPGAs
31321: 01/05/18: Re: CDROMs with Free tools and designs
31385: 01/05/21: Re: free simulator
31389: 01/05/21: LFSR Taps for 64 bit registers?
31431: 01/05/23: FPGA Setup/Configuration Documentation
31434: 01/05/23: C Source for BOOZER (BOOlean ZEro-one Reduction) Program
31455: 01/05/25: Re: JTAG source
31467: 01/05/26: Re: free simulator
31545: 01/05/29: Re: free simulator
31634: 01/05/31: Re: Is anybody using FPGAs for scientific computing?
31651: 01/06/01: Re: Help on Xilinx 6200
31683: 01/06/02: Exact URL for ordering Webpack ISE CDROM?
31685: 01/06/02: Which Tools Work with ATMEL FPSLIC?
31686: 01/06/02: Re: Exact URL for ordering Webpack ISE CDROM?
32217: 01/06/19: Re: Has anyone used the Atmel FPSLIC part ?
32465: 01/06/27: Can 3" CDROMs Damage 5" CDROM Drives?
33025: 01/07/15: Re: Xilinx PCI development board
33275: 01/07/21: Silo-3 Demo Program Crashes onDell 4100
33289: 01/07/22: Re: Spartan2XC2S30 vs ACEXEP1K30
33292: 01/07/22: Re: free VHDL and/or Verilog tools?
33293: 01/07/22: Re: Silo-3 Demo Program Crashes onDell 4100
33295: 01/07/22: Configuration via Xilinx Multilinx Cable
33320: 01/07/23: Re: Silo-3 Demo Program Crashes onDell 4100
33358: 01/07/24: Re: Silo-3 Demo Program Crashes onDell 4100
33359: 01/07/24: Xilinx Foundation Software Eval Pkg Won't Instal
33394: 01/07/25: Re: Silo-3 Demo Program Crashes onDell 4100
33396: 01/07/25: Re: Xilinx Foundation Software Eval Pkg Won't Instal
33415: 01/07/25: Re: Application obstacle course
33438: 01/07/26: Re: Free VHDL cores - where?
33439: 01/07/26: Re: Application obstacle course
33466: 01/07/27: Re: Xilinx Foundation Software Eval Pkg Won't Instal
33467: 01/07/27: Re: Application obstacle course
33490: 01/07/28: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33494: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33496: 01/07/28: Can't Install Modelsim - Alternatives for Verilog Simulation???
33503: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33504: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33505: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33506: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33512: 01/07/28: Re: The Continuing Saga of Installing Modelsim software on Windows 2000 Pro
33550: 01/07/30: Re: 3.3i service pack 8
33572: 01/07/30: Virtex-II Supports AMD Hypertransport Bus Protocol
33573: 01/07/30: Re: multi-context FPGA
33574: 01/07/30: Webpack Tutorials
33689: 01/08/02: Re: computer science Vs Computer Enginnering
33696: 01/08/02: Re: Spanning the heirarchy
33698: 01/08/02: Does Flexlm Licensing Work on Windows 2000 Pro?
33756: 01/08/03: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
33795: 01/08/05: Webpack Default Browser
33835: 01/08/06: Batch Install of Xilinx Webpack?
33855: 01/08/06: Looking for a Particular Used Book
33858: 01/08/07: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33883: 01/08/07: URL for XILINX's free 314-page design and sythesis guide
33898: 01/08/07: Re: Looking for a Particular Used Book
33899: 01/08/07: Re: URL for XILINX's free 314-page design and sythesis guide
33901: 01/08/08: Re: Looking for a Particular Used Book
33919: 01/08/08: Re: Looking for a Particular Used Book
33929: 01/08/08: Re: URL for XILINX's free 314-page design and sythesis guide
33930: 01/08/08: Re: prospects for tiny FPGA supercomputer?
34017: 01/08/11: Re: Reconfigurable Computational Accelerator
34026: 01/08/11: Re: Reconfigurable Computational Accelerator
34045: 01/08/12: Re: Slightly off topic - PCs for running FPGA tools
34083: 01/08/13: Re: Slightly off topic - PCs for running FPGA tools
34128: 01/08/15: Re: Reconfigurable Computational Accelerator
34171: 01/08/15: Re: fpga with the smallest i/o setup and hold requirement
34172: 01/08/16: Re: Reconfigurable Computational Accelerator
34205: 01/08/16: Virtex Pro Info
34210: 01/08/16: Re: Reconfigurable Computational Accelerator
34245: 01/08/17: Re: Virtex Pro Info
34294: 01/08/19: Principles of Verifiable RTL Design (2nd ed)
34380: 01/08/22: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
34394: 01/08/23: Latest Maxim bit serializer-deserializer chip announcements
34424: 01/08/24: Re: Latest Maxim bit serializer-deserializer chip announcements
34507: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
34512: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
34528: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
95675: 06/01/25: open source fpga programmer programs
dave frost:
Dave Fuhriman:
14439: 99/01/29: Help for the scientifically-challenged
Dave Galloway:
438: 94/11/16: Transmogrifier C - a C based hardware description language
2609: 96/01/10: Transmogrifier C 3.1 - a C based hardware description language
2926: 96/03/01: Re: Languages for reconfigurable computing.
2944: 96/03/04: Re: Reconfigurable Computing Languages
2961: 96/03/05: Re: Reconfigurable Computing Languages
2998: 96/03/11: Re: Reconfigurable Computing Languages
3039: 96/03/19: Re: Sq. Roots and Languages
3055: 96/03/22: Re: Sq. Roots and Languages
Dave Garnett:
59804: 03/08/28: Dumb DLL Question
62095: 03/10/19: Re: Configuration Blues
63963: 03/12/10: Re: Soldering of FPGAs
65772: 04/02/06: Re: European supplier of Xilinx chips
69247: 04/05/03: Re: Cheap SRAM?
71548: 04/07/21: Re: Cheap FPGA's
75096: 04/10/26: Re: Clock Extraction from Bi-Phase Data
81675: 05/03/29: Re: Spartan II-e PCB
82315: 05/04/11: Re: LVDS for lcd panel and RocketIO
85584: 05/06/11: Re: computer upgrade time.
85693: 05/06/14: Somewhat OT - falling behind the times ...
85696: 05/06/14: Re: Somewhat OT - falling behind the times ...
85899: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85918: 05/06/18: Re: Xlinix configuration: DONE pin too early?
dave garnett:
48551: 02/10/20: ASIC/CPLD Tradeoff
51165: 03/01/04: Re: conversions and some assistance please
54136: 03/04/03: Re: CoolRunner freezes
55309: 03/05/03: Re: use of DRAM as massive FIFO
59101: 03/08/08: Re: Spartan-IIE LVDS?
Dave Glenton:
15650: 99/04/06: USB IP Core required
29899: 01/03/16: Passing text strings to procedures in VHDL
Dave Grace:
6067: 97/04/09: Re: Pentium Pro Worth it for Altera Max Plus?
Dave Graf:
10054: 98/04/24: Re: XC4000XL and Ground Bouncing
Dave Greenfield:
6526: 97/05/30: Re: VHDL PCI FPGA Implementation
53728: 03/03/20: Re: Altera ACEX 1K
63712: 03/12/01: Re: Quote from Xilinx re: XPLA3
68122: 04/03/26: Re: Spartan III availability
68616: 04/04/09: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68654: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68816: 04/04/19: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
70267: 04/06/10: Re: Nios II really available ?
73379: 04/09/20: Stratix II vs. Virtex 4 - availability & fab partnership
73380: 04/09/20: Stratix II vs. Virtex 4 - features and performance
73382: 04/09/20: Stratix II vs. Virtex 4 - power
73562: 04/09/23: Re: Mr. Greenfield, spare us the propaganda !
75716: 04/11/12: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
76104: 04/11/24: Re: Choice of FPGA device -- my view on benchmarks
84111: 05/05/12: Re: "Mine is bigger than yours..."
85176: 05/06/06: Re: not clear about doing power estimation using xpower
97013: 06/02/14: Re: Altera RoHS Irony
100347: 06/04/06: Re: Altera Talkback
104292: 06/06/22: Re: keys to the Kingdom
104405: 06/06/26: Re: keys to the Kingdom
119190: 07/05/14: Re: Power Consumption Estimation for PCI card, any advice?
128571: 08/01/30: Re: equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera
130141: 08/03/16: Re: DDR3 speed, Altera vs Xilinx
Dave H:
115609: 07/02/14: Can't get the ACE to run software apps on the ML403
115665: 07/02/16: Has anyone gotten the GSRD to run from Ace CF?
130176: 08/03/17: Intermittent failure to start sw app on pwr-on, SysACE reset doesn't
Dave Hansen:
22470: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
56143: 03/05/29: Re: JTAG madness
82060: 05/04/06: Re: ISA vs. patent/trademark
95462: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95609: 06/01/24: Re: OT:Shooting Ourselves in the Foot
Dave Hawkins:
9599: 98/03/25: Re: Looking for space qualified FPGAs/ASICs
10114: 98/04/27: FPGA input data rate limitations?
Dave Haynes:
39649: 02/02/15: Re: Spartan-II becomes Vertex.
40966: 02/03/19: Power Tie in Spartan IIE
Dave Howarter:
1566: 95/07/18: Re: AT&T FPGAs - Opinions needed
Dave Ingram:
4554: 96/11/13: Digital PLL or Sample Rate Multiplier
6651: 97/06/09: Re: readback on xc40xx ?
Dave J. Schwartz:
107: 94/08/16: Re: FPGA Hobbyist and their software/programmer/hardware
Dave Kingma:
400: 94/11/07: Anyone have Altera library for Orcad?
426: 94/11/14: Re: Anyone have Altera library for Orcad?
Dave Koontz:
4021: 96/09/03: Re: DES in Xilinx
Dave Krueger:
18184: 99/10/05: Altera 10K50V in-rush/temp problem...
18199: 99/10/07: Re: Altera 10K50V in-rush/temp problem...
18213: 99/10/07: Re: Altera 10K50V in-rush/temp problem...
18276: 99/10/11: Re: Altera 10K50V in-rush/temp problem...
18277: 99/10/11: Re: Altera 10K50V in-rush/temp problem...
18278: 99/10/11: Re: Altera 10K50V in-rush/temp problem...
18279: 99/10/11: Re: Altera 10K50V in-rush/temp problem...
Dave Lowry:
37263: 01/12/05: Can WebPack and Student Edition Co-exist?
37618: 01/12/17: Problems Installing Foundation 4.1 Under '98SE
Dave Marsh:
69440: 04/05/11: Effects of moisture on CPLD
69447: 04/05/11: Re: Effects of moisture on CPLD
69454: 04/05/11: Re: Effects of moisture on CPLD
69575: 04/05/14: Re: Effects of moisture on CPLD
69652: 04/05/17: Re: Effects of moisture on CPLD
Dave Martindale:
50560: 02/12/12: Re: hardware image processing - log computation
50631: 02/12/14: Re: hardware image processing - log computation
Dave Matthews:
3760: 96/07/26: Re: altera -> xilinx
42662: 02/04/30: Re: Power-up reset of Xilinx Spartan-II
Dave McDonnell:
678: 95/02/04: BLIF specs or BLIF to VHDL converter?
Dave Miller:
22659: 00/05/16: Re: SMT 7 segment display ??
Dave Millman:
36008: 01/10/25: DSP on FPGA Opinions Needed->Earn $100
36044: 01/10/26: Re: DSP on FPGA Opinions Needed->Earn $100
36972: 01/11/27: DSP on FPGA Opinions Needed->Earn $100
Dave Moore:
34847: 01/09/11: FPGA Evaluation Board for image processing
86395: 05/06/27: FPGA for video processing
Dave Mould:
7983: 97/11/05: Job opportunity, UK
Dave Nadler:
27833: 00/12/11: VHDL technique for synchronizer ?
29013: 01/02/01: Spartan-II TBUF questions
Dave Nelson:
48276: 02/10/15: PCI simulation model, available as open source
48942: 02/10/27: Open source PCI simulation model available
Dave NewKirk:
7447: 97/09/10: Opportunities for FPGA Designers
Dave Nunn:
108326: 06/09/08: Re: TI TFP410 DVI transmitter help?
111687: 06/11/08: Re: Chip to Chip LVDS
Dave P:
141656: 09/07/02: Re: Cheapest FPGA with decent PCI- e interface ?
141699: 09/07/03: Re: how to use ram or memory
Dave Pedlow:
65415: 04/01/28: ISE6.1 : using virtex 800
65477: 04/01/30: Re: ISE6.1 : using virtex 800
Dave Pollum:
90596: 05/10/17: Re: Best Async FIFO Implementation
90597: 05/10/17: Re: Best Async FIFO Implementation
90638: 05/10/18: Re: Best Async FIFO Implementation
90818: 05/10/21: Re: "Cannot synthesize logic..." ERROR
90819: 05/10/21: Re: which is Low power FPGA?
91593: 05/11/09: Re: Suggestions/Recommendations with CPLD's and Software
91595: 05/11/09: Re: looking for FPGA pin header board
92199: 05/11/23: Re: Stupid reset question
92566: 05/12/01: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92644: 05/12/02: Re: Quick question, how do I supply +-5V?
92774: 05/12/06: Re: Job available... 2 projects
94107: 06/01/05: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94108: 06/01/05: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94167: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94569: 06/01/13: Re: Don't even get me started on lead,
95451: 06/01/23: Re: Virtex-4 BiDirectional Ports
97001: 06/02/14: Re: Xilinx HDLParsers:810 or HDLParsers:3329
97065: 06/02/15: Re: Xilinx HDLParsers:810 or HDLParsers:3329
97397: 06/02/21: Xilinx ISE 6.3 confusion with CPLD logic results
97450: 06/02/22: Re: Xilinx ISE 6.3 confusion with CPLD logic results
97992: 06/03/02: Re: Spartan 3 Expansion Board
98042: 06/03/03: Re: Spartan 3 Expansion Board
98594: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
101022: 06/04/24: Re: How to avoid this waring in ISE 8.1?
101036: 06/04/24: Re: How to avoid this waring in ISE 8.1?
101294: 06/04/28: Re: please help me out
101295: 06/04/28: Re: initializing array of registers in XST
101296: 06/04/28: Re: Development Platform for begginer
101458: 06/05/01: Re: design optimization
101462: 06/05/01: Re: Book Software for XC3190A?
101687: 06/05/04: Re: async. load line on shift register
101688: 06/05/04: =?utf-8?q?Re:_how_to_set_a_I/O_as_3-state_in_xilinx_FPGA=EF=BC=9F?=
102545: 06/05/17: Re: sending multiple char on RS232
103920: 06/06/14: Re: null waveform element and webpack
104311: 06/06/23: Re: Any eval SW comes with Spartan 3E Dev board from Xilinx/Digilent ?
104337: 06/06/24: Re: Spartan3 or 3E pins to GND
104590: 06/06/30: Re: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
104616: 06/07/01: Re: R: Pc and xcv200e doesn't talk,not exactly the right cable maybe..
105640: 06/07/27: OT (2nd try): do you get paid for your travel time?
105669: 06/07/28: Re: OT (2nd try): do you get paid for your travel time?
106134: 06/08/08: Re: FPGA : PCI-Xilinx Core, PC not booting
106623: 06/08/16: Re: XILINX XAPP694
106870: 06/08/21: Re: CPU design
109086: 06/09/20: Re: Unstable output pin?
110909: 06/10/25: OT: FPGA soft-core humor
110912: 06/10/25: Re: OT: FPGA soft-core humor
110924: 06/10/25: Re: OT: FPGA soft-core humor
113389: 06/12/12: Re: Virtex4 : cleaner signals?
113620: 06/12/18: Re: unpredictable FPGA behaviour
113702: 06/12/19: Re: Need book for verilog on xc9536?
113863: 06/12/26: Re: Impact with non-standard LPT base addresses
113867: 06/12/26: Re: Impact with non-standard LPT base addresses
114001: 07/01/02: Re: Strange JTAG TCK problems with Spartan XC3S400
114007: 07/01/02: Re: Surface mount ic's
114038: 07/01/03: Re: OT. Re: Surface mount ic's
114087: 07/01/04: Re: Surface mount ic's
114232: 07/01/08: Re: First Picture of Craignell Modules
114601: 07/01/20: Re: Beginner VHDL questions
115779: 07/02/20: Re: Selecting device in Project Properties : no XC2V1000?
115864: 07/02/22: Re: VHDL code for Generating registers
116628: 07/03/14: Re: sum of array
116970: 07/03/21: Re: CPLD erase??
117121: 07/03/23: Re: Custom IP ports to be used as GPIOs
117124: 07/03/23: Re: URGENT HELP NEEDED: LVDS
117833: 07/04/11: Re: FIFO newbie question
118088: 07/04/17: Re: Interfacing FPGA with TTL
118263: 07/04/20: Re: Clock signal FPGA XC95288xl144
118264: 07/04/20: Re: DARNAW! - PGA Style FPGA Module
118279: 07/04/21: Re: DARNAW! - PGA Style FPGA Module
118469: 07/04/27: Re: one extra slipway board from fccm
118723: 07/05/02: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
122256: 07/07/24: Re: 3 input adder in Spartan 3E
122299: 07/07/25: Re: Beginners question
122300: 07/07/25: Re: Altera or Xilinx
123031: 07/08/14: Re: Xilinx Spartan FPGA : Strange Errors
123814: 07/09/05: Re: warning 1780 shown while synthesis, in xilinx 6.3i
124327: 07/09/18: Re: Altera / Lattice / Xilinx CPLDs ?
124391: 07/09/20: Re: Is it possible for two wires to share the same FPGA pin?
124873: 07/10/09: Re: Starting FPGA
124874: 07/10/09: Re: Need suggestion on FPGA kit
124921: 07/10/10: Re: UK Supplier XILINX spartan 3 development board??
124988: 07/10/14: Re: R: Newbie,the simplest way to program an FPGA at home?
125293: 07/10/19: Re: LEDs, buttons and LCD
125392: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125513: 07/10/26: Re: Power supply filter capacitors
125716: 07/11/01: Re: Another way to handle floating inputs.
125838: 07/11/06: Re: not totally repulsive
125913: 07/11/08: Re: FIFO interface design
126257: 07/11/18: Re: Altera webpack for Linux?
126793: 07/12/02: Re: ISE WARNING Xst:647
126967: 07/12/07: Re: Drigmorn1 - The Cheapest FPGA Development Board???
127197: 07/12/13: Re: FPGA Board design basics
127562: 08/01/02: Re: Split Plane
127981: 08/01/11: Re: Is it possible to define an Integer so it could be incremented
128024: 08/01/13: Re: Virtex4 burn-in failure
128132: 08/01/16: Re: Basic FPGA question about Reset
128610: 08/01/31: Re: iru1209 regulator
128863: 08/02/07: Re: Modelsim Warning
128979: 08/02/12: Re: microblaze firmware + UART handshaking blues
129693: 08/03/03: Re: clock generation
129864: 08/03/07: Re: XC3S50-4VQ100C fpga chip
130342: 08/03/20: Modelsim XE III 6.x - huge fonts
130346: 08/03/20: Re: Modelsim XE III 6.x - huge fonts
130352: 08/03/20: Re: Modelsim XE III 6.x - huge fonts
130423: 08/03/23: Re: Modelsim XE III 6.x - huge fonts
130447: 08/03/24: Re: Modelsim XE III 6.x - huge fonts
130672: 08/03/29: Re: Newbies: Answer to "What is an FPGA?" in video
130712: 08/03/30: Re: Synthesisable Timer in VHDL
130772: 08/04/01: Re: Xilinx and Modelsim?
131130: 08/04/11: Re: case statements- verilog to vhdl
132087: 08/05/12: Re: Programming XCR3064xl - voltage at output stuck at 0
132118: 08/05/14: Re: xilinx beginner modelsim question
132633: 08/06/04: Re: xilinx and jtag
133047: 08/06/16: Re: CPLD beginner questions
133311: 08/06/24: Re: Linked Group for FPGAs & CPLDs
133822: 08/07/16: Re: Low cost solution to program Spartan 3AN DSP development board
133903: 08/07/18: Re: free of bugs
135163: 08/09/18: Re: Moving to Altera from Xilinx
136352: 08/11/12: Re: Connect XST board with PC through USB
137207: 09/01/02: Re: 7 Segment LED Display - BASYS board
137414: 09/01/14: Re: ttl compatible
137990: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first
138050: 09/02/04: Re: Antti-Brain issue 5 released
138246: 09/02/10: Re: pulser problem
138345: 09/02/16: Re: cpld 9572 xilinx
138356: 09/02/17: Re: Problem using external clock!!!!!
138451: 09/02/23: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
139861: 09/04/17: Re: Xilinx Impact cable not found
140035: 09/04/24: Re: FPGA evaluation board for SD/SDHC Host controller
140426: 09/05/13: Re: Connect two bidirectional pins in FPGA
142161: 09/07/27: OT? Something is wrong with this NG..
142172: 09/07/28: Re: OT? Something is wrong with this NG..
142439: 09/08/11: Re: Spartan-6 Boards - Your Wish List
143170: 09/09/23: Re: Xilinx XST and counter synthesis problem
143789: 09/10/26: Re: HI.. Help Needed Its Urgent
143809: 09/10/27: Re: HI.. Help Needed Its Urgent
144309: 09/11/25: Re: webpack crashed how do I get these things back?
149031: 10/09/22: Re: Xilinx dropping Modelsim XE
Dave R.:
30524: 01/04/12: Is this realistic?
Dave Rich:
132071: 08/05/12: Re: Breaking News ... Accellera Verification Working Group Forming
Dave Risler:
686: 95/02/06: Function Point Analysis
Dave Roberts:
91501: 05/11/07: Delay insertion in Xilinx Verilog
91511: 05/11/07: Re: Delay insertion in Xilinx Verilog
92509: 05/11/30: Xilinx timing constraint problem
92510: 05/11/30: Supplier of Xilinx XC2V1000 or 2V250?
92637: 05/12/02: Re: Xilinx timing constraint problem
Dave Smith:
Dave Storrar:
11579: 98/08/25: Re: PROM alternative
12166: 98/10/02: Re: Synthesis: Exemplar or Synopsys
12230: 98/10/06: Re: Synthesis: Exemplar or Synopsys
16939: 99/06/18: Re: Die size of XILINX fpga's
18298: 99/10/13: Re: GSR on ORCA FPGAs
19656: 00/01/07: Re: Lucent Orca designs
Dave Vanden Bout:
10181: 98/05/01: Re: [Q] Cheap Xilinx Proto Boards
11159: 98/07/21: Re: Wanted: CPLD Primer
13618: 98/12/13: Re: XESS FPGA Board?
17338: 99/07/21: Re: Xilinx/Synopsys License Problem
17345: 99/07/21: Re: Xilinx Foundation Beginner Question
17699: 99/08/24: Re: microcontroller vs FPGA
17871: 99/09/14: Re: free/demo/low cost verilog synthesis tools available?
17872: 99/09/14: Re: simple VHDL?
18063: 99/09/26: Re: Looking for substitute for XC17*** Xilinx Prom
18366: 99/10/19: Re: New to FPGA
18460: 99/10/25: Xilinx WebPACK tutorial
19186: 99/12/03: Re: Command line for FPGA Express
19197: 99/12/05: Re: Command line for FPGA Express
19202: 99/12/05: Re: hobbyist friendly pld?
19357: 99/12/15: Re: hobbyist friendly pld?
19488: 99/12/24: Re: Dumb question springing from a discussion about chess on a chip...
19498: 99/12/27: Re: How can I preset /prereset some Latches
19514: 99/12/28: Re: VGA controller in FPGA
19489: 99/12/24: Re: Dumb question springing from a discussion about chess on a ch
19515: 99/12/28: Re: VGA controller in FPGA
19881: 00/01/15: Re: FPGA + ethernet
19882: 00/01/15: Re: FPGA + ethernet
19901: 00/01/16: Re: Further to board
19902: 00/01/16: Re: Further to board
20182: 00/01/30: Re: Which FPGA to learn with?
20194: 00/01/31: Re: Which FPGA to learn with?
20245: 00/02/02: Re: Which FPGA to learn with?
20246: 00/02/02: Re: Which FPGA to learn with?
20252: 00/02/02: Re: XC9536 and Abel
20278: 00/02/03: Re: VHDL and Xilinx Books for beginners
20634: 00/02/16: Re: How to manage projects with Xilinx?
20680: 00/02/17: Re: How to manage projects with Xilinx?
21197: 00/03/09: Re: FPGA board
21231: 00/03/11: Re: Xilinx Foundation Series and FSM designs
21258: 00/03/14: Re: JTAG by parallel port
21543: 00/03/24: Re: FPGA openness
21767: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
21807: 00/04/01: Re: Adrian Thompson's and GA work on Xilinx
21839: 00/04/03: Re: Xilinx student edition, version 1.5
22202: 00/05/01: Re: Xilinx CPLD Make file
22203: 00/05/01: PR: XESS Introduces Low-Cost Triscend CSoC Development Kit
22455: 00/05/09: Re: HELP - what to choose?
22511: 00/05/10: Re: SpartanXL driving 5V CMOS input
22518: 00/05/10: Re: SpartanXL driving 5V CMOS input
22569: 00/05/12: Re: Do you know xilinx FPGAs well?
22766: 00/05/23: Re: Xilinx tools becoming "RentWare"
22928: 00/06/02: Re: Microprocessors in FPGA
23068: 00/06/12: Re: Xilinx Project manager 1.5
23489: 00/06/27: tutorial on configurable system-on-chip design is available
23680: 00/07/05: tutorial on configurable system-on-chip design is available
23839: 00/07/12: tutorial on configurable system-on-chip design is available
23896: 00/07/14: Re: FPGA Intro
23975: 00/07/19: tutorial on configurable system-on-chip design is available
24050: 00/07/24: Re: New Xilinx Student Edition
24082: 00/07/26: tutorial on configurable system-on-chip design is available
24174: 00/07/28: Re: FPGAExpress fe_shell and FSM encoding
24178: 00/07/28: Re: FPGAExpress fe_shell and FSM encoding
24186: 00/07/28: Re: alternatives to costly FPGA config proms ??
24284: 00/08/02: Re: 8251A USART
24308: 00/08/03: tutorial on configurable system-on-chip design is available
24336: 00/08/04: Re: XST?
24840: 00/08/20: tutorial on configurable system-on-chip design is available
24376: 00/08/05: Re: tutorial on configurable system-on-chip design is available
25984: 00/09/28: Re: FPGA development on the cheap?
25305: 00/09/05: Re: sowtware/programmer
26054: 00/10/02: Re: Xilinx XC2018 Design tools
26517: 00/10/18: Re: scripting with xilinx tools (foundation) ????
26608: 00/10/22: Re: SoC: Triscend vs Atmel FPSLIC
26630: 00/10/23: Re: SV: PCB's for re-casting the form factor of a QFP
26984: 00/11/06: Re: FPGA programming through XC18V00 eeprom
27549: 00/11/28: Re: hard or soft core for FPGA?
28003: 00/12/19: Re: FPGA and Board for Microprocessor Design?
28138: 00/12/22: Re: driving color VGA from FPGA ??
28158: 00/12/23: Re: Methodology
28225: 01/01/02: Re: Jedec to tms/tdi wiggles
28262: 01/01/04: Re: FPGA starter kit recommendations
28828: 01/01/25: Re: Advice on FPGA board.
29042: 01/02/03: Re: Help for a novice. Where to begin?
29415: 01/02/20: Re: UCF problem "- Could not find NET "
29428: 01/02/20: Re: Virtex E:Sample price
29705: 01/03/05: Re: Suggestions for I/O card
29761: 01/03/08: Re: Spartan II: POWERDOWN MODE WAS DELETED!!!
30022: 01/03/20: Re: XESS Prototyping boards - Is there a difference between...
30092: 01/03/22: Re: XS40 and XS95: Recommend books?
30386: 01/04/05: Re: How to combine bus in schematic
30437: 01/04/08: Re: xilinx price lists
30438: 01/04/08: Re: How to combine bus in schematic
30832: 01/04/30: Re: MORE Problems Setting Pins High!
30853: 01/05/01: Re: FPGA Prototyping Kits (Platforms)
31336: 01/05/19: Re: Any Triscend E5 (8051 core w/FPGA) Users ?
31699: 01/06/03: Re: Looking for free (try) xc4000e software ?
31742: 01/06/04: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31851: 01/06/06: Re: FPGA / starterkit / VHDL
32568: 01/06/30: Re: Newbee and FAQ
32705: 01/07/05: Re: 8031 microcontroller on FPGA development board :-(
33104: 01/07/17: Re: Working Design - Anyone
33143: 01/07/18: Re: Project implementation
33272: 01/07/21: Re: free VHDL and/or Verilog tools?
33624: 01/08/01: Re: Webpack Tutorials
33852: 01/08/06: Re: I NEED TO BUY A FPGA BOARD
34422: 01/08/23: Re: hardware damage to a Virtex or Spartan-II?
36090: 01/10/29: New WebPACK 4.1 tutorials
36198: 01/11/01: Re: Xilinx Foundation: Generation of EDIF from VHDL in Batch Mode
36867: 01/11/22: Re: Viewing generated VHDL
38483: 02/01/15: Re: RS232 on Atmel ATSTK40 board
38744: 02/01/23: Re: Missing IPAD, OPAD, etc. in Xilinx WebPACK Schematic Capture Library
39410: 02/02/08: Re: NT parallel port driver
39439: 02/02/09: Re: Help with getting started
40973: 02/03/19: Re: XESS parallel cable
40974: 02/03/19: Re: Webpack + XC4000
45815: 02/08/06: Re: Help Needed -- XESS Board question!
55214: 03/04/30: Re: DSP/FPGA board
55545: 03/05/12: Re: PacMan game in FPGA
62489: 03/10/30: ANNC: WebPACK 6.1 tutorials
62497: 03/10/30: Re: WebPACK 6.1 tutorials
62720: 03/11/05: Re: Prototyping board with 4+ MB SRAM?
66170: 04/02/13: Re: Sensible starter FPGA board
66172: 04/02/13: Re: xsa-50 board
68015: 04/03/24: Re: PULL-UPs on Xilinx-FPGA
68666: 04/04/13: Re: Layout problem
68736: 04/04/16: Re: Bus interface?
68877: 04/04/21: Re: calculate the number of logic gate in FPGA
68891: 04/04/21: Re: calculate the number of logic gate in FPGA
68946: 04/04/22: Re: ATAPI
69839: 04/05/21: Re: Old XCV50 FPGA and Ethernet
69859: 04/05/22: Re: FPGA Board with Flash Memory
70089: 04/06/02: Re: How can I get an output clock phased align with the input clock.
70147: 04/06/05: Re: IDE/ATA _device_ core availablility
70166: 04/06/07: Re: Good SDRAM Controller
71412: 04/07/17: Re: FPGA Development board with onboard Ethernet PHY
71475: 04/07/19: Re: fpga board with audio in/out (xilinx fpga) ?
71768: 04/07/29: Re: VHDL file equation
76026: 04/11/23: Re: Low cost million gate Spartan 3 board?
76210: 04/11/29: Re: VGA signal generator using CPLD
76211: 04/11/29: Re: FPGA design sample for Compact Flash peripheral
76558: 04/12/06: Re: xess boards
77124: 04/12/24: Re: VGA timing
77700: 05/01/14: Re: Questions from a beginner...
77755: 05/01/16: Re: What is the difference between ASIC and FPGA?.
78036: 05/01/23: Re: Google citation top 10 for FPGA
78041: 05/01/23: Re: Google citation top 10 for FPGA
79435: 05/02/19: Re: synthesizable vhdl coding style
80356: 05/03/04: Re: Displays an image in the XS Board RAM on a VGA monitor
80420: 05/03/05: Re: Displays an image in the XS Board RAM on a VGA monitor
80536: 05/03/08: Re: Xilinx / Altera TCLK termination (Pull up or down)
80798: 05/03/11: Re: Xilinx / Altera TCLK termination (Pull up or down)
81085: 05/03/17: Re: Beginning Xilinx FPGA Tutorials?
82034: 05/04/06: Re: Xilinx V2-Pro + Select Map programming
82093: 05/04/06: Re: Xilinx V2-Pro + Select Map programming
82264: 05/04/10: Re: EDK: Microblaze with XMdstub
84830: 05/05/29: Re: beginer
86867: 05/07/07: Re: PS/2 interface
117259: 07/03/27: Re: Tool to convert ISE project into makefile? (for Linux)
132616: 08/06/03: ANNC: ISE WebPACK 10.1i tutorial available
Dave Watkins:
36865: 01/11/22: Wanted - source for discontinued Coolrunner parts
Dave Wilson:
52037: 03/01/29: Reading External .txt files in Quartus II
52059: 03/01/30: Re: Reading External .txt files in Quartus II
52089: 03/01/31: Re: Reading External .txt files in Quartus II
53953: 03/03/28: Leonardo problem
63303: 03/11/19: Apex power calculator
139596: 09/04/06: Re: Modulo-10 counter
139621: 09/04/07: Re: Modulo-10 counter
139622: 09/04/07: Re: Modulo-10 counter
139626: 09/04/07: Re: Modulo-10 counter
139717: 09/04/10: Re: Noise in Stratix3?
139719: 09/04/10: Re: Noise in Stratix3?
140050: 09/04/25: Re: Noise in Stratix3?
DAVE WRIGHT:
33249: 01/07/20: Re: xilinx web pack problem
Dave {Reply Address in.sig}:
91120: 05/10/30: Re: Why are there two patents with same title
Dave, AD5TU:
134547: 08/08/17: Re: xilinx FPGA "program failed"
<dave.g4ugm@gmail.com>:
155095: 13/04/12: Programming the old Spartan S3E Sample Board
dave94024:
88161: 05/08/10: ASIC suggestions
88248: 05/08/12: Re: ASIC suggestions
88250: 05/08/12: Re: ASIC suggestions
88251: 05/08/12: Re: ASIC suggestions
88272: 05/08/13: Re: ASIC suggestions
<dave@aldec.com>:
9416: 98/03/11: Re: ModelSim, Active-VHDL simulators
<dave@axoninstruments.biz>:
137332: 09/01/08: Re: Digilent Nexys 2 Issue
137397: 09/01/14: Re: Digilent Nexys 2 Issue
137432: 09/01/16: Re: Digilent Nexys 2 Issue
<dave@embeddedcomputer.co.uk>:
138723: 09/03/05: Re: Digilent Nexys 2 Issue
<dave@x.com>:
136067: 08/10/29: Re: how to program virtex 4?
<Dave@x.com>:
136172: 08/11/04: Re: Tiny JTAG connector
136240: 08/11/07: Re: led programming
<dave_admin@my-deja.com>:
19863: 00/01/14: Please help : Translogic's .ini files
19916: 00/01/18: Please help : Translogic's .ini files
19997: 00/01/21: Re: Please help : Translogic's .ini files
20748: 00/02/20: Divider
20749: 00/02/20: Divider
22863: 00/05/29: VirtexE prototype board
23121: 00/06/14: FIFO design
23172: 00/06/16: Re: FIFO design
dave_baker_100@yahoo.co.uk:
83645: 05/05/04: Saturating an integer
83647: 05/05/04: Re: Saturating an integer
83649: 05/05/04: Re: Saturating an integer
83650: 05/05/04: Newbie VHDL/FPGA question
83684: 05/05/05: Re: Newbie VHDL/FPGA question
<dave_bernard@my-deja.com>:
22614: 00/05/13: Re: Prom
27040: 00/11/08: Re: Boundary Scan fundamentals
<daveau@verdon>:
1902: 95/09/18: Help needed-how to instantiate Xbloc component with synopsys
Daveb:
93131: 05/12/14: Mission critical & low core voltages
93135: 05/12/14: Re: Mission critical & low core voltages
93139: 05/12/14: Re: Mission critical & low core voltages
108420: 06/09/11: Problem with adding DCM to Spartan-3
112754: 06/11/28: Spartan3 Configuration Puzzler
112763: 06/11/28: Re: Spartan3 Configuration Puzzler
112816: 06/11/29: Re: Spartan3 Configuration Puzzler
120522: 07/06/08: PBGA FPGA in hi-rel application
126525: 07/11/26: Spare Spartan3's
137360: 09/01/11: Spare Spartan3's (XC3S200TQ144) available
<daveb@iinet.net.au>:
4141: 96/09/17: Re: Inaccrate Xilinx simulations ???
4222: 96/10/01: Re: Viewlogic 4.1 (DOS) mouse alternatives?
<daveb@iinet.net.au_spam_trap>:
5350: 97/02/10: Re: FREE CREDIT CARD NUMBER
DaveG:
36062: 01/10/27: Digital image input for simulation on Altera FPGA
davegail:
13765: 98/12/22: This topic is new to me, ANY ONLINE FPGA TUTORIALS?
davelye:
88922: 05/08/31: Hello A newbie to FPGA
davem:
122403: 07/07/26: Re: VCD file doesn't show anything in GtkWave
122648: 07/08/02: Re: VCD file doesn't show anything in GtkWave
122843: 07/08/08: Re: FPGA accelerator service
<davem@hbmltd.demon.co.uk>:
1812: 95/09/05: Re: FPGA to masked gate array conversion
2021: 95/10/03: Xilinx security
2068: 95/10/09: Re: Powerdown & Xilinx devices
DaveP:
12475: 98/10/13: Re: Schematic entry?
daver2:
111140: 06/10/30: Taking forever to synthesise (XILINX ISE 8.1i)
111157: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111158: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111204: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111205: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111209: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111222: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111226: 06/10/31: Re: Programming Virtex II Pro Eval Board
111464: 06/11/03: Re: Scientific Computing on FPGA
118771: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
147205: 10/04/18: Xilinx Virtex-4 Block RAM Initialisation missing
davew:
118788: 07/05/03: Use of "blocks" in Quartus design
118844: 07/05/04: Re: Use of "blocks" in Quartus design
124059: 07/09/11: Stratix III Memory usage efficiency
124116: 07/09/12: Re: Stratix III Memory usage efficiency
124150: 07/09/12: Re: Stratix III Memory usage efficiency
124320: 07/09/18: Verilog simple dual port memory with different input and output widths?
124511: 07/09/25: Re: Verilog simple dual port memory with different input and output widths?
152469: 11/08/27: Re: cheating Arria FPGA i/o count
152470: 11/08/27: Re: cheating Arria FPGA i/o count
153246: 12/01/16: Re: balancing IIR filter (after adding extra registers)
153249: 12/01/16: Re: balancing IIR filter (after adding extra registers)
153254: 12/01/18: Re: balancing IIR filter (after adding extra registers)
153255: 12/01/18: Re: balancing IIR filter (after adding extra registers)
153259: 12/01/19: Re: balancing IIR filter (after adding extra registers)
153306: 12/01/30: Re: Design Notation VHDL or Verilog?
davewang202:
125553: 07/10/28: Re: Changing refresh rate for DRAM while in operation?
<davewang@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE>:
15047: 99/03/04: Re: Selt-Timed circuit
15048: 99/03/04: Re: Selt-Timed circuit
15070: 99/03/05: Re: Selt-Timed circuit
<davewang@wam.umd.edu.delete.after.edu>:
7079: 97/07/29: Quick prototyping? Best solution?
<davezz9472@my-deja.com>:
18390: 99/10/21: Re: External Cloking of Altera MAX 7000S
david:
51256: 03/01/08: Re: Hi xilinx
95612: 06/01/24: undefined reference to `xilkernel_main'
109723: 06/10/04: logic analyzer signal tap 2 - writing data
109753: 06/10/05: Re: logic analyzer signal tap 2 - writing data
109871: 06/10/06: Re: logic analyzer signal tap 2 - writing data
110287: 06/10/13: Re: logic analyzer signal tap 2 - writing data
153296: 12/01/28: TCP/IP
David:
4920: 96/12/30: Re: I2C Bus Interface in FPGAs
15831: 99/04/15: Re: Allowed logic functions in Virtex LE
15830: 99/04/15: I NEED AN FAQ!!!!!!!!!!!! NOW!!!!!
22113: 00/04/25: Any free design of 80C186 ??
35126: 01/09/22: Analyse static timing for Xilinx FPGA
35134: 01/09/23: Re: Analyse static timing for Xilinx FPGA
36125: 01/10/30: Can anyone guide me in selecting an FPGA?
44490: 02/06/21: Self upgrading Data I/O programmers?
47469: 02/09/26: Looking for a dead Virtex
49938: 02/11/26: Re: Anybody know of vendors of PCI boards with FPGAs?
51176: 03/01/05: Re: BP programmer questions, prices, alternatives
51214: 03/01/07: Co-simulation of Spice and Vhdl
51235: 03/01/07: Re: Co-simulation of Spice and Vhdl
51241: 03/01/07: Re: Co-simulation of Spice and Vhdl
51277: 03/01/09: Student development board
51390: 03/01/12: filter coefficient multiplication in vhdl
51907: 03/01/25: Why so many pins?
51914: 03/01/25: Re: Why so many pins?
52109: 03/01/31: Re: How to set leonardo path in Quartus?
52124: 03/02/01: Analog display in modelsim
52191: 03/02/04: Project fits in Leonardo, not in maxplus?!?
52231: 03/02/04: DSP design in fpga - general guidelines please.
52788: 03/02/21: Lpm equivalent for Xilinx devices
52805: 03/02/22: Re: Lpm equivalent for Xilinx devices
53260: 03/03/08: Clocking a spartanIIE with a 5V signal?
53305: 03/03/10: Using divided clock
53321: 03/03/10: Re: Using divided clock
53765: 03/03/21: Xpower problems - can't load vcd
53790: 03/03/23: Re: Xpower problems - can't load vcd
54626: 03/04/14: Xilinx core generator: core speed?
54664: 03/04/15: Re: Xilinx core generator: core speed?
54699: 03/04/16: Basic components with Core generator?
57218: 03/06/25: Multirate system in fpga
57955: 03/07/10: Fpga design with multiple audio rate (44, 48khz ...)
57970: 03/07/10: Re: Fpga design with multiple audio rate (44, 48khz ...)
58001: 03/07/11: Re: Fpga design with multiple audio rate (44, 48khz ...)
58099: 03/07/14: Re: Fpga design with multiple audio rate (44, 48khz ...)
62266: 03/10/23: Searching for 802.11a phy IP
62304: 03/10/25: Searching for 802.11a/g implementations
62392: 03/10/28: Re: Searching for 802.11a/g implementations
71464: 04/07/19: IDE or ATA controler on a Fpga
71795: 04/07/30: Fpga eval. board with spdif receiver?
71914: 04/08/03: Can I use RocketIO to generate pulse edge with very high precision?
71942: 04/08/04: Re: Can I use RocketIO to generate pulse edge with very high precision?
72160: 04/08/10: Re: FAE Job opening
72161: 04/08/10: Re: Available: Open Source VHDL parser - for free
73948: 04/10/01: Removing set/reset logic for shift register (HDL ADVISOR )
74116: 04/10/04: Asynchronous reset timing problem
76152: 04/11/26: Re: 386 IP Core
77301: 05/01/04: Xilinx BlockRAM Memory initialization for ModelSim
77305: 05/01/04: Init BlockRAM for Modelsim
77452: 05/01/07: Re: San Jose job offer - need advice
77530: 05/01/10: Re: San Jose job offer - need advice
77690: 05/01/14: Re: Programming and copyright
77872: 05/01/19: Re: Comparison of LEON2, Microblaze and Openrisc processors
77878: 05/01/19: Re: Comparison of LEON2, Microblaze and Openrisc processors
79858: 05/02/25: Re: NiosII Vs MicroBlaze
79956: 05/02/26: Re: Fast 28x28 multiplier + adder in Virtex4
81947: 05/04/05: Re: Open PowerPC Core?
81955: 05/04/05: Re: Open PowerPC Core?
82041: 05/04/06: Re: ISA vs. patent/trademark
82054: 05/04/06: Re: Structural vs Behavioral
82123: 05/04/07: Re: ISA vs. patent/trademark
82562: 05/04/14: Re: Embedded MicroBlaze solution
82629: 05/04/15: Re: Flowcharts and diagrams
82684: 05/04/16: Xilinx tools on Linux
83292: 05/04/27: Re: *RANT* Ridiculous EDA software "user license agreements"?
83405: 05/04/29: Re: Cygwin & Nios II
83716: 05/05/05: Re: Does this group allow JobPostings?
83915: 05/05/09: Re: Altera: Maxplus rules!
83955: 05/05/10: Re: true dual port memory v/s simple dual port memory
84144: 05/05/13: Re: "Mine is bigger than yours..."
87789: 05/08/01: Re: Best Practices to Manage Complexity in Hardward/Software Design?
100306: 06/04/06: Re: Someone need to port LwIP to ll_temac core/wrapper?
100307: 06/04/06: Re: Problem with LwIP and MicroBlaze
100310: 06/04/06: Virtex-4 Gigabit Ethernet design
101559: 06/05/03: Re: Virtex-4 Gigabit Ethernet design
101560: 06/05/03: Re: Someone need to port LwIP to ll_temac core/wrapper?
104635: 06/07/03: Re: System Generator cc1 error
104779: 06/07/05: DDR Controller problems
104838: 06/07/07: Re: DDR Controller problems
104957: 06/07/10: Re: DDR Controller problems
105327: 06/07/20: tutorial searching
105380: 06/07/20: Re: tutorial searching
106729: 06/08/17: tcp/ip
106952: 06/08/22: uclinux on spartan-3e starter kit
107000: 06/08/23: Re: uclinux on spartan-3e starter kit
107380: 06/08/27: FSL read/write problems
107467: 06/08/28: Re: FSL read/write problems
107535: 06/08/29: Re: FSL read/write problems
110217: 06/10/12: Partial Reconfiguration using XUPV2P
111138: 06/10/30: Virtex-II Pro CRC Test Data
111144: 06/10/30: Re: Virtex-II Pro CRC Test Data
113127: 06/12/06: Remove DCM wrappers from EDK designs
113366: 06/12/11: Re: Partial reconfiguration
113386: 06/12/12: ISP interface
113533: 06/12/15: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
113739: 06/12/20: Manually creating a LUT in VHDL
113802: 06/12/22: Re: Manually creating a LUT in VHDL
114922: 07/01/26: Forcing a LUT to not be optimized
114945: 07/01/27: Re: Forcing a LUT to not be optimized
115860: 07/02/22: MicroBlaze and OPB block ram interface controller run at different frequency
115861: 07/02/22: MicroBlaze and OPB block ram interface controller run at different frequency
123768: 07/09/04: Actel Designer - Specifying multicycle path constraints (via .sdc file) when using synchronous clock enables
128676: 08/02/03: Re: Loading the design from Compact Flash...
128713: 08/02/04: Re: Loading the design from Compact Flash...
136013: 08/10/27: Re: linux usb-drivers: Cable connection failed.
136613: 08/11/25: Re: timer interrupt problem: microblaze
141053: 09/06/03: Re: Open source processors
155852: 13/10/01: Re: Video Framebuffer using Nexys2 (Spartan-3E)
David Hawke:
19278: 99/12/10: Re: EEPROM for spartan xl series FPGA?
20298: 00/02/04: Re: Xilinx Tools
20314: 00/02/04: Re: Xilinx Tools
20479: 00/02/11: Re: HELP ! Problems in mapping
20838: 00/02/23: Re: Installing Xilinx Foundation on PC
20890: 00/02/25: Re: Xilinx PCI pinout ?
20898: 00/02/25: Re: Foundation 2.1i device support?
20961: 00/03/01: Re: Xilinx Tools Vs Altera tools
20984: 00/03/02: Re: Xilinx Tools Vs Altera tools
21219: 00/03/10: Re: SpartanXL route and place
David A Hand:
22057: 00/04/17: Handshaking in Xilinx Foundation Express ???
22068: 00/04/17: Re: Handshaking in Xilinx Foundation Express ???
38545: 02/01/17: How to set PROM package in ISE 4.1 ?
52509: 03/02/12: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
David A Willmore:
3051: 96/03/21: What bus is a Xilinx XC1736DP SPROM?
David A. Baldwin:
14318: 99/01/25: Actel A1280CQFP Prototype Adapter board
David Abbott:
30863: 01/05/02: Re: Comparison of FPGA and DSP
30864: 01/05/02: Re: Comparison of FPGA and DSP
David Abramson:
5021: 97/01/14: Software available for distributing CAD applications across workstations
David Albert:
1612: 95/07/28: CUPL Expert?
David Antliff:
140646: 09/05/20: Re: Can we expect ISE Gui and makefile to produce identical bit
140771: 09/05/25: Re: Can we expect ISE Gui and makefile to produce identical bit
140772: 09/05/25: Re: Can we expect ISE Gui and makefile to produce identical bit
140773: 09/05/25: Re: Can we expect ISE Gui and makefile to produce identical bit
140816: 09/05/26: Re: Can we expect ISE Gui and makefile to produce identical bit
140819: 09/05/26: Re: Can we expect ISE Gui and makefile to produce identical bit
140864: 09/05/27: Re: Can we expect ISE Gui and makefile to produce identical bit
140898: 09/05/28: Re: Can we expect ISE Gui and makefile to produce identical bit
David Ashley:
106810: 06/08/20: Re: Hardware book like "Code Complete"?
107040: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107045: 06/08/24: Global signal conservation
107086: 06/08/24: Re: Global signal conservation
107087: 06/08/24: DDR controller on Spartan-3e 500
107089: 06/08/24: Re: USB PHYs and drivers that folks have used
107090: 06/08/24: Re: Global signal conservation
107094: 06/08/24: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107095: 06/08/24: Re: high level languages for synthesis
107109: 06/08/24: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107113: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107114: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107121: 06/08/24: Re: Global signal conservation
107161: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK
107162: 06/08/25: Re: Xilinx BRAMs question - help needed ..
107214: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK
107223: 06/08/25: Re: high level languages for synthesis
107224: 06/08/25: Re: fastest FPGA
107225: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK
107243: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK
107244: 06/08/25: Re: fastest FPGA
107246: 06/08/25: Re: high level languages for synthesis
107255: 06/08/25: Re: high level languages for synthesis
107274: 06/08/26: Re: fastest FPGA
108040: 06/09/04: Re: Please help me with (insert task here)
108114: 06/09/05: Re: linux 2.4 v 2.6 on xilinx
108130: 06/09/05: Re: FPGA multiplier
108131: 06/09/05: Re: FPGA multiplier
108282: 06/09/07: Re: Qestion about the ability of synthesis
108283: 06/09/07: Re: Qestion about the ability of synthesis
108285: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
108287: 06/09/07: Re: FPGA multiplier
108296: 06/09/07: ddr with multiple users
108307: 06/09/07: Re: ddr with multiple users
108344: 06/09/08: Re: ddr with multiple users
108345: 06/09/08: Re: microblaze programm doesn't fit into bram...
108348: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
108350: 06/09/08: Re: Performance Appraisals
108378: 06/09/10: Re: ddr with multiple users
108411: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant"
108412: 06/09/11: Re: ddr with multiple users
108415: 06/09/11: Re: Forth-CPU design
108449: 06/09/11: Re: ddr with multiple users
108450: 06/09/11: Re: VHDL or Verilog or SystemC?
108451: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant"
108469: 06/09/11: xilinx bram instantation template in vhdl?
108470: 06/09/11: Re: xilinx bram instantation template in vhdl?
108472: 06/09/11: Re: xilinx bram instantation template in vhdl?
108477: 06/09/11: Re: xilinx bram instantation template in vhdl?
108485: 06/09/11: Re: Linear Interploation Algorithms
108518: 06/09/12: Re: xilinx bram instantation template in vhdl?
108520: 06/09/12: Re: Xilkernel: Problem with mutex
108521: 06/09/12: Re: ddr with multiple users
108523: 06/09/12: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant"
108526: 06/09/12: Re: linux 2.4 v 2.6 on xilinx
108527: 06/09/12: Re: Xilkernel: Problem with mutex
108529: 06/09/12: Re: linux 2.4 v 2.6 on xilinx
108544: 06/09/12: Re: use of Barrel shifter IN ARM TDMI 9
108547: 06/09/12: Re: fastest FPGA
108548: 06/09/12: Re: ddr with multiple users
108554: 06/09/12: Re: fastest FPGA
108559: 06/09/12: Re: fastest FPGA
108586: 06/09/13: Re: fastest FPGA
108612: 06/09/13: Prefered ieee libraries?
108614: 06/09/13: Re: Spartan3E availability
108622: 06/09/13: Re: Prefered ieee libraries?
108623: 06/09/13: Re: downloading bitstream on FPGA
108624: 06/09/14: Re: Prefered ieee libraries?
108645: 06/09/14: Re: Prefered ieee libraries?
108648: 06/09/14: Re: downloading bitstream on FPGA
108649: 06/09/14: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
108728: 06/09/15: Re: upgrading firmware on stratix 2 without NIOS IDE
108745: 06/09/15: Re: upgrading firmware on stratix 2 without NIOS IDE
108801: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108870: 06/09/18: ddr clock issues
108879: 06/09/18: Re: ddr clock issues
108881: 06/09/18: Xilinx xapp802.pdf mistake?
108943: 06/09/19: Re: Xilinx xapp802.pdf mistake?
108946: 06/09/19: Re: ddr clock issues
108960: 06/09/19: Re: ddr clock issues
108966: 06/09/19: Re: VHDL oddity
108969: 06/09/19: Re: Buffering the critical path.
108977: 06/09/19: Re: ddr clock issues
108980: 06/09/19: Re: ddr clock issues - success
108981: 06/09/19: Re: ddr clock issues
108984: 06/09/19: Re: ddr clock issues - success
109007: 06/09/19: Re: What is the difference ?
109057: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109059: 06/09/20: Re: Unstable output pin?
109066: 06/09/20: Re: Buffering the critical path.
109081: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109083: 06/09/20: Re: ddr clock issues
109097: 06/09/20: Which soft core to use?
109119: 06/09/20: Re: Verification errors using Xilinx Spartan 3E board
109120: 06/09/20: Re: Profiling issue with EDK 7.1
109165: 06/09/21: Re: Which soft core to use?
109166: 06/09/21: Re: NIOS speed
109167: 06/09/21: Re: NIOS speed
109209: 06/09/21: Re: please tell me how to learn testbench?
109211: 06/09/21: Re: Spartan-3E USB for I/O?
109265: 06/09/22: Re: Xilinx OPB BFM simulation error with m_ABus signal
109307: 06/09/23: Re: edk 8.2 user needed
109323: 06/09/23: Re: X4000 bad configuration
109326: 06/09/23: Re: downloading bitstream on FPGA
109364: 06/09/25: Re: Translate fails in ISE 8.1
109392: 06/09/25: Re: An algorithm with Minimum vertex cover without considering its
109412: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its
109414: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109445: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109446: 06/09/26: Re: PERISHABLE PAPER RELATED TO FPGA!
109605: 06/09/30: Re: DDR RAM
109746: 06/10/04: Re: Just a matter of time
110032: 06/10/09: Re: FPGA to SRAM port interface
110061: 06/10/10: Re: FPGA to SRAM port interface
110063: 06/10/10: Re: FPGA to SRAM port interface
110077: 06/10/10: Re: EDK Bug
110081: 06/10/10: Re: FPGA to SRAM port interface
110367: 06/10/14: Re: DDR Address
110399: 06/10/14: Re: 75Mhz Spartan3e microblaze
110423: 06/10/15: SPAM - Re: Platform USB Cable schematic
110431: 06/10/15: Re: SPAM - Re: Platform USB Cable schematic
110678: 06/10/19: Re: Microblaze uclinux Kernel panic
110723: 06/10/20: Re: i486 FPGA replacement
110748: 06/10/20: Re: Code synthesizes to one FPGA but not to another?
110867: 06/10/24: Re: Microblaze uclinux Kernel panic
110896: 06/10/25: Re: Stream cipher
110953: 06/10/25: Re: Stream cipher
David Atkins:
5472: 97/02/19: Altera EPX 880
5636: 97/03/03: Re: JTAG config on ALTERA FLEX10K10: How?
7742: 97/10/09: Re: FPGA based CPU ideas, and novel extensions
7831: 97/10/20: Re: PROM for FLEX10K
David B. Thomas:
113627: 06/12/18: incremental compiles in quartus
David Badzinski:
4764: 96/12/12: Anyone tried a FFT in a FPGA?
David Baker:
5018: 97/01/13: ANNOUNCE 8051/8052 microcontroller model now available for FPGA
David Barcelo:
19880: 00/01/15: FPGA + ethernet
David Barr:
3357: 96/05/20: Re: is high input number mutliplxer inferrable?
David Barton:
1316: 95/05/31: Re: Display EDIF (EDIF -> ORCAD)
David Belohrad:
93174: 05/12/15: Re: Mission critical & low core voltages
David Betz:
48651: 02/10/22: Re: 6502 core available
David Binette:
157174: 14/10/27: XILINX PCIe read of slow device
157176: 14/10/27: Re: XILINX PCIe read of slow device
157180: 14/10/28: Re: XILINX PCIe read of slow device
157182: 14/10/28: Re: XILINX PCIe read of slow device
157187: 14/10/29: Re: XILINX PCIe read of slow device
157188: 14/10/29: Re: XILINX PCIe read of slow device
157189: 14/10/29: Re: XILINX PCIe read of slow device
157197: 14/10/30: Re: XILINX PCIe read of slow device
157215: 14/11/04: Re: XILINX PCIe read of slow device
David Binnie:
49449: 02/11/12: jedec
122688: 07/08/03: Re: camera module interface to FPGA
122957: 07/08/12: Re: How to locate the internal state machine in timing simulation
122979: 07/08/13: Re: New Xilinx forum.
125683: 07/10/31: Digilent V2P Board
126754: 07/11/30: Re: Using DDR RAM on XUP V2Pro board
126769: 07/12/01: Re: Using DDR RAM on XUP V2Pro board
129721: 08/03/03: Re: Random Number Generation in VHDL
130295: 08/03/19: Re: total cost for virtex II pro FPGA
DAVID BINNIE:
79814: 05/02/24: Re: FPGA board with best cost/CLB ratio?
David Bishop:
6759: 97/06/25: Re: Info on VHDL
13167: 98/11/18: Re: Xilinx COREgen and Leonardo troubles...
13168: 98/11/18: Re: Synthesizeablel fifo
21001: 00/03/02: Re: Xilinx Tools Vs Altera tools
22178: 00/04/28: Re: Instantiating and Compiling Altera LPM Macros with Synplify
22179: 00/04/28: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction
22180: 00/04/28: Re: How to Prevent theft of FPGA design
22181: 00/04/28: Re: Quartus "clock skew excedes data delay" error
22211: 00/05/02: Re: Instantiating and Compiling Altera LPM Macros with Synplify
22325: 00/05/05: Re: How to Prevent theft of FPGA design
22383: 00/05/07: Re: How to Prevent theft of FPGA design
22384: 00/05/07: Re: Virtex clock buffers
39854: 02/02/21: Re: CLKDLL x4 problem
39878: 02/02/21: Floating point synthesis
41111: 02/03/21: Re: A petition for Synplify's new fature (FPGA synthesis tool)
51906: 03/01/25: Re: A Request: VHDL Source of a 32bit Floating Point ALU
73625: 04/09/26: Re: VHDL inout used for non bidirectional uses
74068: 04/10/03: Re: Floating Point Powers and Logs?
74071: 04/10/03: Re: best way to perform multiplies in vhdl
113876: 06/12/27: Re: Matlab (.m) to VHDL
122999: 07/08/13: Re: Synthesizing fixed_pkg in ISE 9.2
123193: 07/08/19: Re: Synthesizing fixed_pkg in ISE 9.2
David Bokaie:
7196: 97/08/13: FPGA power consumption
david braendler:
16815: 99/06/11: Virtex Boards
17552: 99/08/10: Analog FPGA's
17843: 99/09/13: Relative Location attribute
18058: 99/09/27: Obtaining a Synopsys site ID
18087: 99/09/29: Re: Obtaining a Synopsys site ID
David Braendler:
9979: 98/04/21: HOT Works C++ Interface
12532: 98/10/15: Library of boards
12738: 98/10/27: Virtex PCI Board.
15429: 99/03/24: VHDL source code
David Brantley:
14134: 99/01/15: Re: 1-wire
David Bridgham:
159657: 17/01/26: Re: Anyone use 1's compliment or signed magnitude?
159894: 17/04/23: glitching AND gate
159897: 17/04/24: Re: glitching AND gate
159898: 17/04/24: Re: glitching AND gate
159906: 17/04/24: Re: glitching AND gate
159907: 17/04/24: Re: glitching AND gate
159908: 17/04/24: Re: glitching AND gate
159914: 17/04/25: Re: glitching AND gate
159915: 17/04/25: Re: glitching AND gate
159918: 17/04/27: Re: glitching AND gate
161023: 19/01/12: initializing a small array in Verilog
161045: 19/01/15: Re: initializing a small array in Verilog
David Brooks:
878: 95/03/19: Re: Free Viewlogic design kits?
1024: 95/04/18: Free Hardware
1152: 95/05/07: Re: Compression algo's for FPGA's
1468: 95/06/27: Re: Place-n-Route service
1670: 95/08/14: Re: Xilinx FPGAs ---> Xilinx EPLDs
1708: 95/08/18: Re: Timespecs in XNF format
1725: 95/08/21: Re: Email Address of Xilinx
90827: 05/10/22: Re: .dat to .bit
90893: 05/10/25: Re: 24 to 32 8-bit PWM outputs
David Brown:
10969: 98/07/07: Xilinx 4085 FPGA Board
18355: 99/10/18: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
22438: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22439: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22490: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22491: 00/05/10: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22712: 00/05/19: Re: XC1804 JTAG Programming Problems
23072: 00/06/13: Virtex IRDY and TRDY
37474: 01/12/12: chipscope "disable JTAG clock BUFG insertion"
40441: 02/03/07: Converting old Mach 5 project from DSL to VHDL
40506: 02/03/08: Re: Converting old Mach 5 project from DSL to VHDL
40575: 02/03/11: Newbie choosing a language - Verilog, VHDL, or ABEL
40638: 02/03/12: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
41335: 02/03/26: VCC and GND net warnings with ispDesignExpert
41859: 02/04/09: Command-line Verifying Verilog with Synplify
41885: 02/04/10: Re: Command-line Verifying Verilog with Synplify
46546: 02/09/03: Re: Hardware Code Morphing?
52690: 03/02/19: Should I choose Xilink or Altera for a small project
52732: 03/02/20: Re: Should I choose Xilink or Altera for a small project
52733: 03/02/20: Re: Should I choose Xilink or Altera for a small project
52734: 03/02/20: Re: Should I choose Xilink or Altera for a small project
52875: 03/02/25: Licencing for downloadable FPGA tools
52880: 03/02/25: Re: Licencing for downloadable FPGA tools
52886: 03/02/25: Re: Licencing for downloadable FPGA tools
52921: 03/02/26: Re: Licencing for downloadable FPGA tools
52922: 03/02/26: Re: Licencing for downloadable FPGA tools
57242: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57530: 03/07/02: Re: Cyclone vs Spartan-3
57622: 03/07/03: Re: Cyclone vs Spartan-3
57676: 03/07/03: Re: Cyclone vs Spartan-3
59242: 03/08/13: Re: Upgrading OS or WebPack
60126: 03/09/05: Re: Schematic simulation and then FPGA programming?
62128: 03/10/20: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
62257: 03/10/23: Re: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
64625: 04/01/09: Re: FLASH memory programming with Altera NIOS and same question for Xilinx
64796: 04/01/14: Re: nios-build debug option
64907: 04/01/16: Re: Can nios_gnupro support file system?
64917: 04/01/16: Re: Can nios_gnupro support file system?
65022: 04/01/19: Re: Can nios_gnupro support file system?
65439: 04/01/29: Re: FPGA basics
65923: 04/02/10: Re: Quartus II taking forever to compile
65999: 04/02/11: Re: [OT] Re: Quartus II taking forever to compile
66374: 04/02/18: Re: FFT on Virtex-II (Desperation Imminent)
66478: 04/02/20: Copyrights and licenses for NIOS design
66613: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
66619: 04/02/24: Re: Routing algorithm - help needed
66620: 04/02/24: Re: CardBus prototype in FPGA
66838: 04/02/27: Re: Free PCI-bridge in VHDL for Spartan-IIE
66839: 04/02/27: Re: Free PCI-bridge in VHDL for Spartan-IIE
66927: 04/03/01: Re: nios board, apex, tutorial doesn't work
66962: 04/03/02: Re: Mailing list for NIOS kit/Lancelot hackers
67182: 04/03/08: Re: Need to speed up Stratix compiles.
67184: 04/03/08: Re: Need to speed up Stratix compiles.
67185: 04/03/08: Re: Need to speed up Stratix compiles.
67463: 04/03/12: Re: Altera, Cyclone: pin not connected warning
67576: 04/03/15: Re: ANN: new Pulsonix version 3 PCB software released
67742: 04/03/18: Printing from Altera SOPC Builder
67783: 04/03/19: Re: Printing from Altera SOPC Builder
67942: 04/03/23: Re: Virtex-4
67986: 04/03/24: Re: Quartus with AMD64 processors?
68040: 04/03/25: Re: Quartus with AMD64 processors?
68044: 04/03/25: Re: Quartus with AMD64 processors?
68088: 04/03/26: Re: CPLD: assign pins first, or design content first?
68361: 04/04/02: Re: Can't do a single byte read in Nios?
68373: 04/04/02: Re: Can't do a single byte read in Nios?
69235: 04/05/01: Connecting a crystal to a Cyclone or Max PLD
69246: 04/05/03: Re: Connecting a crystal to a Cyclone or Max PLD
69346: 04/05/07: Re: Which board to buy? Status of open source tools?
69427: 04/05/11: Re: Which board to buy? Status of open source tools?
69474: 04/05/11: Re: Which board to buy? Status of open source tools?
69540: 04/05/13: Re: One issue about free hardware
69612: 04/05/15: Re: One issue about free hardware
69981: 04/05/26: Re: Nios II = Microblaze
69982: 04/05/26: Re: Nios II = Microblaze
70069: 04/06/01: Re: NIOS 2 memory limitations
70208: 04/06/09: Re: lancelot VGA daughter board for altera nios dev board
70279: 04/06/11: Re: Nios II really available ?
70383: 04/06/15: Re: >Math Skills = >Engineer ?
70391: 04/06/15: Re: >Math Skills = >Engineer ?
70516: 04/06/18: Nios II and eCos
70580: 04/06/21: Re: Linux.
72343: 04/08/16: NIOS II memory devices on tristate bridges
72412: 04/08/18: Nios II debugging with gdb
72452: 04/08/19: Re: NIOS II memory devices on tristate bridges
72460: 04/08/19: Re: Nios II debugging with gdb
72476: 04/08/20: Re: NIOS II memory devices on tristate bridges
72482: 04/08/20: Re: Nios II debugging with gdb
72521: 04/08/23: Re: NIOS II memory devices on tristate bridges
72637: 04/08/27: Re: Altera MAX II
74011: 04/10/02: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
72918: 04/09/08: Re: Quartus2 V4.1 SP1
72922: 04/09/08: Re: Quartus2 V4.1 SP1
73061: 04/09/13: Questions about clocks on the Cyclone Nios development board
73236: 04/09/16: Re: Twister + Lancelot
73636: 04/09/27: Re: embedded linux on FPGA?
74951: 04/10/22: Re: Anyone routing signals between balls in FBGA?
75026: 04/10/25: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
75148: 04/10/27: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74105: 04/10/04: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
74115: 04/10/04: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74157: 04/10/05: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74158: 04/10/05: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74159: 04/10/05: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74208: 04/10/06: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74220: 04/10/06: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74281: 04/10/07: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
74293: 04/10/07: Re: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
84445: 05/05/19: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board
85136: 05/06/06: Re: XP for NIOS2
85157: 05/06/06: Re: XP for NIOS2
85350: 05/06/08: Re: not clear about doing power estimation using xpower
85680: 05/06/13: Re: SPD interface(Serial presence detect)
85699: 05/06/14: Re: Gated clock question
85700: 05/06/14: Re: SPD interface(Serial presence detect)
85701: 05/06/14: Re: generating 90, 180 and 270 shifts
85714: 05/06/14: Re: Gated clock question
85715: 05/06/14: Re: Problem for xilinx!!!
85727: 05/06/14: Re: Where to buy a Xilinx XCR3384XL tq144 CPLD?
85743: 05/06/15: Re: Auto pipeline logic??
85855: 05/06/17: Re: uart / Nios2
85883: 05/06/17: Re: AbusivepPricing information in marketing publications
85890: 05/06/17: Re: AbusivepPricing information in marketing publications
86041: 05/06/21: Re: Design tools comparison between Xilinx, Altera and Lattice for
86216: 05/06/23: Re: Minimum allowed clock frequency for Nios 2 processor (Stratix
86492: 05/06/29: Re: Good FPGA for an encryptor
89444: 05/09/15: Re: Is a CPLD appropriate for this triple PWM application?
89479: 05/09/16: Re: Is a CPLD appropriate for this triple PWM application?
89550: 05/09/19: Re: Is a CPLD appropriate for this triple PWM application?
89634: 05/09/21: Re: Count "1" bit in bit stream
89883: 05/09/29: Re: Version Control Software
89911: 05/09/30: Re: Version Control Software
90729: 05/10/19: Re: MAC Architectures
91475: 05/11/07: Re: icarus verilog
92693: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92699: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92793: 05/12/07: Re: FPGA : Decimation Filter Implementation
93233: 05/12/16: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
95789: 06/01/26: Re: help:dual-edge flip-flop possible using Verilog?
96164: 06/01/31: Re: Remotely updating Altera FPGA configuration
96236: 06/02/01: Re: Xilinx Legal
96231: 06/02/01: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96229: 06/02/01: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
95387: 06/01/23: Re: OT:Shooting Ourselves in the Foot
95390: 06/01/23: Re: OT:Shooting Ourselves in the Foot
96545: 06/02/06: Re: BGA central ground matrix
96956: 06/02/14: Re: Altera RoHS Irony
97037: 06/02/15: Re: Altera RoHS Irony
97043: 06/02/15: Re: Altera RoHS Irony
97044: 06/02/15: Re: News from Embedded World in Nurnber
97093: 06/02/16: Re: Altera RoHS Irony
97753: 06/02/27: Re: miniuart
99055: 06/03/19: Re: using EDK with the gcc -g option...
99176: 06/03/21: Re: Urgent Help Needed!!!!!
101192: 06/04/27: Re: Async FPGA ~2GHz
101354: 06/04/29: Re: Spartan 3 documentation confusing...
101501: 06/05/02: Re: Spartan 3 documentation confusing...
101506: 06/05/02: Re: Quartus and source control
101557: 06/05/03: Re: Quartus and source control
102223: 06/05/12: Re: reverse engineering ?
102277: 06/05/13: Re: altera cyclone memory example
102370: 06/05/15: Re: Virtex 5 announced and sampling
102712: 06/05/19: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
104061: 06/06/18: Re: Time for a new "Largest FPGA with free tool support"?
104062: 06/06/18: Re: Time for a new "Largest FPGA with free tool support"?
104452: 06/06/27: Re: keys to the Kingdom
104470: 06/06/28: Re: keys to the Kingdom
104471: 06/06/28: Re: keys to the Kingdom
104479: 06/06/28: Re: keys to the Kingdom
104966: 06/07/11: Re: High-speed DAC/ADC with FPGA
107569: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
107592: 06/08/30: Re: placing addiional caps across existing caps to reduce noise
107683: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
108416: 06/09/11: Re: Forth-CPU design
109630: 06/10/02: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109973: 06/10/09: Re: Just a matter of time
110097: 06/10/11: Re: Quartus II 6.0: System clock has been set back
110471: 06/10/16: Re: echo $LM_LICENCE_FILE not working
110522: 06/10/17: Re: echo $LM_LICENCE_FILE not working
110963: 06/10/26: Re: Survey on Quartus SOPC/Nios-II
111559: 06/11/06: Re: Fastest ISE Compile PC?
115620: 07/02/15: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115656: 07/02/16: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
117043: 07/03/22: Re: softcore CPU tools
117115: 07/03/23: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
117183: 07/03/26: Re: Where is Open Source for FPGA development?
117187: 07/03/26: Re: Where is Open Source for FPGA development?
117915: 07/04/13: Re: Are there Quartus II Web Edition limitations?
118003: 07/04/16: Re: Are there Quartus II Web Edition limitations?
123940: 07/09/07: Re: high bandwitch ethernet communication
124034: 07/09/11: Re: Uses of Gray code in digital design
124101: 07/09/12: Re: Uses of Gray code in digital design
124102: 07/09/12: Re: Uses of Gray code in digital design
124165: 07/09/13: Re: Uses of Gray code in digital design
128935: 08/02/11: Re: microblaze firmware + UART handshaking blues
129089: 08/02/14: Re: microblaze firmware + UART handshaking blues
130056: 08/03/14: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
130161: 08/03/17: Re: ISE 9.2SP4 error
130177: 08/03/17: Re: ISE 9.2SP4 error
130482: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130510: 08/03/26: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130566: 08/03/27: Re: A Challenge for serialized processor design and implementation
130605: 08/03/28: Re: A Challenge for serialized processor design and implementation
130606: 08/03/28: Re: VHDL document generation utilities
130888: 08/04/04: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130959: 08/04/07: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130965: 08/04/07: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
131166: 08/04/14: Re: 64 bit WebPack
131195: 08/04/15: Re: 64 bit WebPack
132518: 08/05/29: Re: Are FPGAs headed toward a coarse granularity?
132538: 08/05/30: Re: Are FPGAs headed toward a coarse granularity?
132668: 08/06/05: Re: Xilinx vs Altera
132677: 08/06/05: Re: Xilinx vs Altera
132685: 08/06/05: Re: Xilinx vs Altera
132753: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132872: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from
132893: 08/06/10: Re: how to prevent timer code firmware running on Microblaze from
132929: 08/06/10: Re: how to prevent timer code firmware running on Microblaze from
134565: 08/08/19: Re: More work, less posts
134633: 08/08/22: Re: Workaround for installing EDK on Vista x64?
134738: 08/08/28: Re: Genode FPGA graphics project launched
134764: 08/08/29: Re: Genode FPGA graphics project launched
134766: 08/08/29: Re: Genode FPGA graphics project launched
134767: 08/08/29: Re: crazy patent
134790: 08/09/01: Re: Genode FPGA graphics project launched
134829: 08/09/03: Re: Open source licenses for hardware
134830: 08/09/03: Re: Quartus II priority 19 under Linux
134860: 08/09/04: Re: Open source licenses for hardware
134870: 08/09/04: Re: Open source licenses for hardware
134892: 08/09/05: Re: Open source licenses for hardware
134893: 08/09/05: Re: Quartus II priority 19 under Linux
136273: 08/11/08: Re: Linux on Microblaze
136289: 08/11/10: Re: Linux on Microblaze
136346: 08/11/12: Re: Linux on Microblaze
136437: 08/11/17: Re: How to generate downloadable Nios II cpu ?
136493: 08/11/19: Re: Linux on Microblaze
136588: 08/11/24: Re: opinion about various code generators
137718: 09/01/28: Re: What software do you use for PCB with FPGA ?
137731: 09/01/28: Re: What software do you use for PCB with FPGA ?
137767: 09/01/29: Re: What software do you use for PCB with FPGA ?
137953: 09/02/03: Re: Why the second flip-flop in Virtex-6?
138377: 09/02/18: Re: Suggestion on computer for synthesis and simulation of FPGA
138674: 09/03/04: Re: Lattice announces ECP3
138760: 09/03/09: Re: Lattice announces ECP3
138835: 09/03/12: Re: speeding hough tranformation in microblaze
138972: 09/03/17: Re: Zero operand CPUs
139798: 09/04/14: Re: Low-cost Altera FPGA roadmap
140205: 09/05/04: Re: High-speed signals crossing a split-ground
142557: 09/08/17: Re: Soft Processor IP core report
142561: 09/08/17: Re: Soft Processor IP core report
142644: 09/08/24: Re: Soft Processor IP core report
142781: 09/09/01: Re: Polynomial Function ...
142808: 09/09/02: Re: Polynomial Function ...
142835: 09/09/03: Re: Polynomial Function ...
143446: 09/10/12: Re: Implement ARM cores on a FPGA chip?
143451: 09/10/12: Re: Implement ARM cores on a FPGA chip?
143686: 09/10/21: Re: problem while receiving negative integer in microblaze
143702: 09/10/22: Re: Done pin won't go high
143740: 09/10/23: Re: problem while receiving negative integer in microblaze
143964: 09/11/05: Re: Cyclone IV announced
143969: 09/11/05: Re: Cyclone IV announced
144038: 09/11/09: Re: free software/open source projects and FPGA?
144477: 09/12/09: Re: A new approach to FPGA and PCB System Development Platform, Santa
144970: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
145261: 10/02/04: Re: Board layout for FPGA
145395: 10/02/08: Re: Board layout for FPGA
145863: 10/02/26: Re: Altera data sheets.
145865: 10/02/26: Re: Altera data sheets.
145872: 10/02/26: Re: Altera data sheets.
145907: 10/02/27: Re: Altera data sheets.
146701: 10/03/26: Re: baud rates etc
146702: 10/03/26: Re: result on hyperterminal is not displayed
147054: 10/04/12: Re: I'd rather switch than fight!
147055: 10/04/12: Re: I'd rather switch than fight!
147076: 10/04/13: Re: I'd rather switch than fight!
147094: 10/04/14: Re: I'd rather switch than fight!
147134: 10/04/15: Re: I'd rather switch than fight!
147143: 10/04/15: Re: I'd rather switch than fight!
147144: 10/04/15: Re: I'd rather switch than fight!
147160: 10/04/16: Re: I'd rather switch than fight!
147161: 10/04/16: Re: I'd rather switch than fight!
147162: 10/04/16: Re: I'd rather switch than fight!
147166: 10/04/16: Re: I'd rather switch than fight!
147394: 10/04/26: Re: Quartus II under Windows7?
147469: 10/04/28: Re: Quartus II under Windows7?
147505: 10/04/29: Re: xilinx arm finally announced
147530: 10/04/30: Re: Quartus II under Windows7?
147630: 10/05/10: Re: FPGA Compilation Time Windows vs Linux
148612: 10/08/06: Re: Vendor Tool Stability
148787: 10/08/24: Re: Text compression Huffman Encoder and Decoder
149522: 10/11/02: Re: [O.T.] Audio DAC as AWG (test source)?
149659: 10/11/15: Re: cool BGA pattern
149672: 10/11/16: Re: cool BGA pattern
149673: 10/11/16: Re: cool BGA pattern
149817: 10/11/25: Re: cool BGA pattern
149821: 10/11/25: Re: Synthesis/place and route with Solid-State Drives
149840: 10/11/26: Re: cool BGA pattern
149922: 10/12/02: Re: Brain Cramps...
149944: 10/12/03: Re: Brain Cramps...
149945: 10/12/03: Opinions on Lattice ECP3
149950: 10/12/03: Re: Opinions on Lattice ECP3
149956: 10/12/03: Re: Opinions on Lattice ECP3
149959: 10/12/03: Re: Opinions on Lattice ECP3
149990: 10/12/06: Re: Opinions on Lattice ECP3
149991: 10/12/06: Re: Opinions on Lattice ECP3
150035: 10/12/07: Re: Opinions on Lattice ECP3
150036: 10/12/07: Re: Linux on Microblaze
150051: 10/12/08: Re: Opinions on Lattice ECP3
150052: 10/12/08: Re: Linux on Microblaze
150471: 11/01/24: Re: Xilinx news
150505: 11/01/25: Re: Xilinx news
150507: 11/01/25: Re: Xilinx news, David Brown and ""Xenophobia"" (see H1b FRAUD!)
150509: 11/01/25: Re: Xilinx news
150579: 11/01/27: Re: Xilinx news
151658: 11/05/03: Re: help with a power pc processor based software
152382: 11/08/17: Re: extracting D from 1 / D*D
152513: 11/08/30: Re: A free lunch
152830: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152857: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152858: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152875: 11/10/29: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152882: 11/10/29: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152902: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152914: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
153035: 11/11/19: Re: Production Programming of Flash for FPGAs and MCUs
153563: 12/03/28: Re: FPGA communication with a PC (Windows)
153678: 12/04/16: Re: recomendation on a processor core
153680: 12/04/17: Re: recomendation on a processor core
154649: 12/12/11: Re: Where to move for an embedded software engineer.
154652: 12/12/12: Re: Where to move for an embedded software engineer.
154659: 12/12/13: Re: Where to move for an embedded software engineer.
154689: 12/12/17: Re: Where to move for an embedded software engineer.
154750: 13/01/04: Re: Which to learn: Verilog vs. VHDL?
154751: 13/01/04: Re: Chisel as alternative HDL
154756: 13/01/04: Re: Which to learn: Verilog vs. VHDL?
154775: 13/01/07: Re: Which to learn: Verilog vs. VHDL?
154776: 13/01/07: Re: Chisel as alternative HDL
154782: 13/01/08: Re: Chisel as alternative HDL
154783: 13/01/08: Re: Chisel as alternative HDL
154825: 13/01/16: Re: Chisel as alternative HDL
154833: 13/01/17: Re: Chisel as alternative HDL
155036: 13/04/02: FPGA for large HDMI switch
155043: 13/04/03: Re: MISC - Stack Based vs. Register Based
155059: 13/04/04: Re: FPGA for large HDMI switch
155092: 13/04/09: Re: FPGA for large HDMI switch
155111: 13/04/21: Re: FPGA for large HDMI switch
155113: 13/04/22: Re: FPGA for large HDMI switch
155115: 13/04/23: Re: FPGA for large HDMI switch
155131: 13/04/25: Re: Low cost and/or small size CPU in an FPGA
155190: 13/05/24: Re: Cubic Spline Interpolator
155277: 13/06/21: Re: New soft processor core paper publisher?
155290: 13/06/22: Re: New soft processor core paper publisher?
155308: 13/06/23: Re: New soft processor core paper publisher?
155309: 13/06/23: Re: New soft processor core paper publisher?
155310: 13/06/23: Re: New soft processor core paper publisher?
155323: 13/06/23: Re: New soft processor core paper publisher?
155377: 13/06/25: Re: New soft processor core paper publisher?
155481: 13/07/01: Re: New soft processor core paper publisher?
155491: 13/07/02: Re: New soft processor core paper publisher?
155828: 13/09/27: Re: Legal Issues Reproducing Old CPU
155830: 13/09/27: Re: Legal Issues Reproducing Old CPU
156202: 14/01/17: Re: Math is hard
156238: 14/01/21: Re: Math is hard
156249: 14/01/22: Re: Math is hard
156595: 14/05/07: Re: The USB FPGA?
156708: 14/06/06: Re: ECG signals Compression/Decompression
156710: 14/06/06: Re: ECG signals Compression/Decompression
156732: 14/06/09: Re: 22V10 programmer
156737: 14/06/10: Re: 22V10 programmer
156741: 14/06/10: Re: 22V10 programmer
157040: 14/09/05: Re: Know any good public FPGA projects to contribute to?
157235: 14/11/06: Re: practical experience with GPL IP core in commercial product
157332: 14/11/24: Re: Bypass Xilinx flexlm license check
157337: 14/11/24: Re: Bypass Xilinx flexlm license check
157402: 14/12/03: Re: Which Altera to buy?
157403: 14/12/03: Re: Which Altera to buy?
157409: 14/12/03: Re: Which Altera to buy?
157411: 14/12/03: Re: Which Altera to buy?
157543: 14/12/15: Re: Using FPGA to feed 80386
157574: 14/12/17: Re: Using FPGA to feed 80386
158099: 15/08/06: Re: Finally! A Completely Open Complete FPGA Toolchain
158111: 15/08/11: Re: Finally! A Completely Open Complete FPGA Toolchain
158113: 15/08/11: Re: Finally! A Completely Open Complete FPGA Toolchain
158115: 15/08/11: Re: Finally! A Completely Open Complete FPGA Toolchain
158302: 15/10/07: Re: Question about partial multiplication result in transposed FIR
158384: 15/10/26: Re: Question about partial multiplication result in transposed FIR
158584: 16/01/08: Re: Opinions, on this newfangled thing, please
158864: 16/05/13: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158867: 16/05/13: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158872: 16/05/13: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
159267: 16/09/18: Re: requirement for PC for VHDL design
159269: 16/09/18: Re: requirement for PC for VHDL design
159287: 16/09/23: Re: requirement for PC for VHDL design
159288: 16/09/23: Re: requirement for PC for VHDL design
159301: 16/09/27: Re: requirement for PC for VHDL design
159372: 16/10/17: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of
159378: 16/10/18: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of
159409: 16/10/25: Re: Free timing diagram drawing software
159418: 16/10/26: Re: Free timing diagram drawing software
159450: 16/11/15: Re: Mentor bought by Siemens
159458: 16/11/17: Re: Mentor bought by Siemens
159668: 17/01/27: Re: Anyone use 1's compliment or signed magnitude?
159669: 17/01/27: Re: Hardware floating point?
159673: 17/01/27: Re: Hardware floating point?
159681: 17/01/29: Re: Hardware floating point?
159806: 17/03/09: Re: Analog to digital converters
159931: 17/04/30: Re: RISC-V Support in FPGA
159949: 17/05/02: Re: RISC-V Support in FPGA
159962: 17/05/02: Re: RISC-V Support in FPGA
159988: 17/05/04: Re: RISC-V Support in FPGA
160149: 17/06/21: Re: VHDL or Verilog?
160160: 17/06/22: Re: VHDL or Verilog?
160185: 17/07/31: Re: sram
160325: 17/11/14: Re: grey code counters
160528: 18/03/16: Re: How to handle a data packet while calculating CRC.
160542: 18/03/19: Re: How to handle a data packet while calculating CRC.
160544: 18/03/20: Re: How to handle a data packet while calculating CRC.
160569: 18/04/15: Re: FPGA selection recommendation
160572: 18/04/16: Re: FPGA selection recommendation
160772: 18/11/26: Re: Need Information about Implementing of Modbus protocol in fpga
160774: 18/11/26: Re: Need Information about Implementing of Modbus protocol in fpga
160812: 18/11/29: Re: Periodically delayed clock
160814: 18/11/29: Re: Periodically delayed clock
160819: 18/11/29: Re: Periodically delayed clock
160824: 18/12/02: Re: Periodically delayed clock
160828: 18/12/02: Re: Periodically delayed clock
160840: 18/12/05: Re: How to make Altera-Modelsim free download version to work?
160846: 18/12/06: Re: How to make Altera-Modelsim free download version to work?
160913: 18/12/17: Re: Philips LA PM3585 disassembler software wanted
160915: 18/12/17: Re: Philips LA PM3585 disassembler software wanted
160917: 18/12/17: Re: Philips LA PM3585 disassembler software wanted
160921: 18/12/19: Re: Philips LA PM3585 disassembler software wanted
161113: 19/02/04: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161138: 19/02/04: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161147: 19/02/05: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161148: 19/02/05: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161155: 19/02/07: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161163: 19/02/08: Re: Altera Cyclone replacement
161217: 19/03/19: Re: Tiny CPUs for Slow Logic
161221: 19/03/19: Re: Tiny CPUs for Slow Logic
161235: 19/03/19: Re: Tiny CPUs for Slow Logic
161243: 19/03/20: Re: Tiny CPUs for Slow Logic
161259: 19/03/20: Re: Tiny CPUs for Slow Logic
161265: 19/03/20: Re: Tiny CPUs for Slow Logic
161267: 19/03/21: Re: Tiny CPUs for Slow Logic
161304: 19/03/25: Re: High-level synthesis - MyHDL?
161371: 19/06/13: Re: bare-metal ZYNQ
161397: 19/07/04: Re: Unique uses for the DSP48
161398: 19/07/04: Re: How do big compagnies use Verilog/VHDL for processor designs?
161402: 19/07/08: Re: Unique uses for the DSP48
161500: 19/11/11: Re: FPGA config sizes
161502: 19/11/11: Re: FPGA config sizes
161503: 19/11/11: Re: FPGA config sizes
161597: 20/01/05: Re: Optimizations, How Much and When?
161600: 20/01/05: Re: Optimizations, How Much and When?
161603: 20/01/06: Re: Optimizations, How Much and When?
161604: 20/01/06: Re: Optimizations, How Much and When?
161610: 20/01/08: Re: Displays - Apple Mac vs. IBM PC
161614: 20/01/09: Re: Displays - Apple Mac vs. IBM PC
161664: 20/02/18: Re: Code block in icestudio
161668: 20/02/20: Re: Code block in icestudio
David Buckley:
5858: 97/03/20: Re: Is this really possible?
6318: 97/05/14: Re: Desperate college students need help!!!
6806: 97/06/29: Re: APS-X84 - recommended?
51182: 03/01/05: Xilinx 5202 peripheral mode configuration problem
51371: 03/01/12: Re: Xilinx 5202 peripheral mode configuration problem
David C Hoffmeister:
674: 95/02/02: Configuring XC4000 with Xchecker/JTAG
David C. Hoffmeister:
7682: 97/10/02: High Speed FPGAs
12727: 98/10/26: 8B/10B Encoder Decoder
David C. Young:
543: 94/12/28: Virtual Computers ( a company ), location?
David Carne:
106189: 06/08/08: Spartan 3 StarterKit Weirdness
David Charles Hirschfield:
5063: 97/01/18: [Q] Xilinx FPGA Resources
5419: 97/02/14: Xilinx programming...
5420: 97/02/14: HELP: XC4000 download cable
David Chen:
123660: 07/08/31: How to add additional FSL interface to customized IP?
David Chhoeun:
6960: 97/07/16: Re: UTOPIA?
David Chiron:
6211: 97/04/28: data acquisition
David Clark:
3897: 96/08/15: Re: Technical Job posting ( and ads) not related to the newsgroup.
David Collier:
49134: 02/11/01: Using OrCAD to generate a Xilinx 9536 CPLD
51883: 03/01/24: Xilinx ise 51. how to do a nice simple simulation
63229: 03/11/18: PCI interface with attached PLD
65147: 04/01/21: Xilinx design process....
65595: 04/02/03: Altera programming
David Colson:
46504: 02/09/01: Re: problem configration spartan2 with prom.
77066: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77074: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77097: 04/12/22: Re: Using low-core-voltage devices in industrial applications
77924: 05/01/20: Re: decrease slew rate - Actel Libero
81118: 05/03/17: Stapl, Xilinx, Altera Jam, XCF02S and iMPACT
85827: 05/06/16: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
99407: 06/03/23: Re: JTAG programing specs for XC18V01 PROM
99409: 06/03/23: Memory leaks with ISE 8.1
100262: 06/04/05: Re: JTAG programing specs for XC18V01 PROM
David Cooprider:
69605: 04/05/14: Re: Looking for Synario 3.0 (Lattice)
David Corne:
2632: 96/01/16: CFP:CFP: Reading Workshops on Parallel Computing CFP:CFP
David Corredor:
75665: 04/11/11: Re: Problem with PLL ?
David Dart:
23971: 00/07/19: IP CORE, 8250 core with 16byte fifo which only uses 100CLB's
David de =?iso-8859-1?Q?Andr=E9s Mart=EDnez?=:
38690: 02/01/22: XSV800 video decoder (SAA7113) programming
David de Andrés:
40304: 02/03/05: Synthesizing with CORE Generator
40321: 02/03/05: Re: Synthesizing with CORE Generator
David de Andrés Martínez:
44176: 02/06/13: Virtex Readback
David Dea:
4291: 96/10/10: Re: ORCA 2C10A - RAM placement advice
David Decker:
3576: 96/06/30: sanity check for 100k gate DSP FPGA project (long)
4075: 96/09/09: Re: Help with XACT 6.0 ProSim Problem
4076: 96/09/09: Re: ORCA and Viewlogic - any good?
4077: 96/09/09: DSP capture tools
4160: 96/09/20: Re: OrCAD schematic based multiplier for XC4000 series
4172: 96/09/21: Re: Q: PLD vs. FPGA
4173: 96/09/21: Re: Q: PLD vs. FPGA
4161: 96/09/20: Re: OrCAD schematic based multiplier for XC4000 series
4224: 96/10/02: Re: Has anyone changed from ViewLogic to Foundation [Q]
4594: 96/11/19: MatLab is Great for DSP test vectors
5378: 97/02/12: Re: Random Number Generators with Xilinx FPGA xc4000 series
5379: 97/02/12: Re: Random Number Generators with Xilinx FPGA xc4000 series
7119: 97/08/02: Are 2 PCs better than One?
7149: 97/08/07: Re: Are 2 PCs better than One?
7234: 97/08/17: Re: Price of Serial EEPROM is Outrageous
8073: 97/11/14: Re: Digital PLL?
8349: 97/12/10: Re: gates
8948: 98/02/08: Re: VHDL vs schematics
9002: 98/02/13: Re: VHDL vs schematics
9027: 98/02/15: Re: VHDL vs schematics
9223: 98/03/03: Version Control for schematics?
9311: 98/03/06: Re: Version Control for schematics?
9625: 98/03/27: Re: Lowest POWER FPGAs???
10965: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
12378: 98/10/10: Re: Xilinx F1.5/FPGA Express wackiness
12480: 98/10/13: Re: FOCUS FOCUS FOCUS
12715: 98/10/24: Re: Xilinx F1.5/FPGA Express wackiness (& Floorplanner)
13211: 98/11/20: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13606: 98/12/11: Re: Need basic info on FPGA!
14785: 99/02/17: Re: Synplify resource usage report for Virtex devices
14911: 99/02/25: Re: FPGA/ASIC Design Teams Available
14918: 99/02/25: Re: Xilinx ABEL?
15049: 99/03/04: Re: Clock divider: 100MHz->40MHz
15255: 99/03/16: Re: How can I improve an adder?
15617: 99/04/03: Re: How to implement Matched Filter in FPGA?
15618: 99/04/03: Re: Does any one want to discuss about dynamic configuration?
15619: 99/04/03: Re: How to implement Matched Filter in FPGA?
16034: 99/04/29: Re: Timing Constraint
16051: 99/04/30: Re: High speed PLL inside FPGA
17325: 99/07/21: Re: Frequency multiplier in XC4000
David DOMINGUEZ:
43920: 02/06/06: Re: burning a design
David Dye:
4354: 96/10/18: Re: Xilinx xchecker.exe and Windows NT
5304: 97/02/05: Re: Back annotation under Workview Office/Xilinx...
6389: 97/05/20: Re: xilinx xblox with capture ver 7.00
8323: 97/12/08: Re: Xilinx 3000 Series (old software) to 4000 on New Software
17500: 99/08/02: Re: nuneric_std package in Foundation 1.5
20312: 00/02/04: Re: Spartan 2 & Foundation
20338: 00/02/06: Re: Spartan 2 & Foundation
20224: 00/02/01: Re: Xilinx Foundation 2.1: VHDL to MACRO error
28499: 01/01/15: Re: Looking for prototyping board
28943: 01/01/30: Re: LavaLogic Forge Complier
37617: 01/12/17: Re: Dual-port ram templates
39586: 02/02/13: Re: Xilinx synthesis tools
67480: 04/03/12: Re: very strange error
67653: 04/03/16: Re: Chipscope
67915: 04/03/22: Re: Xilinx map -timing through ise gui
71709: 04/07/28: Re: vhdl code : altera vs xilinx
75518: 04/11/08: Re: chipscope pro problem (par)
78768: 05/02/07: Re: WARNING:Xst:382 - Why so many?
78775: 05/02/07: Re: WARNING:Xst:382 - Why so many?
80995: 05/03/15: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
86150: 05/06/22: Re: Difficult in probing through chipscope
104872: 06/07/07: Re: Can I use all 18bits of a BlockRAM?
113031: 06/12/05: Re: Creating a single logical netlist...
David E. Wallace:
4022: 96/09/04: Re: INDUSTRY GADFLY: EDA Goes OJ
4078: 96/09/09: Re: INDUSTRY GADFLY: EDA Goes OJ
David E. Wheeler Jr.:
30: 94/07/29: Xilinx File formats
David Eadie:
36652: 01/11/14: Prototyping Board
David Empson:
27237: 00/11/17: Re: ANNOUNCE: Checksum and CRC Code/Article
David Emrich:
2885: 96/02/24: PCI models synthesized to FPGAs?
4302: 96/10/11: Re: VHDL for Xilinx designs?
4303: 96/10/11: Re: Xilinx Startup symbol instantiation in VHDL ... ?
4522: 96/11/08: Re: What is the fastest fpga for ...
4783: 96/12/13: Re: How to use Xilinx ?
4820: 96/12/17: Re: Exemplar's Leonardo on Linux
5106: 97/01/23: Re: Altera support better than Xilinx
18800: 99/11/17: Re: implementing TCP/IP on PLD
27398: 00/11/20: Re: Synthesizable VHDL
David Erstad:
5007: 97/01/11: Re: ASICs Vs. FPGA in Safety Critical Apps.
5038: 97/01/15: Re: ASICs Vs. FPGA in Safety Critical Apps.
David Evans:
1111: 95/05/01: Re: Need help about conference chip
2580: 96/01/05: Xilinx Power Estimation
8757: 98/01/23: Re: ALtera Devices.
David F. Leskowicz:
15780: 99/04/13: VCC Hotworks
David F. Skoll:
3456: 96/06/02: Re: LAST MINUTE DAC NOTES
18432: 99/10/24: Re: Announcing Free VHDL Simulator for Windows
David F. Spencer:
2986: 96/03/08: actel act2 ta161 library element
2987: 96/03/08: actel act2 ta161 library element
3026: 96/03/16: experience with Actel Act2 family
3307: 96/05/11: Re: Anyone use Orcad PLD tools ?
David Fejes:
138878: 09/03/13: Re: I2C EEPROM
139163: 09/03/22: Re: DVI in FPGA
139519: 09/04/02: delays in XC95144XL CPLD
139522: 09/04/02: Re: delays in XC95144XL CPLD
139557: 09/04/03: Re: delays in XC95144XL CPLD
140127: 09/04/29: prohibit global clock designation
140165: 09/05/01: Re: prohibit global clock designation
141408: 09/06/23: 10gbit phy interface
144811: 10/01/06: university platform cable
144859: 10/01/08: Re: university platform cable
145393: 10/02/08: different JTAG programming cables
David Feustel:
34653: 01/09/01: Re: FPGA : USB in an FPGA, has anyone done it before?
34826: 01/09/10: ModelSim Licensing SW Installation Opens Computer to Hacking?
36960: 01/11/27: URL for ordering Xilinx ise webpack 4.1i cdrom
David Findlay:
38384: 02/01/13: Homebrew computers using FPGA?
38399: 02/01/13: Re: Homebrew computers using FPGA?
38416: 02/01/14: Re: Homebrew computers using FPGA?
David Forbes:
25884: 00/09/24: Re: 20 bit to 64 bit bus conversion
26049: 00/10/01: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26658: 00/10/23: Re: How secure from pirates is a Quick Logic part ?
26801: 00/10/29: Re: Undergraduate PLD Studies
26894: 00/11/02: Re: Pwer supply for a XCV300. Recommendations please.
David Foulds:
27178: 00/11/13: Re: Leon processor core
David Fowler:
287: 94/10/12: Re: Xilinx configuration
David Fraser:
5354: 97/02/10: Re: FPGAs with internal Tri-state busses ?
David Frith:
19861: 00/01/14: Re: Lattice
21286: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
21287: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
39809: 02/02/20: Re: spartan2 clock input from LVPECL signals
41298: 02/03/25: Xilinx 4.2i not working on my design
41334: 02/03/26: Re: Xilinx 4.2i not working on my design
41392: 02/03/27: Re: Xilinx 4.2i not working on my design
42450: 02/04/24: Re: Xilinx 4.2i not working on my design
42711: 02/05/01: Re: SpartanIIE hold timing
47050: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
David Fura:
4598: 96/11/19: Re: The best timing diagram editor/simulator?
10203: 98/05/03: Re: Xilinx Foundation and Linux
David G Cole:
3108: 96/04/03: Does X-BLOX Work?
David G.:
37918: 01/12/25: Look for FPGA Starterkit
38188: 02/01/08: S-video -> VGA
38210: 02/01/09: Re: S-video -> VGA
David G. Horsman:
11657: 98/08/29: Re: New Evolutionary Electronics Book
11659: 98/08/29: Re: New Evolutionary Electronics Book
David G. Koontz:
5020: 97/01/13: Re: DES Keysearch by FPGA: $10,000 prize
14582: 99/02/04: Re: DES in VHDL for FPGAs
19020: 99/11/24: Re: VHDL vs. schematic entry
David G. Stork:
6589: 97/06/04: Summer Student Job
9473: 98/03/16: Summer job: Compiling for reconfigurable FPGA computing
David Gamboa:
49952: 02/11/26: Re: count based Frequency generator
david garnett:
18657: 99/11/05: AMCC 5933 Woes
21578: 00/03/25: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
23116: 00/06/14: Re: PCI for a fpga board
29276: 01/02/12: Re: double precision floating point arithmetic
29512: 01/02/24: Soldering and Unsoldering PQFP by hand ...
30189: 01/03/27: Powerup problems with XC9500XL
32165: 01/06/17: Re: Xilinx web site ?
32174: 01/06/18: Re: Xilinx web site ?
33695: 01/08/02: Re: Spartan II and asynchronous memory interface
33714: 01/08/02: Re: Spartan II and asynchronous memory interface
38368: 02/01/12: Re: speech recognition - active noise cancellation
David Geirsson:
90520: 05/10/15: 3.3v<->5V
David Gelbart:
71878: 04/08/03: Re: Best tool(s) for filter float->fixed->VHDL flow?
David Geng:
19493: 99/12/27: status during ISP
19544: 99/12/30: Re: status during ISP
David Gesswein:
1114: 95/05/01: Re: Viewlogic VHDL for Xilinx
1901: 95/09/18: Re: Is there a reprogramable XC17256D available?
1915: 95/09/19: Re: Fast FPGA's? (No XILINX PREP data)
2141: 95/10/19: Re: one-hot encoding for fsm's
5820: 97/03/18: Multiple clocks in Xilinx
15230: 99/03/15: Xilinx routing issue
16518: 99/05/26: Re: FPGA express : Schematic viewing options w/o Vista?
19369: 99/12/16: Re: hobbyist friendly pld?
29046: 01/02/03: Re: Encryption is supported in new Virtex II but.....
34281: 01/08/18: Re: does anyone have a datasheet for a 18P8 PAL
49238: 02/11/05: Xilinx HDL Bencher
52612: 03/02/16: Re: Xilinx CORDIC core v1.0 used to compute atan
62711: 03/11/05: Virtex II DCM & ZBT SRAM
62756: 03/11/06: Re: Virtex II DCM & ZBT SRAM
David Gibson:
3305: 96/05/11: Re: Anyone use Orcad PLD tools ?
David Gilchrist:
21313: 00/03/16: Re: Virtex DLL inoperability
23103: 00/06/14: Re: delay variation
23756: 00/07/07: Re: Virtex Demo Board
23720: 00/07/06: Re: Virtex Global Set Reset
27476: 00/11/23: XILINX Virtex SelectMAP configuration
david gilchrist:
20241: 00/02/02: Re: Virtex boards
20590: 00/02/15: Re: Virtex DLL inoperability
David Grugett:
22245: 00/05/02: Free CPLD SW at Lattice Seminar
David Guyard:
10872: 98/06/26: Price of Altera development software platform for Windows NT
12679: 98/10/23: VME address decoder and IRQ handler using a xilinx FPGA ?
David H Eby;627-2949;39-750;tekig6.PEN:
39: 94/08/02: Re: Welcome new XILINX users
David Hand:
127168: 07/12/13: How do you initialize Xilinx ISOCM memory using DCR interface
127207: 07/12/14: Re: How do you initialize Xilinx ISOCM memory using DCR interface
127277: 07/12/16: Re: How do you initialize Xilinx ISOCM memory using DCR interface
David Harper:
6237: 97/05/01: Re: ISP CPLD from AMD or Cypress???
David Hart:
58895: 03/08/04: Re: beginner
61162: 03/09/29: Re: development-tools under linux for altera excalibur
David Hawke:
13686: 98/12/18: Re: Xilinx Foundation vs. Altera Max Plus II
14061: 99/01/11: Xilinx Field Applications Engineer - Vacancy
16460: 99/05/24: Re: IOB tristate register in Xilinx XLA devices
16708: 99/06/03: Re: XILINX/ALTERA compatibility
16760: 99/06/07: Re: XILINX/ALTERA compatibility
23250: 00/06/19: Re: XILINX RAM Useless
27828: 00/12/11: Re: fpga: 32 bit parity generation in 4 ns for virtexE
28035: 00/12/19: Re: Question about Xilinx pins at high-frequency
28079: 00/12/20: Re: Question about Xilinx pins at high-frequency
28081: 00/12/20: Re: Question about Xilinx pins at high-frequency
28125: 00/12/21: Re: Question about Xilinx pins at high-frequency
28486: 01/01/15: Re: JTAG configuration fails with XC95144XL
28918: 01/01/29: Re: Foundation - Source Constraints
29312: 01/02/13: Re: Need help using bitgen
31294: 01/05/17: Re: Ideas for Faster XILINX compilations ?
32113: 01/06/14: Re: Xilinx Coolrunner 100% routable - but the tools aren't
34103: 01/08/14: Re: constaining dll stuff problem
37124: 01/11/30: Re: Ballynuey 2 Hostsoftware
37491: 01/12/12: Re: chipscope "disable JTAG clock BUFG insertion"
37716: 01/12/19: Re: Kindergarten Stuff
37720: 01/12/19: Re: Kindergarten Stuff
37771: 01/12/20: Re: Kindergarten Stuff
39653: 02/02/15: Re: Xilinx XC2V6000 - cannot get anything out of jtag port
39662: 02/02/15: Re: Thingy has the property IOB=TRUE
39752: 02/02/18: Re: Timing constraints
39763: 02/02/19: Re: "DONT TOUCH" with Xilinx XST?
39764: 02/02/19: Re: Some problem initializing a RAMB4S1
39773: 02/02/19: Re: Coolrunner and ISP
39806: 02/02/20: Re: Virtex II multiplier pipeline
40101: 02/02/27: Re: Spartan 2E JTAG
40180: 02/03/01: Re: Altera FPGAs
40263: 02/03/04: Re: Constraining help required for clk_enable
40264: 02/03/04: Re: Other 2 constraining how to questions
40307: 02/03/05: Re: Altera FPGAs
40308: 02/03/05: Re: Constraining help required for clk_enable
40641: 02/03/12: Re: FPGA download fails
42525: 02/04/26: Re: Maximum Usage in a Virtex FPGA
42526: 02/04/26: Re: Xilinx XC2S150 PQ208 slave parallel mode for flash download program
42528: 02/04/26: Re: Changing ROM contents
42932: 02/05/07: Re: Xilinx 2GB limit... something has to be done
49184: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
49939: 02/11/26: Re: Help: Virtex-II Pro eval.brd for System Generator
50036: 02/11/29: Re: What HW/SW do I need to build a PowerPC system on Vertex II Pro?
50039: 02/11/29: Re: programmable FSM
50252: 02/12/06: Re: 285MHz multipliers
54371: 03/04/09: Re: Xilinx Impact and USB/LPT ports
David Hearn:
109226: 06/09/22: Re: Dell Laptop for Embedded Work
109227: 06/09/22: Re: Dell Laptop for Embedded Work
109228: 06/09/22: Re: Dell Laptop for Embedded Work
David Heller:
16608: 99/05/30: Call for Papers/Articles
17157: 99/07/05: A better way to access this newsgroup
David Hinterberger:
2151: 95/10/20: Re: Chip Express Expreiences Wanted
David Hobarth:
5124: 97/01/25: Processorless FPGA computer help
david holmes:
3246: 96/05/02: Re: Mr. Holmes D.
5554: 97/02/24: Re: Q: Xilinx PPR Strategy Tips?
6095: 97/04/11: Cisco, getting tired of SPAM
6144: 97/04/17: Re: Xilinx 4KE's and SBUS
6239: 97/05/01: Re: Viewlogic- PUSH VHDL
David Holmes:
1046: 95/04/20: Re: Exemplar to Powerview
3387: 96/05/23: Re: impossible for Synthesizer to optimize FSM??!
3512: 96/06/12: Re: Xilinx 4013E and PCI
David Horner:
47437: 02/09/25: FPGA programming via microcontroller
David Hough:
756: 95/02/23: Re: Newsgroup for Micro Controllers
David I.Roach:
442: 94/11/17: Looking for VHDL & VIEWLOGIC FPGA Experts/Consult
David J Starr:
1343: 95/06/03: Re: Latch up in Xilinx 3000 Series FPGA's. Part smokes & smells bad.
1318: 95/06/01: Latch up in Xilinx 3000 Series FPGA's. Part smokes & smells bad.
1430: 95/06/22: Xilinx PLDMAP usage. Pro's and Cons?
1452: 95/06/23: Re: Xilinx PLDMAP usage. Pro's and Cons?
1490: 95/06/29: Re: Xilinx PLDMAP usage. Pro's and Cons?
2332: 95/11/21: Re: Xilinx XACT Windows Version
2403: 95/11/30: Re: Xilinx XACT Windows Version
2406: 95/12/01: Re: Xilinx XACT Windows Version
David J. Matthews:
3655: 96/07/09: Xilinx Xc4000E Questions
4032: 96/09/04: Re: Generic FPGA toolkits for PC
4033: 96/09/04: Re: speed up Xilinx P & R
David J. Starr:
4963: 97/01/05: Re: I2C Bus Interface in FPGAs
David Jacobowitz:
20684: 00/02/17: Re: Looking for a small, fast CPU core for FPGA
David Jacobson:
5356: 97/02/10: Re: DES Challenge
David Johnston:
14344: 99/01/26: Re: Hysteresis on PLD Clock Inputs
David Jones:
480: 94/11/30: Re: ASIC emulation (Quickturn, etc.)
20273: 00/02/03: Re: Renoir problem: several engineers sharing a common setup?
20324: 00/02/05: Re: Conditional compilation in VHDL?
51884: 03/01/24: Re: AES(Rijindal) CTR with CBC MAC
67047: 04/03/04: Re: Xilinx Webpack 6.2 and Verilog `define ?
David Joseph Bonnici:
70157: 04/06/06: Where is my Digital Up Convertor in Logicore ??!! :)
70220: 04/06/09: Digital Clock Manager (DCM) Question
David Kallberg:
72195: 04/08/11: Re: How important are software tools while choosing FPGA
72196: 04/08/11: Re: Impact running on wine?
72247: 04/08/12: Re: How important are software tools while choosing FPGA
72248: 04/08/12: Re: Impact running on wine?
74291: 04/10/07: Synplify on Fedora C2
74339: 04/10/08: Re: Synplify on Fedora C2
80768: 05/03/11: Call for FPGAworld 2005
David Kanter:
77290: 05/01/03: Large open source FPGAs?
77295: 05/01/03: Re: Large open source FPGAs?
105486: 06/07/24: Re: Hardware book like "Code Complete"?
David Karchmer:
67777: 04/03/18: Re: Logiclock TCL flow for Quartus II
67831: 04/03/19: Re: Logiclock TCL flow for Quartus II
68407: 04/04/02: Re: AHDL, VERILOG or VHDL??
68710: 04/04/14: Re: Writing PCI constraints in Altera
David Kelly:
103469: 06/06/02: Re: Adding a USB interface to Linksys WRT54G wifi router
118296: 07/04/23: Re: FPGA Newbie
David Kessner:
4863: 96/12/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
12817: 98/10/30: Re: New free FPGA CPU
12823: 98/10/30: Re: New free FPGA CPU
14559: 99/02/04: Re: VHDL problem (Xilinx-problem)
14685: 99/02/11: Re: Xilinx de-compiler
15561: 99/03/30: Re: Info about FPGA/PLD
15750: 99/04/12: Re: FPGA vs CPLD? Any Experts out there?
17476: 99/07/30: Re: Semi-deterministic behaviour in FPGA's
17563: 99/08/10: Re: Emulating a transputer on FPGA
17579: 99/08/11: Re: Emulating a transputer on FPGA
17659: 99/08/19: New 6502 and DES cores available.
17677: 99/08/23: Re: synthesis comparion between Synplify and FPGA express
17806: 99/09/06: Re: synthesis comparion between Synplify and FPGA express
17825: 99/09/08: Re: synthesis comparion between Synplify and FPGA express
17884: 99/09/15: Re: synthesis comparion between Synplify and FPGA express
17788: 99/09/03: Re: FreeDES and Free6502 Comments
17790: 99/09/03: Re: FreeDES and Free6502 Comments
19594: 00/01/03: Re: Using internal RAM in Altera Flex 10KE
20419: 00/02/09: Re: launching a FPGA cores start-up
21743: 00/03/30: Re: Memory cores
22298: 00/05/04: Re: How to Prevent theft of FPGA design
22303: 00/05/04: Re: How to Prevent theft of FPGA design
22307: 00/05/04: Re: How to Prevent theft of FPGA design
22310: 00/05/04: Re: How to Prevent theft of FPGA design
22348: 00/05/05: Re: How to Prevent theft of FPGA design
22400: 00/05/08: Re: How to Prevent theft of FPGA design
23139: 00/06/15: Re: FIFO design
23150: 00/06/15: Re: PWM
24352: 00/08/04: Re: Who needs all those printed ac parameters?
24413: 00/08/07: Re: Help! Troubles using async FIFO cores in Virtex
24981: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
24992: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25001: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25008: 00/08/23: Re: run time doubled with Xilinx 3.1i upgrade
25028: 00/08/24: Re: run time doubled with Xilinx 3.1i upgrade
25162: 00/08/29: Re: run time doubled with Xilinx 3.1i upgrade
25482: 00/09/12: Re: hardware compatibility and patent infringement
25578: 00/09/14: Re: hardware compatibility and patent infringement
25579: 00/09/14: Re: hardware compatibility and patent infringement
David Kinsell:
35516: 01/10/09: Re: Xilinx: JTAG parallel connection problem
53129: 03/03/04: Re: Decoupling Capacitor for CPLD
54015: 03/03/31: Re: Pin failure detection
55436: 03/05/08: Re: flash-disk
56314: 03/06/03: Re: Xilinx Spartan download with Parallel III cable
56329: 03/06/03: Re: Xilinx Spartan download with Parallel III cable
56374: 03/06/04: Re: Xilinx Spartan download with Parallel III cable
60164: 03/09/06: Re: Parallel Cable III Problems
62922: 03/11/11: Re: BGA packages in high vibration environments
65516: 04/01/31: Re: Xilinx JTAG download under Linux (urgent)
66882: 04/02/28: Re: Spartan 3 / XCF02S JTAG problem
David Knell:
10409: 98/05/17: XABEL problem
10441: 98/05/19: Re: XABEL problem
david kong:
73673: 04/09/27: has anyone tried implementing Serpent?
David Kramer:
92279: 05/11/25: Partial Reconfiguration Problems
119198: 07/05/15: Re: bus macros for partial reconfiguration of virtex2pro?
David L. Jones:
34242: 01/08/17: Re: star-wars ascii-animation:)
87993: 05/08/04: Re: System Engineering in the R/D World
93055: 05/12/13: Re: How can I surpress noise in an ADC board?
121894: 07/07/14: Re: highly-parallel highspeed connection between two FPGA boards
131296: 08/04/18: Re: Survey: FPGA PCB layout
131608: 08/04/25: Re: Survey: FPGA PCB layout
131945: 08/05/08: Re: ANNC: FPGA Design Software Webcast
147914: 10/06/02: Re: Graphical User Interface project on Spartan-3 FPGA
151465: 11/04/11: Re: Altium Limited closing up shop - Altium Designer discontinued
151467: 11/04/11: Re: Altium Limited closing up shop - Altium Designer discontinued
151468: 11/04/11: Re: Altium Limited closing up shop - Altium Designer discontinued
David L. Pearson:
11733: 98/09/04: Re: CPLD/FPGA software
11732: 98/09/04: Re: Wait statements and while loops
David Lamb:
40554: 02/03/09: Audio project with an FPGA?
41168: 02/03/21: Working modulo exponent routine?
59400: 03/08/18: DDFS question
59508: 03/08/20: DCM vs state machine
59509: 03/08/20: Re: DCM vs state machine
59540: 03/08/21: Re: DCM vs state machine
59557: 03/08/21: Converstion from foundation4 to ISE 5.2
59793: 03/08/28: Selecting between two clock signals
59800: 03/08/28: DCM divide/phase problem
60013: 03/09/03: Re: Selecting between two clock signals
60014: 03/09/03: ISE 5.2 constraint file problem
60015: 03/09/03: Re: ISE 5.2 constraint file problem
david lamb:
52073: 03/01/30: How to set leonardo path in Quartus?
david langmann:
16391: 99/05/20: Re: Xilinx M1.5 Crash
David Langmann:
14958: 99/02/27: Foundation V1.5 Crash
16499: 99/05/25: Beginner's Virtex pinout Question
33917: 01/08/08: Re: I NEED TO BUY A FPGA BOARD
37518: 01/12/13: Re: FPGA development board
44734: 02/06/28: Problem: Designing for older FPGAs
David Lanza:
719: 95/02/16: Re: Synopsys FPGA Compiler
1026: 95/04/18: Re: PPR problem
1113: 95/05/01: Re: Viewlogic VHDL for Xilinx
1447: 95/06/23: Re: The "InOut" Port mode in the Xilinx FPGA
1740: 95/08/22: Re: FPGAs with embedded RAM
David Lawrence Hoenig:
5669: 97/03/05: Opinions on Cypress/PCI?
David le Comte:
640: 95/01/25: Re: NeoCAD Experience
854: 95/03/14: Protel now connects to Xilinx
David Lin:
10956: 98/07/07: Where to find gate-count information on some implementations?
david lindauer:
25586: 00/09/14: Re: hardware compatibility and patent infringement
David M. Palmer:
56247: 03/06/01: Re: Difficulty in getting the interconnect power
56507: 03/06/06: Re: Xilinx FFT Core Problems
95300: 06/01/22: Re: OT:Shooting Ourselves in the Foot
100674: 06/04/15: Re: Counting bits
101486: 06/05/01: Re: design optimization
101796: 06/05/06: Re: Spartan 3e starter kit & Multimedia
101961: 06/05/08: Re: Spartan 3e starter kit & Multimedia
102057: 06/05/10: Re: Spartan 3e starter kit & Multimedia
102058: 06/05/10: Re: Xilinx 3s8000?
106344: 06/08/11: Gaisler on a Spartan 3E Starter Kit?
106369: 06/08/12: Re: Gaisler on a Spartan 3E Starter Kit?
106470: 06/08/13: Re: Gaisler on a Spartan 3E Starter Kit?
106591: 06/08/15: Re: Gaisler on a Spartan 3E Starter Kit?
106783: 06/08/18: Re: FFT on an FPGA
106794: 06/08/19: Re: FFT on an FPGA
106838: 06/08/20: Re: CPU design
107769: 06/08/31: Re: spartan 3e starter kit usb cable
110634: 06/10/18: Re: Cheapest FPGA board to study VHDL on
110637: 06/10/19: Re: buying xilinx spartan 3E kit just for EDK ?
113566: 06/12/16: Re: Xilins ISE Re-Creating Projects
113947: 06/12/29: Re: FPGA workstation - should I wait for Window Vista?
117990: 07/04/16: Re: Pin Count requirements with MICO32
118126: 07/04/18: Analog FPGAs: how fast?
118272: 07/04/21: Re: Summer with fpgas
118502: 07/04/28: Re: Image compression on FPGA
119040: 07/05/10: Re: Xilinx software quality - how low can it go ?!
122164: 07/07/21: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
134808: 08/09/01: Re: how to built a CCD camera + FPGA ???
143603: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
147734: 10/05/19: Re: sensor-FPGA-DSP image processing
David M. Zar:
1649: 95/08/10: Re: external connections for efficient internal routing
2104: 95/10/15: Re: Problems With Xilinx Software under Solaris 2.4
David Mauro:
1978: 95/09/27: XACT <-> Orcad Interface
2052: 95/10/06: Re: cheap (free) fpga design software (VHDL
David McClanahan:
6305: 97/05/13: Re: Advantages/disadvantages between CMOS/BiCMOS
David McKenna:
3557: 96/06/20: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3649: 96/07/08: Consultant$$Work$$Xilinx
3756: 96/07/25: Re: Daisychain or SPROM?
3758: 96/07/25: Re: ATT serial EEPROMs
David Meigs:
36169: 01/10/31: Re: Leonardo bugs
David Miller:
16043: 99/04/29: Re: Counters
21774: 00/03/31: Actel ProASIC
25604: 00/09/15: Re: Boundary scan
30178: 01/03/27: Re: Asynchronus Mashine States
37419: 01/12/11: SelectIO and Virtex II: PAR weirdness
37430: 01/12/11: apologies.. and functional simulation of DCMs
37685: 01/12/19: DCM stability in Virtex2 -ES
37687: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37739: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37747: 01/12/20: Re: multi-cycle constraint
37764: 01/12/20: Re: DCM stability in Virtex2 -ES
37830: 01/12/21: Re: DCM stability in Virtex2 -ES
37901: 01/12/24: availability of VirtexII production silicon
38450: 02/01/15: Re: Falling edge in PLD
38817: 02/01/26: Xilinx PCI logicore: clarification on nature of COMPLETE
38866: 02/01/27: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
38868: 02/01/27: Re: tri-state vs. Mux
38956: 02/01/29: Re: glitchless clock enable/disable in spartanII
39186: 02/02/04: can comparisons glitch?
39494: 02/02/12: Re: Spartan Program/Verify
39496: 02/02/12: DONE goes high, but the device doesnt seem to "run"
David Moloney:
6397: 97/05/21: Re: Fast comparator
David Moore:
75153: 04/10/27: Looking for an archive of QuartusII v2.0 (yes v2.0) to download
David Mot:
2336: 95/11/21: (no subject)
2337: 95/11/21: (no subject)
2338: 95/11/21: (no subject)
2339: 95/11/21: (no subject)
2341: 95/11/21: (no subject)
2340: 95/11/21: Re: (no subject)
2342: 95/11/21: Low Cost Tools
2381: 95/11/27: (no subject)
2382: 95/11/27: Chipmaster 3000 Universal Device Programmer
2383: 95/11/27: Low Cost Altera Development System
David Murray:
15251: 99/03/16: Constraints! Constraints and more constraints!
19320: 99/12/14: Re: State machine ok with binary encoding but unstable with one hot encoding
19327: 99/12/14: Re: State machine ok with binary encoding but unstable with one hot encoding
19351: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
David Neely:
21434: 00/03/22: FPGA Part Selection Advice
David Newman:
17832: 99/09/09: Re: Virtex BRAM Initialization
17987: 99/09/21: Re: Xilinx XC4005E
David Norton:
17334: 99/07/21: C language to programmable logic
David Nyarko:
29931: 01/03/18: VHDL code required for a given decimator system
30103: 01/03/23: REQ. VHDL code for Single-pole IIR low-pass filter
30844: 01/05/01: Xilinx Virtex-II multiplier reuse examples
31334: 01/05/19: Xilinx 16-point FFT core problem
32362: 01/06/25: Xilinx Alliance tools timing summary results interpretation
32643: 01/07/04: Are these typical VirtexE timing values?
David Nyberg:
65231: 04/01/22: Lining up data...
65234: 04/01/22: Random data generator...
David Pariseau:
32540: 01/06/29: VHDL using Xilinx foundation software
32544: 01/06/29: VHDL using Xilinx foundation
32622: 01/07/02: poor man's floating point...
32633: 01/07/03: Re: poor man's floating point...
34109: 01/08/14: Xilinx foundation multi-pad pin assignments
34151: 01/08/15: Re: Xilinx foundation multi-pad pin assignments
David Pashley:
212: 94/09/23: Re: really good
213: 94/09/23: Re: PLD for async state machine?
224: 94/09/27: Re: XC1765DPD8C
228: 94/09/28: Re: Xilinx 4000
238: 94/09/30: Re: Determine protected PAL's equations
252: 94/10/03: Re: AT&T ORCA FPGA
397: 94/11/07: Re: Xilinx chip partitioning
658: 95/01/30: Re: Exemplar vs. NeoCAD
862: 95/03/16: <--> Proposed Newsgroup for Programmable Logic Users <---
904: 95/03/27: Re: AT&T FPGA Mailing List
1264: 95/05/23: Re: global clocks in ASYL
1687: 95/08/16: Re: Xilinx PROMs
2096: 95/10/13: Re: Help - Searching an PLD/FPGA Selection Software
2386: 95/11/27: Re: Chipmaster 3000 Universal Device Programmer
2409: 95/12/01: Re: NeoCAD and AT&T vs. Xilinx
2602: 96/01/10: Re: [q][Reverse Engineering Protection]
2617: 96/01/11: Re: [q][Reverse Engineering Protection]
2646: 96/01/18: Re: ProSeries + Actel & Xilinx
2653: 96/01/19: Re: Programming Actels in circuit?
2668: 96/01/22: Re: PLD JDEC Files
2798: 96/02/09: Re: Looking for OPAL, PALASM, PLAN
2959: 96/03/05: Re: Comp.Arch.FPGA
3040: 96/03/19: Re: Multiple FPGA Partitioning
3333: 96/05/14: Re: Looking for free FPGA softw./Xilinx
3374: 96/05/22: Re: Xilinx and Viewlogic
3375: 96/05/22: Re: Xilinx and Viewlogic
3422: 96/05/28: Re: Xilinx and Viewlogic
3431: 96/05/29: Re: OTP FPGAs was WEIRD NOISE PROB
3623: 96/07/04: Re: LCA to Schematic
3632: 96/07/05: Re: LCA to Schematic
3633: 96/07/05: RE: Sanity check for 100K gate DSP FPGA project
4079: 96/09/09: Re: ORCA and Viewlogic - any good?
4096: 96/09/10: Re: Help with XACT 6.0 ProSim Problem
4145: 96/09/18: Re: Inaccrate Xilinx simulations ???
4226: 96/10/02: Re: Partition tool for FPGAs?
4249: 96/10/04: Re: Altera Checksums
4595: 96/11/19: Re: The best timing diagram editor/simulator?
4603: 96/11/20: Re: Advantage of third party software?
5817: 97/03/18: Re: viewlogic ...
6926: 97/07/09: ANNOUNCE: Free seminars on language-based FPGA design (UK)
7958: 97/11/03: Re: Altera EPC1 and Chipmaster 6000
9045: 98/02/17: Re: Altera 5032 programming problems
9506: 98/03/19: Re: Strange Xilinx question?
9626: 98/03/27: Re: Newbie question - FAQ for this group?
9629: 98/03/27: Re: XactStep6 - The cure for a dongle
9634: 98/03/27: Re: XactStep6 - The cure for a dongle
9641: 98/03/27: Re: XactStep6 - The cure for a dongle
9664: 98/03/29: Re: XactStep6 - The cure for a dongle
9687: 98/03/31: Re: XactStep6 - The cure for a dongle
9690: 98/03/31: Re: XactStep6 - The cure for a dongle
9709: 98/04/01: Re: XactStep6 - The cure for a dongle
9731: 98/04/02: Re: XactStep6 - The cure for a dongle
9735: 98/04/02: Re: XactStep6 - The cure for a dongle
9921: 98/04/14: Re: FLEX 10K : FPGA or CPLD
10467: 98/05/20: Re: Archives for comp.arch.fpga?
10720: 98/06/12: Re: TESTBENCH
13471: 98/12/04: Re: HELP, Tool selection
13528: 98/12/08: Re: HELP, Tool selection
13572: 98/12/10: Re: HELP, Tool selection
13603: 98/12/11: Re: HELP, Tool selection
13527: 98/12/08: Re: HELP, Tool selection
13600: 98/12/11: Re: HELP, Tool selection
13472: 98/12/04: Re: package/footprint/layout
14524: 99/02/03: ANNOUNCE: Technical seminar on IP Integration (UK)
15530: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
15548: 99/03/30: Re: Free Xilinx Vendor Tools ... NOT :-(
15573: 99/03/31: Re: Free Xilinx Vendor Tools ... NOT :-(
16423: 99/05/21: Re: How synthesize tools concern with size of the design?
16428: 99/05/21: Re: How synthesize tools concern with size of the design?
16475: 99/05/25: Re: How synthesize tools concern with size of the design?
David Payne:
7376: 97/09/04: A fpga DMA design ?
David Peascoe:
9965: 98/04/17: XC4085xl pricing
David Pellerin:
2487: 95/12/15: Free VHDL Simulator (demo version)
3971: 96/08/27: ANNOUNCE: $499 PeakVHDL Training Edition Simulator
4003: 96/09/02: Re: ANNOUNCE: $499 PeakVHDL Training Edition Simulator
5800: 97/03/16: Re: Accolade
5801: 97/03/16: Re: VHDL & ABEL synthesis tools on 95/NT
7479: 97/09/15: Re: pellerin@seanet.com
9825: 98/04/07: Re: Xilinx Foundation Express
64733: 04/01/12: ANNOUNCE: Impulse CoDeveloper for MicroBlaze & Nios FPGAs now available
86975: 05/07/11: Re: Announce: Impulse C-to-RTL Version 2 now available
104157: 06/06/20: Re: using Impulse-C free edition for VHDL only FPGA designs.
104186: 06/06/20: Re: using Impulse-C free edition for VHDL only FPGA designs.
David Q.:
101642: 06/05/04: Re: Virtex-4 Gigabit Ethernet design
103290: 06/05/30: Re: Virtex-4 Gigabit Ethernet design
David Qmd Grieve:
338: 94/10/24: Re: SRAM and antifuse for interconnects
David Quiñones:
100881: 06/04/20: Re: Virtex-4 Gigabit Ethernet design
101001: 06/04/24: Re: Virtex-4 Gigabit Ethernet design
101004: 06/04/24: Re: Virtex-4 Gigabit Ethernet design
David R Brooks:
5700: 97/03/08: Re: Xilinx 4002 RAM Question
5861: 97/03/20: Re: Multiple clocks in Xilinx
5881: 97/03/22: Re: Is this really possible?
6046: 97/04/08: Re: PCI Bus Problems
6539: 97/06/02: Re: In circuit programming of flash --->JTAG?
6777: 97/06/26: Re: FPGA prototype board
7168: 97/08/08: Re: free FPGA software from actel
7199: 97/08/13: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7124: 97/08/03: Re: jtag isp guidance request
7172: 97/08/10: Re: Price of Serial EEPROM is Outrageous
7191: 97/08/12: Re: Price of Serial EEPROM is Outrageous
7247: 97/08/18: Re: Price of Serial EEPROM is Outrageous
7501: 97/09/17: Re: AMD PAL design change
7541: 97/09/19: Re: Atmel 17256 serial config EEPROMs
7565: 97/09/22: Re: Hacking bitstream formats
7848: 97/10/22: Re: help on xc4005a Boundary Scan
7961: 97/11/03: Re: Configuration of XC4000 FPGAs with JTAG
7962: 97/11/03: Re: Questions about FPGA hardware design
7994: 97/11/05: Re: I'm interested in FPGAs. How do I start ?
8141: 97/11/20: Re: what is metastability time of a flip_flop
8156: 97/11/21: Re: what is metastability time of a flip_flop
8253: 97/12/03: Re: FPGAs for hobbyist, HELP
8432: 97/12/14: Re: JTAG configuration of Xilinx XC4000E FPGAs?
9067: 98/02/18: Re: VHDL vs schematics
8901: 98/02/05: Re: Xilinx and Altera CPLDs in JTAG chain
9666: 98/03/29: Re: XactStep6 - The cure for a dongle
10414: 98/05/17: Re: Minimal ALU instruction set.
10430: 98/05/18: Re: Minimal ALU instruction set.
11133: 98/07/21: Re: CRC Implementation
12222: 98/10/05: Re: A Johnson counter
12250: 98/10/06: Re: A Johnson counter
12127: 98/09/30: Re: Xilinx XC95xx JTAG program for DOS
12285: 98/10/07: Re: Catching state machine errors (was: A Johnson counter)
12550: 98/10/15: Re: XILINX 4000XL configuration using M 1.5 JTAG programmer
22882: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22899: 00/05/31: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
26186: 00/10/08: Re: programm Xilinx FPGAs via JTAG
43056: 02/05/11: Re: Adders in Xilinx XC4000
43754: 02/06/01: Re: LFSR with 2^n instead of (2^n)-1
44177: 02/06/13: Xilinx primitives & ModelSim
44221: 02/06/14: Re: Xilinx primitives & ModelSim
44272: 02/06/16: Re: Xilinx primitives & ModelSim
44281: 02/06/16: Re: Stupid WebPack question
44518: 02/06/22: Initialising BlockSelectRAM
45602: 02/07/29: VHDL configurations with Xilinx ISE 4.1i
45908: 02/08/10: Re: RAM simlulation with WebPack4.2
47448: 02/09/26: Re: Clock balancing in DDR SDRAM design
47454: 02/09/26: Finding nets in hierarchy
48185: 02/10/13: Notation for Xilinx *.UCF files
48195: 02/10/14: Re: Notation for Xilinx *.UCF files
49554: 02/11/15: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
50441: 02/12/11: Re: Xilinx ISE 5.1 Wait for statement unsupported??
51546: 03/01/16: Xilinx XST & multiple (source) libraries
52435: 03/02/10: Re: Xilinx ISE 4.2i killing Windows 2000?
52497: 03/02/12: Re: XST choking hazard
53149: 03/03/05: Re: Implementation of latch in FPGA
53264: 03/03/09: Re: Implementation of latch in FPGA
55896: 03/05/23: Re: Asynchronous State Machines and HDLs
55983: 03/05/26: Re: attributes and generics
57608: 03/07/03: Re: Xilinx ISE drops support for more parts
58301: 03/07/20: Re: Initialize Block RAM
60030: 03/09/04: Re: OT: Block diagramming tools?
62038: 03/10/17: Re: Should I worry about metastability
62323: 03/10/27: Re: SDRAM Controller
62446: 03/10/30: Re: How to protect fpga based design against cloning?
62562: 03/11/02: Re: Convert verilog to VHDL??
62686: 03/11/05: Re: Building the 'uber processor'
63196: 03/11/18: Re: SRL16 as synchronizer
63888: 03/12/08: Re: Block RAM simulation VII
64346: 03/12/30: Re: A difference between VHDL sources working
64386: 04/01/01: Re: boolean to std_logic
73318: 04/09/19: Virtex-4 development boards
75100: 04/10/26: Re: Using Sync Reset as Async Reset
81185: 05/03/19: Re: Xilinx webpack map/route questions
82994: 05/04/21: Re: VHDL or Verilog
86869: 05/07/08: Re: SELV - power supply specification
91450: 05/11/07: Re: 24 to 32 8-bit PWM outputs
93841: 06/01/01: Re: basic DSP with FPGA
94473: 06/01/12: Re: Conflicts between ISE4.2 and win2000 SP4
94531: 06/01/13: Re: Conflicts between ISE4.2 and win2000 SP4
95113: 06/01/20: Re: OT:Shooting Ourselves in the Foot
96403: 06/02/03: Re: Die Area
96404: 06/02/03: Re: Die Area
96707: 06/02/09: Re: why does speed grade effect VHDL program??
97482: 06/02/23: Re: query!! need help!!
97630: 06/02/24: Re: Combinatorial Division?
97953: 06/03/02: Retro computers: was Re: Combinatorial Division?
99437: 06/03/24: Re: this JTAG thing is a joke
103067: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103717: 06/06/09: Re: Good free or paid merge software that edits two similar files?
104503: 06/06/28: Re: keys to the Kingdom
104517: 06/06/29: Re: keys to the Kingdom
104930: 06/07/10: Re: Weird JTAG lockup issue, where is the BUG?
106028: 06/08/05: Re: verilog versus vhdl
106405: 06/08/12: Re: Clock domain crossing (again)
108331: 06/09/08: Re: Managing small IP library
108468: 06/09/11: Re: RESET Signals
109353: 06/09/25: Virtex-4 BSCAN
109398: 06/09/26: Re: Virtex-4 BSCAN
109400: 06/09/26: Re: simulation mismatch (xilinx)
109402: 06/09/26: Re: Does anyone know what "SE" and "PE" stand for in ModelSim?
109461: 06/09/27: Re: Pack registers (from submodule) into IOB for bidirectionnal signal
109572: 06/09/29: Re: bit vs std_logic
110830: 06/10/24: Re: How to check if ROM got inferred from synth reports
110949: 06/10/25: Re: Stream cipher
110951: 06/10/25: Re: OT: FPGA soft-core humor
112096: 06/11/16: Re: 8080 FSGA model in an FPGA
112433: 06/11/22: Re: 8080 FSGA model in an FPGA
113988: 07/01/02: Re: Surface mount ic's
114027: 07/01/03: Re: Surface mount ic's
114158: 07/01/05: Anyone seen eASIC?
114340: 07/01/12: Re: LWIP EXAMPLE??
114611: 07/01/20: Re: Phasse Detector
114771: 07/01/24: Re: Surface mount ic's
114844: 07/01/25: Re: How to make a clock delay?
114893: 07/01/25: Re: On-chip randomness (V4FX)
114912: 07/01/26: Re: how do you code this?
114935: 07/01/26: Re: how do you code this?
114946: 07/01/27: Re: how do you code this?
115212: 07/02/02: Re: XST broken for XC9536?
117435: 07/03/30: Re: xilinx ise/edk/modelsim - what does compilation really do?
117436: 07/03/30: Re: ModelSim VHDL Pragmas
119378: 07/05/17: Re: VHDL newbie: building sequential circuits with basic gates
121929: 07/07/16: Re: Which embedded O/S for a 32-bit RISC microcontroller?
123279: 07/08/23: Re: Globally Asynchronous in FPGA
124400: 07/09/21: Re: Comparing Adder synthesis techniques
125695: 07/11/01: Re: can i use dual edge or two clocks?
130397: 08/03/22: Re: A Challenge for serialized processor design and implementation
130409: 08/03/23: Re: Viewing internal signals with ModelSim
135239: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
135698: 08/10/13: Re: Complex Event Processing on FPGA
136304: 08/11/11: Re: Silicon used for realising FPGA logic
David R Mulligan:
5503: 97/02/20: Re: Q: Search Engines for Electronic Parts?
David R. Brooks:
2172: 95/10/25: Re: Xilinx Configuration Memory Hacking
2220: 95/11/03: FPGA => ASIC
2259: 95/11/13: Re: Xilinx Configuration Memory Hacking
David Reid:
15449: 99/03/24: Has anyone used Virtex DLLs for multiple clocks.
15677: 99/04/07: ZBT to Virtex Interface at +100M
David Rinehart:
9347: 98/03/07: Re: Announce - Stuart jumps ship
David Roberts:
67762: 04/03/18: Xilinx ISE 6.2 and Virtex-II
David Robinson:
19290: 99/12/10: Re: Synopsys backannotation
David Rogoff:
17298: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
33764: 01/08/03: ISE 3.3 .npl files
36009: 01/10/25: Xilinx XST vs FPGA Express?
36627: 01/11/13: Re: Hex numbers in VHDL
37501: 01/12/12: Xilinx ISE4.1/FPGA express: specify pin loading
38494: 02/01/15: path for Vital component in assert?
44318: 02/06/17: Internal oscillator in CPLD?
47653: 02/10/01: Re: Rounting of non-global IO pad to a GCLKIOB site.
49150: 02/11/02: Re: Asynchronous clock enable with stable data
51731: 03/01/20: Re: Problem with XST libraries.
52085: 03/01/31: Re: Problem with XST libraries.
59135: 03/08/09: Re: Virtex-II RocketIO: Serial ATA?
66179: 04/02/13: Re: Verilog and VHDL mix
66587: 04/02/23: Re: VQM to EDIF
67657: 04/03/16: Speed of Linux vs Solaris
69349: 04/05/07: Where did Altera tech support go?????
70725: 04/06/24: Why does Quartus take 4 hours for a pin I/O change?
76282: 04/11/29: Physical Synthesis - Quartus vs. Amplify
David Smith:
73858: 04/09/30: A better way to do embedded Floating point?
David Spencer:
124535: 07/09/26: Re: Very basic clock questions.
125250: 07/10/18: Re: What to consider for source synchronous clocking?
125268: 07/10/18: Re: mess around with supply voltage to cyclone III
125350: 07/10/23: Re: Changing refresh rate for DRAM while in operation?
125365: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125444: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
125479: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
125511: 07/10/26: Re: Xilinx Isolate circuitry
125534: 07/10/27: Re: Selecting I/O pins
125597: 07/10/29: Re: 2 FPGAs /w programming FLASH in one JTAG chain
125987: 07/11/11: Re: newbie to 16v8
125992: 07/11/12: Re: newbie to 16v8
126002: 07/11/12: Re: newbie to 16v8
126183: 07/11/16: Re: TI DSP soft core in Xilinx?
126413: 07/11/21: Re: Measuring setup and hold time in Lab
126421: 07/11/21: Re: Measuring setup and hold time in Lab
126545: 07/11/27: Re: Converting a ByteBlasterMV into a ByteBlaster II?
126616: 07/11/28: Re: I/O short circuit protection?
126618: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126629: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126679: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126686: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126695: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126886: 07/12/05: Re: BUFGCE
126898: 07/12/05: Re: why do i see negative clock hold time
128274: 08/01/20: Re: Source of accurate frequency
128295: 08/01/20: Re: Source of accurate frequency
128593: 08/01/31: Re: FPGA in Telecommunications
128846: 08/02/07: Re: Sythesisable subset of VHDL
129917: 08/03/10: Re: its regarding to the Max Frequency in xilinx FPGA
130167: 08/03/17: Re: Designing CPU
130201: 08/03/17: Re: dual clock fifo
130219: 08/03/18: Re: Xilinx interview questions
130373: 08/03/21: Re: Synoplify ???
130388: 08/03/21: Re: Spartan 3E intefacing for dummies
130389: 08/03/21: Re: Actel SX-A Timing Constraints Issues
130439: 08/03/24: Re: Spartan 3E intefacing for dummies
130728: 08/03/31: Re: fpga reset (re-initialize) of spartan3e
131011: 08/04/08: Re: NoisII or else.
131993: 08/05/09: Re: 5 V oscillator output to GCLK
132005: 08/05/09: Re: 5 V oscillator output to GCLK
132050: 08/05/12: Re: RLC package parasitics
132182: 08/05/16: Re: What could be the problem?
132413: 08/05/26: Re: FPGA Programing file
139890: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
David Stanford:
78877: 05/02/09: Re: ProAsic3 (PA3)
78880: 05/02/09: Re: .vho (Xilinx Core Generator) to .vhd ??
David Stevens:
46256: 02/08/22: Re: combinatorial clocks
David Storrar:
6977: 97/07/18: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
7482: 97/09/16: Clock Pulse Width for IFFs
7555: 97/09/22: Xilinx M1 Back Annotated SDF Problem
7572: 97/09/23: Xilinx M1 Back Annotated SDF Question
7839: 97/10/21: Re: Q: Clocking for address decode/chip select.
7842: 97/10/22: ORCA Foundry Back Annotation Quesiton
9032: 98/02/16: Interesting one for anyone using ORCA
David Svensson:
1855: 95/09/10: Overview of FPGAs available?
David T Le:
14284: 99/01/23: PLL in FPGA
20235: 00/02/02: Which is the best HDL book ?
David T.:
64383: 03/12/31: Newbie VHDL issue with CPLD
64627: 04/01/09: Re: Newbie VHDL issue with CPLD
David T. Wang:
4304: 96/10/12: Async with FPGA?
6175: 97/04/22: Verilog vs VHDL once again.
David Tang:
13183: 98/11/18: Re: Atmel AT17C010?
13853: 98/12/29: Xilinx - Virtex Power Estimation?
16730: 99/06/04: Re: Memec 8250 core with Xilinx Spartan device
18247: 99/10/09: Re: ATM srambler
David Thomas:
123238: 07/08/20: FPL 2007 : Final call for participation
David Tucker:
57490: 03/07/01: device selection for game system
58551: 03/07/25: Re: device selection for game system
58552: 03/07/25: Re: device selection for game system
David Tweed:
10373: 98/05/15: Re: Minimal ALU instruction set.
10419: 98/05/18: Re: Minimal ALU instruction set.
87760: 05/07/31: Re: ISE webpack doesnt support Spartan xcs10, solution??
91099: 05/10/29: Re: 24 to 32 8-bit PWM outputs
92614: 05/12/02: Re: Slow FIFO using external SRAM
106364: 06/08/12: Re: Switching two (synchronous) clocks with variable phase difference,
120516: 07/06/08: XST net splitting blocks placement
120579: 07/06/11: Re: XST net splitting blocks placement
120822: 07/06/18: Re: XST net splitting blocks placement
134360: 08/08/07: Re: Downsizing Verilog synthesization.
134362: 08/08/07: Re: Downsizing Verilog synthesization.
134366: 08/08/07: Re: Downsizing Verilog synthesization.
135359: 08/09/28: Re: 50 Ohm Analog Output of FPGA
135362: 08/09/28: Re: 50 Ohm Analog Output of FPGA
136953: 08/12/15: Re: Synthesizable & open 4DDR Infiniband core
David Van den Bout:
28: 94/07/29: inexpensive FPGA prototyping
89: 94/08/12: Re: Microprocessors implemented with FPGAs
120: 94/08/17: Re: Proprietary Configuration Data
155: 94/09/02: Re: PLDshell/Intel ftp site
186: 94/09/15: Altera/Intel nfXboard
240: 94/09/30: Re: What do think about the Intel Flexlogic8160?
247: 94/10/02: new PLDshell FTP site
251: 94/10/03: Re: What do think about the Intel Flexlogic8160?
278: 94/10/11: Re: Xilinx configuration
301: 94/10/17: Re: in circuit programming, was Re: PALASM versions?
313: 94/10/18: Re: in circuit programming, was Re: PALASM versions?
315: 94/10/18: Re: in circuit programming
327: 94/10/20: Re: Analog FPGAs
403: 94/11/08: Re: Random Number Tests
648: 95/01/27: Re: FLEXlogic
652: 95/01/28: Re: Problems programming Intel FX780
669: 95/02/01: Re: "on-fly" reprogrammable devices/research
702: 95/02/09: Re: Low cost Boundary Scan?
739: 95/02/21: Re: PLA? PAL? PLD? GAL?
740: 95/02/21: Free EPX780 FPGA hypertext manual
810: 95/03/05: Re: Power gain when moving from FPGA to Gate Array
823: 95/03/07: hypertext PLDasm manual available online
983: 95/04/07: Free online JTAG tutorial and C library
1009: 95/04/12: Re: Intel Flex Download Cable
1103: 95/04/28: FPGA Downloading Circuit Tutorial
1211: 95/05/15: Re: FLEXlogic opinions?
1307: 95/05/30: HTML version of "FPGA Workout II"
1475: 95/06/27: UART in Altera FlexLogic
1546: 95/07/12: Re: Intel FLEXLogic
1739: 95/08/22: Re: Looking for Good Introductory Book on FPGAs and ELPDs
2008: 95/10/01: Re: FlexLogic download cable/schematics for one ?
2157: 95/10/22: Re: PLD in small package ?? anyone
2178: 95/10/26: Re: FPID's
2252: 95/11/09: Re: JTAG IEEE std 1149.1
2258: 95/11/12: Re: FPGA references and good starting points?
2308: 95/11/18: Re: Industry Trends
2379: 95/11/26: Re: looking for FPGA prototype platform
2400: 95/11/28: Re: Lattice GAL16VP8 -is it real ?
2416: 95/12/02: Re: Industry Trends
2495: 95/12/18: Re: UART in PLD
2663: 96/01/21: Re: Emulation for a wireless chip
2664: 96/01/21: Re: PLD JDEC Files
2821: 96/02/12: Re: FPGA entry for <$1000?
3325: 96/05/13: new FPGA chapters available
4157: 96/09/19: Re: Are there any FPGA Starter Kits?
4156: 96/09/19: Re: Good Starting points to learn FPGA for hobbyist?
4270: 96/10/08: COMMERCIAL: workshop on designing with FPGAs
David Van deV Bout:
988: 95/04/07: Frep onl!op JTAG tutirial and C library
David W. Bishop:
223: 94/09/27: Re: Exemplar CORE experiences?
872: 95/03/17: Boundary Scan in a Xilinx 4010
David W. Glessner:
944: 95/03/31: Data I/O & BP programmers (was Excuse me ...)
David Wade:
157992: 15/06/22: Conditional Interpretation of VHDL
157998: 15/06/23: Re: Conditional Interpretation of VHDL
158173: 15/09/09: Re: How to understand obfuscated IP codes?
158321: 15/10/20: Re: Sum of 8 numbers in FPGA
158571: 16/01/02: Programming waveshare core3s250e with Impact and ISE 14.1
158574: 16/01/05: Re: Programming waveshare core3s250e with Impact and ISE 14.1
158582: 16/01/06: Re: Programming waveshare core3s250e with Impact and ISE 14.1
158604: 16/01/20: Re: Fully preposterous gate arranger
158608: 16/01/23: Re: Fully preposterous gate arranger
158828: 16/04/23: Re: Challenges in data science which can be solved with FPGAs
159029: 16/06/17: Re: J1 forth processor in FPGA - possibility of interactive work?
159803: 17/03/09: Re: Analog to digital converters
160100: 17/05/25: Re: fpga zigbee interface
160393: 18/01/11: Re: HDL simple survey - what do you actually use
160898: 18/12/15: Re: What is the name of the circuit structure that generates a state
161625: 20/01/30: Re: Is FPGA code called firmware?
161630: 20/01/31: Re: Is FPGA code called firmware?
161632: 20/02/01: Re: Is FPGA code called firmware?
David Wang:
6178: 97/04/23: Re: ISP CPLD from AMD or Cypress???
david wang:
141151: 09/06/09: dsp with fpgas by Uwe Meyer-Baese
David Ward:
13010: 98/11/11: Make your own Printed Circuit Boards. Press-n-Peel in Europe
David Wentzlaff:
45736: 02/08/02: Silicon Area for Xilinx FPGAs
David Wilkie:
3052: 96/03/21: Re: What bus is a Xilinx XC1736DP SPROM?
3191: 96/04/22: Re: What bus is a Xilinx XC1736DP SPROM?
David Willmore:
3071: 96/03/26: Re: What bus is a Xilinx XC1736DP SPROM?
3072: 96/03/26: Re: What bus is a Xilinx XC1736DP SPROM?
David Wiltshire:
146680: 10/03/25: Newbie Coding Question
146684: 10/03/25: Re: Newbie Coding Question
146685: 10/03/25: Re: XST optimization
146700: 10/03/26: Re: Newbie Coding Question
David Wong:
3125: 96/04/08: Sun bpp bidirectional parallel port
David Wragg:
13271: 98/11/23: Re: Big-Endian vs Little-Endian
DAVID WRIGHT:
44408: 02/06/19: ATMEL CPLD
44429: 02/06/19: Re: ATMEL CPLD
David Wright:
32469: 01/06/27: Cypress CPLD/ GALAXY WARP
33103: 01/07/17: Working Design - Anyone
33409: 01/07/25: Application obstacle course
33468: 01/07/27: Re: Opinions on cypress warp 6.1 and devices?
34595: 01/08/30: WebPack Con-Game
34726: 01/09/05: Re: WebPack Con-Game
34784: 01/09/07: ISE 4.1
David Yeh:
124: 94/08/18: Help with Boundary Scan in Xilinx XC4000 FPGAs
554: 95/01/03: Xchecker programming limits
<david.manuel.dasilva@gmail.com>:
155853: 13/10/01: Re: Video Framebuffer using Nexys2 (Spartan-3E)
<david.middleton@gmail.com>:
156109: 13/11/25: Re: Interface Xilinx KC705 to BeagleBone?
david.oriot:
108917: 06/09/19: Re: xilinx fir ipcore
118288: 07/04/23: Re: Ouputs during startup and Programming
<David.Stanford@gmail.com>:
78874: 05/02/09: Re: newbie : IP cores
<david.surphlis@gecm.com>:
6753: 97/06/24: lattice / synario and smatmodels
7313: 97/08/25: xlinx shift regs equilivelent parts
7622: 97/09/29: fifos design for fpga
7677: 97/10/02: bidirectional bus problem
8970: 98/02/10: reading crcs from an fpga
<david@fpgaworld.com>:
86689: 05/07/04: Call for FPGAworld 2005
<david@home.com>:
16088: 99/05/01: ISP,schematics and sim for free???
<david@lowrance.com>:
4610: 96/11/20: FPGA Gate Counts: No Truth in Advertising
4620: 96/11/21: Re: FPGA Gate Counts: No Truth in Advertising
<david@opq.se>:
2472: 95/12/12: PALASM under OS/2???
<david_easton@btopenworld.com>:
97949: 06/03/02: Virtex4 MGTs using Aurora Core
<david_hinds@my-deja.com>:
17326: 99/07/21: Synplify - Optimizing Out A Bus
17328: 99/07/21: Synplify - Optimizing out a Bus.
<david_kessner@my-deja.com>:
22338: 00/05/05: Re: How to Prevent theft of FPGA design
<davidbafumba@gmail.com>:
133898: 08/07/18: free video course fpga or asic
<davidc@ad-holdings.co.uk>:
113167: 06/12/07: RTL Hardware design issue: Count Leading Zeros CLZ
113192: 06/12/07: Re: RTL Hardware design issue: Count Leading Zeros CLZ
113221: 06/12/08: Re: RTL Hardware design issue: Count Leading Zeros CLZ
davide:
96492: 06/02/04: handle-c and xilinx
112770: 06/11/28: Re: Spartan3 Configuration Puzzler
113113: 06/12/06: Re: help with Xilinx LVDS syntax
113642: 06/12/18: Re: FX12 ethernet resource usage
113812: 06/12/22: Re: Help with xilinx simulation?
114534: 07/01/18: Re: Ethernet Interface
114545: 07/01/18: Re: PCI Card with FPGA
114674: 07/01/22: Re: Ethernet Interface
114882: 07/01/25: Re: Xilinx USB download cable
114891: 07/01/25: Re: OrCAD symbol for the Xilinx V5LX50 FF676 device
115031: 07/01/29: Re: Change ROM contents, .bit file
115076: 07/01/30: Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?
115122: 07/01/31: Re: cpld version?
115142: 07/01/31: Re: virtex4 configuration via XCF32P Prom
115166: 07/02/01: Re: virtex4 configuration via XCF32P Prom
115167: 07/02/01: Re: Xc2v6000 package for ise
115201: 07/02/02: Re: read fpga
115374: 07/02/08: Re: ISE 9.1 sp1 and EDK 8.2 sp2
115422: 07/02/09: Re: Setting VHDL standard in Xilinx ISE
115498: 07/02/12: Re: Setting VHDL standard in Xilinx ISE
115873: 07/02/22: Re: internal DCM
116047: 07/02/28: Re: Xilinx USB flatform cable length mistery ?
116053: 07/02/28: Re: Xilinx USB flatform cable length mistery ?
116257: 07/03/05: Re: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
116414: 07/03/08: Re: odd warning in Xilinx ISE webpack
116431: 07/03/08: Re: Avnet Virtex-4 FX12 mini module
116746: 07/03/16: Re: XIlinx 9.2 'partition' mode problem - s/w dies....
116755: 07/03/16: Re: How to generate sgmii interface?
117014: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
117376: 07/03/29: Re: Webpack 9.1 Service Pack 3
117382: 07/03/29: Re: Webpack 9.1 Service Pack 3
118724: 07/05/02: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
118987: 07/05/08: Re: SelectMap or serial: How does the PROM know?
118989: 07/05/08: Re: SelectMap or serial: How does the PROM know?
119071: 07/05/10: Re: SelectMap or serial: How does the PROM know?
120678: 07/06/13: Re: programming virtex2 FPGA
120680: 07/06/13: Re: Virtex 4 Config
120695: 07/06/13: Re: ISE write permissions?
120721: 07/06/14: Re: programming virtex2 FPGA
120722: 07/06/14: Re: ISE write permissions?
120765: 07/06/15: Re: Virtex 4 Config
121270: 07/06/29: Re: Xilinx ngdbuild question
121322: 07/07/02: Re: Xilinx programmer, many unknown devices...
122313: 07/07/25: Re: ise 9.2 fatal error
122612: 07/08/01: Re: Fatal Error ISE 9.1
122613: 07/08/01: Re: Xilinx Webpack for Linux 64 bit?
123135: 07/08/16: Re: Reconfiguring a Virtex4 DCM_ADV.
123223: 07/08/20: Re: MCS -> BIT
127920: 08/01/10: Re: cable IV and platform USB cable API now officially public
138543: 09/02/26: Re: virtex 5 columns
Davide Anguita:
16868: 99/06/15: Which Virtex prototype board ?
66211: 04/02/14: PREP benchmark
71140: 04/07/09: Pre-PhD fellowship
89559: 05/09/19: Two short-term research grants
Davide Canina:
63675: 03/11/28: problem with RS485 or RS232
Davide Falchieri:
15273: 99/03/17: PGCK and SGCK
16283: 99/05/13: Xilinx demo board
16825: 99/06/11: FPGA Demonstration Board
19150: 99/12/02: Tristate bidirectional pads with Xilinx
19177: 99/12/03: Re: Tristate bidirectional pads with Xilinx
19375: 99/12/17: Re: Speed grade
20788: 00/02/22: ASP: Addressable Scan Port
Davide Rizzo:
9123: 98/02/22: Advantech pc-uprog
15016: 99/03/03: Re: graphic Lcd control core
17844: 99/09/13: Re: differences between ALTERA-XILINX
DavidS8021:
2806: 96/02/10: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
<davidtle@SoCA.com>:
7684: 97/10/02: Need help for Xilinx Demo Board
Davis Moore:
31031: 01/05/09: Re: Shannon Capacity - An Apology
32468: 01/06/27: Re: Stupid Xilinx Patent
38991: 02/01/29: Re: 18bit counter
39320: 02/02/06: Re: FPGA vs GAL : Lattice Its a TROLL
42637: 02/04/29: Re: Does Vertex II PRO Really work?
43188: 02/05/15: Re: Altera/Quartus II: unconditional loop?
44041: 02/06/10: Re: where did my MHz go!
44382: 02/06/18: Re: 5V tolerance
44838: 02/07/02: Re: Virtex II - Assigning Pins before routing?
44839: 02/07/02: Re: Virtex II - Assigning Pins before routing?
46199: 02/08/21: Re: I2C License
46337: 02/08/26: Re: Export from ModelSim to Excel?
68612: 04/04/09: Re: Fatal error mappin 2v1000 in ISE 6.2
74819: 04/10/19: Re: direction of carry and shift chains in xilinx & Altera
74820: 04/10/19: Re: alternatives to xst-map
77996: 05/01/21: Re: Out of memory error : XPS, microblaze, EDK
78160: 05/01/25: Re: Out of memory error : XPS, microblaze, EDK
Davis Moore (nospam):
38667: 02/01/21: Re: help me!
38674: 02/01/21: Re: help me!
38679: 02/01/21: Re: help me!
Davka:
66250: 04/02/15: Dual-stack (Forth) processors
66257: 04/02/16: Re: Dual-stack (Forth) processors
66281: 04/02/16: Re: Dual-stack (Forth) processors
66683: 04/02/25: Re: Dual-stack (Forth) processors
66734: 04/02/25: Re: Dual-stack (Forth) processors
67884: 04/03/22: Re: Dual-stack (Forth) processors
Davo:
59264: 03/08/14: XILINX FPGA project
59293: 03/08/14: Sorry: XLA5 Vs. XS series
59370: 03/08/18: Which software from Xilinx
59444: 03/08/20: ISE Foundation 4.1i compatibility
Davor Lukacic:
12328: 98/10/09: Re: VHDL'93 in MaxPlus
18510: 99/10/28: Re: Looking for exemplar_1164 package
18505: 99/10/28: Re: Timing & bidirectional buses
Davy:
85332: 05/06/07: [Verilog] How to write a barrel shifter?
85399: 05/06/08: [Vir2] Can I use a 18k ram as 2 single-port ram?
85414: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
85421: 05/06/09: How to convert Matlab to HDL?
85611: 05/06/12: Re: Can I use a 18k ram as 2 single-port ram?
85613: 05/06/12: Re: Can I use a 18k ram as 2 single-port ram?
85615: 05/06/12: How to pipeline Loop Logic?
85705: 05/06/14: Auto pipeline logic??
85733: 05/06/14: Re: Auto pipeline logic??
86233: 05/06/23: How about signed adder?
86273: 05/06/23: Re: How about signed adder?
86370: 05/06/26: Two Verilog FSM style compare
88529: 05/08/21: Re: What is the diffrences between lattice's FPGA and Xilinx's FPGA
90542: 05/10/16: Best Async FIFO Implementation
92538: 05/12/01: Multi-layer switch network?
92607: 05/12/02: Re: Multi-layer switch network?
93214: 05/12/15: Inverter Chain Synthesis Problem
93216: 05/12/15: Re: Inverter Chain Synthesis Problem
93220: 05/12/15: Re: Inverter Chain Synthesis Problem
93874: 06/01/02: Equalizer / Adaptive filter and VLSI implementation
94970: 06/01/19: Constellation symbol to bit's soft-probability?
96581: 06/02/06: Verilog 2's Complement Shifter
96654: 06/02/08: Open Verification Libiary Free Download
99195: 06/03/21: Self-check Testbench Learning
99271: 06/03/22: Verilog's integer and reg?
99477: 06/03/24: Verilog Task pass value problem?
99478: 06/03/24: How to write compact DFF chain?
99485: 06/03/24: Verilog RTL and Behavioral Testbench
99515: 06/03/25: Re: Verilog Task pass value problem?
99521: 06/03/25: Re: Verilog Task pass value problem?
99608: 06/03/27: Verilog, PSL or SystemVerilog of OVL?
99787: 06/03/29: Xilinx ISE DRC: An antenna found
99985: 06/03/31: Concatenate String in Verilog?
99986: 06/03/31: Hierarchical FSM?
100972: 06/04/21: Tcl used in Modelsim?
105326: 06/07/20: Hardware book like "Code Complete"?
105515: 06/07/25: Re: Hardware book like "Code Complete"?
106440: 06/08/13: Arbiter schemes?
106536: 06/08/14: Re: Arbiter schemes?
107151: 06/08/24: Arbiter design problem?
107473: 06/08/28: Sun open SPARC micro architecture document
107593: 06/08/30: Re: Arbiter design problem?
108643: 06/09/14: General Tips of reading Verilog Code
110348: 06/10/13: Scoreboard and Checker in Testbench?
110444: 06/10/15: Re: Scoreboard and Checker in Testbench?
110446: 06/10/15: Synopsys's VMM and Mentor's AVM
110454: 06/10/16: Re: Scoreboard and Checker in Testbench?
110502: 06/10/16: Re: Synopsys's VMM and Mentor's AVM
110560: 06/10/17: Re: Synopsys's VMM and Mentor's AVM
110564: 06/10/17: Re: Synopsys's VMM and Mentor's AVM
111100: 06/10/29: SystemVerilog interface: virtual and ref
111441: 06/11/03: Re: SystemVerilog interface: virtual and ref
111444: 06/11/03: SystemVerilog not use Mail-box directly in VMM and AVM ?
111446: 06/11/03: Conformal compare retiming netlist and RTL
111454: 06/11/03: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111550: 06/11/05: Formal Logic Equivalent Check (LEC)
111551: 06/11/05: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111553: 06/11/05: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111625: 06/11/06: How to simulate netlist with gated clock?
111678: 06/11/07: Re: How to simulate netlist with gated clock?
111730: 06/11/08: Re: How to simulate netlist with gated clock?
111731: 06/11/08: Re: How to simulate netlist with gated clock?
111738: 06/11/09: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111836: 06/11/10: "|->" implicate and sequence in SVA?
111904: 06/11/12: Re: "|->" implicate and sequence in SVA?
112522: 06/11/23: What's Nonpipelined bus mean?
112524: 06/11/23: Re: What's Nonpipelined bus mean?
112526: 06/11/23: Re: What's Nonpipelined bus mean?
112543: 06/11/24: Verilog problem: default case to set signal xxxx
112633: 06/11/26: Re: Verilog problem: default case to set signal xxxx
114070: 07/01/03: DC timing violation, what to do first?
114077: 07/01/04: Re: DC timing violation, what to do first?
114124: 07/01/04: Re: DC timing violation, what to do first?
114210: 07/01/07: Use Multi-cycle Path or Pipeline?
114303: 07/01/11: Interlock and stall in CPU design?
Dayn:
150949: 11/02/24: How to transfer some data with FlashPro through JTAG into Actel Fusion FPGA ?
daytripper:
111704: 06/11/08: Re: How to simulate netlist with gated clock?
db:
7242: 97/08/18: Xilinx & Altera using same configuration lines?
7566: 97/09/22: Re: Hacking bitstream formats
7740: 97/10/09: VHDL SRAM model for testbench?
53363: 03/03/11: FPGA new problems.
57753: 03/07/05: Exceptional conditions on XST.
63477: 03/11/22: Re: Is this a good starter kit?
66008: 04/02/11: Re: sdram controller problems
67034: 04/03/03: Anyone else using the USB JTAG board from Mesa Electronics
68787: 04/04/18: Re: Huh, anybody wants to play some NES???
70133: 04/06/03: Re: USB OTG high speed
DB:
55991: 03/05/26: Any recommendation for an FPGA kit ?
55996: 03/05/26: Re: Any recommendation for an FPGA kit ?
56549: 03/06/09: DSP Kit recommendation in $1000 range ?
76000: 04/11/22: Low cost million gate Spartan 3 board?
dbd:
125627: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
148489: 10/07/27: Re: All Digital PLL
<dbeck88@gmail.com>:
126849: 07/12/04: UK FPGA supplier
dburns:
11578: 98/08/25: Re: Paul Donachs Thesis
DC:
102031: 06/05/09: constraints for DDR bus with 133MHz write and 66Mhz read clocks
102040: 06/05/09: Re: constraints for DDR bus with 133MHz write and 66Mhz read clocks
115151: 07/02/01: Altera DSP Builder
115154: 07/02/01: Re: Graphics demo using FPGA?
dc207:
143494: 09/10/13: FPGA on-die LVDS termination issues
143502: 09/10/13: Re: FPGA on-die LVDS termination issues
143503: 09/10/13: Re: FPGA on-die LVDS termination issues
143527: 09/10/14: Re: FPGA on-die LVDS termination issues
<dc2uv.design@gmail.com>:
156652: 14/05/25: Signal Integrity Failure on Custom FPGA board
dc_rockclimbing:
101238: 06/04/27: Re: Development Platform for begginer
dcabanis:
143711: 09/10/22: SCLive 3.0 With Verilog, VHDL, SystemC kernels available.
<dcaulfield@lowtechsolutions.net>:
114053: 07/01/03: Mapper using wrong EMAC with PowerPC in V4FX60
124176: 07/09/13: genmcs.pl for a V4FX60 aka loading the cache from the prom on a multi processor device
dchui:
71176: 04/07/10: Xilinx Virtex II - questions about CLOCKGEN module for EDK (Multimedia Development Board)
DCUI:
870: 95/03/17: IST New Office
1456: 95/06/24: EDA Sales Person Wanted
1961: 95/09/25: Wanted-Application Engineer
ddale:
37511: 01/12/13: How to use the CoreGen hdl code within my source?
<ddallen@gmail.com>:
118299: 07/04/23: DONE problems
ddfire:
108644: 06/09/14: Re: Xilinx Platform Cable USB on Linux: Impact always wants to update Firmware
ddrinkard:
86194: 05/06/22: Re: Frequency divisors
110493: 06/10/16: Re: Virtex-5 LXT launched today !
110506: 06/10/16: Re: Virtex-5 LXT launched today !
De Valck Joeri:
15528: 99/03/29: HELP NEEDED: FPGA and Neural Networks
15589: 99/04/01: Re: HELP NEEDED: FPGA and Neural Networks
de4:
140212: 09/05/04: FIFO that latches data asynchronic manner
140223: 09/05/04: Re: FIFO that latches data asynchronic manner
144458: 09/12/09: Multiport BRAM for custom CPUs
144461: 09/12/09: Re: Multiport BRAM for custom CPUs
144464: 09/12/09: Re: Multiport BRAM for custom CPUs
144550: 09/12/14: Power dynamic managment in FPGA design
144553: 09/12/14: Re: Power dynamic managment in FPGA design
144560: 09/12/14: Re: Power dynamic managment in FPGA design
144634: 09/12/21: Re: multiprocessor on spartan 3
145617: 10/02/16: Data2Mem ? BlockRAM ? Init BMM and MEM
145621: 10/02/16: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
145624: 10/02/16: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
145660: 10/02/17: Unpredictable design
145668: 10/02/18: Re: Unpredictable design
145672: 10/02/18: Re: Unpredictable design
145674: 10/02/18: Re: Unpredictable design
145682: 10/02/18: Re: Unpredictable design
145705: 10/02/19: Re: Unpredictable design
146085: 10/03/05: FSM in BlockRAM
deadflower:
63698: 03/11/30: about digilent board
Dean:
32315: 01/06/22: Help needed: New user with Xilinx WebPack and XC9572 counter design - how to do basic things
32570: 01/06/30: Where are the BUFE and BUFT symbols in Xilinx WebPACK???
32585: 01/07/01: Xilink WebPACK keeps removing a pin I want to keep.
32962: 01/07/13: Help needed: why am I getting device programming errors on Webpack.
32987: 01/07/14: Re: Help needed: why am I getting device programming errors on Webpack.
33011: 01/07/15: Re: Help needed: why am I getting device programming errors on Webpack.
33126: 01/07/18: Help please: How to build a state machine into a VHDL block?
Dean Armstrong:
27735: 00/12/06: Using CPLD to configure SpartanII from parallel ROM.
27757: 00/12/07: Re: Using CPLD to configure SpartanII from parallel ROM.
27922: 00/12/15: Providing a configuration header for Spartan II
28040: 00/12/20: JTAG port electrical specs
28543: 01/01/17: FPGA driving clock line
28544: 01/01/17: Re: FPGA driving clock line
28546: 01/01/17: Re: FPGA driving clock line
28593: 01/01/18: Re: FPGA driving clock line
30392: 01/04/06: Spartan II Configuration
30447: 01/04/09: Re: Spartan II Configuration
35923: 01/10/24: JTAG question
35951: 01/10/25: Re: JTAG question
36441: 01/11/09: Multiple levels of reset in CPLD
41169: 02/03/22: Clock termination affecting JTAG interface
41277: 02/03/25: Re: Clock termination affecting JTAG interface
41278: 02/03/25: Re: Clock termination affecting JTAG interface
63632: 03/11/26: PCI LogiCORE with ISE 5.2
Dean Brown:
5142: 97/01/26: Re: Altera PCI experience anyone?
5236: 97/01/31: Re: Altera support better than Xilinx
7768: 97/10/13: VHDL Simulation
Dean Dunnigan:
4553: 96/11/13: Fast FPGA
Dean Fitzgerald:
2848: 96/02/16: Re: Altera Simulation
Dean Kent:
105485: 06/07/24: Re: Hardware book like "Code Complete"?
Dean Malandris:
32347: 01/06/24: Re: Help needed: New user with Xilinx WebPack and XC9572 counter design - how to do basic things
32348: 01/06/24: Re: Help needed: New user with Xilinx WebPack and XC9572 counter design - how to do basic things
32555: 01/06/30: Error messages in Xilinx WebPack ISE
32556: 01/06/30: Xilinx WebPACK ISE OBUFT "ngdbuild:467" error.
32577: 01/06/30: Re: Where are the BUFE and BUFT symbols in Xilinx WebPACK???
32610: 01/07/02: Re: Xilink WebPACK keeps removing a pin I want to keep.
33007: 01/07/15: Re: Help needed: why am I getting device programming errors on Webpack.
Dean Susnow:
3057: 96/03/22: MTI VHDL simulation w/ Xilinx
7210: 97/08/14: Wanted: High speed Serial core
<dean.dunnigan@gmail.com>:
92551: 05/12/01: Re: Xilinx Coregen IP Customizer Causes Exception During Customization
DeanNelson:
3553: 96/06/20: XC1765 vs Atmel's AT17C65 Serial EEPROMs
Debashish:
59301: 03/08/14: Problem with Modelsim Lisence server...
59379: 03/08/17: Re: Problem with Modelsim Lisence server...
<debashish.hota@gmail.com>:
93182: 05/12/15: Xilinx DCM Shuts down at 75degree centigrade
94074: 06/01/05: Xilinx DCM
debo:
71001: 04/07/05: Why 18X18 Multipliers in Altera and Xilinx?
<deboleena.minz@st.com>:
71063: 04/07/07: Re: Why 18X18 Multipliers in Altera and Xilinx?
Deborah Peel:
4660: 96/11/26: WinEDA online eng. conf ends
Declan and Caulfield:
49778: 02/11/21: XST Limitations?
deco:
76312: 04/11/30: State Machine Woes
Deefoo:
105389: 06/07/21: Spartan III development: which tools, what kind of PC?
deep:
136426: 08/11/15: vga interfacing for image display
136520: 08/11/19: ip core connection
138698: 09/03/05: synchronization problem
deepak:
154826: 13/01/16: IP core implementation of multiplier on FPGA Spartan 3e
154835: 13/01/17: Re: IP core implementation of multiplier on FPGA Spartan 3e
154836: 13/01/17: Re: IP core implementation of multiplier on FPGA Spartan 3e
154865: 13/01/21: i've used a verilog ip core of 8051...plz someone tell me what should
154869: 13/01/22: Re: i've used a verilog ip core of 8051...plz someone tell me what
154870: 13/01/22: implementation of 8051 ip core on fpga
154878: 13/01/25: ip core implementation on fpga
Deepak Agarwal:
63763: 03/12/03: Partial Reconfiguration:Par fails during Assemble
DEEPAK KUMAR T:
16966: 99/06/21: PLL for FPGA
Deepak Tripathi:
3990: 96/08/29: Generic FPGA toolkits for PC
deepak.lala@gmail.com:
105772: 06/07/31: Re: Verilog case statements
<deepak100@hotmail.com>:
86089: 05/06/21: Altera Net Seminar on 3GPP Release 6 and Beyond
deepakvr@gmail.com:
128446: 08/01/26: buying fpga kits in denmark
Deependra Talla:
6755: 97/06/24: universities offering real-time
8809: 98/01/28: VHDL book
8878: 98/02/04: info on VHDL simulators
10656: 98/06/09: HDL Simulator implementations
10985: 98/07/08: Speed Vs Accuracy
11291: 98/08/02: OO enhancements to VHDL
deepka:
7632: 97/09/29: circuitonline.com
7788: 97/10/15: Design Resource
8098: 97/11/17: Electronics Directory
8102: 97/11/17: Design Resource
8108: 97/11/18: Electronics Directory
8573: 98/01/09: New Jobsite
9034: 98/02/16: High-Tech Jobs/Resume
deerlux:
36123: 01/10/30: How can I design a bi-deriction bus buffer?
36135: 01/10/30: Re: How can I design a bi-deriction bus buffer?
37270: 01/12/06: Where can I find the implemention of block float multiplier?
37606: 01/12/17: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37889: 01/12/23: Does the core or Xilinx Core Generator support timing-simlulation?
41395: 02/03/27: How can I add constrains?
default:
46144: 02/08/20: Re: Poor man's DSP/FPGA instructional tool?
Default Profile:
16873: 99/06/15: Make fast money!!!
Default User:
18086: 99/09/29: money
118593: 07/04/30: Re: debounce state diagram FSM
118603: 07/04/30: Re: debounce state diagram FSM
118736: 07/05/02: Re: debounce state diagram FSM - topical
118737: 07/05/02: Re: debounce state diagram FSM
118786: 07/05/03: Re: debounce state diagram FSM - topical
default@user.com:
25645: 00/09/15: Re: Xilinx Student Edition 2.1 where?
25646: 00/09/15: Good FPGA prototyping boards?
25772: 00/09/19: Re: Good FPGA prototyping boards?
25823: 00/09/21: CORDIC COS/SIN with FPGA implementation
25873: 00/09/23: Re: CORDIC COS/SIN with FPGA implementation
Dejan:
92414: 05/11/29: Re: Cypress FX2 bandwidth problem
129805: 08/03/06: Re: Blast from the past
Dejan Durdenic:
64486: 04/01/05: Re: Altera CPLD - Illegal assignment-global clock
66229: 04/02/15: Re: Programming an EPC1 conf.Dev. from Altera
66235: 04/02/15: Re: Programming an EPC1 conf.Dev. from Altera
Dek:
143218: 09/09/26: ChipScope Pro, storing stimuli in ILA core
143219: 09/09/26: Re: Problem with using write and write function
143221: 09/09/27: Re: ChipScope Pro, storing stimuli in ILA core
143240: 09/09/28: Re: ChipScope Pro, storing stimuli in ILA core
145456: 10/02/10: Reading UDP with FPGA
145743: 10/02/22: Re: Reading UDP with FPGA
145744: 10/02/22: Triming timing constraints from pin ...
145745: 10/02/22: Re: Reading UDP with FPGA
145775: 10/02/23: Re: Triming timing constraints from pin ...
del cecchi:
28281: 01/01/04: Re: Nondeterministic FSMs in hardware?
50364: 02/12/09: Re: vlsi implementation of multipliers
50452: 02/12/10: Re: vlsi implementation of multipliers
Del Cecchi:
6594: 97/06/04: Re: Memory workshop, San Jose
28297: 01/01/05: Re: Nondeterministic FSMs in hardware?
57322: 03/06/27: Re: Eighty layers of metal!
119099: 07/05/11: =?windows-1252?Q?Re=3A_power_consumption_of_integrated_?=
119104: 07/05/11: =?windows-1252?Q?Re=3A_power_consumption_of_integrated_?=
125494: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
150314: 11/01/09: Re: OT: Fast Circuits
delahaye:
55050: 03/04/25: ISE5.2 XST design flow for Partial Reconfiguration
55919: 03/05/23: Constant on Multiplier Synthesis problem with XST for VirteX 2/E
Delayne Plesko:
496: 94/12/07: Re: WWW sites for Product Info
Delbert Cecchi:
82373: 05/04/12: Re: Reverse engineering masked ROMs, PLAs
82447: 05/04/13: Re: Reverse engineering masked ROMs, PLAs
<deleted@googlemail.com>:
120479: 07/06/07: How can i convert char* / string to sc_lv<16> ?
delgeris:
149203: 10/10/07: help with bad synchronous description error
Deli Geng (David):
37396: 01/12/10: DSP or FPGA for ODFM Demodulation?
38774: 02/01/24: Does Xilinx Spartan-II have reserved pin for PCI?
38842: 02/01/26: Re: Does Xilinx Spartan-II have reserved pin for PCI?
39043: 02/01/30: Re: Spartan II power-up current - again
45288: 02/07/18: Re: I want to buy 4 Xilinx FPGA
45360: 02/07/20: Spartan II JTAG connection with other devices
46043: 02/08/15: I2C License
DELLAENTERPRISES:
10335: 98/05/12: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
Delon Levi:
16696: 99/06/03: Re: Evolutionary computation
21801: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
28192: 00/12/27: Re: Question about programming xcv100
<deltabravosingh@gmail.com>:
128991: 08/02/12: Re: Does PC-FPGA communication requires a driver?
128992: 08/02/12: Re: Virtex5 DCM lower limit
128993: 08/02/12: Re: loading unisim in modelsim problem while testin xilinx ipcore
128994: 08/02/12: Re: Critical Path analysis
DeMarcus:
94487: 06/01/12: Re: Newbe Startup Time Question
102686: 06/05/19: Memory Interface: Standards
Demitri Korsikov:
9196: 98/03/01: ORCAD front End Tools
demod:
141304: 09/06/16: QPSK demod development: Integration problems
Demosa:
42331: 02/04/20: FLEX10K ALU question.
Denaice:
92872: 05/12/08: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92919: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92924: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
100099: 06/04/03: Re: hwicap can be used in the virtex4
100133: 06/04/04: Re: hwicap can be used in the virtex4
Deni:
60116: 03/09/05: Re: Flex6K configuration PROM
Deniau:
67046: 04/03/04: Xilinx VirtexII Pro downloading with Platform Flash ?
Denis:
62282: 03/10/24: Xilinx tsi report confusion
Denis Gleeson:
46437: 02/08/29: gate the main FPGA clk
46473: 02/08/30: Re: gate the main FPGA clk
46495: 02/09/01: Re: gate the main FPGA clk
46520: 02/09/02: Basic question: configuring IOBs ???
47072: 02/09/16: Multiple divide by 10
47093: 02/09/17: Re: Multiple divide by 10
57017: 03/06/20: FPGA configure through a PC parallel port.
57280: 03/06/26: XCSO5XL configuration with .bit or .rbt
57336: 03/06/27: Configure an FPGA from the PCs Parallel port. A solution.
57363: 03/06/28: Re: Configure an FPGA from the PCs Parallel port. A solution.
58046: 03/07/13: Combinational logic and gate delays - Help
58070: 03/07/14: Re: Combinational logic and gate delays - Help
58073: 03/07/14: Re: Combinational logic and gate delays - Help
58171: 03/07/16: Re: Combinational logic and gate delays - Help
60934: 03/09/25: Synchronous Binary counter question.
61003: 03/09/26: Re: Synchronous Binary counter question.
62739: 03/11/06: latch and shift 15 bits.
62783: 03/11/07: Re: latch and shift 15 bits.
67052: 04/03/04: Global reset question?
67145: 04/03/06: Re: Global reset question?
67637: 04/03/16: Re: Global reset question?
74955: 04/10/22: Verilog Simulation problem
74995: 04/10/23: Re: Verilog Simulation problem
75994: 04/11/22: Modelsim library problem
denis lachapelle:
14143: 99/01/15: AT40K popularity and available tools...
14307: 99/01/25: Re: DTMF Decoder in a FPGA/XILINX ?
14420: 99/01/29: Re: Atmel IDS 6.00 simulation question
Denis Lachapelle:
5081: 97/01/21: FPGA with SRAM
8378: 97/12/11: XC4003 developpement board
41053: 02/03/20: Re: low cost PCI spartan board needed
denis.r:
52523: 03/02/12: constant on maxplus
Denis2Gif:
141530: 09/06/26: Buy Live design kit from Altium
denish:
136471: 08/11/18: spartan 3A dsp fpga memory
136691: 08/12/01: using memory of spartan 3sd1800a dsp fpga
136993: 08/12/17: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit
138934: 09/03/15: inout pins use in fpga
<denizdikmen@gmail.com>:
88955: 05/09/01: CPLD CoolRunner-II - IO current limited to 8mA?
Denkedran Joe:
126673: 07/11/29: lossless compression in hardware: what to do in case of uncompressibility?
126682: 07/11/29: Re: lossless compression in hardware: what to do in case of uncompressibility?
127285: 07/12/17: global clock (gclk) input at xilinx virtex4 fpga
131463: 08/04/22: How to independently program the embedded PowerPC in a Virtex?
132780: 08/06/06: length compensation for RocketIO channels
132783: 08/06/06: FPGA to FLASH and back?
132981: 08/06/12: Re: FPGA to FLASH and back?
Dennis:
37405: 01/12/10: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37442: 01/12/11: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37484: 01/12/12: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
46420: 02/08/28: Re: Altera Quartus II problems
47566: 02/09/29: design multiplier
102787: 06/05/20: Signal 2 clocks long but only one clock possible
102819: 06/05/21: Re: Signal 2 clocks long but only one clock possible
102986: 06/05/24: Re: Signal 2 clocks long but only one clock possible
103002: 06/05/24: Re: Signal 2 clocks long but only one clock possible
108026: 06/09/04: Re: Please help me with (insert task here)
109213: 06/09/21: Re: Dell Laptop for Embedded Work
109279: 06/09/22: Re: Dell Laptop for Embedded Work
109306: 06/09/23: Re: IBM Thinkpads, used
Dennis Binder:
61844: 03/10/14: problem with XC18v01 and Spartan XCS20XL
61927: 03/10/15: Re: problem with XC18v01 and Spartan XCS20XL
Dennis Garcia:
15443: 99/03/24: Booth or Wallace Trees Multipliers
77796: 05/01/17: FPGA SCSI controller
Dennis Krupp:
21338: 00/03/17: Is there a cheaper alternative to ByteblasterMV?
Dennis Maasbommel:
55434: 03/05/08: Modelsim generating (Sigsegv BadPointer Access)-error on winXP
55750: 03/05/18: Modelsim generating (Sigsegv BadPointer Access)-error on winXP
55800: 03/05/20: problem with modelsim 5.7d on winXP system
Dennis McCrohan:
20945: 00/02/29: Re: Xilinx Abel Problems
20943: 00/02/29: Re: XABEL State Machines?
28373: 01/01/10: Re: Alliance for Linux
31297: 01/05/17: Re: xplaopt.exe - Application error
32120: 01/06/14: Re: Xilinx webpack annoyances (long and whiny)
32810: 01/07/09: Re: Undocumemted Xilinx Tools
33401: 01/07/25: Re: ModelSim and Cygwin
36686: 01/11/15: Re: Xpower and vcd files
38237: 02/01/09: Re: please tell me how to solve xilinx error xml
42746: 02/05/01: Re: Xilinx: delete file problem
44805: 02/07/01: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44918: 02/07/05: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
46377: 02/08/27: Re: Any FSM optimizer?
46403: 02/08/28: Re: Any FSM optimizer?
49506: 02/11/13: Re: jedec
49654: 02/11/18: Re: cpld pin configuration is wrongly assigned
51427: 03/01/13: Re: from ABEL/PLDs to VHDL&VeriLog/FPGAs
51732: 03/01/20: Re: Parsing Xilinx Timing Reports
52910: 03/02/25: Re: ABEL Help!
57321: 03/06/27: Re: Xlilin xc9572XL Default register values
58537: 03/07/25: Re: Should I use ABEL?
64191: 03/12/19: Re: predictable timing for xilinx cpld?
69050: 04/04/26: Re: Xilinx CPLD - FSM - one hot - lost token...
Dennis Morel:
4403: 96/10/24: Synplicity vs. FPGA Express
Dennis O'Connor:
28288: 01/01/05: Re: Nondeterministic FSMs in hardware?
Dennis O'Connor~:
2572: 96/01/04: Re: [q][Reverse Engineering Protection]
Dennis Ritchie:
146157: 10/03/07: Re: using an FPGA to emulate a vintage computer
Dennis Ruffer:
111835: 06/11/10: Quartus download problem?
112249: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112284: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
Dennis Scott:
29818: 01/03/12: Re: IP Cores, Megacores
29896: 01/03/16: Re: IP Cores, Megacores
Dennis Sneijers:
46965: 02/09/13: Re: FPGA comes with a DAC?
47340: 02/09/24: upcoming trened: analogue Fpga's?
47406: 02/09/25: Re: upcoming trend: analogue Fpga's?
Dennis Yelle:
365: 94/10/30: Metastable Immune? (Was: High Bus Drive (24mA) FPGAs/CPLDs?)
3702: 96/07/17: Re: Hardware sort?
Dennis Yurichev:
114591: 07/01/19: Altera EP2S60 rebooting itself
115102: 07/01/31: Graphics demo using FPGA?
142769: 09/08/31: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
145043: 10/01/21: FPGA farm
150422: 11/01/19: Prime number testing on FPGA
<deray@pacbell.net>:
9228: 98/03/03: seeking lead fpga designer
Dereck:
34604: 01/08/30: XCV800 : Jbits
34605: 01/08/30: Jbits: more info required
34671: 01/09/02: Virtex Architecture: Interconnect
34790: 01/09/07: Re: Virtex Architecture: Interconnect
34791: 01/09/07: Virtex: Interconnect Structure
36072: 01/10/27: Jbits 2.0.1: BoardScope
Dereck Fernandes:
55732: 03/05/17: Place and Route tool : PAR
Derek:
115081: 07/01/30: Re: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations
derek:
90408: 05/10/12: Re: Using the BSCAN primitives
91845: 05/11/15: Re: Need some help with interfacing spartan III to a computer...
91846: 05/11/15: Re: BRAMs readback
91850: 05/11/15: Re: Using JTAG cable for general comms
Derek B. Noonburg:
70: 94/08/08: Re: How pricey is FPGA development?
Derek Chang:
2219: 95/11/03: Re: FPGAs as a substitute for glue logic?
Derek Coppen:
282: 94/10/12: Re: Xilinx configuration
Derek Gladding:
90168: 05/10/06: Re: ise (lin64) and debian
90559: 05/10/16: Re: CPLD design software under WINE?
Derek Palmer:
632: 95/01/24: Re: pci source code
1000: 95/04/11: Re: Neocad merges with Xilinx
12158: 98/10/01: Re: Design Security Question
12273: 98/10/07: Re: Synthesis: Exemplar or Synopsys
129872: 08/03/07: Re: Anyone to open "FPGA museum" ? Here is first item :)
Derek Shiels:
52655: 03/02/18: Montgomery Bit-serial multiplier
Derek Simmons:
64010: 03/12/11: Programming Altera MAX 7000E
69807: 04/05/20: Altera LP4 Need Help With Device Drivers and Setting Up
69991: 04/05/26: Re: Altera LP4 Need Help With Device Drivers and Setting Up
70002: 04/05/26: Re: Altera LP4 Need Help With Device Drivers and Setting Up
71788: 04/07/30: What has happened to www.free-ip.com?
71818: 04/07/31: Virtual Computer Corporation (VCC) Virtual Workbench VW300
71912: 04/08/03: Re: VGA Signals
72045: 04/08/06: Power Supply for Xilinx FPGA
72217: 04/08/11: Primitve 3D Graphics Library
72393: 04/08/17: Re: New cache
73447: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
74410: 04/10/10: Re: Newbie, Altera vs Xilinx
74448: 04/10/11: Re: low cost MPEG4 codec (from Atmel )
74602: 04/10/14: Re: low cost MPEG4 codec (from Atmel )
74228: 04/10/06: Re: I need help for Xilinx Demo Board (XC40xx-PC84
75565: 04/11/09: Re: What was the first FPGA?
75612: 04/11/10: Re: Research Project Re: Graphics Processor
75614: 04/11/10: Re: Research Project Re: Graphics Processor
75768: 04/11/14: Re: Research Project Re: Graphics Processor
75816: 04/11/15: Re: Soft Processor Core
97692: 06/02/26: Re: VGA specification
97730: 06/02/26: Re: VGA specification
97767: 06/02/27: Re: Combinatorial Division?
97886: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
98041: 06/03/03: Re: How do I make dual-port RAM from single port RAM?
99644: 06/03/27: Re: Nios II - VHDL Source Code, Licensing
99799: 06/03/29: Re: Multithreaded NIOS II or other embedded cores
99851: 06/03/30: H.O.T. II - Virtual Computer Corp Hardware Object Technology Development System
99894: 06/03/30: Re: Multithreaded NIOS II or other embedded cores
101483: 06/05/01: Re: Quartus and source control
101531: 06/05/02: Re: Quartus and source control
103198: 06/05/28: Re: ADV7321 interlaced mode
105292: 06/07/19: Re: Synthesis Problems with Quartus II Version 6.x
108863: 06/09/18: Re: http://www.srisc.com ?
109065: 06/09/20: Re: Old vs. New FPGAs
109652: 06/10/02: Looking for HDL code for sin( a ) and x ** y Functions
109679: 06/10/03: Re: Looking for HDL code for sin( a ) and x ** y Functions
109680: 06/10/03: Re: Looking for HDL code for sin( a ) and x ** y Functions
109682: 06/10/03: Re: Looking for HDL code for sin( a ) and x ** y Functions
109684: 06/10/03: Re: Looking for HDL code for sin( a ) and x ** y Functions
110532: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
110548: 06/10/17: Re: FPGA + GSM cores
110671: 06/10/19: Re: Fastest ISE Compile PC?
111774: 06/11/09: Re: New Quartus 6.1 is multi-threaded
112189: 06/11/17: Re: Stratix-III announced
112698: 06/11/27: Re: nios2 toolchain sources
113054: 06/12/05: First Look at QuartusII 6.1
113065: 06/12/05: Re: First Look at QuartusII 6.1
113091: 06/12/06: Re: Altera starter kits
114151: 07/01/05: Re: iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
114335: 07/01/11: Re: arbitrator
114463: 07/01/16: Re: microcode in verilog?
116064: 07/02/28: Re: How to implement pipeline in this case?
116996: 07/03/21: Re: Austin the Altera Mole
118189: 07/04/19: Altera MPM7064LC84 vs EPM7064LC84
135602: 08/10/09: Re: Those FPGA boards
136968: 08/12/16: Altera Quartus II - 64 bit?
145729: 10/02/21: Re: State machines in Quartus
145731: 10/02/21: Re: using an FPGA to emulate a vintage computer
145732: 10/02/21: Looking for Ultimate RISC/MISC that runs LINUX Website
147251: 10/04/20: Re: Need to run old 8051 firmware
147284: 10/04/21: Re: Quartus II under Windows7?
147756: 10/05/21: Re: can I do image processing using 8bit color output FPGA board?
Derek Stewart:
8035: 97/11/10: Re: FPGA basics please ?
12104: 98/09/29: Re: I2C controller references needed!
Derek Wallace:
47347: 02/09/24: Xilinx: Marking some latches for pass-thru timing
48337: 02/10/16: SystemACE MPM: problems and poor performance of iMPACT software
48783: 02/10/24: VirtexII: using VCCO at 1.35 for CMOS type interface
141663: 09/07/02: Re: How to keep documentation of control and status registers and
Derek Young:
68219: 04/03/30: Re: rs232 interface on nios
68691: 04/04/14: Re: Yet Another Altera Online Support Is USELESS Rant...
DerekSimmons@FrontierNet.net:
81850: 05/04/02: Re: Xbox , chip mod & CPLD
82372: 05/04/11: Re: Verilog examples???
82861: 05/04/18: Re: Altera logic programmer card
83225: 05/04/26: Re: PCI plug n play and Graphics card implementation
83226: 05/04/26: Re: PCI plug n play and Graphics card implementation
83316: 05/04/27: Re: PCI plug n play and Graphics card implementation
90368: 05/10/11: Re: converting 12v signal to 3.3v
91150: 05/10/31: Re: Mitrion-C
91601: 05/11/09: Re: old xilinx components
93183: 05/12/15: Re: D FLIP -FLOP
93336: 05/12/20: Re: real-time compression algorithms on fpga
94164: 06/01/06: Re: FPGA -> ASIC`
96626: 06/02/07: Looking for information on SGRAM and GDDR
<DerekSimmons@FrontierNet.net>:
77203: 04/12/29: Altera NIOS II/Stratix II vs Xilinx Products
77208: 04/12/29: Re: Altera NIOS II/Stratix II vs Xilinx Products
77259: 05/01/02: Re: Altera NIOS II/Stratix II vs Xilinx Products
77974: 05/01/21: Re: Out of memory error : XPS, microblaze, EDK
77992: 05/01/21: Re: Out of memory error : XPS, microblaze, EDK
79457: 05/02/19: Re: VGA core
79489: 05/02/19: Re: hdl:lament
79517: 05/02/20: Re: why are PCI-based FPGA cards so expensive ?
79734: 05/02/23: Re: Frustrated with Altera
79747: 05/02/23: Re: Frustrated with Altera
79837: 05/02/24: Re: Implementing Multi-Processor Systems in FPGAs
79895: 05/02/25: Re: Implementing Multi-Processor Systems in FPGAs
80023: 05/02/28: Re: packages(2)
80464: 05/03/06: Re: DCT in FPGA
80945: 05/03/14: Re: Question from Newbie about FPGAs
81222: 05/03/19: Re: One-hot statemachine design problems
81299: 05/03/21: Re: Xilinx ISE 7.1 - Can this get any worse?
81338: 05/03/21: Re: Xilinx ISE 7.1 - Can this get any worse?
89425: 05/09/14: Looking for a DIgital Systems book with JPEG example code
<derekwallace1@my-deja.com>:
23361: 00/06/23: Defining a reset concept for VirtexE
<deroberts@my-deja.com>:
18009: 99/09/23: Re: Reset signal and Altera's FPGAs
18297: 99/10/13: Re: Can't detect Flex 10K Altera device through JTAG port
18712: 99/11/09: Re: AMCC 5933 Woes
18981: 99/11/23: Re: Altera JAM
19097: 99/11/29: Re: HDL editor?
19323: 99/12/14: Re: MAX7256A dies during ICP
Derren Crome:
17973: 99/09/20: Problems with Lattice download
43357: 02/05/20: Using Impact with XCR5064 coolrunner?
derrick:
4636: 96/11/23: flex 800 configuration
7927: 97/10/30: Help about ALTERA FPGA!!
Derrick Cheng:
44253: 02/06/14: Xilinx newest version?
44944: 02/07/07: ModelSim License problem
des00:
86632: 05/07/01: Avnet V4 - XC4VLX25
86827: 05/07/07: Re: about fast adder
86836: 05/07/07: Re: about fast adder
88476: 05/08/18: Re: Synthesis : HowTo Preserve FSM encodings
descoubes:
77874: 05/01/19: video decoder for altera dev. board
77904: 05/01/20: Re: video decoder for altera dev. board
DeSheng Li:
53975: 03/03/28: Problems useing ISE4.2
design:
78666: 05/02/05: ambiguous number of BLOCK RAM in SPARTAN3
80896: 05/03/14: FPGA programming
80950: 05/03/14: Re: FPGA programming
81147: 05/03/18: Re: Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
81690: 05/03/29: Driving two DCM with same clock input pad.
81751: 05/03/30: Re: Driving two DCM with same clock input pad.
83492: 05/05/01: cross clock timing constraints
83519: 05/05/02: Re: cross clock timing constraints
designer_india:
141648: 09/07/02: I/O Pads in ASIC
Designfreek:
88477: 05/08/18: PLL
89214: 05/09/07: pll
89851: 05/09/28: Internal clock for apex20ke
Desilva:
29040: 01/02/03: faq or just basic info
Desmond A. Kirkpatrick:
768: 95/02/27: Re: [shin]Synthesis tools ported to Linux available???
Detlef Justen:
4134: 96/09/17: How can I make my XILINX design faster?
<deunhido@gmail.com>:
98684: 06/03/14: Re: Why does Xilinx hate version control?
104574: 06/06/29: Re: Spartan3e starter kit vga mod
104597: 06/06/30: Re: Spartan3e starter kit vga mod
dev:
38094: 02/01/04: help with older xilinx fpga's
devas:
152775: 11/10/21: Re: FPGA development
Devas:
159069: 16/07/24: Re: Mod-24: The State of High-Level Synthesis in 2016
159072: 16/07/25: Re: Mod-24: The State of High-Level Synthesis in 2016
devb:
102530: 06/05/17: ANNC: ISE/WebPACK 8.1i tutorial available
117088: 07/03/22: Re: CRC check error
<devb@xess.com>:
90251: 05/10/07: Re: Xilinx WebPack and command line
90282: 05/10/07: Re: Xilinx WebPack and command line
90835: 05/10/22: Re: .dat to .bit
94686: 06/01/16: Re: Displays an image in the XS Board RAM on a VGA monitor
<developers@tizek.com>:
30553: 01/04/16: Tizek.com is in dire need of a development team...
Devesh Kishore:
154813: 13/01/14: need help in writing VHDL code for modified booths algorithm using
deviant:
22020: 00/04/12: Word up
devices:
109372: 06/09/25: Re: I2C slaves needed
110428: 06/10/15: Nand Flash programming times
110489: 06/10/16: Re: Nand Flash programming times
115203: 07/02/02: Re: circle generation algorithm
121266: 07/06/29: Latches
121276: 07/06/29: Re: Latches
121277: 07/06/29: Re: Latches
122075: 07/07/19: Re: Latches
122186: 07/07/23: On I2C protocol
122195: 07/07/23: Re: On I2C protocol
122196: 07/07/23: Re: On I2C protocol
122217: 07/07/24: Re: On I2C protocol
122218: 07/07/24: Re: On I2C protocol
122240: 07/07/24: Re: On I2C protocol
122530: 07/07/30: Re: Help on TRB_DC2 Camera module interface
122541: 07/07/30: Re: Help on TRB_DC2 Camera module interface
123945: 07/09/07: SRAM on Cyclone Devices
123969: 07/09/08: Re: SRAM on Cyclone Devices
134074: 08/07/24: SD Card Controller
134088: 08/07/24: Re: SD Card Controller
134094: 08/07/25: Re: SD Card Controller
134104: 08/07/25: Re: SD Card Controller
134152: 08/07/28: Re: SD Card Controller
134314: 08/08/06: Re: SD Card Controller
Deville:
42649: 02/04/30: power supply sequencer for Virtex II
Devlin:
100988: 06/04/22: How to avoid this waring in ISE 8.1?
102140: 06/05/10: How can I deal with the output signal in testbech?
102141: 06/05/10: How can I get internal signal in modelsim.(Xlinx ISE),timing-simulation
102161: 06/05/11: Re: How can I deal with the output signal in testbech?
140691: 09/05/21: FC vore support problem
<devlinsearchgroup@usa.net>:
13566: 98/12/09: FAE Field ApplicationS Engineers
<devnull@mighty.morphism.org>:
49352: 02/11/10: CLB numbers for various ops?
devre:
99854: 06/03/30: problem block ram modelsim
Dexin Li:
26103: 00/10/03: test
dexter:
77264: 05/01/02: Re: Verilog /DIP Switch Question....
dexue:
84934: 05/06/01: Re: why can't i use opb_spi core in EDK6.3?
85703: 05/06/14: Re: question - NGC & NGO files & integration
85704: 05/06/14: Re: Viewing internal signal in Modelsim (post P&R)
87497: 05/07/25: Re: DCM.
113185: 06/12/07: Re: FPGA+Ethernet
<dez.ambrose@gmail.com>:
109891: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
<dfab1954@gmail.com>:
157985: 15/06/10: Re: Free timing diagram drawing software
159542: 16/12/07: Re: The TimingAnalyzer (Timing Diagrams and Analysis)
<dfdfdfdf@gmail.com>:
81225: 05/03/19: FPGA and Verilog question
dfg:
32197: 01/06/19: Re: ee
Dfrancis@ihug.com.au:
17654: 99/08/19: Money
<dfrevele@li.net>:
10588: 98/06/03: Foundation M1.4 functional simulation problems
10946: 98/07/06: Spartan S30 DOUT/SGCK4 pin
10947: 98/07/06: Configure with BIT file
18656: 99/11/05: Re: Xilinx M2.1i SP2?
18837: 99/11/18: Re: Xilinx M2.1i SP2?
DFT Specialist:
53960: 03/03/28: Re: Programming fpga
54729: 03/04/16: Re: Dynamic Reconfigurable FPGAs
Dftxpert:
5086: 97/01/22: GATEFIELD from Zycad
dfx:
81469: 05/03/24: Re: Problem writing Pinouts on Webpack > Pin assignment accuracy
82294: 05/04/10: Re: rules to assign pins to FPGA?
82300: 05/04/10: Re: vhdl and clock-pin
89116: 05/09/06: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89251: 05/09/09: Re: Disconnect the FPGA I/O pads from the outside world
dfx2001:
36310: 01/11/06: Counter detects both edge of clock?? (verilog)
DG_1:
38400: 02/01/13: Re: MSP430 + Xilinx via JTAG
38449: 02/01/15: Re: MSP430 + Xilinx via JTAG
38451: 02/01/15: Re: MSP430 + Xilinx via JTAG
38685: 02/01/22: Re: Atmel FPGA configuration memory?!
38852: 02/01/26: Re: MSP430 + Xilinx via JTAG
DG_1 (@remove.this):
19791: 00/01/12: Re: hardware related questions
<DGerimi@googlemail.com>:
120002: 07/05/30: Building Gradually Expertise on VHDL/Verilog Design
<DGILL@priacc.com>:
4125: 96/09/16: manchester clock recovery
dgjk:
36715: 01/11/16: unsetenv LANG
dgreig:
147406: 10/04/26: Inferring mutipliers
147410: 10/04/26: Re: Inferring mutipliers
147428: 10/04/27: Re: Inferring mutipliers
147440: 10/04/27: Re: Inferring mutipliers
147467: 10/04/28: Re: Inferring mutipliers
148462: 10/07/26: Re: Altera EDA Netlist Writer
148463: 10/07/26: Re: Altera EDA Netlist Writer
148497: 10/07/28: Re: Embedded Multipliers in Altera Cyclone
149068: 10/09/28: Re: FPGA For Image Processing[Economical]
149215: 10/10/08: Re: Driving a design via TCP/IP
150934: 11/02/23: Re: Programming FPGAs with Quartus under Linux
152827: 11/10/26: Modelsim on windoz save settings in a file rather than registry
152838: 11/10/26: Re: Modelsim on windoz save settings in a file rather than registry
<dgreig@ieee.org>:
161169: 19/02/10: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
DGW:
61909: 03/10/15: simple project needed
62116: 03/10/20: Waveform Interpreted
62144: 03/10/21: BIT files
DH:
140452: 09/05/13: Open source processors
140581: 09/05/18: Re: Open source processors
dh2006:
112580: 06/11/25: Double buffering
dhaanya nair:
66921: 04/02/29: help needed for NCO code in VHDL
67179: 04/03/08: need help for LOOP filter design in VHDL
dhanashree:
63995: 03/12/11: Which PCI version on my motherboard
<dharmesh_halani@my-deja.com>:
22196: 00/05/01: real clock generation
Dhivya:
91541: 05/11/08: Need some help with interfacing spartan III to a computer...
<dhruvakshad@gmail.com>:
100544: 06/04/11: gemac
108175: 06/09/06: NON-CLK pins failed to route using a CLK template
108291: 06/09/07: Re: NON-CLK pins failed to route using a CLK template
108316: 06/09/07: Re: NON-CLK pins failed to route using a CLK template
108342: 06/09/08: Negative slack
108377: 06/09/09: Re: Negative slack
109280: 06/09/22: DCM for virtex II pro
109282: 06/09/22: Re: DCM for virtex II pro
109289: 06/09/23: DCM virtex II pro
109290: 06/09/23: Re: DCM virtex II pro
109365: 06/09/25: Re: DCM virtex II pro
109559: 06/09/28: state machine
109725: 06/10/04: ISE timing errors
109735: 06/10/04: Re: ISE timing errors
109736: 06/10/04: Re: ISE timing errors
109785: 06/10/05: Re: ISE timing errors
109787: 06/10/05: Re: ISE timing errors
114420: 07/01/15: benchmarks for vhdl
116489: 07/03/10: ddr sdram controller
116730: 07/03/16: Re: ddr sdram controller
116732: 07/03/16: MXE compilation error
122130: 07/07/19: Library unit VPKG is not available in library UNISIM
DHULST:
23483: 00/06/27: Electronic Drivers for Brushless D C Motors
Di Pascale:
80593: 05/03/08: Using BUFG with internally generated clocks
80653: 05/03/09: Re: Using BUFG with internally generated clocks
DialTone:
125394: 07/10/24: Re: LEDs, buttons and LCD
Dick:
128120: 08/01/15: gaussian filter in Altera FPGA
128284: 08/01/20: Re: gaussian filter in Altera FPGA
dick:
124064: 07/09/11: Re: Uses of Gray code in digital design
Dick Ginther:
1435: 95/06/22: Atmel 6005 Experiences
10785: 98/06/18: little endian <-> big endian
33570: 01/07/30: i2c master
45226: 02/07/16: XC2V1500 & XC2V2000 availabilty
Dick Gray:
2343: 95/11/21: Re: NeoCAD and AT&T vs. Xilinx
Dick Maio:
23980: 00/07/19: FPGAs in AC Magnetic Field
Dick Wilmot:
5360: 97/02/10: Re: DES Challenge
didaSofi:
157750: 15/03/01: IIC in microblaze
157773: 15/03/12: code c of HM5883
Didi:
93953: 06/01/03: Re: RTL for Z8000 series CPU?
115477: 07/02/12: Understanding something in a bsdl file
118044: 07/04/16: Debug monitor for Freescale MPC5200
119166: 07/05/14: Re: Xilinx software quality - how low can it go ?!
120718: 07/06/14: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120728: 07/06/14: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
126228: 07/11/17: Coolrunner in system programming - XAPP0058 - viable?
126238: 07/11/17: Re: Coolrunner in system programming - XAPP0058 - viable?
126239: 07/11/17: Re: Coolrunner in system programming - XAPP0058 - viable?
126249: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
126268: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
126272: 07/11/18: Re: Coolrunner in system programming - XAPP0058 - viable?
126280: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126297: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126315: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126316: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126318: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126320: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126326: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126327: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126328: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126331: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126362: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126364: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126370: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126375: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126386: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126390: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126397: 07/11/21: Re: Coolrunner in system programming - XAPP0058 - viable?
126641: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126647: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126664: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126690: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126698: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
132814: 08/06/07: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
134407: 08/08/09: Coolrunner programming - best way?
144063: 09/11/09: XPLA3 coolrunner programming tool?
144089: 09/11/10: Re: XPLA3 coolrunner programming tool?
144090: 09/11/10: Re: XPLA3 coolrunner programming tool?
144093: 09/11/10: Re: XPLA3 coolrunner programming tool?
144097: 09/11/11: Re: XPLA3 coolrunner programming tool?
144114: 09/11/11: Re: XPLA3 coolrunner programming tool?
144117: 09/11/11: Re: XPLA3 coolrunner programming tool?
146932: 10/04/02: XPLA3 Coolrunner - Abel uses twice the needed cells, why?
146935: 10/04/02: Re: XPLA3 Coolrunner - Abel uses twice the needed cells, why?
149535: 10/11/02: Re: LVDS-based LCD Display, Minimum Clock Rates
<didier_ja@yahoo.com>:
106589: 06/08/15: SPI c source code to shift register from apex board..
Diedricher:
34400: 01/08/23: Testbench book
Diego Lillo:
90189: 05/10/06: Re: Xilinx ISE 7.1i file management
diei-unipg-it:
28363: 01/01/10: VIRTEX : pad location
Dieter Keldenich:
62086: 03/10/18: Altium DXP for designing Xilinx FPGA
62148: 03/10/20: Re: Altium DXP for designing Xilinx FPGA
digari:
36183: 01/11/01: Altera Local Routing
36325: 01/11/06: Re: Registered as well as unregistered outputs?
44334: 02/06/18: hierarchy in Altera FPGAs
52681: 03/02/19: Gate boosting
52772: 03/02/21: Re: Gate boosting
70082: 04/06/01: tri-state in altera
70991: 04/07/04: Re: MAP: what are route-through look up tables
70992: 04/07/04: Re: new Lattice FPGAs vs Cyclone and SpartanIII
74795: 04/10/19: direction of carry and shift chains in xilinx & Altera
76364: 04/11/30: Re: Xilinx Virtex 4 question
76365: 04/11/30: Re: 99% Utilisation !
<digari@dacafe.com>:
79578: 05/02/21: Hardcopy Vs ASIC
79673: 05/02/22: Re: Hardcopy Vs ASIC
79783: 05/02/24: Re: Hardcopy Vs ASIC
79994: 05/02/27: Re: spartan 3 vs virtex 2
digi:
79687: 05/02/23: interrupt handler problem
79850: 05/02/25: re:interrupt handler problem
79931: 05/02/26: EDK IPIF FIFO Problems
80066: 05/03/01: FIFO Problem
80146: 05/03/02: Error on launch the Simulator
80337: 05/03/04: re:Error on launch the Simulator
80612: 05/03/09: re:EDK service packs?
80613: 05/03/09: re:PLB IPIF + Master + DMA
81755: 05/03/31: re:IPIF
81797: 05/04/01: IPIF user logic vs. Component insertion
81799: 05/04/01: EDK IPCore insertion
81912: 05/04/04: re:IPIF user logic vs. Component insertion
81913: 05/04/04: re:EDK:Question regarding opb_uart
82055: 05/04/06: re:EDK-Creating new peripheral
82056: 05/04/06: re:IPIF
82567: 05/04/14: re:Simualtion of Rocket I/O MGT in ModelSim XE
83620: 05/05/04: re:VHDL help with adding modules
83621: 05/05/04: re:OPB Intc - HELP !!!!
83622: 05/05/04: re:Simulating custom peripherals
84608: 05/05/23: re:Handling Interrupt
85169: 05/06/06: re:opb bram controller
85286: 05/06/07: re:Upgrading the EDK from 6.3
85437: 05/06/09: re:How to add a lib to the core used
86158: 05/06/22: re:How to reset a PLB/OPB Peripheral
Digi Suji:
136843: 08/12/08: Xilinx UNISIM/SIMPRIM libraries
136863: 08/12/09: Re: Xilinx UNISIM/SIMPRIM libraries
137001: 08/12/18: Xilinx BRAM and Synthesis
137017: 08/12/18: Re: Xilinx BRAM and Synthesis
137078: 08/12/22: Synthesis Problem
137092: 08/12/22: Re: Synthesis Problem
137190: 08/12/31: 7 Segment LED Display - BASYS board
137378: 09/01/13: Digilent BASYS Board and breadboard connections
137451: 09/01/17: Spartan 3E reset problem
137457: 09/01/18: Re: Spartan 3E reset problem
137458: 09/01/18: Re: Spartan 3E reset problem
137892: 09/02/02: fpga reset
137940: 09/02/02: Re: fpga reset
137978: 09/02/03: Re: fpga reset
138823: 09/03/11: I2C EEPROM
139602: 09/04/06: Re: I2C EEPROM
<digi.megabyte@gmail.com>:
131688: 08/04/29: floating point and logarithm in vhdl+xilinx
Digilent RO:
154368: 12/10/16: DIGILENT DESIGN CONTEST 2013
digital designs:
135075: 08/09/13: Xilinx FFT core configured in natural order
Digital EE:
41507: 02/03/31: Orcad Sch f/Xilinx Spartan II
42023: 02/04/13: Xilinx FPGA load - XAPP 502
Digital Mike:
119523: 07/05/21: DDR Controller Blue
119530: 07/05/22: Re: DDR Controller Blue
digitaljanitor:
145966: 10/03/02: Help with avoiding ground-loops on my PCB+external
DigitalSignal:
82974: 05/04/20: ATA FPGA IP Core
digiviki:
140190: 09/05/02: Re: ERROR:MapLib:979
DIGONNET Daniel:
89405: 05/09/14: TAP controller
Digvijay Raghavan:
72038: 04/08/06: Re: What is the future of superconducting circuits
73157: 04/09/14: Re: New to Xilinx Software - help with downlaod
dila77:
149746: 10/11/22: minimum clock period of a combinational circuit
149777: 10/11/24: Re: minimum clock period of a combinational circuit
Dilan:
127961: 08/01/11: setup ETHERNET UDP link suing spartan-3E starter kit
130144: 08/03/17: implementing ethernet FCS code in verilog
130205: 08/03/17: Re: implementing ethernet FCS code in verilog
DILEEP:
51749: 03/01/20: Ram bits for Registers
dilip:
126032: 07/11/13: implementing MAC protocols on fpga
126053: 07/11/13: Re: implementing MAC protocols on fpga
126435: 07/11/22: converter
Dilip V. Sarwate:
43731: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
dim_sar:
149385: 10/10/20: dma for altera fpga
Dima:
117654: 07/04/05: Memory Interface Recommendation for ML410 Design
117816: 07/04/10: Please HELP: timing problems on Virtex-4FX
117847: 07/04/11: Re: Please HELP: timing problems on Virtex-4FX
117905: 07/04/12: Re: Please HELP: timing problems on Virtex-4FX
119179: 07/05/14: Timing constraint question
119181: 07/05/14: Re: Timing constraint question
119184: 07/05/14: Re: Timing constraint question
119236: 07/05/15: Re: Timing constraint question
dima2882:
83307: 05/04/27: XC9500 - creating RS485 Mux
85361: 05/06/08: Re: ISE/EDK 6.3 vs 7.1...
85363: 05/06/08: QuickLogic FPGA : In-Circuit Programming
88915: 05/08/31: ZIF press-fit socket for QFP FPGA packages
Dimitri Turbiner:
85226: 05/06/06: Little Problem with EDK 7.1 (Errors while compiling)
85467: 05/06/09: Question for Alex Gibson
88591: 05/08/23: re:Good SystemC tutorials or books?
88678: 05/08/25: Library of eBooks on FPGA's and other programming stuff
Dimitrij Klingbeil:
161376: 19/06/14: Re: bare-metal ZYNQ
161384: 19/06/15: Re: bare-metal ZYNQ
Dimitris Kontodimopoulos:
66926: 04/03/01: Configuring Altera FLEX10KE using EPC2 device
Dimitris Phoukas:
1860: 95/09/11: ATMEL WWW site?
2118: 95/10/17: Library of Parametrized Modules info
Dimitris Theodoropoulos:
50226: 02/12/05: memory in VHDL
50395: 02/12/10: Synopsys MemPro
54319: 03/04/08: Hammond FPGA board
Dimitry Yegorov 1598864168:
37997: 01/12/29: How do I use Altera's PLL megafunction to multiply some frequency ?
dimmy:
51987: 03/01/28: Re: GNU C for custom processor
dimon1977:
90982: 05/10/26: state machine with 2 clock's
<dimtey@gmail.com>:
115294: 07/02/06: Re: xc3sprog
<dimtey@moc.liamg>:
115604: 07/02/14: Re: Xilinx ISE 8.2
116913: 07/03/20: Virtex-II block RAM problem
dimtsios@ix.netcom.com:
122438: 07/07/27: Re: Altera or Xilinx
122693: 07/08/03: Re: Altera-Xilinx interfacing SERDES transcievers problem
122941: 07/08/11: Re: DDR/DDR2 controller - core
Din:
46179: 02/08/21: Multiple Nios ...
Dinalight .com:
144571: 09/12/15: Re: very wide counter (42-bit)
Dines Justesen:
26163: 00/10/06: Floorplanning
26259: 00/10/10: Re: ModelSim XE/Starter speed issues
26333: 00/10/12: Re: LUT to CLB assignment
26371: 00/10/13: Re: const coeff multiplier w/ LUTs
26466: 00/10/17: Re: ModelSim XE/Starter speed issues
26467: 00/10/17: Re: ModelSim XE/Starter speed issues
27372: 00/11/20: Re: In the news
43143: 02/05/14: Re: Altera/Quartus II: unconditional loop?
43185: 02/05/15: Re: Altera/Quartus II: unconditional loop?
Dinesh:
39510: 02/02/12: spi4-02.0
Dinesh Bhatia:
42: 94/08/02: Re: PPR vs NeoCAD (vs. APR)
<dinesh@wsi.ece.uc.edu>:
40: 94/08/02: Re: PPR vs NeoCAD (vs. APR)
<dineshvc@gmail.com>:
121163: 07/06/27: Adding opb AC97 Controler in Xilinx EDK 8.2
Dino:
diogratia:
123313: 07/08/23: Re: Need to force all signals in a design to a known value at start of simulation
129828: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129829: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
134133: 08/07/27: Re: Creating new operators
134158: 08/07/28: Re: Creating new operators
Dion Kriel:
32142: 01/06/15: Re: Using the Triscend A7 UART
Dionissis Efstathiou:
33142: 01/07/18: Altera's MAX devices configuration
40715: 02/03/13: Universal FPGA Programmer
Dioptre:
100831: 06/04/18: Multiple Independent Circuits on a Single FPGA
Diping:
40657: 02/03/12: Pins levels on Spartan.
Dipl.-Ing. Andreas Schmidt:
33937: 01/08/08: Digital Design/Systems/CAD engineer looking for a job in CA (Fremont
64745: 04/01/13: Re: Anybody know what the REAL story is?
Dipl.-Ing. D. Lenz:
3738: 96/07/23: Information on Actel
4382: 96/10/22: Searching Demoboard for Altera Flex8000
Dipl.-Ing. Hanns-Walter Schulz:
79883: 05/02/25: Can't create Bus-Tap in Xilinx' ECS
82636: 05/04/15: ISE Testbench/Schematic Generation ignores package
82783: 05/04/18: Re: ISE Testbench/Schematic Generation ignores package
dipu bhaskar:
55795: 03/05/19: 8253 vhdl code
<dipumisc@hotmail.com>:
115841: 07/02/21: Using Xilinx DCM FX output without DLL
116365: 07/03/07: using XIlinx impact in batch mode to generate EEPROM files
116747: 07/03/16: Re: using XIlinx impact in batch mode to generate EEPROM files
126565: 07/11/27: Xilinx IO leakage when not powered
Dirk:
66164: 04/02/13: Xilinx EDK and reference system opb_ssp1_v1_00_a
dirk:
85069: 05/06/03: Re: Altera's fast NIOS update service (o;
Dirk =?iso-8859-1?Q?S=FCtterlin?=:
42922: 02/05/07: Xilinx System Generator Simulation Problems
Dirk Bell:
71927: 04/08/03: Re: Best tool(s) for filter float->fixed->VHDL flow?
141765: 09/07/06: Re: How to interpret polyphase coefficients generated in MATLAB
141770: 09/07/07: Re: How to interpret polyphase coefficients generated in MATLAB
141793: 09/07/09: Re: How to interpret polyphase coefficients generated in MATLAB
142088: 09/07/23: Re: How to interpret polyphase coefficients generated in MATLAB
Dirk Brandis:
5826: 97/03/18: EDA tools
6196: 97/04/24: Escalade anyone?
Dirk Bruere:
18799: 99/11/17: Re: implementing TCP/IP on PLD
18801: 99/11/17: Re: implementing TCP/IP on PLD
18820: 99/11/17: Re: implementing TCP/IP on PLD
18821: 99/11/17: Re: implementing TCP/IP on PLD
18897: 99/11/20: Re: implementing TCP/IP on PLD
18973: 99/11/23: Re: implementing TCP/IP on PLD
19027: 99/11/24: Re: implementing TCP/IP on PLD
19053: 99/11/26: Re: implementing TCP/IP on PLD
Dirk Bruere at Neopax:
93993: 06/01/04: Re: Why 'a plurality of N' must be used for 'N' in patent claims
95103: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95140: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95144: 06/01/21: Re: OT:Shooting Ourselves in the Foot
Dirk Dannhäuser:
8198: 97/11/26: Q: Source code needed
Dirk Duesterberg:
7579: 97/09/24: CPLD devKIT for linux?
Dirk Dörr:
53002: 03/02/28: 10 MHz Clock out of 30 MHz
53056: 03/03/02: Re: 10 MHz Clock out of 30 MHz
58649: 03/07/30: Re: Parallel Port EPP in FPGA
Dirk Galda:
27008: 00/11/07: FFT LogiCore
27035: 00/11/08: Re: Anything wrong with Xilinx website?
Dirk Kautz:
28610: 01/01/18: Re: DSP->FPGA development board
Dirk Koch:
52476: 03/02/11: What is wrong with Altera Website?
138740: 09/03/06: Re: 1D or 2D Placement for dynamically partially reconfigurable
138813: 09/03/11: A Builder for Component-based and Partial Runtime Reconfigurable
139055: 09/03/19: Re: How to load an image onto system ace compact flash embedded on
139344: 09/03/27: Re: Dynamic reconfiguration in Spartan 3
139503: 09/04/01: Re: Dynamic reconfiguration in Spartan 3
139757: 09/04/12: Re: Getting efficient logic synthesis
139759: 09/04/12: Re: Don't understand the Partialmask option for partial reconfiguration
140120: 09/04/29: Re: hard macro basic clock reset question
141478: 09/06/25: Has anybody tried ISE for Virtex-6/Spartan-6?
141512: 09/06/26: Re: Virtex-6 shipping?
Dirk Munk:
30648: 01/04/20: What is a FPGA ?
Dirk Stroobandt:
13373: 98/11/30: SLIP'99 CFP (Workshop on System-Level Interconnect Prediction)
Dirk Sütterlin @ newsgroups:
44728: 02/06/28: variable decimation filter with rational sampling factors
Dirk Timmermann:
10034: 98/04/23: Re: Could you help me save CLB's?
Dirk Ziegelmeier:
63366: 03/11/20: Xilinx Microblaze SDRAM burst access
Dirk_Doerr:
50595: 02/12/13: Xilinx Startup Symbol / Global reset net
50688: 02/12/17: Xilinx FPGA PAR warning
50719: 02/12/18: Re: Xilinx FPGA PAR warning
dirnfir:
15189: 99/03/12: I want to learn about programmable logic.
DISACSON:
4935: 97/01/02: 6809 VHDL MODEL
disappointed:
9403: 98/03/09: Re: LARGE SELECTION OF FPGA BOARDS & KITS
9425: 98/03/12: Re: LARGE SELECTION OF FPGA BOARDS & KITS
discover:
<discussions@fpga.usenet>:
132564: 08/05/31: xilinx and jtag
132619: 08/06/03: Re: xilinx and jtag
disk:
22981: 00/06/07: Re: to make few modifications on a design
22986: 00/06/07: Re: Xilinx foundation Student Edition problem.
24499: 00/08/11: Re: what does 0.35 micron mean
24565: 00/08/14: Re: what does 0.35 micron mean
24705: 00/08/17: Re: what does 0.35 micron mean
25142: 00/08/28: Re: Problem instantiating Xilinx primitives in FPGA Express
25222: 00/08/31: Re: Latches
disq:
130814: 08/04/02: Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation
<ditiris@gmail.com>:
155804: 13/09/17: Legal Issues Reproducing Old CPU
155819: 13/09/20: Re: Legal Issues Reproducing Old CPU
<ditsdad@gmail.com>:
109741: 06/10/04: Re: Looking for HDL code for sin( a ) and x ** y Functions
DIVERSEG:
34619: 01/08/31: ISA(PC/104) BUS DECODE ASYNC or SYNC?
34648: 01/09/01: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
divya:
38033: 02/01/02: FPGA
38034: 02/01/02: FLOORPLANNING IN XILINX
Dix:
88956: 05/09/01: bare die (non packaged) FPGA, CPLD, controllers ?
89072: 05/09/05: Re: bare die (non packaged) FPGA, CPLD, controllers ?
89178: 05/09/07: Re: bare die (non packaged) FPGA, CPLD, controllers ?
DIYByteblaster:
62297: 03/10/24: programming Altera AS Configuration Device without Byteblaster II
62314: 03/10/26: bugfix
DJ:
64394: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64406: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64407: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
78337: 05/01/29: i need xilinx edk
Dj:
10491: 98/05/23: fpga, pld video interface
10784: 98/06/18: Fpga Video interface
11517: 98/08/21: Video 256 colors interface HELP!
11518: 98/08/21: Video 256 colors interface HELP!
11519: 98/08/21: Video 256 colors interface HELP!
11667: 98/08/30: Re: Video 256 colors interface HELP!
DJ Delorie:
76994: 04/12/18: Re: PCB construction for PCI
85393: 05/06/08: Re: linker script
96190: 06/01/31: Re: Xilinx Legal
101332: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101334: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
112682: 06/11/27: Re: nios2 toolchain sources
114008: 07/01/02: Re: Surface mount ic's
114016: 07/01/02: Re: Surface mount ic's
118244: 07/04/20: Re: Free Hardware
122828: 07/08/07: Re: New Xilinx forum.
127527: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127544: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
128708: 08/02/04: Re: 4-bit table look-up
128896: 08/02/08: My first verilog/cpld project
128912: 08/02/09: Re: My first verilog/cpld project
128914: 08/02/09: Re: My first verilog/cpld project
129008: 08/02/12: Re: My first verilog/cpld project
129711: 08/03/03: Re: "Use Multi-level Logic Optimization" -- Advanced Fitting option
129713: 08/03/03: Re: my Spartan-4 wishlist
129762: 08/03/05: Re: my Spartan-4 wishlist
130488: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
131066: 08/04/09: Re: Xilinx CPLD programming tool under Linux
133779: 08/07/14: Re: First CPLD project
137733: 09/01/28: Re: What software do you use for PCB with FPGA ?
137740: 09/01/28: Re: What software do you use for PCB with FPGA ?
137750: 09/01/28: Re: What software do you use for PCB with FPGA ?
137784: 09/01/29: Re: What software do you use for PCB with FPGA ?
137795: 09/01/29: Re: What software do you use for PCB with FPGA ?
137803: 09/01/29: Re: What software do you use for PCB with FPGA ?
137910: 09/02/02: Re: Selecting a starter FPGA board
141660: 09/07/02: Re: Sign up for Multimedia SoC project
142456: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142476: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142502: 09/08/13: Re: Spartan-6 Boards - Your Wish List
142525: 09/08/14: Re: Spartan-6 Boards - Your Wish List
142909: 09/09/07: Re: Spartan 3 loading from MCU slave serial problems
142941: 09/09/09: Re: ANN: Coding style guidance for FPGA memory
143720: 09/10/22: Re: CPLD/FPGA with Linux
146451: 10/03/18: Re: Xilinx only on Avnet now
147450: 10/04/27: Re: Question about PCB CAD for FPGA-based project
151440: 11/04/08: Re: Do people do this by hand?
157209: 14/11/04: Re: practical experience with GPL IP core in commercial product
157214: 14/11/04: Re: practical experience with GPL IP core in commercial product
157224: 14/11/05: Re: practical experience with GPL IP core in commercial product
157225: 14/11/05: Re: practical experience with GPL IP core in commercial product
157228: 14/11/05: Re: practical experience with GPL IP core in commercial product
157237: 14/11/06: Re: practical experience with GPL IP core in commercial product
157238: 14/11/06: Re: practical experience with GPL IP core in commercial product
157241: 14/11/06: Re: practical experience with GPL IP core in commercial product
157246: 14/11/06: Re: practical experience with GPL IP core in commercial product
157247: 14/11/06: Re: practical experience with GPL IP core in commercial product
157250: 14/11/08: Re: practical experience with GPL IP core in commercial product
157264: 14/11/10: Re: practical experience with GPL IP core in commercial product
157265: 14/11/10: Re: practical experience with GPL IP core in commercial product
157270: 14/11/11: Re: practical experience with GPL IP core in commercial product
157272: 14/11/12: Re: practical experience with GPL IP core in commercial product
158110: 15/08/10: Re: Finally! A Completely Open Complete FPGA Toolchain
160576: 18/04/17: Re: FPGA selection recommendation
160578: 18/04/18: Re: FPGA selection recommendation
django625:
36109: 01/10/30: Shift Registers with Xilinx Foundation 2.1
<djanisz@et.put.poznan.pl>:
97506: 06/02/23: altera max 7128s blanking
97532: 06/02/23: Re: altera max 7128s blanking
<djeasy22@gmail.com>:
157695: 15/02/04: Re: scanf problem in EDk 9.1i (Microbaze)
Djimm2:
6473: 97/05/27: Xmit data thru X-Checker of Xilinx 4000 series to program a Flash with it
6523: 97/05/30: Re: Xmit data thru X-Checker of Xilinx 4000 series to program a Flash with it
6524: 97/05/30: In circuit programming of flash with Xilinx devices??
6534: 97/05/31: Re: In circuit programming of flash with Xilinx devices??
6536: 97/06/01: In circuit programming of flash --->JTAG?
6557: 97/06/02: Re: In circuit programming of flash --->JTAG?
6742: 97/06/23: Gerhard Hoffmann... my own download program
djj08230:
108684: 06/09/15: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
139146: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139150: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139170: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139178: 09/03/22: Re: How big is my vhdl and am I approaching some size limitation on
139666: 09/04/08: Re: Two stage synchroniser,how does it work?
139951: 09/04/20: Re: FPGA lockup with pinout report view. was: fpga locks up with slow
139963: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
djley:
27224: 00/11/15: Xilinx Foundation Sudent Version 1.5
30412: 01/04/06: Xilinx conflict with Win95 and CPLD BGA's
32192: 01/06/18: Practical Xilinx Designer Lab Book 1.5 and version 2.1
DJohn:
47094: 02/09/17: C\C++ to VHDL Converter
Djohn:
47621: 02/10/01: DFT , Design For Test HELPPPPP
<djoshi@btinternet.com>:
117170: 07/03/25: help needed
117180: 07/03/26: Re: help needed
117182: 07/03/26: Re: help needed
117203: 07/03/26: Quartus warning messages reagarding timming and latchs
117250: 07/03/27: Re: help needed
dk:
134447: 08/08/11: Re: using the mex file model for xfft_v5 Xilinx core-generator
DK:
57430: 03/06/30: Cyclone vs Spartan-3
61361: 03/10/02: High-performance workstation
143085: 09/09/18: Re: Quartus top level entity name vs names of generated files
<dkarchmer@gmail.com>:
105328: 06/07/20: Re: corrupted data when accessing dual port bram in Cyclone II
108555: 06/09/12: Re: FPGA timing
112390: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112401: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112416: 06/11/21: Re: timing constraints
112637: 06/11/26: Re: query in constraining timing
112882: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
117024: 07/03/21: Re: gated clock
120494: 07/06/07: Re: Symbolic names for pll derived clocks in SDC file? (quartus)
120495: 07/06/07: Re: Symbolic names for pll derived clocks in SDC file? (quartus)
120541: 07/06/08: Re: TimeQuest - clocks related by default?
120756: 07/06/15: Re: Quartus Timing Analyzer question
120828: 07/06/18: Re: Quartus Timing Analyzer question
122663: 07/08/02: Re: Static Timing Analysis Using Primetime for FPGAs
122781: 07/08/06: Re: Problem about clock switch in Quartus II 6.0
122820: 07/08/07: Re: Problem about clock switch in Quartus II 6.0
<dkkjhb@hotmail.com>:
DL:
25724: 00/09/18: SoC VSIA meeting
25725: 00/09/18: SoC VSIA Meeting
25936: 00/09/27: VSIA System-Chip Update
35014: 01/09/17: SoC embedded software issues
<dlampret@my-deja.com>:
24449: 00/08/09: opencores doing first silicon
dlaur:
155598: 13/07/29: Instruction time (lwi) on Microblaze
<dldatwyler@gmail.com>:
154874: 13/01/24: Re: Ray Andraka's Book?
dlharmon:
83028: 05/04/21: Re: Xilinx Impact in Linux 2.6.x
83429: 05/04/29: Nuhorizons alternatives for Xilinx parts?
85478: 05/06/09: Re: pcb layers on BGAs Spartan-3
85559: 05/06/10: Re: pcb layers on BGAs Spartan-3
85560: 05/06/10: Re: re:pcb layers on BGAs Spartan-3
88700: 05/08/25: Re: TTL, CMOS and spartan
89105: 05/09/05: Re: TTL, CMOS and spartan
89521: 05/09/17: Re: SDRAM HOW?
90516: 05/10/15: Re: CPLD design software under WINE?
116861: 07/03/19: Xilinx ISE Inferred block rams
117294: 07/03/27: Re: Xilinx ISE Inferred block rams
<dlheliski@gmail.com>:
156271: 14/02/02: Re: PathFinder Source Code (in C)
161011: 19/01/10: Re: Can I use Verilog or SystemVerilog to write a state machine with
161539: 19/11/27: Re: New coding method for a state machine in groups in HDL
dlittle:
48965: 02/10/28: Re: Xilinx ISE 4.2i Student edition on Windows XP
dlopez:
144084: 09/11/10: Dealing wiht multiple clock domain...cleanly?
144390: 09/12/03: Does Xilinx sync FIFO use dual port memory? Does this affect resource?
144396: 09/12/03: Re: Does Xilinx sync FIFO use dual port memory? Does this affect resource?
144401: 09/12/03: Controlling the I2C master from Opencores.org
144439: 09/12/07: Re: Controlling the I2C master from Opencores.org
144450: 09/12/08: Cheapest way to get a chipscope compatible cable?
144453: 09/12/08: Re: Cheapest way to get a chipscope compatible cable?
144509: 09/12/12: Does a 1-bit mux glitch if only one input is known to change at one time?
144512: 09/12/12: Re: Cheapest way to get a chipscope compatible cable?
144517: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144520: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144534: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144561: 09/12/14: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144562: 09/12/14: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144586: 09/12/16: Re: Controlling the I2C master from Opencores.org
145248: 10/02/03: What is the most area efficient CRC method
145275: 10/02/04: Matching hadware and software CRC
145314: 10/02/05: Re: Matching hadware and software CRC
145357: 10/02/06: Re: Matching hadware and software CRC
147283: 10/04/21: Absolute value of a two's complement number
147288: 10/04/21: Re: Absolute value of a two's complement number
147325: 10/04/22: Re: Absolute value of a two's complement number
dls2:
24569: 00/08/14: Re: Memory specification
<dlsnell@my-deja.com>:
17266: 99/07/15: Re: Virtual CPU of SUMMIT design
DM Kolesar:
8467: 97/12/18: Engineers Wanted
dmac:
19554: 99/12/30: Re: License of Atmel free CD ROM Software
19875: 00/01/15: Re: Xilinx Spartan2
19976: 00/01/21: Re: Xilinx vs. other FPGAs manufactrers
22874: 00/05/29: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
23289: 00/06/21: Re: Problem copying text from the Spartan II data sheet
23519: 00/06/28: Re: digital phase lock loop
23677: 00/07/05: Re: Serial Number embedded in PROM.
24348: 00/08/04: Re: Who needs all those printed ac parameters?
40840: 02/03/16: Spartan II IOB tristate control FF use
42014: 02/04/12: Re: "Creat RPM" in Core Generator?
dmackay@gmail.com:
104855: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
dmendesf:
148328: 10/07/07: Programmer for Spartan-6
Dmitri Katchalov:
24613: 00/08/15: Re: Non-disclosures in job interviews
29496: 01/02/23: Getting started
44447: 02/06/20: WebPack - How to view synthesis results?
45533: 02/07/25: ALU in VHDL and a bunch of questions
45578: 02/07/27: Re: ALU in VHDL and a bunch of questions
45599: 02/07/29: Re: ALU in VHDL and a bunch of questions
47945: 02/10/08: Pin-locking in submodules
49837: 02/11/21: Re: Look up tables
51266: 03/01/09: Re: External RAM...
51368: 03/01/12: Re: Asynchronous RAM problems
Dmitriy A. Gorkaev:
9048: 98/02/17: ACROBAT
Dmitriy Bekker:
105347: 06/07/20: Re: Xilinx Virtex-4 APU Controller Questions
Dmitry Cherniavsky:
6847: 97/07/02: Does FAQ for this group exist? (empty)
8626: 98/01/14: FPGA core for ASIC?
8705: 98/01/21: Re: FPGA core for ASIC?
12143: 98/10/01: Re: Where can I get comp.arch.fpga newsarticle archive?
Dmitry Kuznetsov:
18042: 99/09/25: Re: Altera's MaxplusII: incremental compilation
27185: 00/11/14: Re: Config device for Altera 10K10
29285: 01/02/12: Re: JTAG debugging?
32732: 01/07/06: Re: Altera ACEX
35332: 01/09/29: Re: Programming flash connected to CPLD via JTAG
Dmitry Senjakin:
23788: 00/07/08: Re: Xilinx 6200 series data sheets
23852: 00/07/13: Re: How may ns should a 32-bit add take ?
Dmitry Teytelman:
116935: 07/03/21: Re: Virtex-II block RAM problem
116936: 07/03/21: Re: Virtex-II block RAM problem
117023: 07/03/22: Re: Virtex-II block RAM problem
117033: 07/03/21: Re: Virtex-II block RAM problem
117087: 07/03/22: Re: Virtex-II block RAM problem
Dmitry Vodes:
29341: 01/02/15: K-bus interface (ISO-9141)
Dmitry Zarubin:
48102: 02/10/10: Verilog vs VHDL discussion on comp.arch.verilog group
DmitrySn:
16278: 99/05/13: Re: Fancy Dram problem
16281: 99/05/13: Re: Fancy Dram problem
<dmjones6040@my-dejanews.com>:
15932: 99/04/21: Altera: Exceeding maximum input rise/fall time
dmm:
81137: 05/03/18: Re: How much current does an LED take?
81139: 05/03/18: Re: How much current does an LED take?
dMon:
42597: 02/04/29: Re: Price List ?
63487: 03/11/22: Re: 400 Mb/s ADC
dmos:
103628: 06/06/07: Problems with ISE logic optimization
103632: 06/06/07: Re: Problems with ISE logic optimization
103651: 06/06/07: Re: Problems with ISE logic optimization
Dn38517:
115113: 07/01/31: Re: USB 2.0 Streaming using FPGAs
dnardi:
21243: 00/03/12: Standalone EEPROM memories
<dnk@io.com>:
5502: 97/02/21: Q: Anyone bought APS-X84 FPGA board?
5639: 97/03/04: Re: Q: Anyone bought APS-X84 FPGA board?
7178: 97/08/11: Splash-2 et al.?
7417: 97/09/08: FPGA tool list prices
dnkmohan:
17876: 99/09/15: some help required on Virtex configuration
<do_not_bend_42@yahoo.com>:
90418: 05/10/12: NgdBuild:455, Ngd:Build:924 when using MGT XBERT
do_not_reply:
89623: 05/09/21: Re: Modelsim XE, what's the latest version?
<do_not_reply_to_this_addr@yahoo.com>:
77163: 04/12/27: interfacing DDR memory to a spartan-3
77559: 05/01/11: Editting spartan-3 bitstream to change dcm values
87702: 05/07/28: Digilent's JTAG-USB cable with chipscope
87803: 05/08/01: Re: Digilent's JTAG-USB cable with chipscope
DOD:
143067: 09/09/18: FPGA for acoustic adaptive beamforming
Dodderin' Ol' Don:
5904: 97/03/25: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
5983: 97/04/02: Re: @@ it's still very easy to find chipmaker websites (approx. 380 valid sites isted here) @@
dodo:
Dogma:
11207: 98/07/24: Cheap FPGA...
<(DogZ Software Center)>:
4691: 96/11/30: Corel Draw 7.0! only costs US$40 ? Shopping Paradise
doh.....:
55736: 03/05/18: Re: wire and reg and modelling of combinational logic
dohi:
47440: 02/09/26: Re: spartan II and PCI 5 volt
47479: 02/09/27: Re: Choosing Virtex II Speed grade
dolbowent:
91210: 05/11/01: Lead To Lead Free ROHS help?
96378: 06/02/02: I need your process pictures
96379: 06/02/02: I need your process pictures
dollaz:
80434: 05/03/05: spart 3 uart example
80440: 05/03/05: Re: spart 3 uart example
Dolphin:
96599: 06/02/07: Microblaze using SPI flash as instruction memory
98846: 06/03/17: Spartan 3E 500 DCM fine phase shift doesn't work
100880: 06/04/20: OPB_SPI timing problems
101211: 06/04/27: Xilinx: Prohibit propagation of timing constraint through a mux
101248: 06/04/28: Re: Xilinx: Prohibit propagation of timing constraint through a mux
109456: 06/09/27: Configuration of Spartan 3 devices
109483: 06/09/27: Driving a 30 bit wide LVTTL bus at 160MHz
109484: 06/09/27: Re: Configuration of Spartan 3 devices
109833: 06/10/05: Design of a programmable delay line
109837: 06/10/06: Re: Design of a programmable delay line
109842: 06/10/06: Re: Design of a programmable delay line
109867: 06/10/06: Re: Design of a programmable delay line
109870: 06/10/06: Re: Design of a programmable delay line
111695: 06/11/08: Nios2 access to EPCS device without using HAL drivers
111696: 06/11/08: Re: Nios2 access to EPCS device without using HAL drivers
111732: 06/11/09: access to EPCS pins on Altera device without using the NiosII processor
113208: 06/12/08: source synchronous timing (Xilinx)
114656: 07/01/22: Re: what happened to modular design in ISE9
115365: 07/02/08: ISE 9.1 sp1 and EDK 8.2 sp2
117242: 07/03/27: CycloneII altlvds_rx
117251: 07/03/27: Re: CycloneII altlvds_rx
117307: 07/03/28: Re: CycloneII altlvds_rx
117479: 07/04/01: Re: CycloneII altlvds_rx
117516: 07/04/03: re-assemble bootloader for NIOS Processor
117574: 07/04/04: Re: re-assemble bootloader for NIOS Processor
117656: 07/04/06: Nios2: elf2hex settings for epcs bootloader
117657: 07/04/06: Nios2: elf2hex settings for epcs bootloader
122591: 07/08/01: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
122598: 07/08/01: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
122601: 07/08/01: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
122603: 07/08/01: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
122759: 07/08/06: Re: Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
124167: 07/09/13: overloading ' operators in VHDL
127462: 07/12/27: Video processing courses
129220: 08/02/19: MIG and Spartan3 for a 112 bit DQ bus (7chips x16)
129494: 08/02/26: set_input_delay min and max (timequest)
132131: 08/05/15: Cyclone 3 on chip termination
132141: 08/05/15: Altera Cyclone 3 external clamping diode
132232: 08/05/19: Re: Cyclone 3 margins: none at all at 3.3v
Dom Bannon:
150955: 11/02/24: XST returning error code on success?
150958: 11/02/24: Re: XST returning error code on success?
150965: 11/02/24: Re: XST returning error code on success?
150968: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
150974: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
150975: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
Dom Gilligan:
90871: 05/10/24: XC3S4000 pricing?
Domagoj:
20405: 00/02/09: Re: Xilinx "WebCD" gripes
20463: 00/02/11: Re: ROL VHDL operator.. need help!
20948: 00/02/29: Re: Book recommendations?
21510: 00/03/24: StateCAD
21652: 00/03/28: FATAL_ERROR
22908: 00/06/01: Microprocessors in FPGA
22927: 00/06/03: Re: Microprocessors in FPGA
22930: 00/06/03: Re: Microprocessors in FPGA
22987: 00/06/07: XCV vs. XCV-E ?
22991: 00/06/08: Re: XCV vs. XCV-E ?
23005: 00/06/08: Re: XCV vs. XCV-E ?
23085: 00/06/14: Re: Free tools "OpenTech cdrom"
23087: 00/06/14: Re: Virtex questions
23193: 00/06/16: Re: spartan and virtex on the same board ?
23238: 00/06/19: How to cut the power disipation down ?
23255: 00/06/19: Re: How to cut the power disipation down ?
23320: 00/06/22: Re: How to cut the power disipation down ?
23442: 00/06/25: Amba/Daytona/PCI
24274: 00/08/02: Re: tbuf
24488: 00/08/10: Re: tbuf
26156: 00/10/05: Non-standard vhdl expressions
26185: 00/10/07: Re: Non-standard vhdl expressions
26245: 00/10/10: Re: Non-standard vhdl expressions
26546: 00/10/20: Virtex E development boards
28188: 00/12/27: Re: Question about programming xcv100
30350: 01/04/04: Combined Multiplier-Divider in Virtex-E
30356: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
30357: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
30571: 01/04/17: Re: Combined Multiplier-Divider in Virtex-E
31704: 01/06/03: Pentium 4 or AMD ?
31731: 01/06/04: Re: Pentium 4 or AMD ?
37775: 01/12/20: Re: anyone in comp.arch.fpga in irc?
41803: 02/04/08: Re: Handel-C useless.. Move to SystemC
44248: 02/06/14: DCT in fpga ?
44360: 02/06/18: Re: what's the use of BlockRAM
45410: 02/07/22: Re: spiral / waterfall /watersluice : Which are your methods?
45441: 02/07/23: Re: spiral / waterfall /watersluice : Which are your methods?
51787: 03/01/22: Re: FLEXlm
52902: 03/02/25: Polynomial transform based DCT/IDCT
55344: 03/05/04: buffering
Domagoj Babic:
19890: 00/01/16: Random Number Generator
45744: 02/08/03: Re: spiral / waterfall /watersluice : Which are your methods?
63994: 03/12/11: Latches inferred ?
Dombo:
139028: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
<DomGiambo@gmail.com>:
122081: 07/07/19: Re: weird PACE Error, not one google result
<dominetmike@my-deja.com>:
29032: 01/02/02: We are looking for Hardware Engineers in San Jose
Dominic:
22831: 00/05/25: Re: Why I can't place power symbols on my schematic?
22832: 00/05/25: PCI LogiCore M1 Implementation
99619: 06/03/27: Variable Bus Input/Output Fifo
113662: 06/12/19: Re: jtag reset seq
Dominic Camus:
13051: 98/11/13: SIS under Linux
Dominic Reitman:
14154: 99/01/15: Re: Problems with processes
14112: 99/01/13: Foundation Express Problem
14155: 99/01/15: Mentor Graphics
14215: 99/01/20: Design manager
14217: 99/01/20: Re: Foundation Express Problem
14297: 99/01/23: Oscillator
16378: 99/05/19: Foundation FPGA Express
Dominic Richens:
12762: 98/10/28: Re: New free FPGA CPU
Dominic Suter:
61423: 03/10/03: Re: newbie to FPGA
Dominick Cafarelli:
10949: 98/07/06: CRC's and PRBS in Paralell
Dominik Domanski:
115885: 07/02/23: Chipscope with Spartan 3E Starter Kit
Dominik F.:
98577: 06/03/13: FPGA Design Implementation
Dominik Froehlich:
95934: 06/01/27: tristate to logic conversion
95980: 06/01/27: Re: tristate to logic conversion
95988: 06/01/27: Re: tristate to logic conversion
97100: 06/02/16: Re: VHDL or verilog
97109: 06/02/16: Re: VHDL or verilog
97363: 06/02/21: Re: SMSC 91c111 and LwIP
Dominik Gawlowski:
73761: 04/09/29: Encoding systems
73850: 04/09/30: Problem with loading the verilog design to XST
73575: 04/09/24: Re: Xpower - Clock Power
73687: 04/09/28: Re: Xpower - Clock Power
Dominique:
52689: 03/02/19: crc implementation
Dominique SZYMIK:
20621: 00/02/16: Re: clock
20785: 00/02/22: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
23156: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog
23268: 00/06/20: Re: Designing a narrowband bandpass filter to pass a tone (analog
23511: 00/06/28: Hanging PCI interrupt
23514: 00/06/28: PLXMon sources
23766: 00/07/07: Re: PLXMon sources
don:
73746: 04/09/29: FPGAs as a PCI (target) controller
Don:
22788: 00/05/24: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
23567: 00/06/30: Re: Which notebook is for you?
49539: 02/11/14: xc9500 tristate question
61351: 03/10/02: Evaluation time of Emac Core?
110635: 06/10/19: Re: Cheapest FPGA board to study VHDL on
111083: 06/10/28: Re: Scoreboard and Checker in Testbench?
Don Brouse:
14915: 99/02/25: Xilinx ABEL?
Don Ansley:
108947: 06/09/19: Re: Writing VHDL, Software dummy!
Don Bockenfeld:
27704: 00/12/04: Re: ANNOUNCE: Checksum and CRC Code/Article
27707: 00/12/04: Re: ANNOUNCE: Checksum and CRC Code/Article
Don Bowey:
95057: 06/01/20: Re: OT:Shooting Ourselves in the Foot
99883: 06/03/30: Re: deglitching a clock
Don Bruder:
108042: 06/09/04: Re: Please help me with (insert task here)
108054: 06/09/04: Re: Please help me with (insert task here)
108062: 06/09/04: Re: Please help me with (insert task here)
108070: 06/09/04: Re: Please help me with (insert task here)
Don Clerk:
1738: 95/08/22: Looking for Good Introductory Book on FPGAs and ELPDs
Don Frevele:
24485: 00/08/10: Deterministic FPGA routing?
Don Gamble:
587: 95/01/11: Re: Motorola FPGA
889: 95/03/21: Re: Beyond Futurenet including PLD ?
941: 95/03/31: Re: Neocad merges with Xilinx
Don Golding:
15879: 99/04/18: Forth Processor
20074: 00/01/26: Has anyone created VHDL code to interface to a 68HC11 SPI port yet?
20430: 00/02/10: Re: VHDL and Xilinx Books for beginners
20540: 00/02/14: Public Domain Micro Processor Project
22613: 00/05/13: New Robot info and general news site
71609: 04/07/24: Re: VHDL
73477: 04/09/22: Re: How To Synchronize FPGAs
73478: 04/09/22: Re: combinatorial loops / feedback paths discussion
Don HUsby:
17053: 99/06/28: Re: 100 Billion operations per sec.!
17064: 99/06/28: Re: 100 Billion operations per sec.!
don husby:
453: 94/11/21: Re: any XC4000 Horror Stories?
537: 94/12/27: LCA file disassembler and other tools.
589: 95/01/12: Xilinx marketing knuckleheads
601: 95/01/16: Re: Xilinx marketing knuckleheads
638: 95/01/25: Re: Xilinx Marketing Knuckleheads
750: 95/02/22: Xilinx / NeoCad utilities
755: 95/02/23: Re: Xilinx / NeoCad utilities
924: 95/03/30: Re: Neocad merges with Xilinx
961: 95/04/04: Re: Neocad merges with Xilinx
1041: 95/04/19: Re: Viewlogic 4.1 & Windows '95
1065: 95/04/24: Re: (none)
1122: 95/05/02: Re: AT&T ORCA data book
1144: 95/05/04: Re: IOLOC or Other Xilinx Tools
1161: 95/05/08: Re: How to choose an FPGA vendor
Don Husby:
1196: 95/05/12: Re: How to choose an FPGA vendor
1352: 95/06/05: Re: FPGAs for PCI Interfaces
1315: 95/05/31: Re: FPGAs for PCI Interfaces
1325: 95/06/01: AT&T serial EEPROMS
1378: 95/06/09: Re: Pricing Info anyone?
1444: 95/06/23: Re: Xilinx PLDMAP usage. Pro's and Cons?
1551: 95/07/13: Re: AT&T FPGAs - Opinions needed
1622: 95/08/03: AT&T ORCA: Using register input mux?
1644: 95/08/09: Re: AT&T ORCA: Using register input mux?
1645: 95/08/09: Re: AT&T ORCA: Using register input mux?
1692: 95/08/16: Re: external connections for efficient internal routing
1700: 95/08/17: Re: high pinout - low logic devices
1747: 95/08/24: Orca FLoor planning tool
2067: 95/10/09: Workview Pro-series doesn't work with windows 95.
2218: 95/11/03: Re: AT&T vs. Xilinx
2248: 95/11/09: Re: Can X30xx Reset itself?
2251: 95/11/09: Re: Can X30xx Reset itself?
2715: 96/01/29: Re: AT&T Orca vs Xilinx
2771: 96/02/05: Re: AT&T Orca vs Xilinx
2862: 96/02/19: Re: JAVA and beer
2923: 96/02/29: ORCA and 3.3V logic
2934: 96/03/01: Re: ORCA and 3.3V logic
3048: 96/03/20: Re: Sq. Roots and Languages
3049: 96/03/21: Re: Sq. Roots and Languages
3078: 96/03/27: Re: Sq. Roots and Languages
3096: 96/04/01: Re: Reconfigurable Computer Languages
3124: 96/04/08: Re: ISA Plug & Plug models ?
3193: 96/04/23: The problem with ECL (was Re: ECL, PECL gate arrays or FPGA's)
3194: 96/04/23: Re: ECL, PECL gate arrays or FPGA's
3229: 96/04/30: Re: FPGA for Space Application
3233: 96/04/30: Re: On FPGAs as PC coprocessors
3300: 96/05/10: Re: Xilinx Mapping & Placing in HDL
3386: 96/05/23: Re: Xilinx and Viewlogic
3430: 96/05/29: Re: Xilinx and Viewlogic
3484: 96/06/07: Re: Is someone using...
3546: 96/06/18: Workview-Office doesn't work with ORCA
3547: 96/06/18: Viewlogic netlist flattener for ORCA (and Xilinx)
3891: 96/08/15: Re: Technical Job posting ( and ads) not related to the newsgroup.
4015: 96/09/03: Re: query: C to FPGA?
4067: 96/09/06: Re: ORCA and Viewlogic - any good?
4080: 96/09/09: Re: ORCA and Viewlogic - any good?
4081: 96/09/09: Re: EPROM Xilinx second source
4094: 96/09/10: Re: ORCA and Viewlogic - any good?
4250: 96/10/04: Re: Reconfigurable hardware
4271: 96/10/08: Re: Reconfigurable hardware
4314: 96/10/14: Re: ORCA 2C10A - RAM placement advice
4338: 96/10/17: Re: Update on Atmel AT17C128 Problem
4445: 96/10/30: Re: VHDL for Xilinx designs?
4465: 96/11/01: Re: VHDL for Xilinx designs?
4483: 96/11/04: Re: What is the fastest fpga for ...
4505: 96/11/06: Re: Info on FPGA Internal Architecture/ Programming
4513: 96/11/07: Re: Info on FPGA Internal Architecture/ Programming
4725: 96/12/06: Re: Name this chip !!
5079: 97/01/21: Re: FPGA Lab.
5450: 97/02/17: Re: Lucent Foundry (PC) bug
5601: 97/02/27: Re: Customizing Viewdraw in Workview Office 7.3 ... Is it possible?
5709: 97/03/10: Galileo... Leonardo... Renoir... ?
5747: 97/03/12: Re: Galileo... Leonardo... Renoir... ?
6212: 97/04/28: Re: Announcing new division & an fpga implementation
7064: 97/07/28: Re: Should Xiling have more local clock nets?
7130: 97/08/04: Re: Are 2 PCs better than One?
7586: 97/09/24: Gray code difference
7588: 97/09/24: Re: Gray code difference
9232: 98/03/03: News Server Test
9277: 98/03/05: Re: Viewlogic file format for schematic symbols
9431: 98/03/13: Re: Strange Xilinx question?
9482: 98/03/17: Re: Strange Xilinx question?
9491: 98/03/18: Re: Strange Xilinx question?
9556: 98/03/23: Orca Floorplanning tools
9570: 98/03/24: Re: Dual port
9579: 98/03/24: Re: Orca Floorplanning tools
9597: 98/03/25: Re: Orca Floorplanning tools
9619: 98/03/26: Re: XactStep6 - The cure for a dongle
9677: 98/03/30: Re: XactStep6 - The cure for a dongle
9874: 98/04/10: Re: XactStep6 - The cure for a dongle
10222: 98/05/05: Re: 3.3V design conversion
10724: 98/06/12: Re: Fastest and biggest FPGA fast and big enough?
10743: 98/06/15: Re: Fastest and biggest FPGA fast and big enough?
11121: 98/07/20: Re: Partial reprogramming
11223: 98/07/27: Re: Delay Element for async design.
11584: 98/08/25: Re: PROM alternative
11992: 98/09/23: Re: How to reduce ringing/ground bounce from FPGA output pin?
12642: 98/10/21: Re: Schematic entry?
12759: 98/10/28: Re: Q: Configure FPGA from an ISA bus?
12780: 98/10/29: Re: Q: Configure FPGA from an ISA bus?
13198: 98/11/19: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13364: 98/11/30: Re: Will XILINX survive?
13384: 98/11/30: Re: Will XILINX survive?
13385: 98/11/30: Re: Will XILINX survive?
14438: 99/01/29: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14471: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14472: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14473: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14424: 99/01/29: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14587: 99/02/05: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14676: 99/02/10: Re: Supercomputer uses 280 Xilinx FPGAs
15639: 99/04/05: Re: XILINX CLB architecture
15885: 99/04/18: Re: High speed reconfigurability
15920: 99/04/21: Re: PIN/PAD files to Schematic Symbols
15954: 99/04/23: Re: Job Advert Netiquette?
16018: 99/04/28: Re: Storage of 32Bit-Vectors
16173: 99/05/07: Re: BGA Prototyping ?
16682: 99/06/02: Re: Printing to picture files
16718: 99/06/04: Re: virtex vs apex20k family comparison for DSP ?
17237: 99/07/13: Dongle problems.
17332: 99/07/21: Re: Solaris vs. NT
17354: 99/07/22: Re: Solaris vs. NT
17883: 99/09/15: Re: Opinions Wanted
17975: 99/09/20: Re: Loadable arithmetic in Virtex
18003: 99/09/22: Virtex questions
18266: 99/10/11: Re: GSR on ORCA FPGAs
18284: 99/10/12: Re: GSR on ORCA FPGAs
18324: 99/10/14: Need a Lucent chip in T100 package.
18698: 99/11/08: OrcaLut from VHDL?
18879: 99/11/19: Re: Why not Lucent ORCA FGPAs?
18878: 99/11/19: Re: Why not Lucent ORCA FGPAs?
18934: 99/11/22: Re: Why not Lucent ORCA FGPAs?
18935: 99/11/22: Re: Why not Lucent ORCA FGPAs?
19210: 99/12/06: Re: Problems with routing Virtex device
19251: 99/12/08: Re: constraints between clock domains: can't advance
19440: 99/12/21: Re: Dumb question springing from a discussion about chess on a chip...
19767: 00/01/11: Re: Lucent Orca designs
20107: 00/01/27: Re: Why Sinplicity make combinatorial loops from latches ?
20195: 00/01/31: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20196: 00/01/31: Re: Lucent Orca designs
20221: 00/02/01: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20596: 00/02/15: Virtex size: Row,Col or Col,Row ?
20707: 00/02/18: Re: multiplier
21022: 00/03/03: Re: New name: DLLs, PLLs and videotape...
21079: 00/03/06: Re: New name: DLLs, PLLs and videotape...
21087: 00/03/06: Re: New name: DLLs, PLLs and videotape...
21120: 00/03/07: Re: New name: DLLs, PLLs and videotape...
21538: 00/03/24: Re: FPGA openness
21542: 00/03/24: Re: No- FPGA openness
21550: 00/03/24: Re: FPGA openness
21557: 00/03/24: Re: FPGA openness
21561: 00/03/24: Chip-to-Chip benchmarks?
21964: 00/04/10: Re: multiprocessor support of IC design tools
22119: 00/04/25: Re: Segregation between synthesis code and simulation code
22499: 00/05/10: Re: HELP - what to choose?
22588: 00/05/12: Re: Future of FPGAs?
22721: 00/05/19: Re: FPGA emultaion of a microprocessor
23689: 00/07/05: Re: Altera Ships Largest PLD
23698: 00/07/05: Re: Altera Ships Largest PLD
23736: 00/07/06: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23743: 00/07/06: Re: Using LUTs in Virtex with ViewDraw and ViewSim
23763: 00/07/07: Re: calculating modulo N
23855: 00/07/13: Silicon Valley Housing Nightmare?
23979: 00/07/19: Summary: Re: Silicon Valley Housing Nightmare?
24004: 00/07/20: Re: Summary: Re: Silicon Valley Housing Nightmare?
24319: 00/08/03: Re: Viewlogic Licencing
24458: 00/08/09: Re: Who needs all those printed ac parameters?
32041: 01/06/11: Gray Code Guard bits (was Re: Help in FIFO design)
32620: 01/07/02: IPAD primitive is broken in exemplar xilinx verilog libraries?
32876: 01/07/10: Virtex2: Is it possible to place distributed DPRAM
32903: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
33060: 01/07/16: Re: Design entry
33163: 01/07/18: Re: Help please: How to build a state machine into a VHDL block?
33361: 01/07/24: Re: Register Chain
34513: 01/08/28: Re: Defending Austin Franklin
35039: 01/09/18: Synplicity logic replication
35058: 01/09/19: Re: Synplicity logic replication
35100: 01/09/20: Re: Synplicity logic replication
35152: 01/09/24: Re: Synplicity logic replication
35154: 01/09/24: Re: Forcing a LUT logic function (was Synplicity logic replication)
35229: 01/09/26: Re: Virtex2 slice level instantiation in verilog question
35569: 01/10/10: High level synthesis will never work well :)
35601: 01/10/11: Re: High level synthesis will never work well :)
35615: 01/10/11: Re: High level synthesis will never work well :)
35620: 01/10/12: Re: High level synthesis will never work well :)
35659: 01/10/12: Re: High level synthesis will never work well :)
36160: 01/10/31: Re: Leonardo bugs
36220: 01/11/02: Re: Synplicity, Xilinx, & unwanted BUFGs
37075: 01/11/29: Re: don't cares and X's in a case statement?
37190: 01/12/03: Re: problem with manual floorplanner
37646: 01/12/18: Re: SPI interface in VHDL
Don Ingram:
8483: 97/12/21: Schmitt Trigger on ISP
Don J. Thompson:
7344: 97/08/29: FS:iFX8260 FPGA Evaluation Board
Don Kuenz:
156232: 14/01/19: Re: my first microZed board
Don Labriola:
9548: 98/03/22: Re: Dual port
Don Lancaster:
114202: 07/01/07: Re: Basic questions about digital phase locked loop
Don Logan:
2775: 96/02/05: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
Don Matson:
17515: 99/08/04: Re: looking for software
Don McCarley:
20616: 00/02/16: Re: multiplier
21186: 00/03/09: Virtex and Virtex E package availability
22472: 00/05/09: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22498: 00/05/10: Re: Error with Quartus for Altera APEX20K device: clock skew is greater
22519: 00/05/10: clock skew doesn't compute with Altera
Don McKenzie:
18726: 99/11/10: Re: CAN tools reccomendations?
92837: 05/12/08: Re: VGA controller
Don North:
1210: 95/05/14: Re: FLEXlogic opinions?
Don Prescott:
67516: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
Don S:
59120: 03/08/08: speeding up quartus
59212: 03/08/12: Re: speeding up quartus
Don Seglio:
107953: 06/09/03: Spartan-3 Starter Kit newbie question
107983: 06/09/03: Re: Please help me with (insert task here)
107992: 06/09/03: Re: Please help me with (insert task here)
108031: 06/09/04: Re: Spartan-3 Starter Kit newbie question
108117: 06/09/05: Re: Please help me with (insert task here)
109447: 06/09/26: Re: BSD Indi FPGA processor seeks new webserver
109748: 06/10/04: Re: Just a matter of time
Don Stauffer:
36003: 01/10/25: Probing BGA Designs
Don Taylor:
62653: 03/11/04: Re: Building the 'uber processor'
Don Teeter:
26652: 00/10/23: Specifying pin in design file
27432: 00/11/22: Another simple Xilinx question
27504: 00/11/24: Re: Another simple Xilinx question
37141: 01/11/30: XNF file is rewritten and rendered useless
41618: 02/04/03: How to force Foundation to NOT use an ILB flop?
43218: 02/05/16: Articles on FPGA-based design validation / verification?
Don Wilkerson:
5271: 97/02/03: FPGA Power Diss. Comparison
5552: 97/02/24: Re: Xilinx or Altera?
5632: 97/03/03: Altera 10K50 Demo Board?
Don Y:
157640: 15/01/12: Re: [cross-post] nand flash bad blocks management
157643: 15/01/13: Re: [cross-post] nand flash bad blocks management
Don Yuniskis:
8128: 97/11/20: Re: what is metastability time of a flip_flop
9564: 98/03/24: Re: New radix-4 CORDIC for computing sine and cosine
10737: 98/06/15: Re: Free Computer --BULLSHIT! ADMAX/ComputerMania/PCmania MLM/Spam/ SCAM !!!
13790: 98/12/28: Re: 22V10 Metastability - help please
13794: 98/12/28: Re: 22V10 Metastability - help please
13813: 98/12/28: Re: 22V10 Metastability - help please
donald:
129889: 08/03/08: Re: Datasheet on Micron's secure products
129956: 08/03/11: Re: BRAM synthesis question
130393: 08/03/21: Re: Designing CPU
Donald:
110630: 06/10/18: Re: Cheapest FPGA board to study VHDL on
117760: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
123177: 07/08/18: Re: help on camera ports
Donald Espinoza:
12353: 98/10/09: Xilinx may not support schematics for Virtex?????
Donald Gillies:
5144: 97/01/27: Re: ASICs Vs. FPGA in Safety Critical Apps.
12159: 98/10/01: Re: Fastest Add
17253: 99/07/14: Re: Alto in an FPGA (was CPU's directly executing HLL's)
19004: 99/11/23: Re: implementing TCP/IP on PLD
20285: 00/02/03: Re: Count 1's algorithm...
27229: 00/11/15: Re: ANNOUNCE: Checksum and CRC Code/Article
Donald Sinclair:
1309: 95/05/31: Re: Help on Programming FPGAs
<donald7@dreamwiz.com>:
32724: 01/07/06: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
Donato Pace:
105807: 06/08/01: Virtex4 ML455 do you know this board?... help me!
106050: 06/08/07: Re: FPGA : PCI-Xilinx Core, PC not booting
Dong-Lok Kim:
785: 95/03/02: Limits on on-chip FPGA virtual computing
803: 95/03/03: Re: Limits on on-chip FPGA virtual computing
Dongho:
47114: 02/09/17: Feasibility of 100 tap adaptive FIR design on FPGA
47151: 02/09/18: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47488: 02/09/26: implementation of adaptive FIR with many input channels?
47781: 02/10/03: Re: implementation of adaptive FIR with many input channels?
48134: 02/10/11: Re: implementation of adaptive FIR with many input channels?
48257: 02/10/15: how to generate LUT for DA?
48860: 02/10/25: Re: how to generate LUT for DA?
51577: 03/01/16: adaptive filter with many zero input
Dongho Chung:
7926: 97/10/31: Re: Help about ALTERA FPGA!!
17644: 99/08/18: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17831: 99/09/09: Re: Feasibility of 200 MHz, 12K design on FPGA
donghun:
84707: 05/05/24: Re: warning place and route ise7.1?
Donna J. Wages:
9706: 98/04/01: Re: Best solution
Donna Simms:
17609: 99/08/13: Computers & Causes
Donna Vance:
14109: 99/01/13: ASIC/FPGA H/W ENGINEERS ASAP!!!!
Donnelly:
3480: 96/06/06: Re: FPGA Design flow
<dont.reply.com>:
8565: 98/01/08: Visit WWW.WIN-SHAREWARE.COM !!!
dont_reply:
59130: 03/08/09: Xilinx Webpack ISE and Verilog-2001?
81344: 05/03/22: Re: ISE 7.1 WebPack + EDK 6.3
<doomeddave@yahoo.co.uk>:
90355: 05/10/11: Re: 64 bit processor for FPGA workstation?
doomsten:
147849: 10/05/26: how to decrypt Xilinx ISE12.1 IPCORE source code
147850: 10/05/26: Xilinx ISE12.1 IPCORE source code
DoPeti:
123751: 07/09/03: Re: opb_timer interrupt self test problem
<dorama2@gmail.com>:
122014: 07/07/17: Actel. Libero. Synplify
Dorian Nawrath:
2787: 96/02/07: Re: PIC16C71 CORE for XC4000 ?
Doris Cheng:
1906: 95/09/19: FAQ?
dormanpeter1@gmail.com:
151079: 11/03/03: Finding cheap PCI-E FPGA board for a student
151123: 11/03/08: Re: Finding cheap PCI-E FPGA board for a student
<dormanpeter1@gmail.com>:
123564: 07/08/30: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
123580: 07/08/30: Re: Spartan 3E starter kit (Rev.D) modification : 3E500 -> 3E1200
123707: 07/09/02: opb_timer interrupt self test problem
doron nisenbaum:
12596: 98/10/19: Re: Synthesis with Altera RAM instances
dosextender:
57109: 03/06/23: Bus Mastering DMA
<dotexe@gmail.com>:
78628: 05/02/04: Beginner : problem in Xilinx Platform Studio with selection of board names
<dotnetters@gmail.com>:
98962: 06/03/17: Microblaze FSL peripheral problem
98973: 06/03/18: Re: Microblaze FSL peripheral problem
99188: 06/03/21: Re: Microblaze FSL peripheral problem
99335: 06/03/23: XST takes unusually long
99365: 06/03/23: Re: XST takes unusually long
99431: 06/03/24: How to do profiling on hardware target on Microblaze
dotty1319:
38170: 02/01/07: please tell me how to solve xilinx error xml
38251: 02/01/09: xilinx service pack error
38576: 02/01/17: service pack8 can't use
Doug:
38069: 02/01/03: Spartan-IIE interfacing issues
doug:
20209: 00/01/31: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
25450: 00/09/11: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
26789: 00/10/29: Re: Xilinx Spartan2 and VirtexE availability
44308: 02/06/17: lfsr and implementation and alpha
44359: 02/06/18: Re: lfsr and implementation and alpha
114751: 07/01/23: Re: Xilinx ISE 8.2
114819: 07/01/24: Re: Xilinx ISE 8.2
114829: 07/01/24: Re: Xilinx ISE 8.2
114887: 07/01/25: Re: Xilinx ISE 8.2
114931: 07/01/26: Re: Xilinx ISE 8.2
116076: 07/03/01: Re: Spartan-3AN
117097: 07/03/22: Re: Off topic: what is the purpoe of XST?
117147: 07/03/23: Re: Off topic: what is the purpoe of XST?
121288: 07/06/30: Re: Xilinx programmer, many unknown devices...
135260: 08/09/23: Re: Use of divided clocks inside modules
135261: 08/09/23: Re: Is it possible to get an RTL netlist from Xilinx tools?
135266: 08/09/23: Re: Use of divided clocks inside modules
135345: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
135351: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
135980: 08/10/24: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
135988: 08/10/25: Re: Learning WinCUPL; Tried Atmel Suppport but no solution!
136880: 08/12/10: Re: Sampling a clock
136883: 08/12/10: Re: Sampling a clock
138518: 09/02/25: Re: Fm digital baseband demodulation
138545: 09/02/26: Re: Fm digital baseband demodulation
138577: 09/02/28: Re: Fm digital baseband demodulation
138590: 09/03/01: Re: New person to CPLD programming
138591: 09/03/01: Re: New person to CPLD programming
138594: 09/03/01: Re: New person to CPLD programming
138596: 09/03/01: Re: New person to CPLD programming
138598: 09/03/01: Re: New person to CPLD programming
138815: 09/03/11: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138848: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
140724: 09/05/22: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140892: 09/05/28: Re: phase locking a slow (2Mhz) signal.
140913: 09/05/29: Re: phase locking a slow (2Mhz) signal.
140914: 09/05/29: Re: phase locking a slow (2Mhz) signal.
140917: 09/05/29: Re: phase locking a slow (2Mhz) signal.
140959: 09/05/31: Re: phase locking a slow (2Mhz) signal.
141012: 09/06/02: Re: the reach of VHDL
141930: 09/07/17: Re: FPGA to PC connection
141951: 09/07/18: Re: FPGA to PC connection
142931: 09/09/08: Re: IMPACT-Xilinx Platform Cable USB II
142976: 09/09/11: Re: Behavior of crystal oscillator?
142998: 09/09/14: Re: Behavior of crystal oscillator?
143713: 09/10/22: Re: Time stability of clock on FPGA board
143721: 09/10/22: Re: Time stability of clock on FPGA board
143723: 09/10/22: Re: Time stability of clock on FPGA board
143733: 09/10/22: Re: Time stability of clock on FPGA board
143746: 09/10/23: Re: Time stability of clock on FPGA board
143747: 09/10/23: Re: Time stability of clock on FPGA board
143754: 09/10/23: Re: Time stability of clock on FPGA board
143772: 09/10/24: Re: Time stability of clock on FPGA board
143791: 09/10/26: Re: Time stability of clock on FPGA board
143792: 09/10/26: Re: Time stability of clock on FPGA board
143820: 09/10/27: Re: Time stability of clock on FPGA board
144027: 09/11/08: Re: Sinewave generation
Doug Dillon:
3526: 96/06/14: Re: troubles on the way from exemplar to Altera's MAX+PLUSII
Doug Hahn:
499: 94/12/09: driving PCI
Doug Hall:
919: 95/03/29: Re: Excuse me while I vent about Data I/O & Abel...
Doug Hillmer:
28627: 01/01/18: Re: revision control tools ??
28655: 01/01/19: Re: revision control tools ??
Doug Jones:
86650: 05/07/01: FPGA system RAM
86652: 05/07/01: Re: FPGA system RAM
86654: 05/07/01: Re: FPGA system RAM
115425: 07/02/09: Re: DCT/IDCT on FPGA
Doug MacKay:
107435: 06/08/28: Re: Arbiter design problem?
Doug McIntyre:
161418: 19/07/29: Re: New uses of FPGAs
Doug Merritt:
8425: 97/12/13: Re: RC5-64 on FPGA
Doug Miller:
70439: 04/06/17: Xilinx RAM64x1D simulation problems
70440: 04/06/17: Re: Xilinx RAM64x1D simulation problems
71093: 04/07/07: Re: FSM in illegal state
71184: 04/07/11: Modelsim crash (code 211) when using library
Doug Reed:
619: 95/01/19: Re: [shin]OrCad .sch to Xilinx .xdf conversion seeking
Doug Shade:
757: 95/02/23: Re: Newsgroup for Micro Controllers
926: 95/03/30: Re: Excuse me while I vent about Data I/O & Abel...
1658: 95/08/11: Re: Xilinx PROMs
1744: 95/08/23: Re: Synario/OrCad/Viewlogic
1878: 95/09/14: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
2176: 95/10/26: Re: PLD in small package ?? anyone
2291: 95/11/17: Wanted-limited Verilog or VHDL synthesis
2640: 96/01/17: Re: ProSeries + Actel & Xilinx
2726: 96/01/30: Re: GAL programming for hobby use...Is there no hope?
2969: 96/03/07: EEPROM for Xilinx
8754: 98/01/23: Re: ASIC and PCB makers for Hobbyists wanted
Doug Smith:
1928: 95/09/20: Re: ATMEL WWW site?
1930: 95/09/20: DMA design needed for Xilinx FPGA
Doug Smith - Sun BOS Hardware:
11042: 98/07/14: Quickturn users group
Doug Thomae:
64: 94/08/08: Re: How pricey is FPGA development?
Doug Wilson:
33600: 01/07/31: Virtex2: Xilinx PCI core mapping error
44806: 02/07/01: Xilinx XAPP622: Info on ROUTE constraint?
45444: 02/07/23: Xilinx DCMs, RST, and phase coherence
douge:
65456: 04/01/29: VirtexII Pro MMU/Cache Setup for VxWorks
dougeh:
104261: 06/06/22: Xilinx Library Conversion
dougfgd@gmail.com:
107939: 06/09/02: Re: Performance Appraisals
douglas:
47150: 02/09/18: xilinx jtag chain question
47164: 02/09/19: Re: xilinx jtag chain question
Douglas:
36853: 01/11/21: The Xilinx Practical Designer Lab Book
123986: 07/09/10: Re: Clock boundary crossing
124020: 07/09/11: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
125081: 07/10/16: Re: FPGA quiz: what can be wrong
125169: 07/10/17: Re: FPGA quiz: what can be wrong
125170: 07/10/17: Re: FPGA quiz: what can be wrong
Douglas Armstrong:
22641: 00/05/16: Propogation Delay
22706: 00/05/18: Re: Propogation Delay
22708: 00/05/18: Re: CLKing external RAM from FPGA (Virtex E)
Douglas Beattie Jr.:
11247: 98/07/30: Asynchronous Building Blocks?
Douglas Clayton:
10059: 98/04/24: Re: Could you help me save CLB's?
10129: 98/04/28: Re: FPGA input data rate limitations?
10142: 98/04/29: Re: FPGA input data rate limitations?
douglas fast:
52214: 03/02/04: xilinx virtex II floorplanning
52283: 03/02/05: Re: xilinx virtex II floorplanning
54103: 03/04/02: odd virtex-ii bufgmux behavior??
54118: 03/04/02: Re: odd virtex-ii bufgmux behavior??
54153: 03/04/03: Re: odd virtex-ii bufgmux behavior??
Douglas Grant:
34571: 01/08/29: Re: Ethernet CRC
Douglas L Datwyler:
8787: 98/01/27: ABEL to Altera-HDL? Group FAQ?
Douglas L. Datwyler:
3103: 96/04/02: VHDL books with demo software????
Douglas Miller:
43223: 02/05/17: Timing constraints on internal signals
Douglas Sykora:
77598: 05/01/11: Signaltap - Finding Nodes - FSM state register
77898: 05/01/19: Quartus II v4.2 LogicLock Regions
80949: 05/03/14: Quartus II and DSE
80962: 05/03/15: Re: Quartus II and DSE
81049: 05/03/16: Re: Quartus II and DSE
81123: 05/03/17: Re: Bit-Rounding Algorithm
81142: 05/03/18: Re: Quartus II and DSE
81143: 05/03/18: Re: Quartus II and DSE
81176: 05/03/18: Re: Quartus II and DSE
Douglas W. Jones,201H MLH,3193350740,3193382879:
3585: 96/07/01: Re: REQ:Old Picture of Bus
19593: 00/01/03: Re: An online division unit with constant divisor
19615: 00/01/04: Re: An online division unit with constant divisor
Douglas W. Olsen:
9517: 98/03/20: Actel system available
9798: 98/04/06: Actel gear available
20169: 00/01/30: Re: looping FIFO?
DouglasUT:
13122: 98/11/16: CE Student Seeks Research Pointers
DougMiller:
52582: 03/02/14: Xilinx CORDIC core v1.0 used to compute atan
<dougs@dougs.com>:
65648: 04/02/04: Passing user-defined types through the port (global variables??)
DougW:
146984: 10/04/07: Re: EDK map error 1492 - incompatible programming error
DoVHDL:
124911: 07/10/10: HELP, how to time constraint part of a design?
124915: 07/10/10: Re: HELP, how to time constraint part of a design?
124917: 07/10/10: Re: HELP, how to time constraint part of a design?
124926: 07/10/10: Re: HELP, how to time constraint part of a design?
<dowers.irl@gmail.com>:
126891: 07/12/05: Re: Low cost FPGA w/serdes
126925: 07/12/06: Re: Low cost FPGA w/serdes
dowlers:
133984: 08/07/21: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
142037: 09/07/22: Laser marking / custom graphics on blank FPGA?
142049: 09/07/23: Re: Laser marking / custom graphics on blank FPGA?
142071: 09/07/23: Re: Laser marking / custom graphics on blank FPGA?
142171: 09/07/28: Re: Lattice EC - some .bit files not loading from SPI flash
downunder:
82620: 05/04/14: clock input over an I/O pin
82655: 05/04/15: Re: clock input over an I/O pin
<dozer@netwizards.net>:
4997: 97/01/10: would you be my friend?
dp:
91071: 05/10/28: Re: System ACE equivalent for CPLDs
91079: 05/10/28: Re: System ACE equivalent for CPLDs
91194: 05/11/01: Re: System ACE equivalent for CPLDs
91795: 05/11/13: Re: PC networking through modems
91919: 05/11/16: Re: RoHS
92556: 05/12/01: Re: Slow FIFO using external SRAM
93424: 05/12/21: Re: Place and Route Algorithms: where's the fat?
93489: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93493: 05/12/22: Re: Going insane - Xilinx VGA controller...
93547: 05/12/23: Re: RTL for Z8000 series CPU?
94538: 06/01/13: Re: OT: RoHS and Lead?
94542: 06/01/13: Re: OT: RoHS and Lead?
94566: 06/01/13: Re: Don't even get me started on lead, and alphas
94582: 06/01/13: Re: Don't even get me started on lead,
95836: 06/01/26: Re: open source fpga programmer programs
95842: 06/01/26: Re: open source fpga programmer programs
95875: 06/01/26: Re: open source fpga programmer programs
95903: 06/01/26: Re: open source fpga programmer programs
95978: 06/01/27: Re: XilNet server data streaming problem from PPC
96007: 06/01/27: Re: XilNet server data streaming problem from PPC
96377: 06/02/02: Re: BGA central ground matrix
96384: 06/02/02: Re: BGA central ground matrix
96386: 06/02/02: Re: BGA central ground matrix
96390: 06/02/02: Re: BGA central ground matrix
96389: 06/02/02: Re: BGA central ground matrix
96416: 06/02/03: Re: BGA central ground matrix
96421: 06/02/03: Re: BGA central ground matrix
96423: 06/02/03: Re: BGA central ground matrix
96838: 06/02/11: Re: LVDS
99295: 06/03/22: Re: this JTAG thing is a joke
99374: 06/03/23: Re: this JTAG thing is a joke
99945: 06/03/31: Re: PCB Bypass Caps
101131: 06/04/26: Re: Async FPGA ~2GHz
101150: 06/04/26: Re: Async FPGA ~2GHz
101167: 06/04/26: Re: Async FPGA ~2GHz
101778: 06/05/06: Re: Anyone use Xilinx ppc405 profiling tools?
101892: 06/05/08: Re: Anyone use Xilinx ppc405 profiling tools?
102083: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102092: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102268: 06/05/12: Re: reverse engineering ?
102292: 06/05/14: Re: reverse engineering ?
102412: 06/05/15: Re: reverse engineering ?
102924: 06/05/23: Re: CPLD (CoolRunner failures)
103075: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103085: 06/05/25: Re: Remote Application delivery for EDA
103097: 06/05/25: Re: Remote Application delivery for EDA
103127: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103187: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
103251: 06/05/29: Re: hard disk drivers problem
103980: 06/06/16: Re: bga routing
103987: 06/06/16: Re: bga routing
152887: 11/10/30: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
152901: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
<dp11@my-dejanews.com>:
10846: 98/06/25: ARM ASPIRE board Beta Trial
10914: 98/06/30: ARM ASPIRE Board Beta Trial
dp@tgi-sci.com:
85927: 05/06/18: CPLD fusemap data - why the secrecy?
85930: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85933: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85936: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85940: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85944: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85947: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85951: 05/06/18: Re: CPLD fusemap data - why the secrecy?
86154: 05/06/22: Re: 5 Volt tolerance - Altera
dpetrov:
153238: 12/01/15: Effective square root algorithms implemented on FPGAs already
153240: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
153244: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
153248: 12/01/16: Re: Effective square root algorithms implemented on FPGAs already
Dr A.P. Whichello:
39441: 02/02/10: Re: solutions manuals, and no they are not for school
Dr Chris Dick:
11634: 98/08/27: FFT -Speed
Dr Daz:
29059: 01/02/04: Xilinx post-synthesis (leonardo) simulation (modelsim)
Dr Edmund Lai:
3358: 96/05/20: Xilinx and Viewlogic
Dr Justice:
79976: 05/02/27: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79980: 05/02/27: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79981: 05/02/28: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79986: 05/02/28: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
81282: 05/03/21: Re: Is the Xilinx EDK free?
82415: 05/04/12: 5V PCI interface
82423: 05/04/12: Re: 5V PCI interface
82445: 05/04/13: Re: 5V PCI interface
83012: 05/04/21: Re: DSP-PC architectural advice needed.
85937: 05/06/18: Re: SystemC comments
85977: 05/06/19: Xilinx webshop
86248: 05/06/23: Re: Xilinx webshop
86254: 05/06/23: Re: Xilinx webshop
Dr Mike Addlesee:
12011: 98/09/24: Re: easier testing for PCI cards??
Dr VBaSiC:
7345: 97/08/29: WEB PAGE CREATION
Dr. Abbes Amira:
53060: 03/03/02: University Research Scholarships
Dr. Andy Nisbet:
42950: 02/05/08: FPGA Development Boards for Xilinx Virtex II 2V6000 & HandelC Support
46453: 02/08/30: Re: Handel-C data widths
46682: 02/09/05: Re: C/C++ to Verilog/VHDL ?!
49390: 02/11/11: Re: LU-decomposition
60490: 03/09/15: Xilinx Timing Constraints for Asynchronous Logic (asynch latches)
Dr. Anton Squeegee:
56517: 03/06/07: Re: Logical analyzer via USB or printer port
Dr. B. Love, C.P.A.:
Dr. Beau Webber:
153710: 12/04/28: Re: FPGA acceleration v.s. GPU acceleration
153711: 12/04/28: FPGA Modular Firmware Skeleton for multiple instruments -
153743: 12/05/04: Re: FPGA communication with a PC (Windows)
153789: 12/05/21: Re: Interfacing a circuit in an FPGA to a PC
Dr. Endric Schubert:
6581: 97/06/03: Re: Your recommendation needed
6603: 97/06/04: Re: The Advanced FPGA Design Demonstration at DAC
6697: 97/06/16: Re: readback on xc40xx ?
Dr. Franz Pucher:
898: 95/03/23: FAQ
Dr. Jason Cong:
2510: 95/12/21: FPGA'96 Adv. Program
2576: 96/01/04: FPGA'96 Adv. Program
2686: 96/01/24: FPGA'96 Adv. Registration Deadline is tomorrow (1/25/96)
2772: 96/02/05: FPGA'96 Final Program -- It's next week!
Dr. Jeff Jackson:
38195: 02/01/08: Re: ROM synthesis question
Dr. Jones:
52695: 03/02/19: WebPack 4.2i and Block RAM instantiation
52723: 03/02/20: Re: WebPack 4.2i and Block RAM instantiation
52756: 03/02/20: Re: WebPack 4.2i and Block RAM instantiation
52985: 03/02/27: Re: Spartan2 internal bus state?
Dr. K.W.Ng:
780: 95/03/01: Setting up a Rapid Systems Prototyping Lab.
Dr. Michael D. Foegelle:
39164: 02/02/03: LARGE ultra low power FPGA/CPLD recommendation
Dr. Neil Bergman:
6167: 97/04/21: Postdoc: Brisbane Australia: FPGAs, Image Processing, GPS
6168: 97/04/21: PART 97 Conference: Special Session - Reconfigurable Computing
Dr. Peter Schulz:
15493: 99/03/26: Re: What do you think about philips XPLA?
Dr. Thomas Ansorg:
141351: 09/06/19: Preselection counter in verilog
141363: 09/06/20: Re: Preselection counter in verilog (Verilog Version)
141410: 09/06/23: index in arrays doesn't work
141412: 09/06/23: Re: index in arrays doesn't work
Dr. Vitit Kantabutra:
6356: 97/05/17: Re: VHDL or Verilog?
6417: 97/05/22: Re: Cheap way to develop for FPGAs?
14254: 99/01/21: Re: CORDIC (was: Best way to digitally synth. stable frequencies?)
14410: 99/01/28: Atmel IDS 6.00 simulation question
31340: 01/05/19: Re: CDROMs with Free tools and designs
31342: 01/05/19: Does anyone have fpga technology code for Atmel AT40 on Electric?
<Dr. Vitit Kantabutra, Associate Professor of Computer Science>:
32076: 01/06/12: ATMEL carry-select adders
dr.no:
49252: 02/11/06: Re: tips for cutting down on slice usage in a VirtexII
49281: 02/11/07: Re: Programming Altera EPC16
49913: 02/11/25: Re: Problems With DW8051 Synthesis
<dr0ne@my-deja.com>:
17862: 99/09/14: free/demo/low cost verilog synthesis tools available?
<dr@kbrx.com>:
118452: 07/04/26: Re: picoblaze C compiler download wanted
dr_mckay:
137494: 09/01/20: Ethernet on Spartan 3A to send Data to PC
dracosilv:
138584: 09/03/01: New person to CPLD programming
138587: 09/03/01: Re: New person to CPLD programming
138589: 09/03/01: Re: New person to CPLD programming
138592: 09/03/01: Re: New person to CPLD programming
138593: 09/03/01: Re: New person to CPLD programming
138605: 09/03/01: Re: New person to CPLD programming
138721: 09/03/05: Re: New person to CPLD programming
Dragan Cvetkovic:
55450: 03/05/08: Re: Software and hardware monopoly is bad
dragomir milojevic:
40128: 02/02/28: rloc for a flip flop
Dragon:
18988: 99/11/23: Re: How to use multiple resets?
18989: 99/11/23: Re: How to use GSR-net in Virtex?
18991: 99/11/23: Re: Why not Lucent ORCA FGPAs?
19161: 99/12/02: Re: Tristate bidirectional pads with Xilinx
19162: 99/12/02: Re: Tristate bidirectional pads with Xilinx
19166: 99/12/02: Re: Tristate bidirectional pads with Xilinx
20303: 00/02/04: Re: Count 1's algorithm...
20581: 00/02/15: Re: Advice please
dragon:
33859: 01/08/07: How to generate *.vfe from viewdraw
dragonfly:
152155: 11/07/14: ASM vs. RAM
152167: 11/07/15: Re: ASM vs. RAM
152175: 11/07/15: Re: ASM vs. RAM
drake:
40672: 02/03/12: cyphers
DrB:
71202: 04/07/12: Re: FSM in illegal state
71236: 04/07/12: Re: DCM / DLL issues was: FSM in illegal state
DrBill:
140325: 09/05/08: Re: Any Experiences with the GN4124 PCI Express - FPGA bridge?
<drdimf@soundom.net>:
24638: 00/08/16: WONDERFUL!
drdoom_97:
77978: 05/01/21: Re: Embeddded PPC - V2Pro - Interrupts
Dre:
111689: 06/11/08: Platform USB Cable and Windows XP Pro x64
<dre32d@msn.com>:
6887: 97/07/06: sell/your/photos$$$$$
dream_life_0102:
127108: 07/12/11: I try to Tri-Mode Embedded EMAC
127161: 07/12/12: Re: I try to Tri-Mode Embedded EMAC
DRENGER GABI:
48723: 02/10/23: PCI ARBITER
Dresdenboy:
83216: 05/04/26: Re: A PC for make synthesis
Drew:
71382: 04/07/16: How Bidirectional (AHDL) or INOUT (VHDL) are displayed in the Waveform Simulation?
71472: 04/07/19: Re: How Bidirectional (AHDL) or INOUT (VHDL) are displayed in the Waveform Simulation?
71498: 04/07/20: Open Collector Circuit - How to Simulate?
71569: 04/07/22: Converting High Rise Time clock to Low Rise time clock - Chellenge!
71680: 04/07/27: On-Chip Oscillator
71798: 04/07/30: Re: On-Chip Oscillator
72600: 04/08/26: EPM7064LC44-7 - Not there in Quartus II...
72645: 04/08/27: Re: EPM7064LC44-7 - Not there in Quartus II...
72646: 04/08/27: How to Figure out EPLD can be socketed or not!
72780: 04/09/01: Programming using .pof File and In-system Programming
72796: 04/09/02: Re: Programming using .pof File and In-system Programming
73065: 04/09/13: JTAG Prog. and Power Requirments
drg:
93783: 05/12/30: using internal POR
93819: 05/12/31: basic DSP with FPGA
93833: 06/01/01: Re: basic DSP with FPGA
94115: 06/01/05: Re: basic DSP with FPGA
93954: 06/01/03: Re: basic DSP with FPGA
Drgtec:
8205: 97/11/27: Re: barrel shifter
Drily Lit Raga:
94722: 06/01/16: Migrating Project from Xilinx ISE 4.1 to 8.1?
94775: 06/01/17: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
94809: 06/01/17: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
94842: 06/01/18: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
94723: 06/01/16: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
94811: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
<driverram@gmail.com>:
160617: 18/05/27: Re: Searching for info about very old FPGA devices
Drizzt:
17373: 99/07/23: Hardware FFT Design?
DrKW LON Mail AutoReply:
drl3:
18779: 99/11/15: Altera programming leads
drmali2001@gmail.com:
98625: 06/03/13: xiilnx spartan 3 starter kit connection to Ethernet LAN
DrNo:
5391: 97/02/12: Re: Altera BitBlaster/ByteBlaster replacement
<droberts@cam-orl.co.uk>:
17545: 99/08/09: Max+Plus II Verilog Parameters
<drop669@gmail.com>:
111536: 06/11/04: Using Altera Nios II Stratix II dev kit just as FPGA.
121643: 07/07/10: lpm_constant function in Altera Quartus 7.1
122732: 07/08/05: OpenSPARC
122733: 07/08/05: FPGA accelerator service
122735: 07/08/05: Re: OpenSPARC
123716: 07/09/02: Low-level FPGA programming?
123731: 07/09/03: Re: Low-level FPGA programming?
123977: 07/09/09: Minimize power consumption
123980: 07/09/09: Re: Minimize power consumption
123983: 07/09/09: Re: Minimize power consumption
123989: 07/09/10: Re: Minimize power consumption
124061: 07/09/11: Re: Minimize power consumption
124515: 07/09/25: Own soft-processor
dross:
46232: 02/08/22: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
Drotos Daniel:
17971: 99/09/20: Programming Spartan XL
<drs39@cornell.edu>:
105994: 06/08/04: Noob quesion about SDRAM usage.
106085: 06/08/07: Re: Newbie question about SDRAM usage
Dru:
48: 94/08/03: Re: How pricey is FPGA development?
78: 94/08/11: Re: Proprietary Configuration Data
Drule Anonymous Remailer:
14251: 99/01/22: Re: help w/ broken xilinx dongle
drummer_man:
156256: 14/01/25: Re: Xilinx BSCAN primitives proper use
156257: 14/01/25: Re: Xilinx BSCAN primitives proper use
ds:
46355: 02/08/27: Re: Anyone already on QUARTUS II V2.1 ?
46382: 02/08/27: Re: Anyone already on QUARTUS II V2.1 ?
46419: 02/08/29: Re: My SpartanII thinks it's a Virtex??
46441: 02/08/30: Re: Anyone already on QUARTUS II V2.1 ?
46644: 02/09/05: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46698: 02/09/06: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46747: 02/09/07: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46780: 02/09/09: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46959: 02/09/13: Re: Quartus 2 flow
47191: 02/09/20: Re: designing DDR I/O in CPLD
47256: 02/09/21: Re: Cheap development package for beginner?
47304: 02/09/23: Re: Altera Cyclone low-cost FPGA chips?
47399: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47458: 02/09/26: Re: FPGA programming via microcontroller
47559: 02/09/29: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47573: 02/09/29: Re: memory block instantiation in altera devices/FPGAs
47580: 02/09/30: Re: design multiplier
48028: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
48189: 02/10/13: Re: lpm library in mentor platform
48699: 02/10/23: Re: mif /hex files for lpm models
ds12:
13179: 98/11/18: VHDL testbench supporting reconfiguration?
16698: 99/06/03: Using Virtex LUT and MULT_AND
dsa fsag:
141831: 09/07/11: What is Clock Input? (Proofread)
dscolson@rcn.com:
102079: 06/05/10: Re: Programming the JTAG flash in circuit
102367: 06/05/15: Re: Virtex 5 announced
104537: 06/06/29: Re: help downloading picoblaze from xilinx
108303: 06/09/07: Re: Altera CPLD 7128S heating up
108304: 06/09/07: Re: Altera CPLD 7128S heating up
114727: 07/01/23: Re: Xilinx ISE 8.2
115777: 07/02/20: Re: ACTEL ProAsic Plus
116900: 07/03/20: Re: Programming XCF from MicroBlaze over JTAG???
119999: 07/05/30: Re: PacoBlaze 2.2
120028: 07/05/31: Re: PacoBlaze 2.2
124439: 07/09/21: Re: proasic plus. actel
133416: 08/06/27: Xilinx abandoning IEEE-1532 as programming option for iMPACT
148406: 10/07/19: Re: Another Xilinx webpack download rant
152458: 11/08/25: meta assembler
dsf:
53702: 03/03/20: Re: usb spartan prototype
<DSL_Warning@wsomwivfc.edu>:
28206: 00/12/29: DSL Availability In Your Area? .................... OVr9QUZ4ta3v
dsp:
97072: 06/02/15: system generator : change the default parameters
DSP_MADE_EASY:
115546: 07/02/13: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
<dspadmin@dspnet.dspnet.com>:
3045: 96/03/20: CFP - ICSPAT / DSP World Expo. Reminder ! (1 month to deadline)
DSPnet:
713: 95/02/15: NEW DSP Product Catalog on the WWW
DSPnet Administrator:
602: 95/01/17: Mercury Computer System described on the WWW
<dspnet!dspadmin@>:
482: 94/12/01: White Mountain's "DSP Summit" on the WWW
DSPtronics:
152074: 11/06/30: [ANNOUNCE] DSP-FPGA Programming Contest
DSS96:
9199: 98/03/01: Re: ORCAD front End Tools
17958: 99/09/19: Re: xilinx software
17959: 99/09/19: Re: simple VHDL?
18041: 99/09/25: Re: Fineline BGAs
<dstewart@dmicros.com>:
7180: 97/08/11: Re: free FPGA software from actel
<dteira@gmail.com>:
127159: 07/12/12: WARNING:PAR:289 and bitgen error.
<dtheodor@gmail.com>:
117311: 07/03/28: Compiling simulation libraries of EDK 8.1.02i under Linux
DTHIBAUL:
3846: 96/08/08: Re: Xilinx clock doubler?
3998: 96/08/31: Re: Looking for s/w to generate test vectors
4023: 96/09/03: Re: XACT STEP 6.0.1 SETUP PROBLEM
4024: 96/09/03: Re: xilinx programing
4065: 96/09/06: Help with XACT 6.0 ProSim Problem
4708: 96/12/04: Re: Memory Requirements
5254: 97/02/01: Re: Reconfigurable Logic Query
6284: 97/05/08: Re: X-BLOX
<dthiele@ccmail.esd.ray.com>:
8048: 97/11/11: Re: FPGA basics please ?
dtrang:
154384: 12/10/19: JTAG and Altera Cyclone-IV
dts4theworld:
139432: 09/03/29: USB port on FPGA - How is data transmitted?
139449: 09/03/30: Re: USB port on FPGA - How is data transmitted?
<dtsi.india@gmail.com>:
110600: 06/10/18: Re: Scoreboard and Checker in Testbench?
Duane:
23220: 00/06/17: Re: Request for experiences with Linux CAE tools
25145: 00/08/28: Re: availability of Spartan II
25397: 00/09/09: Re: pcilogic celss
26010: 00/09/30: Re: SV: hdl
26602: 00/10/21: Re: Xilinx 4000 reset
26847: 00/10/31: Re: Alliance under Linux?
26860: 00/11/01: Re: Alliance under Linux?
26859: 00/11/01: Re: Alliance under Linux?
26925: 00/11/03: Re: Alliance under Linux?
26949: 00/11/04: Re: Alliance under Linux?
26959: 00/11/05: Re: Alliance under Linux?
27119: 00/11/11: Re: Alliance under Linux?
27321: 00/11/17: Re: Schematics & VHDL
27568: 00/11/28: Re: Wide AND function.
27763: 00/12/06: Re: Wide AND function.
27831: 00/12/11: Re: fpga: 32 bit parity generation in 4 ns for virtexE
28097: 00/12/20: Re: Samsung SDRAM behavioural models
28342: 01/01/08: Re: Viewlogic to Eagle and vs.
28383: 01/01/10: Re: Alliance for Linux
28452: 01/01/12: Re: CRC - from long division to XOR, how?
28657: 01/01/19: Re: Alliance for Linux
Duane Clark:
6998: 97/07/21: Re: PCI burst transfers
8447: 97/12/15: Serial PROMs for Xilinx FPGAs
31129: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31198: 01/05/14: Re: Xilinx and Actel
31317: 01/05/18: Re: FPGA Express 3.5 One hot state machine Synthesis problem
31384: 01/05/21: Re: Finally, an FPGA tool chain for Linux (Also Synplicity)
32340: 01/06/23: Re: what tools run OK on windows 2000?
32358: 01/06/24: Re: what tools run OK on windows 2000?
32957: 01/07/12: Re: Xilinx makefile under RedHat
33257: 01/07/20: Stopping the clock in Virtex
33933: 01/08/08: Generate constants with a function
33983: 01/08/09: Re: Generate constants with a function
34078: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
34123: 01/08/14: Re: Porno Junk cluttering up CAF
34815: 01/09/09: Re: Xilinx dev. kit for Linux?
37366: 01/12/08: Re: I need a Xilinx Spartan PCI Development Board
37373: 01/12/08: Re: I need a Xilinx Spartan PCI Development Board
37389: 01/12/09: Re: I need a Xilinx Spartan PCI Development Board
37393: 01/12/09: Re: I need a Xilinx Spartan PCI Development Board
37397: 01/12/09: Re: I need a Xilinx Spartan PCI Development Board
38014: 01/12/30: Re: Innoveda Speedwave vs. Modelsim?
38344: 02/01/11: Re: Xilinx PAR and Editor speed up
38393: 02/01/13: Re: Homebrew computers using FPGA?
38426: 02/01/14: Re: Xilinx PAR and Editor speed up
39451: 02/02/10: Re: Xilinx EDIF to BIT transation
40662: 02/03/12: Re: exceeding 2GB limits in xilinx
43599: 02/05/25: Re: Time for a new computer. Suggestions?
43714: 02/05/30: Re: place and route simulation time
44551: 02/06/23: Re: Xilinx webpack if - else if statement ??
44653: 02/06/25: Re: How to generate a valid EDIF netlist?
44713: 02/06/27: Re: Xilinx tools under WinXP
44981: 02/07/08: Re: ISE 4.2i : Clock Buffer Disable
45166: 02/07/14: Re: Webpack under Linux ?
45254: 02/07/17: Re: How to add BUFG to an internal signal?
45264: 02/07/17: Re: How to add BUFG to an internal signal?
45492: 02/07/24: Re: vhdl dll question....help please
47172: 02/09/19: Re: Modelsim XE question
47217: 02/09/20: Re: Modelsim XE question
47233: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
47279: 02/09/22: Re: Xilinx ISE5.1 and Windows NT
47457: 02/09/25: Re: ISE 5.1 Linux?
49604: 02/11/17: Re: CLB logic function capabilities
50610: 02/12/13: Packing clock enable flipflops into IOB
50645: 02/12/15: Re: Packing clock enable flipflops into IOB
51829: 03/01/22: Re: Xilinx Spartan2 with more than 4 clocks
52632: 03/02/17: Re: VITAL_primitives Library in Xilinx WebPack
52821: 03/02/23: Re: VHDL & FPGA Design tools
52841: 03/02/24: Re: VHDL & FPGA Design tools
52980: 03/02/27: Re: linux vs windows
53523: 03/03/14: Re: Xilinx WebPACK on WINE -- getting close
53530: 03/03/14: Re: IFDs in Xilinx Foundation 4.1i
53532: 03/03/14: Re: Adding delay to a signal?
53539: 03/03/15: Re: Adding delay to a signal?
53617: 03/03/17: Re: IFDs in Xilinx Foundation 4.1i
54114: 03/04/02: Re: Help implementing BlockRAM on Spartan-II
54242: 03/04/05: Re: Xilinx Divider Core
54244: 03/04/05: Re: Help implementing BlockRAM on Spartan-II
54424: 03/04/10: Re: Xilinx IOB flip flop mapping
54425: 03/04/10: Re: Webpack 5.2 and Win98se
54444: 03/04/10: Re: Webpack 5.2 and Win98se
55023: 03/04/24: Re: ise4.2i and wine
55332: 03/05/04: Re: cable length on homemade Parallel Cable III
55769: 03/05/19: Re: a (PC) workstation for FPGA development
55841: 03/05/21: Re: a (PC) workstation for FPGA development
55846: 03/05/21: Re: a (PC) workstation for FPGA development
55899: 03/05/22: Re: a (PC) workstation for FPGA development
60018: 03/09/03: Re: Using a different editor for ISE 5
60516: 03/09/15: Re: need help with Xilinx ISE 4.2i software
61018: 03/09/26: Re: WARNING do not use your real email address in USENET postings!
61111: 03/09/28: Re: Free WebPack 6.1i Download Available Now for Spartan-3
63302: 03/11/19: Re: How do you keep layout info in VHDL?
67810: 04/03/19: Re: Speed of Linux vs Solaris
70478: 04/06/17: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70594: 04/06/21: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70836: 04/06/29: Re: Trouble with $readmemh in ModelSim
71084: 04/07/07: Re: FSM in illegal state
71143: 04/07/09: Re: FSM in illegal state
71150: 04/07/09: Re: FSM in illegal state
71282: 04/07/13: Re: micron sdram module
71353: 04/07/15: Re: micron sdram module
71354: 04/07/15: Re: FSM in illegal state (conclusion)
71414: 04/07/17: Re: Xilinx 6.2i ISE WebPACK running under wine?
71440: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
71441: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
71519: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71543: 04/07/21: Re: Xilinx 6.2i ISE WebPACK running under wine?
71544: 04/07/21: Re: xilinx ngdbuild old command flow problem
71621: 04/07/25: Re: Modelsim: No default binding for component
71683: 04/07/27: Re: xilinx ngdbuild old command flow problem
71801: 04/07/30: Re: Foundation evaluation on linux
72046: 04/08/06: Re: EDK tutorial?????
72209: 04/08/11: Re: ISE 6.2 : Place problem with V2PRO
72210: 04/08/11: Re: Impact running on wine?
72270: 04/08/12: Re: Attention Xilinx: command line tools would be useful [Was: Re:
72271: 04/08/12: Re: ISE 6.2 : Place problem with V2PRO
72489: 04/08/20: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72700: 04/08/29: Re: Impact vs. Linux RedHat Linux
72779: 04/09/01: Re: MGT
75514: 04/11/08: Re: ISE problems with Linux
75533: 04/11/08: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75700: 04/11/12: Re: Xilinx Webpack, simulate with off-chip-connected-pins? (VHDL)
76159: 04/11/26: Re: Searching for rad tolerant, non-volatile (once programmable)
77318: 05/01/04: Re: Procedure exit on global signal
77613: 05/01/12: Re: Starting with xilinix and Linux
78143: 05/01/25: Re: Updating Xilinx Bitstream/HEX file
78163: 05/01/25: Re: Linux on V2P
78218: 05/01/26: Re: Another problem getting ISE 6.3i running on Linux
78220: 05/01/26: Re: looking for the opb_core_ssp0_ref
78227: 05/01/26: Re: looking for the opb_core_ssp0_ref
78396: 05/01/31: Re: IPIF
78676: 05/02/05: Re: PPC on Virtex2P: Jumpstart, recommended reading?
78678: 05/02/05: Re: EDK+IPIF: Customizing wizard result
80042: 05/02/28: Re: RocketIO, where to start?
80252: 05/03/02: Re: Xilinx ISE7.1
80370: 05/03/04: Re: 100Mbps ethernet core
80398: 05/03/04: Re: 100Mbps ethernet core
80404: 05/03/04: Re: 100Mbps ethernet core
81027: 05/03/16: Re: Sensitivity list
81710: 05/03/30: Re: Xilinx EDK tool flow
81822: 05/04/01: Re: modelsim: Types do not match
82296: 05/04/10: Re: edk annual renewal cost?
82739: 05/04/17: Re: Xilinx tools from the commandline
82740: 05/04/17: Re: Xilinx tools on Linux
82849: 05/04/18: Re: Xilinx tools on Linux
82852: 05/04/18: Re: Xilinx tools from the commandline
82853: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82854: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82960: 05/04/20: Re: source control and Xilinx ISE 6 and 7
83098: 05/04/23: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83106: 05/04/23: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83140: 05/04/24: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83141: 05/04/24: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83245: 05/04/26: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83247: 05/04/26: Re: Sync + FIFO
83266: 05/04/26: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83306: 05/04/27: Re: Sync + FIFO
83633: 05/05/04: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83766: 05/05/06: Re: including components, i.e. SRL16
83768: 05/05/06: Re: DDR SODIMM on Avnet Virtex II PRO development kit
84185: 05/05/13: Re: Tristate-Master-Slave testbench description
84548: 05/05/20: Re: Simulation of rocket IO in virtex 2 pro
84684: 05/05/24: Re: more and more and more issues with Xilinx tools
84734: 05/05/25: Re: VHDL vs. Schematic Capture
84902: 05/05/31: Re: Xilinx DDR output registers
84943: 05/06/01: Re: why can't i use opb_spi core in EDK6.3?
84961: 05/06/02: Re: Quick way to synthesize pcores in EDK
86149: 05/06/22: Re: Xilinx
86187: 05/06/22: Re: simple SRAM memory controller Avnet V2P development board
86241: 05/06/23: Re: simple SRAM memory controller Avnet V2P development board
86354: 05/06/26: Re: unisim for synthesis?
86543: 05/06/29: Re: edn macro in ISE
86778: 05/07/06: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
86780: 05/07/06: Re: VHDL Clock Domains
86791: 05/07/06: Re: VHDL Clock Domains
86846: 05/07/07: Re: aurora reliability
86910: 05/07/08: Re: Xilinx ISE 7.1 : Macro search path in Transalate
87693: 05/07/28: Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone
87726: 05/07/29: Re: simple SRAM memory controller on the Altera Nios Dev Kit (Cyclone
87804: 05/08/01: Re: Xilinx Best Source for Reset
87805: 05/08/01: Re: Modifying opb_bram under EDK
87807: 05/08/01: Re: Bidirectional Bus problem with ModelSim.
87809: 05/08/02: Re: Modifying opb_bram under EDK
88369: 05/08/16: Re: Creating EDIF from VHDL
88599: 05/08/23: Re: chipscope problems
88649: 05/08/24: Re: DCM does not do anything?
88738: 05/08/26: Re: Kingston module structure
88859: 05/08/30: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
88918: 05/08/31: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
89137: 05/09/06: Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected
89199: 05/09/07: Re: Spartan-3E Starter Kit availability slips to December
89200: 05/09/07: Re: ISE7.1 SP4: proble and chipscope problem
89202: 05/09/07: Re: RocketIO code example
89290: 05/09/11: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89325: 05/09/12: Re: ISE 7.1i & Linux / reg code question
89600: 05/09/20: Re: how to set OPB EMC for flash use?
89601: 05/09/20: Re: how to set OPB EMC for flash use?
89605: 05/09/20: Re: Core import into ISE
89610: 05/09/20: Re: Core import into ISE
89867: 05/09/28: Re: Version Control Software
89954: 05/09/30: Re: Power on reset generation in FPGA
89956: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89966: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
89972: 05/09/30: Re: Version Control Software
91270: 05/11/02: Re: FPGA : PCI-CORE
91759: 05/11/11: Re: Add files to Xilinx ISE Project w/script
92008: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92104: 05/11/22: Re: Patient Monitors: Reading RS232 output w/ an FPGA
92122: 05/11/23: Re: Disabling Xilinx clock enable usage...
92174: 05/11/23: Re: Aurora over Rocket IO and EDk
92178: 05/11/23: Re: Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a
92205: 05/11/23: Re: Bidirectional Bus
92402: 05/11/29: Re: ISE question on whats a "X_LUT3"?
93276: 05/12/18: Re: How to use ISE FPGA Editor to compare timing path easily?
93363: 05/12/20: Re: Virtex II Pro XC2VP100
93782: 05/12/30: Re: PPC405 on ISE
94291: 06/01/09: Re: CRC error correction
94378: 06/01/11: Re: application running on the top of Linux on virtex-ii pro
94712: 06/01/16: Re: BRAM/XMD strangeness?
94947: 06/01/19: Re: How to NON_CLK pin that messes my clock
95228: 06/01/21: Re: Modelsim problem
95527: 06/01/23: Re: LVDS Input buffer in VHDL (ISE)
95883: 06/01/26: Re: Are the Xilinx pcores files not searchable?
95997: 06/01/27: Re: Are the Xilinx pcores files not searchable?
95999: 06/01/27: Re: HOW CAN I USE OPB EMC
96041: 06/01/28: Re: HOW CAN I USE OPB EMC
96675: 06/02/08: Re: vhdl to edif
96727: 06/02/09: Re: vhdl to edif
97766: 06/02/27: Re: FPGA: Model-SIm XE problem
97768: 06/02/27: Re: FPGA: Model-SIm XE problem
98097: 06/03/04: Re: EDK: choices for simple internal control
98103: 06/03/04: Re: EDK: choices for simple internal control
98104: 06/03/04: Re: why use an FPGA when a CPLD will do ??
98156: 06/03/06: Re: EDK: choices for simple internal control
98233: 06/03/07: Re: what do the following constraints mean?
98796: 06/03/16: Re: Where are FPGA heading?
99284: 06/03/22: Re: need help on asynchronous buffer
99362: 06/03/23: Re: ACE Formatter for Linux (was Re: Parallel Cable IV...)
100018: 06/04/01: Re: Testing sample Aurora design on ML321 board
100019: 06/04/01: Re: Discrete
100303: 06/04/06: Re: ddr in virtex2
100399: 06/04/07: Re: Testing sample Aurora design on ML321 board
100411: 06/04/08: Re: Why does Synplify add clock buffers?
100415: 06/04/08: Re: Why does Synplify add clock buffers?
100571: 06/04/12: Re: Testing sample Aurora design on ML321 board
101473: 06/05/01: Re: Book Software for XC3190A?
102647: 06/05/18: Re: OFFSET constraints with derived clocks - Xilinx FPGA
102659: 06/05/18: Re: DCM and Clock
103426: 06/06/01: Re: Using version control for Xilinx 8.1i ISE projects and source
103902: 06/06/14: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
103903: 06/06/14: Re: Xilinx XST Error
103911: 06/06/14: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
103918: 06/06/14: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
103933: 06/06/15: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
103948: 06/06/15: Re: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
104171: 06/06/20: Re: Xilinx ISE 8.1i Trouble
104251: 06/06/21: Re: Xilinx ISE S/W Install kernel version "mismatch"
104315: 06/06/23: Re: Xilinx ISE S/W Install kernel version "mismatch"
104377: 06/06/26: Re: R: still having same error
104379: 06/06/26: Re: VHDL model for Micron SDRAM simulation ?
104383: 06/06/26: Re: R: R: stillcan't access xilinxcorelib,where does modelsim looks
104392: 06/06/26: Re: R: R: R: stillcan't access xilinxcorelib,where does modelsim
104441: 06/06/27: Re: Synplify & Fedora core 5
104456: 06/06/27: Re: RS232 to access TX registers of Aurora using PPC (EDK)
104463: 06/06/28: Re: RS232 to access TX registers of Aurora using PPC (EDK)
104488: 06/06/28: Re: RS232 to access TX registers of Aurora using PPC (EDK)
104491: 06/06/28: Re: Spartan 3E, Output File
104613: 06/07/01: Re: How to control the uart
105045: 06/07/12: Re: Binary Counter Core
105060: 06/07/12: Re: Binary Counter Core
105722: 06/07/29: Re: Issues w/ 8 lane Aurora sample design
105831: 06/08/01: Re: Problems compiling with ISE Webpack 8.2.01i
105894: 06/08/02: Re: Problems compiling with ISE Webpack 8.2.01i
107446: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107653: 06/08/30: Re: Aurora implementation
107990: 06/09/03: Re: Here are the URLs (was Re: Impossible to download WebPACK?)
108032: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
109904: 06/10/07: Re: An implementation of a clean reset signal
110365: 06/10/14: Re: EDIF Design Entry tools
110366: 06/10/14: Re: DDR Address
110376: 06/10/14: Re: EDIF Design Entry tools
110390: 06/10/15: Re: EDIF Design Entry tools
110429: 06/10/15: Re: EDIF Design Entry tools
110764: 06/10/21: Re: Can ISE text editor generate CRLF line endings?
110903: 06/10/25: Re: Single Bank Vs Multiple Banks in sdram
111348: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111494: 06/11/03: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111503: 06/11/04: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111529: 06/11/04: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111530: 06/11/04: Re: Cleaning generated files in Xilinx 8.2 EDK and ISE
111574: 06/11/06: Re: reset
112212: 06/11/17: Re: PCMCIA interface
113116: 06/12/06: Re: Clock phase shift
115130: 07/01/31: Re: Where is help for schematic entry?
116597: 07/03/13: Re: Dual edge detection
116886: 07/03/20: Re: How to use the DDR SDRAM instead of Block RAM?
116922: 07/03/21: Re: Virtex-II block RAM problem
117131: 07/03/23: Re: Virtex-II block RAM problem
117132: 07/03/23: Re: Virtex-II block RAM problem
117334: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117341: 07/03/28: Re: Problems with Xilinx Parallel III Cable
117345: 07/03/28: Re: Problems with Xilinx Parallel III Cable
118498: 07/04/27: Re: Is there a reset signal available in verilog in Xilinx FPGAs?
119697: 07/05/24: Re: Ddr sdram feedback pin
119868: 07/05/28: Re: Ddr sdram feedback pin
120126: 07/06/01: Re: Ise Flow with PowerPC
120185: 07/06/02: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120208: 07/06/03: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120280: 07/06/04: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
121928: 07/07/15: Re: How to create and map user library in command-line?
122131: 07/07/19: Re: Library unit VPKG is not available in library UNISIM
122665: 07/08/02: Re: Xilinx Webpack 9.2 and Windows 2000 Pro?
122906: 07/08/09: Re: EDK speed issue
123228: 07/08/20: Re: At what frequencies is it acceptable to generate a clock from
124920: 07/10/10: Re: HELP, how to time constraint part of a design?
124931: 07/10/10: Re: HELP, how to time constraint part of a design?
124943: 07/10/11: Re: HELP, how to time constraint part of a design?
124972: 07/10/13: MIG for Linux?
124983: 07/10/14: Re: MIG for Linux?
124986: 07/10/14: Re: MIG for Linux?
125016: 07/10/15: Re: MIG for Linux?
125023: 07/10/15: Re: Xilinx timing constraints incorrect?
125028: 07/10/15: Re: MIG for Linux?
125130: 07/10/16: Re: Xilinx timing constraints incorrect?
125150: 07/10/16: Re: Xilinx timing constraints incorrect?
125185: 07/10/17: Re: Xilinx timing constraints incorrect?
125269: 07/10/18: Re: VHDL trivia?
125397: 07/10/24: Re: Paper about selecting fixed point bit widths?
125975: 07/11/10: Xilinx USB cable in Fedora 7
126023: 07/11/12: Re: Strange VHDL Error
126157: 07/11/15: Re: EDK 9.1 Issues
126158: 07/11/15: Re: synopsys translate_off
126189: 07/11/16: Re: simulating xilinx block ram with modelsim
126202: 07/11/16: Re: simulating xilinx block ram with modelsim
126231: 07/11/17: Re: simulating xilinx block ram with modelsim
126332: 07/11/19: Re: simulating xilinx block ram with modelsim
126766: 07/12/01: Re: Using SRAM Memory CY7C1386C
126767: 07/12/01: Re: Using DDR RAM on XUP V2Pro board
127134: 07/12/12: Re: Xilinx RocketIO problems
127138: 07/12/12: Re: Debugging designs that are running on FPGA
127160: 07/12/12: Re: FPGA Board design basics
127189: 07/12/13: Re: Debugging designs that are running on FPGA
127201: 07/12/13: Re: Debugging designs that are running on FPGA
127470: 07/12/27: Re: Core Generators...
127472: 07/12/27: Re: Xilinx EDK 9.2 problems under Centos 5
127929: 08/01/10: Re: Cant capture data with Chipscope 7.1
128180: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128193: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128401: 08/01/24: Re: EDK 9.2i install issues in Linux
128607: 08/01/31: Re: PC requirements for ISE webpack
128651: 08/02/01: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128959: 08/02/11: Re: ModelSim versus Active-HDL....redux
128996: 08/02/12: Re: ModelSim versus Active-HDL....redux
130186: 08/03/17: Re: Help on Virtex-II Pro global clocks.
130198: 08/03/17: Re: Help on Virtex-II Pro global clocks.
130251: 08/03/19: Re: Help on Virtex-II Pro global clocks.
130813: 08/04/02: Re: coregenerator bram in synplify pro error
130821: 08/04/02: Re: coregenerator bram in synplify pro error
130860: 08/04/03: Re: coregenerator bram in synplify pro error
130863: 08/04/03: Re: coregenerator bram in synplify pro error
131278: 08/04/17: Re: how do I test signals in a testbench that are 1 or 2 levels down
131590: 08/04/25: Re: How to arrange these SRL16 in a straight column
131693: 08/04/29: Re: Chirp generator / CORDIC algo ?
131694: 08/04/29: Re: Functional Simulation of Virtex-4 Block Memory
131737: 08/04/30: Re: Functional Simulation of Virtex-4 Block Memory
131751: 08/04/30: Re: Functional Simulation of Virtex-4 Block Memory
131762: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
131764: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
131768: 08/05/01: Re: Old FPGA question
131769: 08/05/01: Re: Old FPGA question
131775: 08/05/01: Re: Old FPGA question
131776: 08/05/01: Re: FLASH vs SRAM (was Re: Old FPGA question)
131782: 08/05/02: Re: Functional Simulation of Virtex-4 Block Memory
131998: 08/05/09: Re: Chirp generator / CORDIC algo ?
135005: 08/09/10: Re: Signed multiplication
136079: 08/10/30: Re: ISE 9.2.03i problem
Duane Hague:
25663: 00/09/16: Reassurance on Xilinx Sought
35380: 01/10/02: Re: Barrel Shifter
35396: 01/10/02: Re: Barrel Shifter
39304: 02/02/06: Re: Programming Altera PGAs.
Duane Perry:
45933: 02/08/11: 485 core
DUBOSSE Thierry:
54915: 03/04/22: Re: Webpack 5.2 Install problems?
Duc Quan:
68141: 04/03/27: Single port RAM with latch at the output
Duccio:
97656: 06/02/25: Low power consumption board with memory
97926: 06/03/01: Re: Low power consumption board with memory
98756: 06/03/16: CoolRunner 2 CPLD
Duck Foot:
14076: 99/01/12: Pre-route simulation in SYNOPSYS
14085: 99/01/12: Pre-simulation in SYNOPSYS
14180: 99/01/18: constant and signal for fuction parameter
14414: 99/01/29: Hold Time Violation
14415: 99/01/29: Hazard
14482: 99/02/01: Hazard again
14500: 99/02/02: Re: Hazard
16614: 99/05/31: sif_wildcard_eql?
18929: 99/11/22: Hierarchical Scan Insertion
dude:
122214: 07/07/24: ise 9.2 fatal error
Dude Whocares:
152896: 11/10/30: Fundamental DSP/speech processing patent for sale
dudesinmexico:
133829: 08/07/16: Xilinx/Altera gate equivalence
133832: 08/07/16: Re: Xilinx/Altera gate equivalence
133835: 08/07/16: Re: Xilinx/Altera gate equivalence
134506: 08/08/14: Question on V4 HSPICE model
135063: 08/09/12: Problem with Virtex-4 IBIS model
<dudesinmexico@gmail.com>:
95763: 06/01/25: Xilinx on the fifo16 issue
124523: 07/09/25: Logic minimization software with LUT6 support?
124567: 07/09/26: Re: Logic minimization software with LUT6 support?
124572: 07/09/26: Re: Logic minimization software with LUT6 support?
<dudesinmexico@yahoo.com>:
135090: 08/09/15: Re: Problem with Virtex-4 IBIS model
135091: 08/09/15: Re: Problem with Virtex-4 IBIS model
dudu:
45591: 02/07/28: Re: Translate the design from FPGA to Custom IC
<duke@hrsupport.com>:
10120: 98/04/28: Cartoons For Engineers
<dulik@dcse.fee.vutbr.cz>:
21292: 00/03/15: SystemC vs. VHDL
<dulik@my-deja.com>:
18538: 99/10/29: Altera - how to make probe to a routed chip ?
20065: 00/01/26: Re: Atmel config PROMs
20066: 00/01/26: Anyone has Synplify 5.1 eval ?
<dumak23@yahoo.com>:
99684: 06/03/28: OPB monitor error
99710: 06/03/28: Re: OPB monitor error
99713: 06/03/28: Re: OPB monitor error
Duncan Charity:
3941: 96/08/23: Re: FPGA vs. Custom design
Duncan Crowther:
15902: 99/04/20: Re: Question about Statechart
16297: 99/05/14: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
37544: 01/12/14: Re: datapath schematic editor
Duncan Davis:
4664: 96/11/27: Re: Which Mentor Graphics synthesis tool?
5367: 97/02/11: Gate level Simulation with Mentors Quicksim from Galileo
6396: 97/05/21: Re: Problem in Leonardo synthesis targetting Altera
Duncan Enright:
7319: 97/08/26: FPGA design text
Duncan Entwisle:
73542: 04/09/23: Re: Problem with Xilinx Webpack documentation
Dunstan Power:
12880: 98/11/03: Xchecker cable NT problem
128721: 08/02/05: Re: Bitstream verification through readback
128723: 08/02/05: Re: Minimum Oscillator Frequency
128727: 08/02/05: Re: A way to limit the data path delay
128729: 08/02/05: Re: How to optimize my design area to fit?
129136: 08/02/15: Re: Erratic Behavior of Virtex 4 FPGA
duola:
36346: 01/11/07: How can I use the instance of block RAM of Spartan2 in Synplify?
36389: 01/11/07: How can I implement such a counter in Verilog?
36689: 01/11/15: How can I solve the "clock" warning of synplify.
36690: 01/11/15: Why can not I find the 2S200PQ208 in the aldec's Spartan2 familly?
Duraid Madina:
2155: 95/10/21: FPGAs as a substitute for glue logic?
Durham 206 Mac 7200:
4330: 96/10/16: PCI compliant ?
Durward:
67149: 04/03/06: Best Starter Guide for Xilinx FPGA Editor?
67152: 04/03/07: Newbie Question on Xilinx Macros and Pads
Dustin:
152232: 11/07/25: Re: About the setup time of BUFGMUX in Spartan6
Dustin Brothers:
152210: 11/07/21: Re: FPGA not getting programmed
152211: 11/07/21: Re: source synchronous DDR bus with non-continuous clock
152231: 11/07/25: Re: FPGA not getting programmed
dutchgoldtony:
82646: 05/04/15: Re: Functional vs, Timing
Duth:
101545: 06/05/02: Re: ISE 8.1 Comment Bug, Very hideous
106774: 06/08/18: Re: Webpack ISE simulator error
109056: 06/09/20: Re: ISE Simulator Error 222: SuSE 10.1 Linux
109094: 06/09/20: Re: ISE Simulator Error 222: SuSE 10.1 Linux
114168: 07/01/05: Re: ISE Simulator radix question
114694: 07/01/23: Re: Different Modelsim versions disagree in same backannotation!
114702: 07/01/23: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114704: 07/01/23: Re: what happened to modular design in ISE9
114705: 07/01/23: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114919: 07/01/26: Re: ModelSim Leaf Instances
114994: 07/01/28: Re: Inferring Xilinx RAM's with Byte enable options
115099: 07/01/30: Re: How to use the test bench wave form simulator?
115219: 07/02/03: Re: Question about simple design
115228: 07/02/03: Re: Xilinx (without init value) has a constant value of 0?
116820: 07/03/19: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
117333: 07/03/28: Re: Post PAR simulation for RAM Block implementations
117783: 07/04/10: Re: record type port in vhdl and simulation in ISE
117785: 07/04/10: Re: Why I cannot use the XAUI core(generated by xilinx)
118186: 07/04/19: Re: Problems in simulation (Webpack 9.1.03i)
118187: 07/04/19: Re: Compiling a library
119096: 07/05/11: Re: JTAG_SIM_VIRTEX5
119100: 07/05/11: Re: JTAG_SIM_VIRTEX5
120058: 07/05/31: Re: Problems to simulate (behavioural) in XPS
120136: 07/06/01: Re: Problems to simulate (behavioural) in XPS
120518: 07/06/08: Re: HELP with Asynch RAM
120833: 07/06/18: Re: Enumerated type simulation issue (ISE simulator, 9.1.03i)
120835: 07/06/18: Re: How to simulate testbenches using the ISE simulator in linux
120839: 07/06/18: Re: Enumerated type simulation issue (ISE simulator, 9.1.03i)
120840: 07/06/18: Re: How to simulate testbenches using the ISE simulator in linux
120875: 07/06/19: Re: How to simulate testbenches using the ISE simulator in linux
120928: 07/06/20: Re: How to simulate testbenches using the ISE simulator in linux
121640: 07/07/10: Re: regarding post place and route timing simulation steps........
121834: 07/07/13: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121841: 07/07/13: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
123078: 07/08/15: Re: How to save simulation results in Xilinx ISE ?
123380: 07/08/26: Re: how to keep all settings between runs
123540: 07/08/29: Re: Question about xflow?
123541: 07/08/29: Re: how to keep all settings between runs
123992: 07/09/10: Re: DDR Simulation via MIG
133355: 08/06/25: Re: Xilinx SecureIP simulation and third-party simulators?
133357: 08/06/25: Re: Xilinx SecureIP simulation and third-party simulators?
133421: 08/06/27: Re: Xilinx SecureIP simulation and third-party simulators?
136421: 08/11/15: Re: Would like to try ISIM, simple question
141980: 09/07/20: Re: VIRTEX-6 FXT announced soon?
duy:
40363: 02/03/05: Block Ram
Duy K Do:
46519: 02/09/02: IT consultant vs Engineer
48180: 02/10/12: Polisilicon ???
51342: 03/01/10: MicroBlaze MDK2.2 opb_timer
Duy Loi Vu:
330: 94/10/21: iFX780's experiences
<dvakar@gmail.com>:
155217: 13/06/12: Re: MIPI CSI-2 camera interface to parallel
<dvpysz@yahoo.com>:
Dwayne Dilbeck:
127375: 07/12/19: ASIC verification job info request
127378: 07/12/19: Re: ASIC verification job info request
127404: 07/12/20: Re: ASIC verification job info request
128063: 08/01/14: Re: Debbuging a RISC processor on an FPGA
128064: 08/01/14: Re: Read/Write SRAM on Spartan3 Starter kit
128084: 08/01/14: Re: ieee_ proposed library
128188: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128192: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128262: 08/01/19: Re: Quartus-II 7.2sp1 and Systemverilog Assertion SVA?
128264: 08/01/19: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128432: 08/01/25: Re: Random Number Generation in VHDL
128441: 08/01/25: Re: Random Number Generation in VHDL
128611: 08/01/31: Re: I need a SDRAM controller
128613: 08/01/31: Re: Design security for pre-Virtex2 parts ?
128616: 08/01/31: Re: Design security for pre-Virtex2 parts ?
128703: 08/02/04: Re: A video tutorial: The Xilinx FPGA Editor
128712: 08/02/04: Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to set Spartan-3E as target
128749: 08/02/05: Re: GCLK overmapped
129022: 08/02/12: Re: My first verilog/cpld project
129116: 08/02/14: Re: My first verilog/cpld project
129120: 08/02/14: Re: Spartan 3 configuration download error
129126: 08/02/14: Re: Spartan 3 configuration download error
129156: 08/02/15: Re: distorted sine wave
129302: 08/02/20: Re: From ASIC RTL to FPGA, what are the things I should take care of?
129303: 08/02/20: Re: MicroBlaze simulator, software ownership rights for SALE
129358: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129479: 08/02/25: Re: Problem with PINs XC3S700A-4FG484
129515: 08/02/26: Re: Convert some table into combinatorial circuit + optimization
129516: 08/02/26: Re: Convert some table into combinatorial circuit + optimization
129518: 08/02/26: Re: Convert some table into combinatorial circuit + optimization
129568: 08/02/27: Re: ADC to FPGA Interface Webcast
129608: 08/02/28: Re: What demokit and VHDL compiler pair to buy
129708: 08/03/03: "Use Multi-level Logic Optimization" -- Advanced Fitting option
129714: 08/03/03: Re: "Use Multi-level Logic Optimization" -- Advanced Fitting option
129802: 08/03/05: Re: could use some help with verilog/vhdl
129803: 08/03/05: Re: Anyone to open "FPGA museum" ? Here is first item :)
129809: 08/03/05: Re: question about verilog language constructs
129958: 08/03/11: Re: Could I develop a new gui using java based on the script language of ChipScope?
129960: 08/03/11: Re: New FPGA beginner's Video guide
129961: 08/03/11: Re: New FPGA beginner's Video guide
130001: 08/03/12: Re: Could I develop a new gui using java based on the script language of ChipScope?
134639: 08/08/22: Re: Image input
Dwayne J. Padgett:
3282: 96/05/08: Re: FPGA for Space Application
Dwayne Surdu-Miller:
67955: 04/03/23: Re: Altera and PCI-X
68060: 04/03/25: Re: How many times can I burn an FPGA?
68386: 04/04/02: Re: PCI development kit
68760: 04/04/16: Re: PCI Express specification.
68854: 04/04/20: Re: PLL and DLL
68905: 04/04/21: Re: FPGA within demonstration
68985: 04/04/23: Re: PLL and DLL
69058: 04/04/26: Re: PLL and DLL
69059: 04/04/26: Re: PLL and DLL
69509: 04/05/12: Re: Looking for Synario 3.0 (Lattice)
70695: 04/06/23: Re: 5V board in a 3.3V PCI slot
70739: 04/06/25: Re: Large fast FIFO?
70740: 04/06/25: Re: Large fast FIFO?
70743: 04/06/25: Re: 5V board in a 3.3V PCI slot
70790: 04/06/28: Re: 5V board in a 3.3V PCI slot
71039: 04/07/06: Re: VHDL in Xilinx : why this signal is regarded as Global Clock
71040: 04/07/06: Re: VHDL in Xilinx : why this signal is regarded as Global Clock
71041: 04/07/06: Re: VHDL in Xilinx : why this signal is regarded as Global Clock
75516: 04/11/08: Re: SDRAM sustained bursts
75535: 04/11/08: Re: SRAM to be able to read/write Micron SDRAM
75695: 04/11/12: Re: Xilinx Tshirts in football package.....
75696: 04/11/12: Re: Xilinx Tshirts in football package.....
76045: 04/11/23: Re: Help! What is this card?
76056: 04/11/23: Re: Low cost million gate Spartan 3 board?
76057: 04/11/23: Re: Low cost million gate Spartan 3 board?
dwecker:
142095: 09/07/24: spartan-3 starter kit board JTAG-usb cable
dwerdna:
80670: 05/03/09: Re: Global Reset paths
80677: 05/03/09: Re: 1,5Mhz Clock
80681: 05/03/09: Re: Global Reset paths
146395: 10/03/15: VHDL-2008 'protect
dwesterg@gmail.com:
83368: 05/04/28: Re: Cygwin & Nios II
84479: 05/05/19: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
Dwight Elvey:
2304: 95/11/18: Re: Industry Trends
dwight elvey:
50483: 02/12/11: Re: Tiny Forth Processors
50486: 02/12/11: Re: Tiny Forth Processors
66472: 04/02/19: Re: Dual-stack (Forth) processors
<dwp@deltanet.com>:
3259: 96/05/05: FS Actel development system
dwtdw:
8574: 98/01/09: Altera Flex10K Standby Current
8604: 98/01/12: Re: Altera Flex10K Standby Current
<dwukuo@speedyinternet.com>:
Dylan Buli:
31016: 01/05/09: Re: Need Advice on what Xilinx Tools to purchase
32372: 01/06/25: Re: Xilinx Alliance tools timing summary results interpretation
33473: 01/07/27: Re: Simple question
Dziadek:
30637: 01/04/20: Re: wanted: dig. board with FPGA and processor
30988: 01/05/08: Re: analog and digital?
41409: 02/03/27: XC9500 low temp. problem
41433: 02/03/28: Re: XC9500 low temp. problem
42365: 02/04/22: Re: XC9500XL problem
47195: 02/09/20: Re: Overheat with XCV-600E
48254: 02/10/15: Re: low power embedded FPGA
49743: 02/11/20: Xilinx programming and PCI printer port
49786: 02/11/21: Re: Xilinx programming and PCI printer port
51297: 03/01/10: Spartan-2 reset: sync or async?
53107: 03/03/04: Re: Spartan II PCB, bypass Capacitors
56333: 03/06/03: Re: JTAG madness
56386: 03/06/04: Re: JTAG madness
57977: 03/07/11: Re: Missing something...
92268: 05/11/25: Re: XC2000
Dzintar Dravnieks:
6378: 97/05/20: Job opportunity, Xilinx experience, Berkeley CA
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