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> I'm not sure, but it seems to me that there are two main advantages to > using an fpga: 1) design is quicker because it may be programmed through > software 2) production is quicker/cheaper because there is no "glue-logic" > all over the place and you don't have to wait for in-factory designed ASICs. > > For reason 1, I see why reprogrammability is a good thing. > For reason 2, why is reprogrammability important? > > If I'm missing something, please let me know. > > Garett The idea behind this form is that fpgas can be used for computing. To me this means being able to reprogram an fpga over and over again. By taking a program and implementing the compute intensive part of that program in hardware we seek to accelerate an application. The buzz words we are tring to push are 1) Transformable computers - Computer systems that use the reconfigurable features of fpgas to implement an algorithm. 2) Hardware object - That portion of an algorithm that gets implemented in hardware. At Virtual Computer we make what is possibly the simplest transformable computer the Engineers' Virtual Computer (EVC). The EVC is a single fpga (xc4010 or xc4013) based SBus card. We have interfaces on the hardware and software side that makes it easy to implement part of a algorithm in hardware and then talk to that hardware. We currently support hardware programming interfaces with Viewlogic schematic capture and verilog. So after you do a design we convert the Xilinx raw-bits file into a static array that can be downloaded into the xilinx at any time. The hardware object is emmbeded right in the complied exacutable. We believe that machines that allow the execution of a transfom in reconfigurable hardware are a new style of computer architecture which is why this form is comp.arch.fpga and not vlsi.fpga. Transformable system are like a cross between data-flow/risc/vlwis computers and present some of the most flexible and powerful computing solution available today. Of course being so flexible these computers are more difficult to program. The EVC is a step to easy programming since all EDA vendors support programming a single part. We need "C" compliers that understand (or can be directed) how to identify what parts of the code can benefit from hardware acceleration. Anyway thats just the tip of the iceburg as they say! Steve Casselman Virtual ComputerArticle: 351
Hmm.. Is there a somebody who can tell me about the current situation the ALTERA fpga series? I have very interesting about the toggle rate. Thanks SiwonArticle: 352
Andrew Wolfe <awolfe@oink.Princeton.EDU> writes: >Why bother. Transistors cost a nickel each! Since you seem to be cost (not >space) driven - just add a transistor to each output as a driver. Current >limit each segment with a resistor. For under $2 you can get a very bright >display. No worries about burning up a Xilinx chip. > >(Of course - we know that the real problem is that most EE's don't know how >to design a circuit with a transistor anymore :-) LEDs, transitors ? Why not Nixie tubes ? Just be carefull of the 150V suply, I once smoked a BUNCH of chips in a device that used Nixie tubes. Martin MoellerArticle: 353
I have a high frequency clock (25 MHz) that I want to divide down to something under 1 KHz. The exact divisor is not important. I want to do this in a large PAL (AMD Mach device) at minimal cost in terms of product terms, routing use, and logic block fan-in use so I thought a LFSR might be applicable. I've got a design now with 15 stages and the input is the XOR of the LSB and the MSB, it seems to do reasonably well but I'd like to know a little more about how to design a circuit as needed. For example, if you had a particular divisor to implement, is there an algorithm to generate the circuit? -- Congratulations to the people who saved Mono Lake!Article: 354
In article <PFILE.94Oct24140539@sun33.cs.wisc.edu> pfile@sun33.cs.wisc.edu (Rob Pfile) writes: >In article <fliptronCy5pz4.98A@netcom.com> fliptron@netcom.com (Philip Freidin) writes: > > > Actually, the XC4000A parts are also specified for 24mA. In the realm > of FPGAs, only Xilinx makes FPGAs with 24mA drive. There are some PAL > >Is this true? I thought that Altera FLEX8000 parts can sink or source >25mA per pin. > >rob >pfile@cs.wisc.edu The spec for the Altera FLEX8000 parts is Ioh = -4mA , Iol = 8mA. >From the FLEX8000 data sheet dated Feb-93, page 12. As noted else where in this thread by Pak Chan, the outputs of the Xilinx do sink 24mA and source -4mA (XC4000A, 1994 databook, p2-72, XC4000H, p2-92) This asymetric drive is somewhat of a holdover from the days of TTL that has a similar low and high current, and is somewhat driven by the way busses are designed. A typical terminated bus has a 220 ohm resistor to VCC, and 330 ohm to ground. This gives a thevinin eqivalent value of 132 ohms. The undriven state of the bus line is 3 volts, which is a logic high. To drive this line to a TTL logic high ( > 2.4 volts) requires no source current at all. A driver (like the XC4000/A/H) that supplies 4 mA will just get the line to a logic high faster. To drive the line low to the specified Vol of 0.5 volts means putting 4.5 V across the 220 ohm resistor. This takes 20.4 mA. Allowing for voltage, temperature and VCC margins, causes the driver to be built for 24 mA continuous current sink. Most drivers that meet these specs can actually source and sink far more current than these guaranteed numbers, but exceeding these values is outside the range of the specification, and when you smoke the chip the manufacturer is not going to be very sympathetic. Typical limits for this can be foud in the I/V curves for the products, as I have mentioned in my earlier post. All the best, Dont smoke chips Philip Freidin.Article: 355
In article <38gsu5$pdo@mordred.gatech.edu> npomponi@cmdl.gatech.edu (Nick Pomponio) writes: >I have a project coming up that will require very low power (sub-mA), 3V >logic operating in the few hundreds of KHz. I would like to persue a >FPGA/CPLD design. What manufacturers offer the lowest operating >power devices? > >Thanks. > As usual, I will tell you about the Xilinx products: The lowest power parts that Xilinx makes are the XC3000L product line that goes from XC3020L to XC3090L, about 1200 to 4500 gates, your milage will vary. These devices are rated at 3.3 Volts, and idle current as low as 30 uA. Total current is design dependant, clock dependant, and output load dependant. I dont know of any other FPGA/EPLD/CPLD/PAL that has operational current as low as these parts. These can also be used at 5.0 V, and the standard XC3000 can also run at power levels similar to the XC3000L, but they wont run at 3.3 V All the best Philip FreidinArticle: 356
In article <38j80e$ghk@mark.ucdavis.edu> gbchoy@salsa.engr.ucdavis.edu (Garett B Choy) writes: >But, but I did want a discussion on different fpga >technologies (good and bad experiences). > >I'm not sure, but it seems to me that there are two main advantages to >using an fpga: 1) design is quicker because it may be programmed through >software 2) production is quicker/cheaper because there is no "glue-logic" >all over the place and you don't have to wait for in-factory designed ASICs. Well, actually, you do the design, the in-factory part is manufacturing > >For reason 1, I see why reprogrammability is a good thing. >For reason 2, why is reprogrammability important? > >If I'm missing something, please let me know. > >Garett > Here are a few reasons that reprogrammable parts are desirable in 1 and 2 A) The devices can be FULLY tested through many different actual paths through the chip, at speed. (Cant do this with anti-fuse. probably wont do it on an EPROM process because the erase time is nontrivial and multiple test patterns takes too long, and requires multiple cycles between the tester and the eraser.) B) In YOUR system, you might want to use the reprogrammability as part of your design, to dynamically change the function. A good example is the RADIUS PIVOT computer screen for the MAC. You can rotate the screen 90 degrees to switch from portrait to landscape mode. The video system for this monitor has a Xilinx chip in it which is reconfigured for the different operating mode. Although it does not seem to be happening, This news group was created specifically to discuss computing engines that are made up of FPGAs, and that are reconfigured either as the application is running, or between applications. (Probably not happening because I post too many articles). C) Many designers use the reconfigurability to load a different design into the FPGA during system test. This facilitates generating and verifying test patterns, at speed, when the board is on the board tester. You could, for example load the chip with a JTAG design. D) There are many more, but I think I have posted enough articles tonight. All the Best Philip Freidin.Article: 357
In article <38j80e$ghk@mark.ucdavis.edu>, Garett B Choy <gbchoy@salsa.engr.ucdavis.edu> wrote: >I'm not sure, but it seems to me that there are two main advantages to >using an fpga: 1) design is quicker because it may be programmed through >software 2) production is quicker/cheaper because there is no "glue-logic" >all over the place and you don't have to wait for in-factory designed ASICs. > >For reason 1, I see why reprogrammability is a good thing. >For reason 2, why is reprogrammability important? > >If I'm missing something, please let me know. OTP = One Time Programmable I would put the advantages more as: 1) Design is quicker because it is more of a compile/link/execute sort of cycle. You can try multiple changes in a single day and fix one problem at a time. [ Applied mostly to reprogrammables, since it is wasteful to throw away the OTP part after only making one minor change. ] 2) Production is quicker because there is less chance of a new board layout being required. You can 'hide' your mistakes inside the FPGA. You can also (sometimes) make small adjustments to the design if required. [ Applies equally to both ] 3) Maintenence is better because many ECOs require only a programming change. [ Applies equally to both, but cost of ECO is higher for OTP part. You might have some programmed parts on the shelf that you have to throw away. The SRAM based reprogrammables are cheaper to upgrade, since you can socket a single PROM to handle all of them. ] 4) Support in the field is better because many changes can be done by changing the EPROM on the card and reprogramming the parts. [ Applies only to reprogrammable. Can socket a single EPROM, tougher and more expensive to socket every OTP part on the card. ] I am doubtfull of any claims about not needing as much glue logic. -Bret #include <std_disclaimer.h> #! gunbatch ‹Article: 358
In article <1994Oct27.075211.13088@adobe.com> pngai@mv.us.adobe.com (Phil Ngai) writes: >I have a high frequency clock (25 MHz) that I want to divide down to >something under 1 KHz. The exact divisor is not important. I want to >do this in a large PAL (AMD Mach device) at minimal cost in terms of >product terms, routing use, and logic block fan-in use so I thought a >LFSR might be applicable. I've got a design now with 15 stages and the >input is the XOR of the LSB and the MSB, it seems to do reasonably well >but I'd like to know a little more about how to design a circuit as >needed. > >For example, if you had a particular divisor to implement, is there >an algorithm to generate the circuit? > >-- > Congratulations to the people who saved Mono Lake! I have had this problem often, so I wrote a program to do it for me. The input is the division ratio that I need. It calculates the minimal length LFSR that will support the division ratio I want, plus also figures out the optimal tap positions for the XNOR gate. (Optimal means in this case that I prefer the taps to be at the shift in end of the LFSR, plus one from the shift out end. The LFSRs always start at all zeroes, and my program tells me the value that will be in the LFSR after N-1 clocks. I use this to synchronously reset the LFSR on the next clock. If you give me the exact division ratio, I will run it and give you the answers. I intend to make this program public, when I have written some docs for it so others can use it All The Best, Philip Freidin.Article: 359
Can somebody please help me. For my 4th year project i'm implementing stochastic processes on the altera flex FPGA. Could anyone give me some book names that explain how FPGA's work Thanks, Simon Mackay e-mail : smackay@cee.hw.ac.ukArticle: 360
KevSteele (kevsteele@aol.com) wrote: : I'm familiar with the Xilinx 4kH series that can drive busses : directly...are there any others out there that are capable of IOL 24mA? Enter shameless plug mode: While not a high density (CPLD/FPGA) device, Philips offers 7.5ns 22V10's that offer high drive (16mA source / 48mA sink) in both 5 Volt and 3.3 Volt versions (5V = ABT22V10; 3.3V = LVT22V10). They are also spec'ed for lowest noise, and the ABT is the only PLD available that is Metastable Immune. -- Mark Aaldering mma@RT66.comArticle: 361
In article <lfadden.1.00116606@harris.com> lfadden@harris.com (Lee Fadden) writes:
>Hi,
> Can anyone point me to a forum or book on work being done in associative
>memory architecture? I'd appreciate any info on alternative
>computer architecuture. Thanks.
>
>LF
>
Assuming you're looking for fpga-related information, we have a novel
fpga architecture that is based on associative memory rather than
lookup tables. It allows the fpga to support a wider class of circuit
styles than conventional fpgas do. In particular it supports PLA or
AND/OR style circuits. Though not a primary design requirement, the
design naturally supports associative CAM circuits as well.
You can find details via our www home page:
http://www.comlab.ox.ac.uk/oucl/hwcomp.html
Ian Page.
Article: 362Article: 363
I'm new to the group. Where can I find background info on FPGA design? I don't see a FAQ. Have I missed something? LFArticle: 364
In article <lfadden.4.00133F1E@harris.com>, lfadden@harris.com (Lee Fadden) says: > >I'm new to the group. Where can I find background info on FPGA design? >I don't see a FAQ. Have I missed something? > >LF Try have a look on http://www.super.org:8000/FPGA/caf.html. This is a WWW server for FPGA. Hope this helpful to you K.M. ChungArticle: 365
In article <38qs07$84m@mack.rt66.com> mma@mack.rt66.com writes: > >While not a high density (CPLD/FPGA) device, Philips offers 7.5ns 22V10's >that offer high drive (16mA source / 48mA sink) in both 5 Volt and 3.3 Volt >versions (5V = ABT22V10; 3.3V = LVT22V10). They are also spec'ed for lowest >noise, and the ABT is the only PLD available that is Metastable Immune. Metastable Immune?? Please tell us what you mean by that. I thought that was an unsolvable problem. -- dennis@netcom.com (Dennis Yelle) "It's a small mind that can think of only one way to spell a word." -- M. TwainArticle: 366
dennis@netcom.com (Dennis Yelle) writes: >Metastable Immune?? >Please tell us what you mean by that. >I thought that was an unsolvable problem. Phillips/Signetics has long had a couple of devices that their data book claims in "metastable immune" the 74F5074 single-stage flip-flop and the 74F50728 two-stage synchronizer are the ones I know about. When I first heard about them in 1990, I ran a few experiments in our lab with them by using a couple of pulse generators (one connected to the D input and the other connected to the CLOCK input) and a digital oscillscope set to infinite persistance on the display. I didn't record any imperical data or anything like that, but I was impressed enough with what I saw that I have been designing them in whenever possible. They are pin-for- pin compatible with the ubiquitous 74F74 device. -- Gregg Mack -------- __o gmack@paceline.sps.mot.com ------- _`\<,_ Motorola RISC - Austin, TX ------- (*)/ (*)Article: 367
Hi - In <dennisCyGLqy.E0z@netcom.com> dennis@netcom.com (Dennis Yelle) writes: > >In article <38qs07$84m@mack.rt66.com> mma@mack.rt66.com writes: >> >>While not a high density (CPLD/FPGA) device, Philips offers 7.5ns 22V10's >>that offer high drive (16mA source / 48mA sink) in both 5 Volt and 3.3 Volt >>versions (5V = ABT22V10; 3.3V = LVT22V10). They are also spec'ed for lowest >>noise, and the ABT is the only PLD available that is Metastable Immune. > >Metastable Immune?? > >Please tell us what you mean by that. >I thought that was an unsolvable problem. It is. When sampling an asynchronous signal in a synchronous system, you can make the probability of metastable upset arbitrarily small, but you can't eliminate it entirely. Whenever I read the phrase "Metastable Immune" in a data sheet, I automatically replace it with "Written by Marketing." Regards, Bob PerlmanArticle: 368
Seong-Woon Kim (ksw@kiwi.etri.re.kr) wrote: : Hmm.. : Is there a somebody who can tell me about the current : situation the ALTERA fpga series? : I have very interesting about the toggle rate. : Thanks : Siwon The EPF81188A provides 24000 available gates, (12000 useable) 1188 flip flops 1008 logic elements and 184 I/O pins. The current speed grades are -5, -4 and -3 with a -2 available sometime next year. a 16 bit loadable counter can be clocked at 71Mhz,83Mhz and 95 Mhz on the -5, -4 and -3 respectively. A 16-bit prescaled counter can be clocked at 151Mhz, 185Mhz and 232Mhz respectively. Paul Brown.Article: 369
In article ghk@mark.ucdavis.edu, gbchoy@salsa.engr.ucdavis.edu (Garett B Choy) writes: >I'm not sure, but it seems to me that there are two main advantages to >using an fpga: 1) design is quicker because it may be programmed through >software 2) production is quicker/cheaper because there is no "glue-logic" >all over the place and you don't have to wait for in-factory designed ASICs. > >For reason 1, I see why reprogrammability is a good thing. >For reason 2, why is reprogrammability important? > >If I'm missing something, please let me know. Depending on how you classify debugging/system integration (design or production), reprogrammability is a BIG time and money saving feature. I've had situations, during system integration, where changing my circuitry was easier/faster/cheaper than changing the other side of the system. With Xilinx, I used a PC to download the new designs for testing, then when we found one we liked, I burned the serial PROM (OTP). As an example of reason 2, I have seen a design for a flexible interface that had the same Xilinx hardware reprogrammed 20 times for 20 different boxes he was talking to. The interface was in a ruggedized portable PC, and he had the different downloads stored on the hard disk. Downloading a new IFC configuration took less than a second. The ruggedized PC (with the custom IFC card in it), plus a bunch of adapter cables was all he needed to talk to any of the target boxes. Very slick. Very cheap. Andy Jones Engineering Specialist Lockheed Fort Worth Company andy@cjet1.lfwc.lockheed.comArticle: 370
In article <391qh8$cjr@ixnews1.ix.netcom.com> BobPerl@ix.netcom.com (Robert Perlman) writes:
>>>...the ABT is the only PLD available that is Metastable Immune.
>>
>>Metastable Immune??
>>Please tell us what you mean by that.
>>I thought that was an unsolvable problem.
>
>It is...
>Whenever I read the phrase "Metastable Immune" in a data sheet, I automatically
>replace it with "Written by Marketing."
Actually, it sometimes seems to be used as a buzzphrase for "avoids the
worst forms of metastable behavior" ("worst" in the opinion of some specific
engineer, that is). On the Signetics flipflops, for example, it seems to
mean that they may be arbitrarily slow about making a decision but their
outputs won't flail back and forth or hang in the middle meanwhile.
It can also mean just "metastable resistant", and that's certainly within
the range of what's physically plausible. You can't eliminate metastability,
but you can certainly reduce the probability.
--
Justice for groups that doesn't include justice | Henry Spencer
for individuals is a mockery. | henry@zoo.toronto.edu
Article: 371In article <1994Oct27.075211.13088@adobe.com>, Phil Ngai <pngai@mv.us.adobe.com> wrote: >I have a high frequency clock (25 MHz) that I want to divide down to >something under 1 KHz. The exact divisor is not important. I want to >do this in a large PAL (AMD Mach device) at minimal cost in terms of >product terms, routing use, and logic block fan-in use so I thought a >LFSR might be applicable. I've got a design now with 15 stages and the >input is the XOR of the LSB and the MSB, it seems to do reasonably well >but I'd like to know a little more about how to design a circuit as >needed. > >For example, if you had a particular divisor to implement, is there >an algorithm to generate the circuit? I did something like this many years ago (circa 1978) with ECL 10K MSI devices. What I needed than was a divide-by-37 circuit that ran at 75 Mhz. The LFSR is ideal for this application because it uses only one level of logic in the feedback circuit. I won't be able to draw the circuit off the top of my head, but I can explain the method. First I selected a primitive degree six polynomial (probably from Golomb's book "Shift Register Sequences") and designed the basic circuit from D flip-flops and XOR gates. Next, I put all the Q outputs through a six-input OR gate to make a detector for the all 0's state and I wire-OR'd all of the the otherwise unused Q-bar outputs of the flip-flops together to make a detector for the all 1's state. These two signals were ANDed with CLKIN to make a gated clock which would generate pulses when the device was in any state other than all 0s and all 1s; I tied this signal to the clock inputs of the D flip-flops. The complement of CLKIN was NORed with the state detectors to make a signal which would pulse low only when the device was in either of the detected states; this signal was wired to either the asynchronous PRESET# or the asynchronous CLEAR# input of each D flip flop to create the initial state which would require 37 clocks to reach the all 1's state, and was also the divide-by-37 output. I used it to clock a T-type flip flop which drove a DPLL's phase detector. For what it's worth the purpose was to derive a direct-sequence spread-spectrum modulation clock of 32.432432 Mhz from a 300 Mhz (4 x 75 Mhz) IF reference; the modulation clock divided by 16 was the other DPLL input, the VCO output itself being the modulation clock. The same technique can be used for synchronously dividing by some VERY large moduli. You will need to find a suitable polynomial (the degree of which depends on the desired divisor), and you will need to write a program which simulates a shift register which divides by the RECIPROCAL polynomial (i.e. wire the coefficients in reverse order). Start the program with the shift register in the all 1's state and stop it after a number of cycles equal to the desired modulus. The resulting state is what you must jam-set the actual generator to when it reaches the all 1's state. The purpose of detecting the all 0's state is so that the generator does not get stuck in that state in case it happens to start there. This method works well with ECL because that technology admits wire-or logic with very little propagation delay. Logic block fan-in will be a problem in technologies which don't allow this. Your terminal state detector may require multiple combinatorial stages in that case, and this will limit the speed. Maybe other readers have some ideas which will can get around this problem for AMD MACH devices and the like. Regards, Mike -- -- C. M. Heard VVNET, Inc. voice: (408) 247-9375 4040 Moorpark Ave. Suite 206 fax: (408) 244-3651 San Jose, CA 95117 e-mail: heard@btr.comArticle: 372
Kevin: Check out Intel's (now Altera's) FLEX logic devices. Are you Kevin of MEI? Jim MedeirosArticle: 373
Charles Michael Heard heard@btr.com (heard@btr.btr.com) wrote: (Lots of good stuff on an ECL implementation of a /37 deleted...) : a problem in technologies which don't allow this. Your terminal state : detector may require multiple combinatorial stages in that case, and : this will limit the speed. Maybe other readers have some ideas which : will can get around this problem for AMD MACH devices and the like. I'd like to outline something which has worked for me for small divisiors at least (and could probably be handled programatically if you want). If you use logic which is easy to set started in the all-"zeros" state, then you can use XNOR feedback to implement a "maximal length" sequence, or for that matter, any other sequence. Sometimes maximal length are useful, but there is no reason they _have_ to be used. Let's say you want to build a divide-by-n circuit. Then determine k, the number of stages required, such that 2^k>n>=2^(k-1). In other words, to divide by 8 through 15, you need 4 stages, 4 flip-flops. This is a minimum number, and there may actually be an advantage to using more, as will become apparent. Now, list all the states of each possible feedback connection; it only makes sense to try feedback which includes the final stage, since if you don't, that stage could be omitted. But forget other rules for maximal length sequences (unless you know you need maximal length, 2^k-1, anyway) like that you need an even number of feedback taps. Now search for the feedback connection which results in _minimal_ decoding to detect the final state. That is, if the final state has a "01" as the final two bits, and no other state before it has that particular pattern, then that is all you have to decode to know the final state. Now, look at the _next_ state, and see where it differs from the intial (all zeros) state. You only need to modify the inputs to the bits which would end up as 1's. So, for example, if the nth state were 010001 and the next state were going to be 001000, then you only need to detect that final state and gate the input to the third stage to a zero; all the other stages were going to be in the right state anyway. Doing this manually for anything over perhaps 5 bits is quite tedious, but it could probaby be handled programatically, to at least search for likely candidates. This sort of impelmentation is particularly easy to do in a field-programmable gate array or PAL; it doesn't make quite so much sense with a packaged shift register, though even there, if there is a reset pin, it can make sense. Another extension of this idea is to search for sequences which result in minimum decoding of intermediate states, if what you really wanted was a way to sequence through several steps in a loop n states long. Sometimes only _some_ of the states are important, and it's helpful if those states are easy to decode. You very well may not need to decode all the bits to know you are in a particular state; this can be especially true if you use more bits in the shift register than you really needed. Hope some of you find this useful or at least food for thought.Article: 374
I am now writing a assembly program to configure a FPGA through AT-bus. But I don't know what the actual configuration bitstreams are. The .bit file seems to have some unnecessities just like "3020PC6894/10/3120:49:43demo3020.lca:". Should I delete it or keep it? Please help me. Thanks.
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