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In article <395u4p$84t@news.csie.nctu.edu.tw> yau@theda18 (Ching-Yau Jong) writes: >I am now writing a assembly program to configure a FPGA >through AT-bus. But I don't know what the actual configuration >bitstreams are. The .bit file seems to have some unnecessities >just like "3020PC6894/10/3120:49:43demo3020.lca:". >Should I delete it or keep it? >Please help me. Thanks. > The .bit files are not documented, so knowing where the file header ends and the bitstream header starts is somewhat of a problem. Re-run the makebits program with the -b flag set. this generates a .rbt file which you can edit, and which is reasonably easy to be transformeded into a format that your download program can use. Another option is to pass the .bit file through makeprom, which will conver it to a .EXO or .TEK or other format, which may be easier to use. There is a neat program on the Xilinx BBS called makesrc which uses a descriptor file to convert bitstream to source code for any language. i.e. it can create 'C' source code (an array initialization) or ASM86 source code (loads of .db instructions). then process the file with the rest of your program. All the best, Philip FreidinArticle: 376
Paul Brown (brown@uk.co.gec-mrc) wrote:
: The EPF81188A provides 24000 available gates, (12000 useable) 1188 flip flops
: 1008 logic elements and 184 I/O pins.
: The current speed grades are -5, -4 and -3 with a -2 available sometime next
: year.
: a 16 bit loadable counter can be clocked at 71Mhz,83Mhz and 95 Mhz on the -5,
: -4 and -3 respectively. A 16-bit prescaled counter can be clocked at
: 151Mhz, 185Mhz and 232Mhz respectively.
Very useful summary information, thanks. If anybody puts together
a FAQ, make sure stuff like this goes in it.
However, you left off one key tidbit of information: are these
$10 parts, $100 parts, or $1000 parts? It makes a difference
to some people. I realize exchange rates may vary, and all prices
are subject to change without notice, ...
- Larry Doolittle doolittle@cebaf.gov
Article: 377Ching-Yau Jong (yau@theda18) wrote: : I am now writing a assembly program to configure a FPGA : through AT-bus. But I don't know what the actual configuration : bitstreams are. The .bit file seems to have some unnecessities : just like "3020PC6894/10/3120:49:43demo3020.lca:". : Should I delete it or keep it? : Please help me. Thanks. Why don't you generate a prom file using makeprom? That'll remove all the unnecessary bits for you. Matthew matthew@rd.bbc.co.uk My opinions, not Auntie's.Article: 378
In article <CyM0p5.FIw@murdoch.acc.Virginia.EDU>, doolitt@recycle.cebaf.gov (Larry Doolittle) writes: > However, you left off one key tidbit of information: are these > $10 parts, $100 parts, or $1000 parts? It makes a difference > to some people. I realize exchange rates may vary, and all prices > are subject to change without notice, ... List pricing for the epf81188 in 100pc quantities ranges from $149.00 to $350.00 depending on speed and package. Info from Altera OEM price lst, September/October 1994. Gerry BelangerArticle: 379
> In article <1994Oct27.075211.13088@adobe.com>, > Phil Ngai <pngai@mv.us.adobe.com> wrote: > >I have a high frequency clock (25 MHz) that I want to divide down to > >something under 1 KHz. The exact divisor is not important. I want to > >do this in a large PAL (AMD Mach device) at minimal cost in terms of > >product terms, routing use, and logic block fan-in use so I thought a > >LFSR might be applicable. I've got a design now with 15 stages and the > >input is the XOR of the LSB and the MSB, it seems to do reasonably well > >but I'd like to know a little more about how to design a circuit as > >needed. > > > >For example, if you had a particular divisor to implement, is there > >an algorithm to generate the circuit? > Two tips: 1 - Page 9-24 of the 1994 Xilinx Data Book has a short XCELL article on LFSRs. 2 - The October issue of ASIC & EDA magazine has a great article by an engineer at HighGate Designs on high speed FPGA design. In this article there is a very good discussion of the application of LFSRs along with a reference to a BBS for a free LFSR sequence generator program. I don't have the BBS number since I threw away the magazine, but the ZIP file lists their voice phone at (408)255-7160. Hope this helps... -- Lou Santisteban Computer Sciences Corporation Email - lsantist@lsantist.dfrf.nasa.gov P.O. Box 387 Phone - (805)258-3786 Edwards, CA 93523-0387 Fax - (805)258-3567 "Even if you win the rat race, you're still a rat" - Lilly TomlinArticle: 380
In article <CyDpIM.HJ7@cee.hw.ac.uk>,
Simon Hermann MacKay <smackay@cee.hw.ac.uk> wrote:
>
>Could anyone give me some book names that explain how FPGA's work
For somewhat obvious reasons, I recommend:
Trimberger, ed. "Field Programmable Gate Array Technology", Kluwer, 1994.
With sections written by authors from Xilinx, Actel and Altera, it covers
process, circuitry, architecture, software and applications for FPGAs
built from SRAM, Antifuse and E[E]PROM.
To get one, contact kluwer@world.std.com.
Other good books in this area:
Brown, et al, "Field Programmable Gate Arrays", Kluwer.
Chen and Mourad, "Digital Design Using Field Programmable Gate Arrays",
Prentice Hall
Jenkins, "Designing with FPGAs and CPLDs", Prentice Hall
Ukeiley, "FPGAs, The 3000 Series", Prentice Hall
There are a couple others that are conference proceedings, but they
won't work as an introductory text.
I know of a couple more in progress, but that won't help you.
I'm sure I'm forgetting someone, but I don't see it on my bookshelf.
I know other authors are lurking out there. If I didn't mention your
book, chip in.
Article: 381
In article <Pine.A32.3.90.941031214032.21484D-100000@pinot.callamer.com>,
SLO JAM <jmedeiro@pinot.callamer.com> writes:
>Kevin:
>Check out Intel's (now Altera's) FLEX logic devices.
>Are you Kevin of MEI?
>Jim Medeiros
Thanks, Jim.. The 8160 device in particular looks very good. Designed for
PCI.
(Yep..that's me)
Article: 382Mark Aaldering mma@RT66.com wrote: >Enter shameless plug mode: >While not a high density (CPLD/FPGA) device, Philips offers 7.5ns 22V10's >that offer high drive (16mA source / 48mA sink) in both 5 Volt and 3.3 Volt >versions (5V = ABT22V10; 3.3V = LVT22V10). They are also spec'ed for lowest >noise, and the ABT is the only PLD available that is Metastable Immune. Wow, metastable immune! Whoever holds the patent on this device is one lucky dude. It ranks right up there with perpetual motion machines. Try reading: L. Kleeman, A. Cantoni "Metastable Behaviour in Digital Systems", IEEE Design & Test of Computers, December 1987. for a discussion on the *unavoidability* of metastable behaviour in digital systems. Andrew Phillips (andrew@atri.curtin.edu.au) Cooperative Research Centre for Broadband Telecommunications & Networking Bentley, Perth Western AustraliaArticle: 383
Hi -
In <CyJtp2.DDI@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes:
>
>In article <391qh8$cjr@ixnews1.ix.netcom.com> BobPerl@ix.netcom.com (Robert
Perlman) writes:
>>>>...the ABT is the only PLD available that is Metastable Immune.
>>>
>>>Metastable Immune??
>>>Please tell us what you mean by that.
>>>I thought that was an unsolvable problem.
>>
>>It is...
>>Whenever I read the phrase "Metastable Immune" in a data sheet, I automatically
>>replace it with "Written by Marketing."
>
>Actually, it sometimes seems to be used as a buzzphrase for "avoids the
>worst forms of metastable behavior" ("worst" in the opinion of some specific
>engineer, that is). On the Signetics flipflops, for example, it seems to
>mean that they may be arbitrarily slow about making a decision but their
>outputs won't flail back and forth or hang in the middle meanwhile.
>
>It can also mean just "metastable resistant", and that's certainly within
>the range of what's physically plausible. You can't eliminate metastability,
>but you can certainly reduce the probability.
Quite right - vendors sometimes use the word "immune" to refer to parts whose
metastable characteristics are enhanced in some way. To me, though, using the
word "immune" to refer to such parts is similar to using the word "free" to
describe parts that are inexpensive.
Then again, I tend to be something of a crank about these things.
Regards,
Bob Perlman
Article: 384as others mentioned, you can use makebits with the -b option to get the .rbt file. then skip everthing until the first line starting with a "1". transmit every "1" and "0" bit starting with this line to the end of file don~t forget to strip the end of line characters in each line for the first time controll every step of the programming sequence: lower prog, lower reset, wait for init low, rise reset, wait for init high, ... etc andreasArticle: 385
--- We're interested in partitioning logic among more than one Xilinx 4000 series FPGA. What's the best way to get a file that has the logic partitioned into function generators? In addition, we'd also like to retain some notion of hierarchy so that we don't put half of a RPM for an adder in one chip and the other half in a different chip. Any ideas? Thanks, Mike ******************************************************* Mike Wazlowski EMAIL: mew@lems.brown.edu Box D VOICE: (401)-863-3005 (lab) LEMS, Div. of Eng. FAX: (401)-863-1157 Brown University Providence RI 02912 *******************************************************Article: 386
Matthew Marks (matthew@rd.eng.bbc.co.uk) wrote: : Ching-Yau Jong (yau@theda18) wrote: : : I am now writing a assembly program to configure a FPGA : : through AT-bus. But I don't know what the actual configuration : : bitstreams are. The .bit file seems to have some unnecessities : : just like "3020PC6894/10/3120:49:43demo3020.lca:". : : Should I delete it or keep it? : : Please help me. Thanks. Two suggestions. One, like the other two guys recommended, use the .mcs (Intel hex) output from makeprom. Two, keep a finger on the chip when you run your download program. If you download it wrong, or it gets a really weird file, you can smoke it within 3-5 seconds of the download 'cos you short the VCC bus to GND through improperly programmed gates. If it gets hotter than warm, cut the power INSTANTLY. Don't wait, or it's a goner.Article: 387
Larry Doolittle (doolitt@recycle.cebaf.gov) wrote: : Paul Brown (brown@uk.co.gec-mrc) wrote: : : The EPF81188A provides 24000 available gates, (12000 useable) 1188 flip flops : : 1008 logic elements and 184 I/O pins. : Very useful summary information, thanks. If anybody puts together : a FAQ, make sure stuff like this goes in it. : However, you left off one key tidbit of information: are these : $10 parts, $100 parts, or $1000 parts? It makes a difference : to some people. I realize exchange rates may vary, and all prices : are subject to change without notice, ... : - Larry Doolittle doolittle@cebaf.gov I was recently quoted 130 pounds stirling for this device, its probably cheaper in the states and I'm not sure on the quantity I believe it was for 10 of. The smaller Altera FPGA e.g. EPF8282A, 2500 useable gates, 282 flip flops and 78 i/o pins were quoted in the 10-20 pounds region. A suitable datasheet containing information on the flex family can be got from Altera, but you will have to enquire about pricing yourself as we may get different discounts as a large user of Altera parts. Paul BrownArticle: 388
I prefer the rbt (raw bits) file format. It's uniary (0s and 1s) so you don't have to think about which end of the byte goes first.Article: 389
In article <39b348$lrc@cat.cis.Brown.EDU>, mew@lems.brown.edu (Mike E. Wazlowski) writes: |> |> |> --- |> |> |> We're interested in partitioning logic among more than one Xilinx 4000 series |> FPGA. What's the best way to get a file that has the logic partitioned into |> function generators? In addition, we'd also like to retain some notion of |> hierarchy so that we don't put half of a RPM for an adder in one chip and the |> other half in a different chip. Any ideas? |> |> Thanks, |> Mike |> |> |> I am afraid that you are on your own on this one. As far as I know there is no automatic partitioner available for Xilinx chips although I would like to be proven wrong. The only chips that I know of that have a partitioner available for them are the Altera parts. I plan to test this partitioner out soon but have not done so yet. - Russell Petersen petersr@fpga.ee.byu.eduArticle: 390
Does anyone know if there is an ftp mirror for Altera's bulletin board? - Russell Petersen petersr@fpga.ee.byu.eduArticle: 391
In article <39dt27$b4c@bones.et.byu.edu>, <peterser@utah.et.byu.edu> writes: > |> > |> We're interested in partitioning logic among more than one Xilinx 4000 series > |> FPGA. What's the best way to get a file that has the logic partitioned into > |> function generators? In addition, we'd also like to retain some notion of > |> hierarchy so that we don't put half of a RPM for an adder in one chip and the > |> other half in a different chip. Any ideas? > |> > |> Thanks, > |> Mike > |> > |> > |> > > I am afraid that you are on your own on this one. As far as > I know there is no automatic partitioner available for Xilinx chips > although I would like to be proven wrong. The only chips that I know > of that have a partitioner available for them are the Altera parts. > I plan to test this partitioner out soon but have not done so yet. > > > - Russell Petersen > petersr@fpga.ee.byu.edu The Data I/O Abel 5.1 product has partitioners for several FPGAs and CPLDs. I use Viewlogic ProPLD (based on ABEL 5.1) and it also supports partioners. I believe that you must purchase the partioners separately. I have never used any of the partitioners, so I don't know how automatic or how good they are. YMMV -- Lou Santisteban Computer Sciences Corporation Email - lsantist@lsantist.dfrf.nasa.gov P.O. Box 387 Phone - (805)258-3786 Edwards, CA 93523-0387 Fax - (805)258-3567 "Even if you win the rat race, you're still a rat" - Lilly TomlinArticle: 392
>We're interested in partitioning logic among more than one Xilinx 4000 series >FPGA. What's the best way to get a file that has the logic partitioned into >function generators? In addition, we'd also like to retain some notion of >hierarchy so that we don't put half of a RPM for an adder in one chip and the >other half in a different chip. Any ideas? > > Thanks, > Mike NeoCAD has a partitioner called Prism. In addition to using the design hierarchy, it also uses timing constraints to determine the best partition. You can just give it a clock frequency and it will determine which paths can and cannot be split across devices. There are two reasons that an RPM would not get split across devices: the hierarchical name and the fact that it is a macro and therefore cannot be split. ------------------------------ Steve Lass NeoCAD, Inc. 2585 Central Ave. Boulder, CO 80301 (303)442-9121 steve@neocad.comArticle: 393
In article <393aqa$2j7@cliffy.lfwc.lockheed.com>, Andy Jones <andy@cjet1.lfwc.lockheed.com> wrote, in response to comments by Garett B Choy <gbchoy@salsa.engr.ucdavis.edu>: >>I'm not sure, but it seems to me that there are two main advantages to >>using an fpga: 1) design is quicker because it may be programmed through >>software 2) production is quicker/cheaper because there is no "glue-logic" >>all over the place and you don't have to wait for in-factory designed ASICs. >> >>For reason 1, I see why reprogrammability is a good thing. >>For reason 2, why is reprogrammability important? [ snip ] >As an example of reason 2, I have seen a design for a flexible >interface that had the same Xilinx hardware reprogrammed 20 times for >20 different boxes he was talking to. The interface was in a >ruggedized portable PC, and he had the different downloads stored on >the hard disk. Downloading a new IFC configuration took less than a >second. The ruggedized PC (with the custom IFC card in it), plus a >bunch of adapter cables was all he needed to talk to any of the target >boxes. Very slick. Very cheap. Let me mention another increasingly common application: test equipment. Two products I've worked on -- the Tektronix/LP COM TC-2000 PCM analyzer and the Telecommunication Techniques Corp. FB500 WAN protocol analyzer -- made extensive use of Xilinx parts which were loaded with different configurations depending on the test function selected by the user. The PCM analyzer used XC2064 devices both as "glue" logic and as pseudo-random pattern generators to allow the R8070 T1 framers to be used in parallel mode to operate in a drop-and-insert configuration or in serial mode to run bit error rate tests. The WAN analyzer used XC4005 parts to implement serial controllers for both HDLC and SMDS protocols, using a different bit file for each. These controllers had special capabilities useful in a test instrument which are not available in off-the-shelf LSI devices. Look for more in this vein in VVNET's products when and if they appear :-) Mike -- C. M. Heard VVNET, Inc. voice: (408) 247-9375 4040 Moorpark Ave. Suite 206 fax: (408) 244-3651 San Jose, CA 95117 e-mail: heard@btr.comArticle: 394
mew@lems.brown.edu (Mike E. Wazlowski) writes :- >We're interested in partitioning logic among more than one Xilinx 4000 series >FPGA. What's the best way to get a file that has the logic partitioned into >function generators? In addition, we'd also like to retain some notion of >hierarchy so that we don't put half of a RPM for an adder in one chip and the >other half in a different chip. Any ideas? MINC PLDesigner can partition a design across up to 20 (supported) PLD's/CPLD's/FPGA's. The partitioning can be either automatic, guided or manual. PLDesigner takes you as far as a xnf file(s). A word of warning though, the XILINX 4000 support isn't brilliant. For example the wide edge decoders are not directly supported and the use of long lines can be a bit messy. T.H.Article: 395
In article <39akqg$pi4@darum.uni-mannheim.de> Andreas Kugel, kugel@mp-sun6.informatik.uni-mannheim.de writes: >as others mentioned, you can use makebits with the -b option to >get the .rbt file. >then skip everthing until the first line starting with a "1". >transmit every "1" and "0" bit starting with this line to the end of file >don~t forget to strip the end of line characters in each line Someone said there is a Xilinx utility but we wrote our own for converting a program into a C array. This is bound into the program (we create const arrays, so they are bound into the program space, and would be mapped into ROM if required). This is not without its problems though. We currently hardwire the size of the arrray into the program, but I would prefer to zero terminate or similar. Does anyone know a byte value that can never turn up the idea is to make the driver code independent of the array in question. The other problem is that these arrrays can grow in size. I wondered if anyone had tried compression something like the gzip algorithm. > >for the first time controll every step of the programming sequence: > >lower prog, lower reset, wait for init low, rise reset, wait for init high, ... etc Of course for 4000s the programming sequence is different and don't forget you often have to send an extra byte than seems really necessary. _____________________________________________________________ Dr John Forrest Tel: +44-161-200-3315 Dept of Computation Fax: +44-161-200-3321 UMIST E-mail: jf@ap.co.umist.ac.uk MANCHESTER M60 1QD UKArticle: 396
Philip Freidin (fliptron@netcom.com) wrote: <some helpful info about bitstreams deleted> : There is a neat program on the Xilinx BBS called makesrc which uses a : descriptor file to convert bitstream to source code for any language. : i.e. it can create 'C' source code (an array initialization) or ASM86 : source code (loads of .db instructions). then process the file with : the rest of your program. : All the best, : Philip Freidin What's this? It will make source-code out of a bitstream? How much info do I have to give it along with the bitstream? -bryan chaseArticle: 397
NeoCAD's PRISM (very nice, timing-driven tool), IST's ASYL+ (retains existing hierarchy, automatic migration), Zycad (used to be Inca), ACEO, Aptix... There are now quite a few commercial partitioners for Xilinx on the market. David Pashley Direct InsightArticle: 398
I have a random number generator and I'd like to test the "randomness" does any know of a program to test the randomness of a set of numbers? Steve Casselman Virtual ComputerArticle: 399
In article <1994Nov4.122644@fpga.ee.byu.edu> petersr@fpga.ee.byu.edu (Russell Petersen) writes: > > Does anyone know if there is an ftp >mirror for Altera's bulletin board? > > >- Russell Petersen > petersr@fpga.ee.byu.edu Currently, we do not have an ftp site but this is likely to be resolved in Q1 95. In the meantime, here are some contact numbers for Altera information: Application Engineering : tel (800) 800-epld Application Engineering : tel (408) 954-0348 Application E-Mail : sos@altera.com Marketing/Product : tel (408) 894-7104 Marketing/Literature : tel (408) 894-7144 Customer Service : tel (800) sos-epld Sales, California USA : tel (408) 894-7900 BBS (<=14k4,8,1,n) : tel (408) 954-0104 Stephen Smith (home: sjsmith@netcom.com) Product Planning Manager (work: sjsmith@altera.com) Altera Corporation, 3 W. Plumeria, San Jose, CA 95134, USA
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