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Article: 226
Has anyone sampled the ifx8160 from intel? What do think of it? -- Benjamin Gene Cheung Computer Engineer Georgia Institute of Technology Internet: gt0361b@prism.gatech.eduArticle: 227
fliptron@netcom.com (Philip Freidin) writes:
... much good info deleted, Phil obviously knows X4K well ...
:Here are some excerpts of Bob's mail with my comments.
:
:>2. Don't use the -4 (fastest) speed grade. Design to the -5 speed
:> grade (or slower), and then specify -4 speed grade (or whatever
:> the next fastest speed grade is) parts for production.
:
:This seems a little over precautious / pessamistic. The Xilinx
:speed files seem to be weighted to the pessamistic side already
:so designs that meet timing specs acording to XDELAY have always
:worked for me.
I stand by what I said in my original posting. I've discussed the issues
involved with Phil, and perhaps his perspective may have shifted a bit,
but I don't want to put words in his mouth.
I get paid to design products that make money for our company, on schedule
and meeting design specs (including reliability and performance), and
with best possible manufacturing cost. At this point in time, I would
*not* design for anything more aggressive than -5 performance, and I *would*
make sure that the FPGAs used in production were one speed grade faster
than my design criteria.
There is nothing more I can add to this subject. Do as you see fit.
:> I don't think the BUFGS/BUFGP delay differences are well
:> characterised; they certainly aren't described well in the data books.
:
:The BUFGPs are about 1 nS faster than the BUFGSs.
:
:> You will probably be happier if you stick to the BUFGPs for all
:> clock distribution where clock skew is a concern.
:
:The clock skew for both is < 1 nS. I have measured them both and seen
:skews in the 300 to 500 pS range. Worst case skew is between an IO FF
:in the middle on the top or bottom edge , and a corner IO FF
:
:> There are some at
:> Xilinx who would debate this contention. I have personal reasons
:> for this conviction which relate to using the on-chip RAM.
:
:I have seen differences in the BUFGP to BUFGS skew too, but it is
:of the order of a few 100 pS, and less than 1 nS
I believe that there are differences in drive between the two types of
clock buffers, and resulting differences in rise/fall time which may
affect absolute timing over temperature, etc. I can't prove this, however.
:>7. Be careful about using both clock edges with tight timing tolerances.
:> The clock buffers have TTL thresholds and asymmetric rise/fall times
:> internally. So 50% duty cycle clock waveforms externally don't
:> necessarily translate into 50% duty cycle square waves internally.
:> If you clock on both clock edges, you probably should provide at least
:> 4 nS of timing margin.
:
:The I/O input buffers have TTL thesholds (~ 1.5V), so a 5V square wave
:of 50% duty cycle will end up being seen as more clock high time and
:less clock low time, assuming equal rise and fall times. If the rise
:and fall times are fast ( < 3 nS), then the effect is about 1 nS.
:Slower edges will have more effect. Higher frequencies will make the
:effect a higher percentage of the cycle time. Internaly the FPGAs
:have their thresholds set to minimize clock stretching and shrinkage.
:4nS seems like a good safe number for clock margin, when doing things
:on both edges. Dont assume that CLK-BAR gets to the FFs later than CLK,
:as the clock might be distributed as CLK-BAR, not CLK.
I agree with Phil, if you are using a 5V square wave for external clock
signal. Timing variation is greater if your clock signal is a typical
TTL signal which peaks around 2.5 or 3.0 V (check the 10125 data sheet for
max VOH). The waveshape *around* (i.e. below, at, and above) the
"reference" voltage affects the transfer characteristic of the internal
buffer. This is real-world consideration that not all semi vendors
appreciate in their characterisation processes.
Perhaps the best advice is to make your TTL clocks as sharp and
"full-swing" as possible. External clock buffers will add skew,
however, but you get the idea.
:>8. Don't be lulled by a batch of Xilinx FPGAs with excellent timing
:> margins. All FPGA vendors, including Xilinx, are aggressively pursuing
:> smaller and smaller fab processes. As the distribution of their
:> parts with respect to timing performance changes, and as their order
:> demand for different speed grades shift, you may get parts which
:> greatly exceed minimum timing specs. The next month you may get parts
:> which aren't quite so fast. So don't get over-confident from the
:> excellent yield and/or margins on the first 50 boards.
:
:ABSOLUTELY. Thats what speed files and simulation are for: Make sure
:your design will work with the slowest silicon that meets the databook
:guarantees, at high temperature, and low VCC
The value of speed files, simulators, and simulation is limited by the
quality of the characterisation on which the speed files are based, the
competency of the simulator (or timing verifier/calculator), and the
applied skill of the user of the simulator. There are a lot of IFs in
this equation, especially considering that characterisation of *ANY* FPGA
technology is a very, very complex matter. I would suggest being very
conservative, and weigh the consequences of mis-guessing on the over-
aggressive side.
:I've designed with 4003, 4003A, 4005, 4008, 4010, and lots of XC3K
Phil's experience shows.
May the electrical force be with you.
Bob Elkind
Article: 228In article <CwqKLu.LFL@hpqmoea.sqf.hp.com> marting@hpqtdla.sqf.hp.com writes: "Hi All, " After several years of 3000 Series Xilinx work, I'm considering a 4000 "device because of it's internal RAM. " "I was wondering if anyone with experience of the 4000 RAM could give some hints," "or just some general 4000 best practices?? " " "If people prefer to mail direct rather than post to the newsgroup, I'll post a "summary of what I receive. " " Thanks " " Martin Curran-Gray " There's quite a lot to say in response to this. You'll find 4000 series substantially different. There are more implementational details to take care of if you want to achieve decent clock speeds. However, one thing I would strongly recommend is that you take a look at the AT&T ORCA devices, especially the 2CXX series. This device series offers good price/performance and has 16x4 potential RAM per logic block. I'm not saying it's better than XC4000 - just that it's an alternative worth looking at. As always, it's your design which dictates which is the best device to use! David Pashley Direct Insight Ltd The independent CPLD/FPGA experts Tel: +44 280 700262 Fax: +44 280 700577Article: 229
Richard Vireday (rvireday@pldote.intel.com) wrote: > In article G26@netcom.com, bbutler@netcom.com (Bryan Butler) writes: > >I always thought it was counter-productive to charge for software that is only > >good for one vendors chips > Well Bryan, when it can cost any company over 1 million dollars > to get the software written for their hottest new device, you had better > do your part and buy a lot of chips to amoritise the cost. > If a typical PLD/FPGA sells only 10,000 units in the first year > of introduction (this is an industry average, ref. Dataquest), then you can tell > your suppliers to tack on an extra $20 onto each device you buy! > (Just assume there are four other people out there buying it too! :-) > --Richard Vireday > Formerly of Intels PLD & FPGA Business Unit So you used to work for Intel? One of the main reasons I started using Intel FPGAs is because I could get the software for free. If I had to buy the software, I probably wouldn't use them. (Yes I know they sold the FPGA line to Altera. I hope Altera keeps up the free policy). One thing you may be missing is that small sales of FPGAs now may result in larger sales later. I work for a consulting company. I will choose and FPGA based on the tools I have available. I probably won't purchase many FPGAs, but my customers will. The customer probably won't make much use of the design tools; he'll probably just program his parts with the JEDEC file I give him. So, as the design engineer, I'm primarily concerned with the cost of developing the prototype, which means that I can't spend a lot of money on design tools, particularly if I'm not sure whether the FPGA for which the tools are targeted will even work in the design. A customer might spring for a new design tool if it means a reduction in manufacturing costs. However, this tool now belongs to the customer, so I won't be able to use it for future designs for other customers. I would speculate (with no real evidence) that the major market for FPGAs is for low volume production, prototype, or proof-of-concept research projects. Large volume production would probably favor ASICs, with higher NRE but lower per device costs. Thus, there is a relatively large number of copies of the design software (desired) compared to the number of devices sold. By selling the software for a low (preferably $0) cost means more of these small-time users will try your chips, thus more chip sales. Obviously, the cost of developing the software has to be recovered, which means higher device costs. I would not balk too much at paying $10-20 more for a device with free software. If I need a handful of devices, this cost is negligible. If the alternative is to try to use a less appropriate device, I might spend more time trying to make the design fit that the small savings is worth. For the production customer, a solution could be to offer steeper price breaks for volume purchase. The price breaks could even be cummulative, so if I buy 100, then 100 more, I can get the quantity 200 price break on the second purchase. -- ------- Bryan Butler bbutler@netcom.comArticle: 230
mcgaugh@eng.iac.honeywell.com (Paul McGaugh) writes: >: Not true, auto partitioning is included with PDS+ Exactly what is pDS+? I am using pDS, and have never heard of pDS+ from lattice Tom Varghese tomv@s1.arc.umn.eduArticle: 231
In article <CwqpnH.4qG@ips.cs.tu-bs.de>, Andreas Koch <koch@eis.cs.tu-bs.de> wrote: >We would be interested in hearing about any experiences with >Exemplar's CORE/TopDown+ synthesis tool. It seems somewhat >less hardware-hungry than the Synopsys suite. While our primary >target would be Xilinx 4000 FPGAs, comments regarding other >technologies (eg. standard-cell ASICs like ES2) would be >useful. > >Thanks, > Andreas Koch >-- >Andreas Koch Email : koch@eis.cs.tu-bs.de >Institut f"ur theoretische Informatik Phone : x49-531-391-2384 >Abteilung Entwurf Integrierter Schaltungen Phax : x49-531-391-5840 >Gaussstr. 11, D-38106 Braunschweig, Germany Telex : 95 25 26 I did work on Exemplar and Synopsys for the XC4000 series. Hardware requirements for exemplar are a tad less, but the FPGA compiler was consistantly performing better than Exemplar(20%-35%) depending on the design. The Design compiler is comparable to Exemplar. Synopsys has a lot of options and tweaks to mess around with, to tune you design and optimize it. Exemplar is very limited. Just my experience. Danny.Article: 232
tomv@arc.umn.edu (Tom Varghese) writes :- >Exactly what is pDS+? I am using pDS, and have never heard of pDS+ from lattice Try pages 6-15 onwards of the 94 databook. Although I have never used PDS, I think the main difference is that PDS+ supports design entry from other tools ;- ABEL Viewlogic schematic ISDATA LOG/iC VHDL MINC (soon) and probably others I have failed to mention. Looking at the PDS data sheets it look a little crude wrt design entry (boolean only) when compared to the likes of ABEL/VHDL/MINC etc.. T.Hall Goldrush Project ICLArticle: 233
David Pashley (david@fpga.demon.co.uk) wrote: : I think you are being led astray by whoever told you that you need : to use a jedec file. The jedec format is only applicable to : programmable logic devices, whereas the XC1765 is an EEPROM device. : Therefore (and certainly for all the leading programmer types), you : can present the data to the programmer an any supported PROM type : format, but definitely *not* JEDEC. : Some older programmers have trouble with this particular device as : the susceptibility to clock pin noise is somewhat higher than the : norm. : David Pashley : Direct Insight Ltd : The independent CPLD/FPGA experts : Tel: +44 280 700262 : Fax: +44 280 700577 Unfortuanately there are programmers around - Stag 3000 in particular - that for some unknown reason treat the Xilinx serial proms as PLDs and therefore insist on Jedec format. Stag in the past have been prepared to give out conversion utilities to customers who complain or it is fairly straight forward to write your own. -- ****************************************************************************** * Phil Layton, Senior R & D Engineer * * BBC Research & Development Department * * Kingswood Warren, Tadworth, Surrey KT20 6NP, UK * * * * internet: phill@rd.bbc.co.uk * * phone: 0737 836575 (+44 737 836575) fax: 0737 832336 (+44 737 832336) * ******************************************************************************Article: 234
David Pashley (david@fpga.demon.co.uk) wrote: : ... : However, one thing I would strongly recommend is that you take a : look at the AT&T ORCA devices, especially the 2CXX series. This : device series offers good price/performance and has 16x4 potential : RAM per logic block. I echo this recommendation. In my work I target a number of designs to a variety of FPGA device architectures, including XC4000 and Orca. The att2c family is excellent, from a number of standpoints. First, it's very easy to place and route, and as a result, the amount of processor time spent in the place and route tools is significantly reduced. All of the Orca devices can handle very high utilization -- in fact, I have not yet seen an Orca design which we couldn't get to route, even at 100% PFU utilization. High TBUF usage will have the biggest impact on routability, but will still be easier to route than in an equivalent XC4000. You won't sacrifice speed for this ease of routing, either; in my experience designs will run at least as fast in an Orca part as they will in Xilinx chips. These are real customer designs, too, not contrived test cases or PREPCO designs. Also, if you're working with very large designs, you'll want to look at the att2c15. Every XC4013 we retargeted to the att2c15 fit and routed without effort; conversely, there's no way a packed att2c15 design would fit (let alone route) in a XC4013. In fact, in most cases an att2c12 will handle a design which routed in a XC4013. : I'm not saying it's better than XC4000 - just that it's an : alternative worth looking at. As always, it's your design which : dictates which is the best device to use! Agreed, every architecture has its strong points. But if you're evaluating different FPGAs for a project and aren't tied to any one vendor, definitely check out the Orca devices. ///////////////////////////////////////////////////////////////////////// Ian McEwen Opinions expressed here are a product of my NeoCAD, Inc. heredity and environment, and should not be 2585 Central Ave. considered the same as those of my employer. Boulder, CO 80301 Internet: ian@neocad.com Phone: (303)442-9121 FAX: (303)442-9124 /////////////////////////////////////////////////////////////////////////Article: 235
Benjamin Gene Cheung (gt0361b@prism.gatech.edu) wrote: > Has anyone sampled the ifx8160 from intel? What do think of it? Were they ever made available by Intel? Just before Intel sold to Altera I was told they weren't available yet. Is Altera going to bring it out? -- ------- Bryan Butler bbutler@netcom.comArticle: 236
Registration Information and Advance Program
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Preliminary Program
Workshop Physics and Computation, PhysComp 94
Harvey Hotel-Addison
====================================================================
==================== Wednesday pm, Nov 16, 1994 ===================
6:00 - 9:00 Registration, Reception, and cash bar
====================================================================
==================== Thursday am, Nov 17, 1994 ===================
7:30 - 8:30 --- Continental Breakfast ---
Session 1: The Technologist's Perspective on Nanoelectronics
---------- Chair: Gary Frazier
8:30 - 9:00 Integrated Circuits, Nanoelectronics, and
21st Century Electronic Systems
Bob Bate (Texas A&M University)
9:00 - 9:30 The Life Expectancy of CMOS Technology
Bob Doering (Texas Instruments)
9:30 - 10:00 Research Toward Nanoelectronic Computing
Technologies in Japan
Rick Kiehl (Fujitsu)
10:00 - 10:30 --- BREAK ---
Session 2: Computing With Quantum Devices
---------- Chair: Gary Frazier
10:30 - 11:00 Resonant Tunneling Quantum Devices and Circuits
Alan Seabaugh (Texas Instruments)
11:00 - 11:30 Quantum Cellular Automata: The Physics os Computing
with Arrays of Quantum Dot Molecules
Craig S. Lent, P. Douglas Tougaw,
and Wolfgang Porod (Univ. Notre Dame)
11:30 - 12:00 Results on Two-Bit Gate Design for Quantum Computers
David DiVincenzo (IBM)
12:00 - 1:30 --- LUNCH ---
====================================================================
==================== Thursday pm =================================
Session 3: Architecture Issues in Nanoelectronics
---------- Chair: Wolfgang Porod
1:30 - 2:00 Horizons of Parallel Computation
Gianfranco Bilardi (University of Padova)
2:00 - 2:30 Multiprocessor Architectures and Physical Law
Paul Vitanyi (CWI / Univ. of Amsterdam)
2:30 - 3:00 Algebras and Architectures for Nanoelectronics
Gary Frazier (Texas Instruments)
3:00 - 3:30 --- BREAK ---
Session 4: Architecture Issues for Computation
---------- Chair: Doug Matzke
3:30 - 4:00 The Latest in Adiabatic Computing
John Denker (AT&T)
4:00 - 4:30 Impact of Locality and Dimensionality Limits
on Architecture Trends
Doug Matzke (Texas Instruments)
4:30 - 5:00 Space, Time, Logic, and Things
Dick Shoup (Interval Research)
5:00 - 5:30 Space and Time in Computation, Topology
and Discrete Physics
Louis H. Kauffman (Univ. Illinois at Chicago)
====================================================================
==================== FRIDAY am, Nov 18, 1994 =====================
8:00 - 9:00 --- Continental Breakfast ---
Session 5: KEYNOTE ADDRESS
---------- General Chair: Doug Matzke
9:00 - 10:00 Computation in Analog and Digital Physical Systems
Carver Mead (Cal Tech)
10:00 - 10:30 --- BREAK ---
Session 6: QUANTUM COMPUTERS
---------- Chair: Bill Frensley
10:00 - 10:30 Is Quantum Mechanics Useful?
Rolf Landauer (IBM)
10:30 - 11:00 The Stabilisation of Quantum Computations
Andre Berthiaume (Univ. Montreal), David Deutsch
(Univ. Oxford), and Richard Jozsa (Univ. Plymouth)
11:00 - 11:20 Can Quantum Computers Have Simple Hamiltonians?
Michael Biafore (MIT)
11:20 - 11:40 Quantum Oblivious Transfer Is Secure Against All
Individual Measurements
Dominic Mayers and Louis Salvail (Univ. Montreal)
11:40 - 1:30 --- LUNCH ---
====================================================================
==================== FRIDAY pm ===================================
Session 7: QUANTUM COMPUTATION
---------- Chair: Wolfgang Porod
1:30 - 2:15 A Fast Algorithm for Factoring on Quantum Computers
Peter Shor (AT&T)
2:15 - 3:00 Decoherence and Quantum Computers- A Problem
Bill Unruh (Univ. B. C., Vancouver)
3:00 - 3:30 --- BREAK ---
Session 8: PHYSICS as COMBINATORIAL COMPUTATION
---------- Chair: Riley Jackson
3:30 - 4:00 Physical Parallelism and Computation
Keith Bowden (Univ. East London)
4:00 - 4:30 Bit-String Physics: A Novel "Theory of Everything"
H. Pierre Noyes (Stanford Univ.)
4:30 - 5:00 Toward an Information Mechanics
Michael Manthey (Aalborg Univ.)
====================================================================
==================== SATURDAY am, Nov 19, 1994 ====================
7:30 - 8:30 --- Continental Breakfast ---
Session 9: REVERSIBLE LOGIC
---------- Chair: Paul Vitanyi
8:30 - 9:00 Reversible Logic Issues in Adiabatic CMOS
Bill Athas and Lars Svensson (USC)
9:00 - 9:20 Thermal Logic Circuits
J. G. Koller, W. C. Athas, and L. J. Svensson (USC)
9:20 - 9:40 A Reversible Instruction Set Architecture and Algorithms
J. Storrs Hall (Rutgers Univ.)
9:40 - 10:00 Encoded Arithmetic for Reversible Logic
Akhilesh Tyagi (Iowa State Univ.)
10:00 - 10:30 --- BREAK ---
Session 10: CELLULAR AUTOMATA & REVERSIBLE CA
----------- Chair: Andrew Ilachinski
10:30 - 10:50 Some Results on Invertible Cellular Automata
Andrea Clementi, Patrizia Mentrasti (Univ. Roma),
and Pierluigi Pierini (MIT)
10:50 - 11:10 On the Average-Case Complexity of the Reversibility
Problem for Finite Cellular Automata
Andrea Clementi (Univ. Roma), Pierluigi Pierini (MIT),
and Russell Impagliazzo (UC San Diego)
11:10 - 11:30 Necessary and Sufficient Conditions for Reversibility in
One Dimensional Cellular Automata
Jose Alberto Baptista Tome (INESC Lisbon)
11:30 - 12:00 Coupling Computations Through Space
Pedro P. B. de Oliveira (Nat'l Inst. Space Res., Brazil)
12:00 - 1:30 --- LUNCH ---
====================================================================
========================= SATURDAY pm ============================
Session 11a: QUANTUM COMPUTATION
------------ Chair: Bill Frensley
1:30 - 1:50 Quantum Waveguide Structures and Devices
Stephen M. Goodnick, A. Weisshaar, A. Ecker,
and V. K. Tripathy (Oregon State Univ.)
1:50 - 2:10 On a Method of Solving SAT Efficiently Using
the Quantum Turing Machine
Takashi Mihara and Tetsuro Nishino
(Japan Adv. Inst. Sci. & Technol.)
2:10 - 2:30 Chu Spaces: Automata with Quantum Aspects
Vaughan Pratt (Stanford Univ.)
Session 11b: STATISTICAL MECHANICS and INFORMATION
------------ Chair: Riley Jackson
2:30 - 2:50 Statistical Mechanics of Combinatorial Search
Tad Hogg (Xerox PARC)
2:50 - 3:10 Phase Transitions and Coarse-Grained Search
Colin P. Williams and Tad Hogg (Xerox PARC)
3:10 - 3:30 --- BREAK ---
Session 12: ENTROPY and INFORMATION
----------- Chair: Andrew Ilachinski
3:30 - 4:00 The Boltzmann Entropy and Randomness Tests
Peter Gacs (Boston Univ.)
4:00 - 4:20 Entropy Cost of Information
Paul N. Fahn (Stanford Univ.)
4:20 - 4:40 The Complexity and Entropy of Turing Machines
Paul A. Dufort and Charles J. Lumsden (Univ. Toronto)
4:40 - 5:00 A Fast Algorithm for Entropy Estimation of Grey-Level Images
Salvatore D. Morgera and Jihad M. Hallik (McGill Univ.)
6:30 - 9:00 --- Reception, cash bar, and Banquet ---
Making waves with our troubadour
Gilles Brassard (Universit\'e de Montr\'eal
and Ecole Normale Sup\'erieure)
====================================================================
====================== SUNDAY am, Nov 20, 1994 ===================
7:30 - 8:30 --- Continental Breakfast ---
Session 13: PARALLEL COMPUTATION
----------- Chair: Sharad Saxena
8:30 - 9:00 Computational Spacetimes
E. Theodore L. Omtzigt (Intel)
9:00 - 9:20 Evolution, Entropy, and Parallel Computation
Kurt Thearling (Thinking Machines)
9:20 - 9:40 On Physical Models of Neural Computation and Their
Analog VLSI Implementation
Andreas G. Andreou (Johns Hopkins Univ.)
9:40 - 10:00 Analog Computation with Continuous ODEs
Michael S. Branicky (MIT)
10:00 - 10:30 --- BREAK ---
Session 14: Panel session on Physics and Computation
----------- Chair: John Denker
10:30 - 12:00 Topic: Will PhysComp make an impact?
==============================================================================
==============================================================================
PLEASE POST AND FORWARD
Article: 237
Folks,
Look! AT&T has announced the biggest FPGA device, ORCA 2C26, and it seems
very powerful. Any comments?
Simon.
*****************************************************************************
AT&T MICROELECTRONICS ANNOUNCES 26,000 GATE ORCA FPGA
AT&T Microelectronics announced the ATT2C26, a 26,000 gate device
which is the highest density single chip FPGA to date. Like the
earlier introduced ATT2C15, the 2C26 is based on a half micron, three
level metal CMOS process.
These half micron devices deliver up to 150MHz clock rates. Both
the 2C15 and 2C26 meet the PCI bus specification requirement with a
pin-to-pin, clock-to-out delay of less than 11 nanoseconds. Using
PREP benchmarks as a reference, the 2C26 delivers an average capacity
of 104 instances and an average benchmark speed of 50MHz. The average
Fext is 40MHz.
The 2C26 is available in two speed grades, -2 and -3, with logic
delays of 2.5ns and 1.8ns respectively. Offering users 384I/O's,
36,864 bits of user RAM, and 2,304 flip-flop in the core logic cells,
the 2C26 leads the industry as the highest density single chip FPGA.
The various packages offered provide footprint compatibility with any
other ORCA FPGA device so users can easily integrate more logic and
upgrade to the 2C26.
Compared to competitive devices using two level metal, ORCA Series
2C devices exhibit 33 percent more routing tracks to sustain and even
increase performance. Additional routing resources are incorporated in
the Series 2C architecture, permitting easier routing in highly complex
designs, as well as higher speeds as a result of minimized interconnect
delays.
Price and Availability
ORCA FPGA users can route designs in the 2C26 by utilizing the
ORCA development system version 3.0 or the NeoCAD tool set version 6.1.
Samples of the ATT2C26-2PS208 are currently available. 1000 unit price
is $720.00. The device will sell for $395.00 in volume by the middle
of 1995. The 2C26 is available in the following package options.
208-Pin Quad Flat Pack
240-Pin Quad Flat Pack
304-Pin Quad Flat Pack
429-Pin Ceramic Pin Grid Array
Article: 238In article <9409271733.AA08796@dpi.inpe.br> celso@dpi.inpe.br writes: "If you need to determine the equations of (or duplicate) "protected PALs of the series 16L8, 20L8, 16R4/6/8, "20R4/6/8 and others, we may help you. For more information, "contact us: " "C.R.Sonnenburg or C.L.Mendes "sonnen@ieav.cta.br celso@inpe.dpi.br " I can think of at least one commercially available tool that does this - and not just for simple PALs. David Pashley Direct Insight Ltd The independent CPLD/FPGA experts Tel: +44 280 700262 Fax: +44 280 700577Article: 239
Hi:
I would like to compare FPGA technology against conventional VLSI approaches
(say gate-arrays, full custom, etc...). I have seen in the literature
some figures comparing the area and speed of the different approaches but
they are not useful enough for me. I want to compare the silicon area
used by our FPGA based Computing Machine, against the one used by a conventional
processor. Our system uses Xilinx XC4008 FPGAs.
1.- How much area has a tile on a XC4008-6 FPGA?
(A tile is a CLB with the adyacent routing network)
2.- How much area is devoted to the routing and how much to the CLB inside
the tile?
3.- How much area is devoted to the lookup table inside the CLB?
4.- How much area (on a tile) is spent on making it programmable?
(I mean the fraction of logic used just to program
the device, and not used by the application).
5.- What technology is currently being used? (CMOS 0.8, two metal layers; I guess)
I do not know what information may be classified by the people of Xilinx.
However, I think that questions 1, 2 and 5 are too general to be sensitive, and
anyone could get this information just looking (very close) at the chip.
Any information from other manufacturers will also be appreciated.
Thank you.
Javier Moran.
Department of Electronic Engineering.
Technical University of Madrid. SPAIN.
email: moran@die.upm.es
Article: 240>Were they ever made available by Intel? Just before Intel sold to Altera >I was told they weren't available yet. Is Altera going to bring it out? The word from Altera is that they will definitely bring out the 8160 and also improved versions of the 780 and 740 (with flash instead of EPROM). -- || Dave Van den Bout || || Xess Corporation ||Article: 241
Tomas Whitlock (txw@festival.ed.ac.uk) wrote: : I'm sure someone has already posted this, but I am new to this newsgroup. : Is there a Xilinx FTP site with public domain software anywhere? Its : address would be much appreciated. No, all they currently offer is a billboard system accessed by Modem :-( I hope they will soon provide something more convenient. I do not know the uk phone number for the billboard. Call Xilinx UK for this. --Murdo McKissock (modem - whats that?)Article: 242
Up until recently, Xilinx 4K has had the playing field pretty much to themselves. I 've heard from several designers that the ATT ORCA 2Cxx family is real, and is worth considering. I'm interested in your opinions of the 2Cxx technology, particularly if you have real-world, production (i.e. shipped products) experience with the stuff. If your comments are necessarily confidential, I will respect your confidentiality (please reply via private email!). As time and work level permit, I will post a summary of the responses to the net. Keep in mind, selecting an FPGA technology is not a popularity contest. There are many considerations with varying importance for differing customers and applications. Often we have the tendency to vilify the beast with whom we've lived over the years because we are intimately familiar with each others' shortcomings, and (as they say) the grass appears somewhat more green on the other side of the fence. As a designer, I'm performing due diligence responsibility in considering the technology alternatives. I've designed with Xilinx 3K and 4K products for >4 years, and I have many successful designs "under my belt". I have a lot of respect for Xilinx, and their sales reflect their having done their work very well. Bob Elkind, Tek TV bobe@tv.tv.tek.comArticle: 243
I'm looking for a description of the PCMCIA protocols (ie. bus timing and signals, standard pinout if applicable). Can anyone point me in the right direction? Thanks in advance.Article: 244
I have a pc card that has a lattice 'gal16v8b 25lp'. I suspect the gal is used for address decoding, the card is a simple parallel-type interface, but not a lpt parallel port. I would like to re-create the card on to another card (combining 3 cards to one for a slot-starved portable...) I have no problem with removing this gal (it is in a socket) and putting it into the new card, but... what IF I let the smoke out? I would be sunk. the card was mfg by a 3rd party, and the second party is not going to tell me who/what/when or sell me the part itself (they will sell me another card for us$150.00, but that defeats the project goal). Can the gal be duplicated without having the original .jed file? -- [todd] Saving Virtual Trees; www file://ftp.netcom.com/pub/tparker/home.htmlArticle: 245
Bryan Butler (bbutler@netcom.com) wrote: : Benjamin Gene Cheung (gt0361b@prism.gatech.edu) wrote: : > Has anyone sampled the ifx8160 from intel? What do think of it? : Were they ever made available by Intel? Just before Intel sold to Altera : I was told they weren't available yet. Is Altera going to bring it out? I think Intel is sampling them now. Only Altera knows if they are going to sell it or not. -- Benjamin Gene Cheung Computer Engineer Georgia Institute of Technology Internet: gt0361b@prism.gatech.eduArticle: 246
David Van den Bout (devb@char.vnet.net) wrote: : >Were they ever made available by Intel? Just before Intel sold to Altera : >I was told they weren't available yet. Is Altera going to bring it out? : The word from Altera is that they will definitely bring out the 8160 : and also improved versions of the 780 and 740 (with flash instead of : EPROM). I think intel is sampling them now. Has anybody tried them out? -- Benjamin Gene Cheung Computer Engineer Georgia Institute of Technology Internet: gt0361b@prism.gatech.eduArticle: 247
Since Intel will drop their FTP site for PLDshell on Oct 1, XESS Corp. will begin providing an FTP site for PLDshell 3.1. The site is ftp.vnet.net Transfer to directory pub/xess and get the files pldsh.zip and install.txt. pldsh.zip has the 3.1 version of PLDshell, the downloading software, and all the design examples from the "FPGA Workout" text. the install.txt file describes how to unpack and install the software. You will need the PKUNZIP tool to do this. XESS Corp. will maintain this FTP site until Altera can provide this service directly. We will upgrade to PLDshell version 4.0 once Altera provides us with an officially released copy of the software. -- || Dave Van den Bout || || Xess Corporation ||Article: 248
In article <36h0ur$lpr@char.vnet.net>, David Van den Bout writes: > >Were they ever made available by Intel? Just before Intel sold to Altera > >I was told they weren't available yet. Is Altera going to bring it out? > > The word from Altera is that they will definitely bring out the 8160 > and also improved versions of the 780 and 740 (with flash instead of > EPROM). Cool. Any idea of time frame for the improved 780's and 740's? This would eliminate my biggest beef about the FlexLogic chips, the #$@ OTP EPROM. ---- Eric Edwards: Bang= cg57.esnet.com!wolf359!eric Domain= eric@exile.org Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 249
I'm interested in obtaining the PREP Benchmark Results, Version 1.3. Does this document exist on-line? Can it be mail ordered? Any and all info is greatly appreciated !! Thanks in advance ... Rich Potral
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