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In article <1994Aug13.215500.26985@xilinx.com> mcgett@xilinx.com (Ed McGettigan) writes:
> 1. First you need to have a design that takes up a lot of gates...
> 2. Now you need a design entry system...
> 3. You need a dynamic simulator that interfaces with your DES...
> 4. You need a place and route tool...
> 5. You need a static timing analyzer...
> 6. Finally you need to generate the programming bit stream...
> 7. You need a programmer to program the chip...
Golly gosh, I wonder how we ever managed to make TTL or CMOS circuits work
without dynamic simulators, and place&route tools, and timing analyzers...
Yet somehow we did it. Even big ones, sometimes.
Hobbyists, and engineers trying to sell their managements on spending $$$
for a "real" development system, would be quite willing to do a lot of
this stuff by hand to reduce up-front investment. The only part of the
above list that is really essential to the low-end market is #7 (and #6 if
your technology isn't up to building reverse-engineering-proof chips). For
the rest, all the low-end users need is adequate documentation on what the
rules are.
If you're worried about support costs, make the low-end support interface
a high-priced 900 number. Very few low-end users will ever call it.
--
"It was blasphemy that made us free." | Henry Spencer
-- Leon Wieseltler | henry@zoo.toronto.edu
Article: 101
Henry Spencer (henry@zoo.toronto.edu) wrote:
: In article <1994Aug13.215500.26985@xilinx.com> mcgett@xilinx.com writes:
: > 1. First you need to have a design that takes up a lot of gates...
: > 2. Now you need a design entry system...
: > 3. You need a dynamic simulator that interfaces with your DES...
: > 4. You need a place and route tool...
: > 5. You need a static timing analyzer...
: > 6. Finally you need to generate the programming bit stream...
: > 7. You need a programmer to program the chip...
: Golly gosh, I wonder how we ever managed to make TTL or CMOS circuits work
: without dynamic simulators, and place&route tools, and timing analyzers...
: Yet somehow we did it. Even big ones, sometimes.
: Hobbyists, and engineers trying to sell their managements on spending $$$
: for a "real" development system, would be quite willing to do a lot of
: this stuff by hand to reduce up-front investment.
Maybe a few hobbyists and engineers would, but in general, I doubt it
very much. If this were true, hobbyists and engineers would also save
$$$ by writing their own C/C++ compilers, instead of buying one from
SUN, Microsoft, etc. The tools you're talking about are not simple,
and the amount of time you'd spend rolling your own would certainly
cost more (unless you're unusually cheap :->) than if you bought the
vendor's tools up front.
I think the majority of hobbyists who love spending hours wire wrapping
TTL and poking around with a logic probe would not have the inclination
to develop map/place/route (at a minimum) required to move their hobby
into an FPGA (I'm sure some of you would, but not many). And the few
who would do this certainly do not drive the market.
-- Ian
--
/////////////////////////////////////////////////////////////////////////
Opinions expressed here are a product of my
heredity and environment, and should not be
considered the same as those of my employer.
Article: 102In article <1994Aug15.181531.2553@neocad.com>, ian@neocad.com (Ian McEwen) writes... >Henry Spencer (henry@zoo.toronto.edu) wrote: >: In article <1994Aug13.215500.26985@xilinx.com> mcgett@xilinx.com writes: >: > 1. First you need to have a design that takes up a lot of gates... >: > 2. Now you need a design entry system... >: > 3. You need a dynamic simulator that interfaces with your DES... >: > 4. You need a place and route tool... >: > 5. You need a static timing analyzer... >: > 6. Finally you need to generate the programming bit stream... >: > 7. You need a programmer to program the chip... > >: Golly gosh, I wonder how we ever managed to make TTL or CMOS circuits work >: without dynamic simulators, and place&route tools, and timing analyzers... >: Yet somehow we did it. Even big ones, sometimes. I suspect that a lot of hobbyists (myself included) do not really push the technology to the limit very often. It's nice to have a good logic analyser when doing close-to-max-speed TTL designs, but let's face it, a lot of hobbyist stuff runs at <10MHz. And I suspect that hobbyists do not need to get maximum utilisation out of the FPGAs. Hell, I have been known to patch the JEDEC files that I program GALs from. And the only tool I have to generate those files is a program that converts the optimised equations into the JEDEC file. I have to design the circuit, and produce the equations in the right form, myself. Simulators - don't trust them. Nothing I have ever designed has evern been on a simulator. Yes, I design pretty high-speed (50MHz +...) digital circuits, which work first time. > >: Hobbyists, and engineers trying to sell their managements on spending $$$ >: for a "real" development system, would be quite willing to do a lot of >: this stuff by hand to reduce up-front investment. > > >Maybe a few hobbyists and engineers would, but in general, I doubt it Look at Linux for what hobyists do on there own :-) >very much. If this were true, hobbyists and engineers would also save >$$$ by writing their own C/C++ compilers, instead of buying one from Some do. I chose not to, but I could have done if I'd wanted to. The necessary information to write said compiler is easily available. >-- Ian >-- -tony Bristol University takes no responsibility for the views expressed in this posting. They are the personal views of the user concerned.Article: 103
jgealow@mtl.mit.edu (Jeffrey C. Gealow) writes: >In article <CuJv63.9M9@qus102.qld.npb.telecom.com.au> pclink@qus102.qld.npb.telecom.com.au (Rick) writes: > 1. Sell it without support. Jeez, the reason we do hobby type > 2. Sell the software cheap but charge for support. Those that >The problem with this approach is that it assumes that the software is >coherent, complete, and has relatively few bugs. Otherwise, struggling Well, I dont think my preferred solution - make the source available - would be acceptable to the big boys. If they were willing to listen to bug reports and make bi-annual bugfix releases, I could live with it. -- Rick "JT" Lyons | C/C++/x86/X | What claim? Dis claim! Telecom Australia | Unix/DOS/Novell | Usenet before net uses you. ACN 051 775 556 | | work:pclink@qus102.qld.npb.telecom.com.au | play:rick@razorback.brisnet.org.auArticle: 104
In article <1994Aug15.181531.2553@neocad.com> ian@neocad.com (Ian McEwen) writes:
>: > 1. First you need to have a design that takes up a lot of gates...
>: > 2. Now you need a design entry system...
>: > 3. You need a dynamic simulator that interfaces with your DES...
>: > 4. You need a place and route tool...
>: > 5. You need a static timing analyzer...
>: > 6. Finally you need to generate the programming bit stream...
>: > 7. You need a programmer to program the chip...
>: Hobbyists, and engineers trying to sell their managements on spending $$$
>: for a "real" development system, would be quite willing to do a lot of
>: this stuff by hand to reduce up-front investment.
>
>Maybe a few hobbyists and engineers would, but in general, I doubt it
>very much. If this were true, hobbyists and engineers would also save
>$$$ by writing their own C/C++ compilers...
I think you've missed my point. I'm not saying that these folks would be
writing their own tools; I'm saying that they'd be doing the design the
old-fashioned way, with pencil and paper, rather than using the fancy
computerized tools. Believe it or not, there are people who can design
working circuits without simulating them, devise workable two-dimensional
layouts using just paper and pencil (and lots of erasers!), and perform
timing analyses using a four-function calculator or even manual arithmetic.
*If* they have the necessary information.
Sure, this gives less than optimal results in many cases. And it's a lot
more time and hassle. But there are plenty of people who see that as a
favorable tradeoff.
When Bill Gates and his cronies set out to write Altair BASIC, they did
not use an optimizing C++ compiler with integrated full-screen editor and
symbolic debugger. They nevertheless got results.
--
"It was blasphemy that made us free." | Henry Spencer
-- Leon Wieseltler | henry@zoo.toronto.edu
Article: 105References: <32jhq4$psa@news.service.uci.edu> Sender: Followup-To: Distribution: Organization: US Dept. of Defense Keywords: In article <32jhq4$psa@news.service.uci.edu> cho@balboa.eng.uci.edu (Jae Cho) writes: >Hi; > >I am looking for a free or very inexpensive translator >that will translate XILINX design to a structural Verilog >or EDIF netlist. I have tried Viewlogic's EDIF translator, >but it contains not only the primitive elements but also >the simulation related delays and so on. My intent is to >be able to simulate a design with multiple XILINX devices >using Verilog XL (for the functionality for the time being). >If anyone knows such SW, please let me know. > >Thank you very much. > >Sincerely, > >Jae Cho. I don't know what your definition of inexpensive is. We currently use the Xilinx xnf2edif and edif2verilog tools to write structural Verilog from Xilinx designs. Two output files result, the structural Verilog involving the primitives, and an SDF file with the post-route delay information. You need only the former for functional simulation. Since you mention Verilog-XL you must have some sort of University agreement with Cadence to obtain SW? They now OEM the Xilinx tools, so I would check with them on obtaining the above two translators. Chris TscharnerArticle: 106
Ed McGettigan (mcgett@xilinx.com) wrote: : The FPGA houses will provided at a bare minimum the place and route tool : and the programming software and some version of a timing analyzer. But : all of this requires a great deal of time and money to develop and support. : Yes, you can argue that once a piece of software is written that the cost : per copy is negligible ~$15.00 or so with all of the manuals. But the biggest : cost is in support for the product. If the FPGA house sold the software to : anyone with $50-$100 and a programmer for another $20 the resulting support : calls would dwarf any profit that would generated by the hobbyist. So there : is no driving economic force to drop the price below $1000. Note: In a recent : EE Times a Distributor had an ad for the Xilinx Basic Development Kit for $995 1) I feel a little ripped off: We recently payed $3000 for a basic development kit. (Which is still not completely delivered) 2) Yes your argument is correct. What I'd suggest is that on the "cheap" hobbyist versions you don't provide support. To be honest: that's what Quicklogic is (was) doing. We (a few hobbyists) bought a "demo version" for $100 that didn't include the simulator. Demo version buyers can look at the software, and are not elegible for support. Simple problem, simple solution. : BIG TIME DISCLAIMER: This post is my own personal opinion on this topic and : is NO way endorsed or supported by Xilinx. : |mcgett@xilinx.com | FPGA Applications Engineer (408)879-4772 | : +----------------------------------------------------------------------+ Ok. ok. But you are someone "on the inside" that may be able to talk to the right people? (please .... :-) Roger. -- * As a protest against the recent bunch proposed anti-cryptography * * laws, this message has been doubly encrypted using the rot13 algorithm. * EMail: wolff@dutecai.et.tudelft.nl ** Tel +31-15-783643 or +31-15-142371Article: 107
Henry Spencer (henry@zoo.toronto.edu) wrote:
:
: Golly gosh, I wonder how we ever managed to make TTL or CMOS circuits work
: without dynamic simulators, and place&route tools, and timing analyzers...
: Yet somehow we did it. Even big ones, sometimes.
:
We were able to do it because we could place each device ourselves, one at
at time, and probe all ports with a scope or logic analyzer. We also only
needed to add the devices and routings we needed, we didn't have to start
with a generic board with hundreds of devices and thousands of routings and
try to eliminate all but the ones we needed in some efficient manner.
If our designe turned out to need one more gate we added it; we weren't forced
to by the next larger generic array that would be significantly more
expensive and power hungry, not to mention even more complex to route.
------------------------------------------------------------------------------
/ | Dave Schwartz - Hewlett Packard, Spokane Division
/__ __ | P.O. Box 2500
/ / / / | Spokane, WA. 99220-2500
/ / /__/ |
/ | Internet: schwartz@hpspkla.spk.hp.com
/ | Phone: (509)921-3648
-----------------------------------------------------------------------------
These opinions are strictly my own
-----------------------------------------------------------------------------
Article: 108Has anyone heard what QuickTurn is up to these days? Are they looking at new parts like AT&T's ORCA 2c series? Are they looking towards MCMs? ____________________________________________________________________________ Jon C. Russo e-mail: jrusso@atl.ge.com Martin Marietta Corporation phone: (609) 866-6546 Advanced Technology Laboratories dial comm: 8*777-6546 Building 145-2 FAX: (609) 866-6397 Moorestown, NJ 08057 ____________________________________________________________________________Article: 109
I wrote:
>>: Hobbyists, and engineers trying to sell their managements on spending $$$
>>: for a "real" development system, would be quite willing to do a lot of
>>: this stuff by hand to reduce up-front investment.
>Sure, this gives less than optimal results in many cases. And it's a lot
>more time and hassle. But there are plenty of people who see that as a
>favorable tradeoff.
To elaborate on this slightly, as I meant to but forgot to:
Saying "but the cost of our tools equals only [say] 100 engineer man-hours"
assumes that man-hours and capital investment cash are interchangeable.
Often they aren't.
Hobbyists, and for that matter engineers in little struggling "sweat equity"
startups, have much easier access to man-hours than to cash. Even in more
established organizations, engineers who *don't* have strong support from
management for using FGPAs find it a lot easier to bootleg time than money.
Sure, Andy Bechtolsheim will compare the numbers and buy the tools. But
the *next* Andy B. won't -- he can't afford them until he starts shipping
something.
(For those who don't recognize the name: Bechtolsheim was one of the
founders of Sun.)
--
"It was blasphemy that made us free." | Henry Spencer
-- Leon Wieseltler | henry@zoo.toronto.edu
Article: 110rob pfile@cs.wisc.edu writes: > >So, has anyone measured these parts and come up with an average pad to >pad time thru FFs and using only IO buffers? > >I talked to some of my friends in the physics department that use Act2 >series parts, and they say that their ActionProbe reports IO pad >delays that are 3x that in the manual. This is bad news for us if the >accuracy of all of the published numbers is that bad. If you want to know what the path delays are, have you tried using the ALS Timer? Or the back annotation feature of timer? I don't know if your CAE platform supports backannotation. Two that do are Orcad and Viewlogic's ProSeries. Since when does an ActioProbe report delays? John Massoth _____________ All opinions are my own and do not reflect those of TI.Article: 111
From: "Sundar Gopalan sundar@btr.com" <uunet!btr.btr.com!sundar> To: uunet!qcktrn.com!mbutts Subject: Re: Emulation Systems Dear Mr. Butts, I am very keen on posting the following over on the NET to inform the readers of your response, but I am not able to do so. Everytime I try to post the same my server kicks me out! Please if possible do post the following and thank you for all your help including this one! Sundar In article <mbuttsCuBvL0.Mvq@netcom.com>, Mike Butts <mbutts@netcom.com> wrote: >sundar@btr.btr.com (Sundar Gopalan sundar@btr.com) writes: > >>I am looking for information on Emulation systems. I tried calling Quickturn >>Systems here in Mt. View, CA, but I guess they are not interested in sending >>information to small companies like ours. >>Any pointers is appreciated. > >On the contrary! Please send me your address and I'll see that you get >the information you need. I'm sorry if we haven't responded to you yet. >Send me email at mbutts@qcktrn.com. > >In fact we recently introduced a smaller single-board logic emulator, >the Logic Animator, which handles up to 50K gate designs, at a lower >cost than our larger systems. > > --Mike Butts, Quickturn Design Systems > >-- >Mike Butts, Portland, Oregon mbutts@netcom.com > It was unfortunate that I did not receive the information about Quickturn's product the first time. Thanks to you, I have received all the information I need for the present. Also one of your Sales Engineers called me up and offered to help me out with any of my needs in the future. Once again, Thanks! Sundar Gopalan -- Mike Butts, Portland, Oregon mbutts@netcom.comArticle: 112
In article <CunB7F.H2H@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes: > Hobbyists, and for that matter engineers in little struggling "sweat equity" > startups, have much easier access to man-hours than to cash. Even in more > established organizations, engineers who *don't* have strong support from > management for using FGPAs find it a lot easier to bootleg time than money. Yes. The custom-VLSI-CAD-workstation of necessity for a lot of sweat-equity startups these days is a commodity PC + Linux + an assortment of university CAD tools compiled with gcc and running under XFree. All free software and commodity hardware; not even Bill gets his cut from these folks sometimes, when they build their systems from the motherboard up to avoid the MSDOS/Windows charges. When they can afford to they'll bump up to Suns and Cadence, but its often not feasible at first ...Article: 113
In article <4AUG94.09565313@bureau.ucc.ie>, stee8033@bureau.ucc.ie writes: >Has anyone out there used Field Programmable Interconnect. >I recently read something about Aptix programmable interconnect and it >seems it could be of use. Therefore can anybody answer the following? >1. Is the development system expensive >2. Easy to use? >3. Are there other products? Regarding #3, there is another vendor supplier field programmable interconnect chips (FPICs); they are: I-Cube Santa Clara, CA (408) 986-1077 I think you will find that Aptix has moved away from the chip level business and more towards the hardware emulation business where they offer systems (HW and SW) that implement logic (ASICs and parts of systems) on a board that consists of FPGAs and FPICs. I-Cube appears to be content with being a chip vendor rather than moving up the food chain as did Aptix.Article: 114
Ian McEwen (ian@neocad.com) wrote:
: Maybe a few hobbyists and engineers would, but in general, I doubt it
: very much. If this were true, hobbyists and engineers would also save
: $$$ by writing their own C/C++ compilers, instead of buying one from
: SUN, Microsoft, etc. The tools you're talking about are not simple,
: and the amount of time you'd spend rolling your own would certainly
: cost more (unless you're unusually cheap :->) than if you bought the
: vendor's tools up front.
Nope. Not true. It turns out that large group of internet hackers can
be brought together to collectively develop a complete system that
involves hundreds of man-years of development time (*). Some will
mostly use the stuff, others will be hacking the innards to make
it better.
Roger.
(*) Linux, the kernel, I estimate Linux at a 5-20 man-year
project. Software engineering texts says you should be very
happy at 10000 code lines (application code lines that is)
per man-year. The Linux kernel counts 171000 lines of C code.
Gcc is much larger. (around 7 times larger -> 100 man-years)
Emacs is even bigger......
XFree86 ... . . . . . . . .
--
* As a protest against the recent bunch proposed anti-cryptography *
* laws, this message has been doubly encrypted using the rot13 algorithm. *
EMail: wolff@dutecai.et.tudelft.nl ** Tel +31-15-783643 or +31-15-142371
Article: 115Brad Hutchings (hutch@timp.ee.byu.edu) wrote: : partial configuration; however, that is not the same thing as : "self-modifying" hardware. That would require an internally addressable : configuration store. The configuration store of the Atmel device can : only be addressed *externally*. Thus all configuration data must come : from a source external to the FPGA. One may have to wire (on PCB) certain programming pins of the FPGA to certain other user pins. In this way, data generated inside the FPGA can be fed back to the configuration control, which still sees it as data coming from external source. Satwant SinghArticle: 116
Is there ane actel user's group on internet? Thanks Daniel Lapierre phone 514-289-4299 fax 514-289-4695 Hydro Quebec lapierre@dlapierre.ccr.hydro.qc.caArticle: 117
Is there anyone out there that has had experience with using Concept with Actel FPGA software? Let's say I want to do a bit-by-bit AND of two 8-bit buses to yield an 8-bit result. I want to be able to lay down a single symbol and attach a size property of 8b to it to avoid having to lay down 8 AND gates, split out the buses, attach them, and then collapse the 8 output bits into the resulting 8-bit bus. Is this possible with Concept? I've heard it is possible with Verilog. Anyone? Jeff Lucas jlucas@dow.comArticle: 118
jrusso@atl.ge.com (Jon C Russo) writes:
>Has anyone heard what QuickTurn is up to these days? Are they
>looking at new parts like AT&T's ORCA 2c series? Are they looking
>towards MCMs?
Sure, we're always looking at everything that can make logic
emulation better - bigger, easier, cheaper, faster. We just
came out with a single-board 50K gate machine based on XC4013
(Logic Animator). Stay tuned, and thanks for the interest!
--Mike Butts, Quickturn R&D
--
Mike Butts, Portland, Oregon mbutts@netcom.com
Article: 119
Rogier Wolff (wolff@einstein.et.tudelft.nl) wrote:
: Ian McEwen (ian@neocad.com) wrote:
: : Maybe a few hobbyists and engineers would, but in general, I doubt it
: : very much. If this were true, hobbyists and engineers would also save
: : $$$ by writing their own C/C++ compilers, instead of buying one from
: : SUN, Microsoft, etc. The tools you're talking about are not simple,
: : and the amount of time you'd spend rolling your own would certainly
: : cost more (unless you're unusually cheap :->) than if you bought the
: : vendor's tools up front.
: Nope. Not true. It turns out that large group of internet hackers can
: be brought together to collectively develop a complete system that
: involves hundreds of man-years of development time (*). Some will
: mostly use the stuff, others will be hacking the innards to make
: it better.
: Roger.
: (*) Linux, the kernel, I estimate Linux at a 5-20 man-year
: project. Software engineering texts says you should be very
: happy at 10000 code lines (application code lines that is)
: per man-year. The Linux kernel counts 171000 lines of C code.
: Gcc is much larger. (around 7 times larger -> 100 man-years)
: Emacs is even bigger......
: XFree86 ... . . . . . . . .
What you're saying is certainly true, although I was arguing that
*individuals* would be unlikely to develop their own FPGA development
tools even if the bitstream information was available. Few people
would have the ability, and of those, even fewer would actually
embark on such a project ("I could have if I wanted to, but I decided
not to...")
I understand your argument to be that there are hordes of hackers
ready to develop free FPGA software tools, and are only held up by
the fact that chip vendors refuse to publish the bitstream data.
Does this mean that these hackers are not capable of figuring out
the bitstream format without the vendors' help/blessings, but that
they could write the rest of the software? I don't think so. If
there truly is enough interest, these hackers would overcome the
proprietary nature of the bitstreams just like any other hurdle.
I believe that the world's hobbyists/hackers/students are quite
talented, and probably *could* write tools for FPGA development.
If there really is a need and an interest, go do it! If not, it's
not just because you don't have free access to the bitstream data.
The makers of FPGA chips and software don't reveal their bitstream
formats for reasons already put forth in this newsgroup (plus probably
some other reasons), and the fact that a handful of hobbyists want
to use their chips too, but can't afford the tools, doesn't have
much impact. The vendors work to satisfy corporate users, the ones
which will buy lots of chips. Hobbyists don't drive the market.
-- Ian
--
/////////////////////////////////////////////////////////////////////////
Opinions expressed here are a product of my
heredity and environment, and should not be
considered the same as those of my employer.
Article: 120At least with every FPGA I have used, you can't wire user pins to the programming pins in order to have the FPGA reprogram itself because the user-defined logic of the FPGA is disabled as soon as the FPGA begins its configuration sequence. -- || Dave Van den Bout || || Xess Corporation ||Article: 121
Concept does support the SIZE property for bodies. I think the question is does the whatever (Actel?) libraries you are using for your design entry have sizeable parts? If they do not size then the interface to Actel might choke. (To see if they are sizeable edit the body drawing for the part. If it is sizeable I would expect a SIZE property to be attached. If there is a sim drawing, the Interface signals should be vectors with <SIZE-1..0> in the names, i.e. A<SIZE-1..0>\I.) If you are using the Cadence PIC designer for design entry the pld_lib schematic parts for concept have sizeable gates and such. I am using the Xilinx libraries and certain of their parts are sizeable. Certain other things (like input pads and buffers) the Xilinx tools like to have explicitly placed in the schematic withOUT the size property. I've not used Actel parts so I do not know what your design process and interface is. Hope that helps. -- Joe Dalton (only unofficial opinions in the above)Article: 122
In article <1994Aug15.181531.2553@neocad.com>, Ian McEwen writes: > Maybe a few hobbyists and engineers would, but in general, I doubt it > very much. If this were true, hobbyists and engineers would also save > $$$ by writing their own C/C++ compilers, instead of buying one from > SUN, Microsoft, etc. The tools you're talking about are not simple, To an extent, they do. Hobbyist use freeware compilers, like GCC or stripped down commercial systems that lack exotic development tools. You won't find many hobbyist using CASE tools, for instance. Hardware hacking, much more so than software hacking, is a expensive hobby. Getting by with less than adequate tools is just part of the game. Many get by without osciloscopes or even good soldering stations. Surviving without simulators or static timing analysers is hardly an unusual hardship. Eric Edwards: Bang= cg57.esnet.com!wolf359!eric Domain= eric@wolf359.esnet.com Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 123
Is there a FAQ for this? I would like to see a table of FPGA families, there sizes and functionality. For instance I know that Xilinx manufacture large FPGAs that have to be loaded from ROM at power up, while TI manufacture a range of smaller one time programmable FPGAs that are ready to run at power up. What others are available? What is the gap between the larger GALs and the smaller FPGAs? Thanks in advance Michael Milway Dept Computer Science Uni of Wollongong.Article: 124
My present project is to build a multiprocessor decoder using Xilinx FPGAs. It will consist of over 30 4010 and 4005 surface mount Xilinx FPGAs. My problem is that once I complete this system, I want some method of observing and testing the system. There is something called readback which allows me to probe pins but that only applies to one FPGA. Xilinx allows the possibility of using boundary scan to help test the system. I've read the literature in the Xilinx databooks and some other material; however, whereas readback is executed using the Xchecker or XDE software, I have been unable to find software to execute the boundary scan instructions. Does anyone have any experience with boundary scan and could possibly point me in the right direction and to some software (preferably FREE)? Thanks. David Yeh
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