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As an alternate suggestion, I would imagine that there's some competitor/3rd party company that's hacked Xilinx' bitstream stuff (NeoCAD, for example, may have documented it in some of their old specs). ATT, as part of competing against Xilinx, may have hacked it. Unfortunately, I wouldn't imagnine either company is now going to help you get inside Xilinx code. But maybe there's someone else (Viewlogic, DATA IO, perhaps?) ErikArticle: 2176
Perhaps you should be considering one of the standard 20-24 pin PLDs, but in the SOIC pacakage footprint. These little surface mount guys take up about the same board footprint is an 8 pin DIP. My $0.02 worth. Doug Shade rxjf20@email.sps.mot.comArticle: 2177
Hi, Has anyone ever used Field Programmable Interconnect Devices? - for example like the ones made by I-CUBE?. These i would imagine are extremely useful devices, just think of all those possible applications!! - Nerual Nets, Comms, FFT butterfly networks etc.. IainArticle: 2178
In article <46ohoe$q8f@scotsman.ed.ac.uk>, Iain Rankin <idr@ee.ed.ac.uk> wrote: >Hi, > >Has anyone ever used Field Programmable Interconnect Devices? - for >example like the ones made by I-CUBE?. These i would imagine are >extremely useful devices, just think of all those possible applications!! - >Nerual Nets, Comms, FFT butterfly networks etc.. I used the ICUBE IQ160 for the RIPP10 reconfigurable board. It is a very easy part to deal with. Just a big crossbar that you program through the JTAG port. ICUBE supplies a JTAG library for working with the chip. You don't need a monstrous development system like you would with the Aptix chip. This was two years ago. ICUBE has changed their chip since then. The biggest change (as I remember) is the addition of a fast programming port that would allow a microprocessor to quickly change connections in the chip without having to reprogram the entire matrix through the JTAG port. -- || Dave Van den Bout -- XESS Corp. || || 2608 Sweetgum Dr., Apex, NC 27502 || || (919) 387-0076 FAX:(919) 387-1302 || || devb@xess.com devb@vnet.net ||Article: 2179
first problem with the expansion rom bios enable, system refuse to boot. System consist of a Dell pentium 590 with adaptec pci scsi controller 2940. If expansion rom bios disable no boot problem. AMCC are aware of this problem, but there is no fix at this time. second. Presently having a hard time writing and reading the flash memory 29C512. This morning I could read the first 64 byte no problem. Then I went to write mode, was never successful in writng a location and reading back the proper info. By afternoon I got deeper in the hole now cannot read back successfully a lot of the bytes being read are FF. Any help would be appreciated. Even AMCC nvbuild program is not successful in writing to the flash memory everytime. This message might be in the wrong newsgroup, if so please direct me to the proper newsgroups. Thank you in advance.Article: 2180
Please send me your Digest. I'm LouisSwart@ist.co.zaArticle: 2181
Why on earth would anyone want to hack a bit stream? If you have a legit reason, try contacting Xilinx directly. If not, spend your time on these alternatives: Get a life. Look for honest employment. Community service, charity, etc. More education so you can design yourself. --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 2182
Dear netters, we are looking for a low cost solution to set up as quickly as possible protyping boards composed of several FPGA's and some glue logic for image processing applications. FPID are a very good solution to this problem but, at least here in Italy, the Aptix development system is VERY expensive (30000 US$). What I would like to find is board with sockets for 5-10 Xilinx FPGA's a breadbord area and a serial/parallel interface. Has anyone seen such a beast? Thanks in advance, -Arrigo BenedettiArticle: 2183
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Hello world,
We use a network with an HP server (9000 series) and LAN Manager
software in the PCs (486-33). A network failure & an internal error 1012 (PPR)
occur frequently when we run our designs. We've discovered a desconection
between the server and the PC happens. However, the AUTODISCONECTION parameter
in the server is set to -1 (this means no disconection is allowed). We don't
undestand what's happening!!!! Can you help us?
Thanks in advance,
Xilinx group
TSC Dpt.
UPC
Barcelone
SPAIN
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<UL>
<LI><B> Where to find more info on PCI</B>
<UL><LI><A NAME=3D"466i1m$rda@nz12.rz.uni-karlsruhe.de" HREF=3D"466i1m$rda@=
nz12.rz.uni-karlsruhe.de">Roland Knapp</A> (14)
<LI><A NAME=3D"46foo3$c25@outlaw.zfe.siemens.de" HREF=3D"46foo3$c25@outlaw.=
zfe.siemens.de">Christian Grebe</A> (228)
</UL><LI><A NAME=3D"814177561snz@tile.demon.co.uk" HREF=3D"814177561snz@til=
e.demon.co.uk"><B>Xilinx 5000 - any user feedback?</B> - Simon Bacon</A> (=
9)
<LI><A NAME=3D"1995Oct20.055604.5351@super.org" HREF=3D"1995Oct20.055604.53=
51@super.org"><B>subscribe</B> - sharono@ukefl.demon.co.uk</A> (2)
<LI><A NAME=3D"4666dk$re@ixnews7.ix.netcom.com" HREF=3D"4666dk$re@ixnews7.i=
x.netcom.com"><B>Re: Needed: Suggestions for FPGA design CAD</B> - Erik Jes=
sen</A> (9)
<UL><LI><A NAME=3D"DGpv8r.1Iv@data-io.com" HREF=3D"DGpv8r.1Iv@data-io.com">=
Tom Bowns</A> (25)
</UL><LI><A NAME=3D"466ao3INN2uh@scarecrow.mke.ab.com" HREF=3D"466ao3INN2uh=
@scarecrow.mke.ab.com"><B>Re: one-hot encoding for fsm's</B> - Roger Landow=
ski</A> (7)
<LI><A NAME=3D"DGr2yG.JpB@attatl.AtlantaGA.NCR.COM" HREF=3D"DGr2yG.JpB@atta=
tl.AtlantaGA.NCR.COM"><B>Re: Chip Express Expreiences Wanted</B> - Nelson W=
illhite</A> (74)
<UL><LI><A NAME=3D"468p4q$mm6@kodak.rdcs.Kodak.COM" HREF=3D"468p4q$mm6@koda=
k.rdcs.Kodak.COM">David Hinterberger</A> (10)
</UL><LI><A NAME=3D"468uu6$3od@nyheter.chalmers.se" HREF=3D"468uu6$3od@nyhe=
ter.chalmers.se"><B>Problem using Xilinx XC4025</B> - Mats Olsson</A> (28)=
<UL><LI><A NAME=3D"46gjb7$9a9@ixnews2.ix.netcom.com" HREF=3D"46gjb7$9a9@ixn=
ews2.ix.netcom.com">Erik Jessen</A> (20)
<LI><A NAME=3D"46i89e$g6s@outlaw.zfe.siemens.de" HREF=3D"46i89e$g6s@outlaw.=
zfe.siemens.de">Christian Grebe</A> (48)
</UL><LI><A NAME=3D"468v5n$a5t@mailman.xilinx" HREF=3D"468v5n$a5t@mailman.x=
ilinx"><B>Re: Help - Searching an PLD/FPGA Selection Software</B> - "Steven=
K. Knapp, Xilinx, Inc."</A> (21)
<LI><A NAME=3D"1995Oct19.133023.4819@wmi.com" HREF=3D"1995Oct19.133023.4819=
@wmi.com"><B>PC Silos and DOS/16M</B> - Floyd Miller</A> (17)
<LI><A NAME=3D"469jtr$vgg@zipper.zip.com.au" HREF=3D"469jtr$vgg@zipper.zip.=
com.au"><B>FPGAs as a substitute for glue logic?</B> - Duraid Madina</A> (=
13)
<UL><LI><A NAME=3D"46h1d1$kfn@yama.mcc.ac.uk" HREF=3D"46h1d1$kfn@yama.mcc.a=
c.uk">John Forrest</A> (30)
<LI><A NAME=3D"46gj1e$9a9@ixnews2.ix.netcom.com" HREF=3D"46gj1e$9a9@ixnews2=
=2Eix.netcom.com">Erik Jessen</A> (14)
<LI><A NAME=3D"46k5l2$ipp@newshost.quickturn.com" HREF=3D"46k5l2$ipp@newsho=
st.quickturn.com">Tom Biggs</A> (34)
</UL><LI><A NAME=3D"199510202137.RAA02235@ground.cs.columbia.edu" HREF=3D"1=
99510202137.RAA02235@ground.cs.columbia.edu"><B>My own hard macro in VHDL?<=
/B> - Fu-Chiung Cheng</A> (25)
<UL><LI><A NAME=3D"46fhk5$mnd@yama.mcc.ac.uk" HREF=3D"46fhk5$mnd@yama.mcc.a=
c.uk">John Forrest</A> (38)
</UL><LI><A NAME=3D"466p44$b0p@cnn.MOTOWN.GE.COM" HREF=3D"466p44$b0p@cnn.MO=
TOWN.GE.COM"><B>Re: Xilinx Configuration Memory Hacking</B> - Francesco Mic=
ale, X4438</A> (6)
<UL><LI><A NAME=3D"46mgfq$vus@classic.iinet.com.au" HREF=3D"46mgfq$vus@clas=
sic.iinet.com.au">David R. Brooks</A> (22)
<UL><LI><A NAME=3D"46omjf$m5a@ixnews4.ix.netcom.com" HREF=3D"46omjf$m5a@ixn=
ews4.ix.netcom.com">Erik Jessen</A> (8)
</UL></UL><LI><A NAME=3D"463ee8$61t@nnrp2.nfs.primenet.com" HREF=3D"463ee8$=
61t@nnrp2.nfs.primenet.com"><B>Re: Programming AMD Mach Parts</B> - Ray Saa=
rela</A> (39)
<UL><LI><A NAME=3D"peter.presti-2310952158280001@mac9.oip.gatech.edu" HREF=3D=
"peter.presti-2310952158280001@mac9.oip.gatech.edu">Peter Presti</A> (22)
</UL><LI><A NAME=3D"46chnl$1e5@info.sta.net.cn" HREF=3D"46chnl$1e5@info.sta=
=2Enet.cn"><B>China business guide</B> - keysoft@public.sta.net.cn</A> (51=
)
<LI><A NAME=3D"46d214$o46@ping1.ping.be" HREF=3D"46d214$o46@ping1.ping.be">=
<B>PLD in small package ?? anyone</B> - Vincent Himpe</A> (17)
<UL><LI><A NAME=3D"46dfu8$mqr@lys.vnet.net" HREF=3D"46dfu8$mqr@lys.vnet.net=
">David Van den Bout</A> (21)
<UL><LI><A NAME=3D"46eqh0$m2t@a3bsrv.nai.net" HREF=3D"46eqh0$m2t@a3bsrv.nai=
=2Enet">Gerry Belanger</A> (18)
</UL><LI><A NAME=3D"46leuf$kbr@osh2.datasync.com" HREF=3D"46leuf$kbr@osh2.d=
atasync.com">Manoj Chaubal</A> (24)
<UL><LI><A NAME=3D"46o71h$6ii@aurns1.aur.alcatel.com" HREF=3D"46o71h$6ii@au=
rns1.aur.alcatel.com">William J. Wolf</A> (19)
<LI><A NAME=3D"46oc0t$6nm@newsgate.sps.mot.com" HREF=3D"46oc0t$6nm@newsgate=
=2Esps.mot.com">Doug Shade</A> (7)
</UL></UL><LI><A NAME=3D"1995Oct23.192642.27404@super.org" HREF=3D"1995Oct2=
3.192642.27404@super.org"><B>Re: Comp.Arch.FPGA Reflector V1 #354</B> - Sha=
ron Okoli</A> (3)
<LI><A NAME=3D"46ohoe$q8f@scotsman.ed.ac.uk" HREF=3D"46ohoe$q8f@scotsman.ed=
=2Eac.uk"><B>FPID's</B> - Iain Rankin</A> (9)
<UL><LI><A NAME=3D"46ol97$6t1@lys.vnet.net" HREF=3D"46ol97$6t1@lys.vnet.net=
">David Van den Bout</A> (24)
</UL><LI><A NAME=3D"46m9r9$abi@news00.btx.dtag.de" HREF=3D"46m9r9$abi@news0=
0.btx.dtag.de"><B>Help needed: TNM attributes (Xilinx)</B> - Peter Wurbs</A=
> (19)
<LI><A NAME=3D"DH2nzv.6Kt@emr1.emr.ca" HREF=3D"DH2nzv.6Kt@emr1.emr.ca"><B>A=
MCC pci kit- problems</B> - Simon M=E9thot</A> (16)
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---------------------------------179882765124098--
Article: 2184
In article <46qgfi$e69@aurns1.aur.alcatel.com> wolf@aur.alcatel.com (William J. Wolf) writes:
Why on earth would anyone want to hack a bit stream?
If you have a legit reason, try contacting Xilinx directly.
If not, spend your time on these alternatives:
Get a life.
Look for honest employment.
Community service, charity, etc.
More education so you can design yourself.
I'm working on an idea for late value binding which should prove trivial
with bit-stream modifications, but the application will not tolerate
running through the tool chain again.
If Xilinx decides not to help me, then I've got to do it on my own, but its
all *my* design so I won't be upsetting myself.
None of these features have anything to do with criminal activity,
and your presumption that they do is a bit niave and upsetting.
Bill
Article: 2185>I'm working on an idea for late value binding which should prove trivial >with bit-stream modifications, but the application will not tolerate >running through the tool chain again. As has been reported here, Xilinx will be releasing a new part that is designed for partial reloading of routing so that a user can 'swap in' the circuitry needed. The target market is for co-processors, but perhaps is is a better match for your work than the Xc4000 family is. Unfortunately, I can't find the seminar notes. Can someone help out with a recap? --- Joe -- +===============================================================+ + Joe Samson (313) 994-1200 x2878 + + Research Engineer, ERIM + + P.O. Box 134001 email samson@erim.org + + Ann Arbor, MI 48113-4001 + +===============================================================+Article: 2186
In article <46o71h$6ii@aurns1.aur.alcatel.com> wolf@aur.alcatel.com writes: >So what *is* the smallest PLD available today? I have seen a number >of fine pitch packages that were tiny, but didn't pay that much attention. >- Bill Wolf, Raleigh NC I'm currently doing some designs for a client using the XC3030 in a VQ100 package. About 80 I/O pins in 16mm by 16mm (.63 inch) package. This is a bit bigger in real estate than the original posters hope for an 8 pin dip, and way more gates. Xilinx also has a VQ64 package which is 12mm by 12mm (.47 inch) which is close in size to a 8 pin dip real estate, but needs far better PCB technology !! Philip Freidin.Article: 2187
In article <BILLMS.95Oct27081834@gsfo.janet.ucla.edu> billms@gsfo.janet.ucla.edu (Bill Mangione-Smith) writes: >In article <46qgfi$e69@aurns1.aur.alcatel.com> wolf@aur.alcatel.com (William J. Wolf) writes: > Why on earth would anyone want to hack a bit stream? > If you have a legit reason, try contacting Xilinx directly. > > If not, spend your time on these alternatives: > Get a life. > Look for honest employment. > Community service, charity, etc. > More education so you can design yourself. > >I'm working on an idea for late value binding which should prove trivial >with bit-stream modifications, but the application will not tolerate >running through the tool chain again. > >If Xilinx decides not to help me, then I've got to do it on my own, but its >all *my* design so I won't be upsetting myself. SO... have you called Xilinx to help you??? The information you want is usually available and requires the signing of an NDA. I've done this and got the info I need, and will be doing some designs where the new bitstreams are created at the rate of about one every second. Like you, my application can not tollerate the time to run the tools for each design needed. The tools are run once, then my software will create the derivatives. >None of these features have anything to do with criminal activity, >and your presumption that they do is a bit niave and upsetting. > >Bill Philip Freidin.Article: 2188
ALL,
Hi. I am currently evualuating a new FPGA technologies for our next generation
product. I have looked at Xilinx and AT&T. The new Xilinx software seem a bit more
polished and easer to use than the AT&T neo stuff. However, it seems that the part
architecture from AT&T is much better.
I work at a fairly slow moving large company who is only interested in dealing with a
BIG FPGA manufacture. I have been told of routing problems with the 4025 part. I
have also been told that the AT&T part is hands down faster.
I'm interested in REAL experience. (BTW my target designs are 8-10K in size)
Comments / Stories [Good and BAD]
Stan
--
===============================================
Name: Stan Hodge | Watch this space for
E-mail: stb@dnaco.net | interesting
Date: 10/28/95 | things
Time: 09:44:56 | to come!
===============================================
Article: 2189What the heck is "late value binding?"Article: 2190
Dear Netters: Does anyone have ever tried to implement a small superscalar processor design using FPGAs ? I would like to have an idea of the gate complexity level for say a 16 bits superscalar with roughly 3 FP units and 2 Int units and a limited number of instructions. Any pointers on books, TRs and projects descriptions for undergraduates and graduates will be appreciated. regards, O.HammamiArticle: 2191
In article <DH2nzv.6Kt@emr1.emr.ca>, methot@ccrs.emr.ca (Simon Mithot) writes: >first problem with the expansion rom bios enable, system refuse to boot. >System consist of a Dell pentium 590 with adaptec pci scsi controller >2940. If expansion rom bios disable no boot problem. AMCC are aware of >this problem, but there is no fix at this time. > >second. Presently having a hard time writing and reading the flash memory >29C512. This morning I could read the first 64 byte no problem. Then I >went to write mode, was never successful in writng a location and >reading back the proper info. By afternoon I got deeper in the hole now >cannot read back successfully a lot of the bytes being read are FF. Any >help would be appreciated. Even AMCC nvbuild program is not successful >in writing to the flash memory everytime. > >This message might be in the wrong newsgroup, if so please direct me to >the proper newsgroups. Thank you in advance. > Unfortunately I can reply only to the last paragraph - this is probably the news group to write. Please post! Oded -------- Oded Ilan System Engineer ASP Solutions Email: oded@asp.co.ilArticle: 2192
Here are the articles I received about Chip Express. Overall, I recieved 3 articles
about Chip Express, 1 on Atmel, and 1 on Orbit. Most seemed to be positive
expereinces.
Thanks to all those who took time to give me their opinions!
==================================================================================
Chip Express Post 1
==================================================================================
Please contact the following person for more info on the company AND for
references to speak with about our product, service etc...
Ehud (Udi) Yuhjtman
Chip Express Corporation
2903 Bunker Hill Lane suite 105
Santa Clara, CA. 95054
Tel: (408)-988-2445 Ext. 127
Fax: (408)-988-2449
E-mail: udi@chipx.com
best regards, yehuda yizraeli
yehuda@chipx.co.il
==================================================================================
Chip Express Post 2
==================================================================================
OK, I've hung back a bit on this item since my experiences with Chip Express
are slightly dated, but since you have no info yet maybe this will help.
The last time we used them was about a year ago. Took a Verilog netlist
for our REAL ASIC (NCR Microelectronics 0.5 micron gate array) and let a
third party here, Oasix, Inc., do the conversion to Chip Express gates,
rerun sims and reverify against our sim results. To do the conversion,
they read the Verilog netlist into Synopsys and retargeted. And prior to
that, I have direct experience running the conversions and resimulations
for two other ASICs while I was an employee at Oasix, Inc. Same flow,
same tools for the conversion, same original library, same target library.
The target library was Chip Express' QYH400, I believe.
The ASICs were not huge but not small either. They ranged from about 15k gate
equivalents to about 30k gate equivalents. At the time, the 30k gate device
was near the upper end of what Chip Express could support in their arrays.
As many are well aware, Synopsys will crank out netlists using small cells
and requiring a higher ratio of routing to gates if not carefully directed
to do otherwise. Since we were in a big hurry to get a netlist (who isn't
if they're willing to pay ChipExpress for rapid prototypes) no real tweaking
of the Synopsys runs were done. I understand Chip Express has come out with
a new array family since then (but please correct me if I'm wrong).
The bottom line:
In each case I was personally involved in, and a couple more I know of from
my days at Oasix, we got working silicon from ChipExpress within a week. This
allowed software/firmware developers to get a huge jump on debugging their
code for the projects. (Like, 2 months, at the time. Symbios Logic's lead
times might be shorter now.) The silicon from ChipExpress was capable of
between 60 and 80% of the speed of the NCR gate array, but that meant it
could run at designed speed at room temperature which the code developers
were happy with. In at least two cases, the ChipExpress parts alerted us
to functional bugs in the designs which were corrected before the netlist
was released to NCR for fab, saving us and our customers a silicon turn at
NCR.
The remapping efforts were NOT trivial for us, especially the first couple
of times. But I believe remapping from one library to any other vendor's
library involves at least a few timing issues to be resolved. So while
frustrating at times, the process was typical, I believe, for the task.
For their part, the folks at ChipExpress were very competent and helpful,
bending over backwards quite often to help squeeze the netlists into the
target array whenever possible, or providing insight on their flow and
tools. They could be a little hard to get ahold of at times however.
For what it's worth, the organization has grown since then, so that aspect
may have changed a little.
Would I recommend them to others? Yes, in the right situations. Don't
expect same speed out of a ChipExpress array as in your leading-edge technology
ASIC. But it'll be fairly close. And don't be surprised if your netlist
counts up as X gate equivalents in your ASIC library, but 1.5X gate equivalents
in the ChipExpress library after conversion. I think their tools and flow and
documentation of said items are pretty good now. So doing it yourself with
their package should be pretty straightforward. But give yourself at least 2 weeks
total to make the conversion, reverify the functionality, and finally get through
the rest of the ChipExpress flow to release to ChipExpress for laser programming,
for the first time through the process. Then about 1 week for designs thereafter.
Finally, I'll say I am not connected with ChipExpress or Oasix, Inc. in any way,
shape or form other than being a fairly satisfied customer of the former, and
having good friends who are very competent implementors at the latter.
Regards and best of luck,
Mark
markwrob@btc.adaptec.com
==================================================================================
Chip Express Post 3
==================================================================================
I am also designing a Chip's Express chip. I have been having some
difficulty with on-chip memory and am suspicious of their speed claims.
David Shoemaker
shoe@goldfish.lcs.mit.edu
==================================================================================
Atmel Post 1
==================================================================================
I would recomend that you talk to ATMEL about your conversions. I have not
used them for conversions yet, but they do them. I have received the first
two of four gate arrays that we are doing with them, and will receive our
third soon.
Working with them on the gate arrays has gone very smoothly. The smallest we
are doing is about 20k gates and the NRE is in the $20K to $30K range. These
numbers may be off a bit, I am at home now and don't have them with me.
They have not required any volume commitments from us, and have worked very
hard to make us happy. For example, one of the gate arrays we have received
from them is designed to do two functions. In one mode it will be used on
a new board in a 160 pin PQFP. In the other mode, it is designed to be a
drop-in replacement for an obsolete chip in a 168 pin CPGA.
We only want 100 of the CPGA parts, and told them that. It was still easier,
cheaper and less risky to have them produce 100 CPGA chips for us than to
do a new layout of our board for the PQFP part. They even found the same
package from the same vendor that the old chip came in.
Atmel has quality people that have done an excellent job on the work they have
done for us. They have a new fab and are adding capacity to it, so getting
chips from them has not been a problem. We are using them for a 250K gate
floating point FFT chip, and they have handled it very well. I do not know
how their cost for a conversion compare to Orbit and Chip Express, but I
would recomend letting them quote on your job. If you do, please let me know
how they compare.
We have been dealing with Bill Gross, who is one of their product marketing
managers. You can reach him at 719-540-1833, or bgross@atmel.com. Tell him
I recommended them to you, so he will know that we are pleased with their work.
John McCaskill
mccask@mccaskill.com
==================================================================================
Orbit Post 1
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We have just completed an FPGA conversion with Orbit Semiconductor. Since they
were mentioned, I thought I'd comment briefly. We used VHDL for design entry and
mapped a ~2K gate design operating at 2.3 MHz to an Altera FPGA using Synopsys
FPGA Compiler. (Yes, I know, not lightening speed or density.) After testing
this design in the FPGA, we sent Orbit the following information:
1. EDIF Netlist (Synopsys Output)
2. Print-on-change style simulations from Mentor Graphics Quicksim II
3. Desired Package/Pinout
4. Package Marking
Orbit successfully converted this design into their Encore! gate array process
with very little interaction from our engineering group. In fact, the level of
interaction required was so minimal it bothered us! They completed the conversion
and had working parts in our hands in about 8 weeks (just within the upper
variance of their commited design schedule). The parts performed 100% to
specification.
After meeting with their Engineering staff in Sunnyvale last month, I learned that
Orbit is much more successful with designs generated from a top-down, synochronous
design methodology (as most ASICs are developed), as opposed to schematic-based
FPGA designs which tend to be problematic.
Orbit's process technology is not the most advanced (1 micron I believe), but they
are VERY cost-effective. I would recommend them for small to medium size
(up to 45K gates) designs up to moderate speeds. They offer superior value,
particularly in low volumes. (We only needed around 2,000 parts, but couldn't use
an FPGA for production due to the board layout... we needed a drop-in
replacement for an obsolete part.) The nearest ASIC competitor quoted 2.5 times
the NRE for this design and wanted a guarantee of 6K parts! I highly recommend
Orbit Semiconductor for FPGA conversions... they are very experienced.
Hope others find this information useful...
Nelson W. Willhite
Nelson.Willhite@AtlantaGA.ATTGIS.COM
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Again, thanks to everyone who posted :)
---
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/ TED L. BOYDSTON IV \
+ Harris Corporation, GASD * PO Box 94000 * MS 102-4823 * Melbourne, FL 32902 +
\ Email: tboydsto@harris.com * Fax: (407) 729-2782 * Voice: (407) 729-7999 /
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Article: 2193William J. Wolf (wolf@aur.alcatel.com) wrote: : Why on earth would anyone want to hack a bit stream? : If you have a legit reason, try contacting Xilinx directly. : If not, spend your time on these alternatives: : Get a life. : Look for honest employment. : Community service, charity, etc. : More education so you can design yourself. : --- : - Bill Wolf, Raleigh NC : - My opinions, NOT my employer's Some people are interested in understanding how things work. Some other people don't want to spend thousands of $$$ to buy design tools for personal/hobbyist use. Most people don't take kindly to insults. Please remember that the next time you are considering responding to a posting. ---------------------------------------------------------------- Ewan D. Milne / Computervision Corporation (milne@petra.cv.com)Article: 2194
billms@gsfo.janet.ucla.edu (Bill Mangione-Smith) writes: >I'm working on an idea for late value binding which should prove trivial >with bit-stream modifications, but the application will not tolerate >running through the tool chain again. > >If Xilinx decides not to help me, then I've got to do it on my own, but its >all *my* design so I won't be upsetting myself. > >None of these features have anything to do with criminal activity, >and your presumption that they do is a bit niave and upsetting. Sorry that I missed the humor in your subject line and that I posted while I was still a presumptious grump Friday morning. For the record, I wish Xilinx would open their architecture also. But Xilinx's proprietary design belongs to them and they have the right to control it, regardless of what you or I may wish. If they choose to close their architecture, so be it. It seems to me that several constructive threads could take off from this point. These topics seem more interesting and up front to me than a thread on hacking bit streams. Someone please take them and start some new threads. And stop a war :) 1. An open-architecture FPGA. I am all for this. While I am not surprised Xilinx chooses to protect their architecture, I am a little surprised that some other vendor hasn't pushed an open architecture with partners to get a foothold in the business. Anyone remember when Sun came out of nowhere in the workstation business? There is a also a win-win-win situation between academic researchers, tool developers and companies with this business strategy. 2. Third party tool development. It would be nice if Xilinx, Altera, Actel, Quickturn, etc would post their policies toward third party tool development. Ie, do they actually help tool companies promote their architecture or are they so worried about hanging on to their crown jewels and/or their own CAE revenue that they won't even let third parties tackle businesses niches they are not pursuing? 3. Reconfigurable products. Again, Xilinx, Altera, Actel, Quickturn, I-Cube, etc could post what if anything they are doing to help people who are developing reconfigurable products and need to be able to program the parts directly. How open are they willing to be? What support do they provide? --- - Bill Wolf, Raleigh NC - My opinions, NOT my employer'sArticle: 2195
Stan Hodge wrote:
>
> Hi. I am currently evualuating a new FPGA technologies for our
> next generation product. I have looked at Xilinx and AT&T. The
> new Xilinx software seem a bit more polished and easer to use
> than the AT&T neo stuff. However, it seems that the part
> architecture from AT&T is much better.
Actually, Xilinx tools seems better only if you wish to use their
old parts: forget XC4000E series, or XC5200 series. Their
XACT 5.1.1 tools cannot merge a function generator with a flip-
flop in the same CLB!
The "neo stuff" you are refering to is NeoCad. AT&T use it.
Actually, it is so good that Xilinx bought NeoCad a couple of
months ago. Unfortunately, an despites of what Xilinx says, the
next version of XACT (6.0) won't be out until a year. If you're
ready to wait that long for good tools, choice is yours!
We too are in the decision phase: ATT or XILINX. I believe our
choice will end up with AT&T:
- Tools are very cheap for designs under 10k gates.
- A ATT2C06 is almost half the price of a XC4006, and it has
a lot more routing ressources, more RAM and more I/O pins.
- Altough it has it downsides, even the ATT1C05 seems almost
as good as a XC4005, yet one third of the price.
Patrick.
Article: 2196In article <472r2v$amu@aurns1.aur.alcatel.com>, William J. Wolf <wolf@aur.alcatel.com> wrote: > >For the record, I wish Xilinx would open their architecture also. >But Xilinx's proprietary design belongs to them and they have the >right to control it, regardless of what you or I may wish. If >they choose to close their architecture, so be it. It's quite possible to legally open a closed architecture if there are sufficient financial reasons to do so -- see the original IBM-PC clones or P5/P6 microprocessor clones, or from an earlier era, IBM mainframe, DEC VAX clones, and unlicensed 8-bit microprocessor clones. There are legal and illegal ways to go about reverse-engineering, for sure, but its quite possible in theory for someone to create software that inputs a Xilinx bit-stream and outputs a Viewlogic schematic without breaking U.S. laws during the creation of the software, if sufficient attention is paid to legal issues from the start. -- ------------------------------------------------------------------------------- John Lazzaro My Home Page: http://http.cs.berkeley.edu/~lazzaro lazzaro@cs.berkeley.edu Chipmunk CAD: http://www.pcmp.caltech.edu/chipmunk/ -------------------------------------------------------------------------------Article: 2197
Has anybody found a fix to get XACT 5.11 running under Win95? Xilinx aren't planning support 'til next April, and I haven't had any clues from their tech. support people.... Thanks in advance, AndyGArticle: 2198
In RAVIcad we specialize in:
a) PCI simulation models - Verilog & Vhdl source
includes model to drive the bus, monitor to decode and show what is
going on, and compliance check - to validate what goes on the bus
b) PCI Synthesizable cores - Verilog & Vhdl source
RTL synth sources tuned for different PCI applications - currently
available are: hostbridge, PCI2PCI, and PCI satellite (for peripherals)
We also have similar models for PCMCIA CardBus (PC Card), and also have
vendor certified models for SDRAM, SGRAM, RDRAM etc, ATM models etc + plus
many many more bus simulation models + cores.
Our basic approach is to sell you the PCI etc knowledge (in models and
cores) to hook your chips to the bus (& validate them) - we save you the
2-3 years of effort to understand the protocols and then design the h/w
interface.
Our PCI cores have been proven in silicon many times and several of our
customers' products are shipping in quantity.
For more info contact: sales@ravicad.com, or in US 1-800-RAVICAD
(tel 408 452 1600, fax 408 452 0952)
Regards,
Simon Davidmann
email: simond@ravicad.com
RAVIcad Inc. Wavertree House, 18 High Street,
Thame, Oxfordshire, OX9 2BZ, U.K.
Tel: +44 (0)1844 260058, Fax: +44 (0)1844 218804
In article <474u9j$ces@due.unit.no>, torela@idt.unit.no (Tore H.Larsen) wrote:
> In article <465mt8$igu@neptune.myri.com>,
> wen-king@myri.com (Wen-King Su) wrote:
> >In my current project I need to design a PCI interface using FPGA. I
> >have the official PCI spec book, but I need more information on the actual
> >implementations that are out there. For example, what is the maximum
> >"cache line size" that people actually use in their machine. It will
> >have an effect on how complicated the FPGA code will be. Do I need a
> >cache line size computation circuit on the whole 8 bits for the write
> >line and invalide operation? Also what is the maximum DMA throughput
> >between device and memory I can expect on a real system under each transfer
> >type. Any info or pointers to info will be appreciated. Thanks.
>
> You might be interested in xilinx own PCI-complient interface. The link is
>
> http://www.xilinx.com/products/appsweb.htm#PCI
>
> Sincerely,
> Tore
> torela@idt.unit.no
Article: 2199This is a multi-part message in MIME format. ---------------------------------1845971506643957635790599936 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii Hi Stan, being a Xilinx user I experienced routing problems with the 4025 while using the part in a rapid prototyping project. Having a very high connectivity in my design there was an upper bound of about 50% utilization, which is quite realistic with this part. The design needed intensive manual floorplanning. When timing is too tight the router will run forever while building subnets on large and slow nets to speed up signals, making the routing problem worse. It is no secret that Xilinx is aware of this problems. They claim that the new XC4000E series will overcome this problem, having more routing ressources while being pin compatible. I can't tell you if your design will fit in a 4013, which should'nt have that much routing problems. But this will depend on your design. Basically very regular designs will work fine with the Xilinx 4000 series. Regards ---------------------------------1845971506643957635790599936 Content-Transfer-Encoding: 7bit Content-Type: text/plain Christian Grebe Siemens Nixdorf Informationssysteme AG Line of Business High-Performance Printers ASIC's (HLD ST 35) Siemensallee 2 85586 Poing Germany Phone : +49 (8121) 72-4912 Fax : +49 (8121) 72-3173 EMail : grebe@sun2.zfe.siemens.de ---------------------------------1845971506643957635790599936--
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