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In article mq3@henge2.henge.com, David Mot <logdev@henge.com> () writes: >Low Cost Tool: >PLD Designe Language CUPL PALexpert $495.00 Simulation included ? What sort of chips ? Fax ? --- -------------------------------------------------------- Andreas Kugel Chair of Computer Science V Phone:(49)621-292-5755 University of Mannheim Fax:(49)621-292-5756 A5 D-68131 Mannheim Germany e-mail:kugel@mp-sun1.informatik.uni-mannheim.de --------------------------------------------------------Article: 2351
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---------------------FINAL CALL FOR PAPERS-----------------------
FOURTH International Symposium on
Signal Processing and its Applications
Royal Pines Resort, Gold Coast, Australia
26th-28th August 1996
ISSPA 96 is the fourth in a series of international symposia focussing
on the theory and applications of signal processing. It provides a
forum for engineers and scientists engaged in research and development
to discuss common and disparate objectives and applications of Signal
Processing. The symposium will run for three days from the 26th to
the 28th of August 1996. The conference will be followed by two
parallel two-day workshops on Robot Vision and Time-Frequency Signal
Analysis, following the format of previous ISSPA conferences. In
addition, tutorial sessions will be held on the 25th of August 1996.
Papers are invited in, but not limited to, the following topics:
1. Digital Filter Design & Structures
2. Multirate Filtering & Wavelets
3. Adaptive Signal Processing
4. Higher Order Spectrum Analysis
5. Radar & Sonar Signal Processing
6. Speech Processing & Recognition
7. Image and Multidimensional Signal Processing
8. Biomedical Signal Processing
9. Statistical Signal and Array Processing
10. VLSI for Signal Processing
11. Communications Signal Processing
12. Time-Frequency & Time-Scale Analysis
13. Neural Networks for Signal Processing
14. Industrial Signal Processing
15. Signal Processing Education
16. Other (Optical Signal Processing,
Aerospace Applications, Multimedia, etc)
Submissions should consist of three copies of a 400 to 500 word
summary including a short description of the problem and its
significance with references to previous work, plus the title,
authors' names, affiliations, addresses, topic category, telephone
and facsimile numbers, and e-mail addresses if available.
Submission implies a commitment to present the paper if accepted.
Prospective authors are encouraged to use the LaTeX style file
available for anonymous ftp on the host "www.bee.qut.edu.au" in the
file "/pub/sprc/isspa.sty". A full proceedings will be published,
which will be ready for distribution during the conference. Final
papers will be limited to six pages.
Send three (3) copies of the paper summary to:
ISSPA 96
Signal Processing Research Centre,
Queensland University of Technology,
2 George Street,
G.P.O. Box 2434, Brisbane, Qld, 4001, Australia.
Telephone: +61-7-3864-5351, Fax: +61-7-3864-1516
For more information, email "isspa96@qut.edu.au", or see the WWW
page at "http://www.eese.qut.edu.au/~sprc/isspa96.html".
Conference Schedule
-------------------
Paper proposal due: 15th January 1996
Notification of acceptance: 4th March 1996
Submission of photo-ready paper: 5th May 1996
Advanced registration before: 24th June 1996
Tutorials 25th August 1996
Conference Registration 26th-28th August 1996
Workshops 29th-30th August 1996
Steering Committee
------------------
B Boashash (Chair) Y Attikiouzel
Queensland Univ. of Technology University of Western Australia
b.boashash@qut.edu.au yianni@ee.uwa.edu.au
R R Bitmead R E Bogner
Australian National University} University of Adelaide
robert.bitmead@anu.edu.au bogner@eleceng.adelaide.edu.au
R J Evans G Poulton
University of Melbourne CSIRO, Division of Radiophysics
r.evans@mullian.ee.mu.oz.au gpoulton@rp.csiro.au
Technical Chair
---------------
A M Zoubir
Queensland Univ. of Technology
a.zoubir@qut.edu.au
Organisation Chair
------------------
N Harle
Queensland Univ. of Technology
n.harle@qut.edu.au
European Liaison
----------------
M Benidir
Laboratoire des Signaux et Systemes
Supelec, Plateau de Moulon
Gif-sur-Yvette, France 91190
benidir@lss.supelec.fr
U.S. Liaison
------------
A El-Jaroudi
Real-Time Signal Processing Lab
Department of Electrical Engineering
University of Pittsburgh
Pittsburgh, PA 15261, USA
amro@ee.pitt.edu
Asian Liaison
-------------
F Fukuda
Department of Micro Systems Engineering
Department of Mechano-Informatics and Systems
Nagoya University
Furo-cho Chikusa-ku
Nagoya 464-01 Japan
fukuda@mein.nagoya-u.ac.jp
Organisation Committee
----------------------
Finance: Registration:
V Chandran B Senadji
Queensland Univ. of Technology Queensland Univ. of Technology
v.chandran@qut.edu.au b.senadji@qut.edu.au
Exhibition: Publicity:
N Bergmann M Deriche
Queensland Univ. of Technology Queensland Univ. of Technology
n.bergmann@qut.edu.au m.deriche@qut.edu.au
Social Program: Local Arrangements:
W Boles G Roberts
Queensland Univ. of Technology Queensland Univ. of Technology
w.boles@qut.edu.au ga.roberts@qut.edu.au
Publications: Tutorials:
M Bennamoun S Sridharan
Queensland Univ. of Technology Queensland Univ. of Technology
m.bennamoun@qut.edu.au s.sridharan@qut.edu.au
Workshop:
M Bennamoun and N Harle
Queensland Univ. of Technology
m.bennamoun@qut.edu.au
n.harle@qut.edu.au
Technical Committee
-------------------
T Aboulnasr, University of Ottawa, Canada
M G Amin, Villanova University, USA
K Assaleh, Motorola, GSTG, USA
Y Attikiouzel, University of Western Australia, Australia
M M Bayoumi, Queens University, Canada
M Benidir, Laboratoire des Signaux et Systemes, France
R R Bitmead, Australian National University, Australia
B Boashash, Queensland University of Technology, Australia
J F Bohme, Ruhr University Bochum, Germany
R E Bogner, University of Adelaide, Australia
A Bouzerdoum, University of Adelaide, Australia
T Caelli, Curtin University of Technology, Australia
V Chandran, Queensland University of Technology, Australia
A G Constantinides, Imperial College of Science & Technology, UK
M Deriche, Queensland University of Technology, Australia
R Deriche, INRIA, France
T S Durrani, University of Strathclyde, UK
A El-Jaroudi, University of Pittsburgh, USA
R J Evans, University of Melbourne, Australia
F Faruqi, Queensland University of Technology, Australia
T Fukuda, Nagoya University, Japan
S Furui, NTT Human Interface Labs, Japan
F Ghorbel, Ecole Nouvelle d'Ingenieurs en Comunication, France
G B Giannakis, University of Virginia, USA
D A Gray, CRC for Sensor Signal & Info Processing, Australia
Y Hua, University of Melbourne, Australia
A K Jain, Michigan State University, USA
R A Jarvis, Monash University, Australia
G Jones, Raytheon Canada Limited, Canada
B H Juang, A T & T Bell Labs, USA
M Kaveh, University of Minnesota, USA
M A Lagunas, National Research Plan of Spain, Spain
A Leyman, Nanyang Technological University, Singapore
S K Mitra, University of California - Santa Barbara, USA
K Paliwal, Griffith University, Australia
G Poulton, CSIRO Division of Radiophysics, Australia
E Powers, The University of Texas at Austin, USA
B G Quinn, University of London, UK
S Sridharan, Queensland University of Technology, Australia
A Swami, Army Research Lab, USA
A H Tewfik, University of Minnesota, USA
D J Thomson, AT & T Bell Laboratories, USA
H T Tsui, The Chinese University of Hong Kong, Hong Kong
J K Tugnait, Auburn University, USA
Article: 2352>I have trouble installing XAct for Windows. The problem is that the dongle >can't be found by the software. Any idea?? In my office, the dongle can't be found by the USERS! In the last few years, 81% of the staff in my lab was laid off, and their corporate 'last remains' occupy 40 or so cardboard boxes. No dongle in there. Luckily, I only use the PC version for Xchecker, which doesn't require the dongle. I use the Sun version of the compilers, but I have a useless CD of the Windows software because upgrades assume that you haven't lost the dongle. -- +===============================================================+ + Joe Samson (313) 994-1200 x2878 + + Research Engineer, ERIM + + P.O. Box 134001 email samson@erim.org + + Ann Arbor, MI 48113-4001 + +===============================================================+Article: 2353
****** Most up-to-date on-line symposium program is available at ********* ****** http://www.cs.washington.edu/research/projects/lis/www/fpga96 ********* FPGA `96 Advance Program ------------------------ 1996 ACM/SIGDA Fourth International Symposium on Field-Programmable Gate Arrays February 11-13, 1996 Monterey Beach Hotel, Monterey, California, USA Sponsored by ACM SIGDA, and Xilinx, Inc., Altera Corp. and Actel Corp. Over the past ten years FPGAs have revolutionized the way many systems are designed by providing a low-cost, fast-turnaround implementation alternative. This is an exciting time in an exciting field that is still expanding as new technologies appear, new architectures are proposed, and new CAD tools are developed to address problems specific to FPGAs. This Symposium focuses on the architectural and algorithmic issues that FPGA architects and CAD designers face today and in the future. This is a forum where researchers from industry and university present and debate the latest ideas in FPGA design and application. The technical program consists of papers concerning both the practical and theoretical aspects of FPGA architecture, CAD algorithms for using and testing FPGAs, and applications. The Symposium will be of interest to those developing FPGA architectures, both at the chip and board level, and those developing CAD algorithms for FPGAs. The Symposium is not of direct interest to immediate users of FPGAs. General Chair: Jonathan Rose, University of Toronto Program Chair: Carl Ebeling, University of Washington Publicity Chair: Jason Cong, UCLA Local Chair: Pak Chan, UC Santa Cruz Finance Chair: Steve Trimberger, Xilinx Program Committee Michael Butts, Quickturn Pak K. Chan, UCSC Paul Chow, U. Toronto Jason Cong, UCLA Ewald Detjens, Mentor Carl Ebeling, U. Washington Gareth Jones, Pilkington Dwight Hill, Synopsys Brad Hutchings, BYU Sinan Kaptanoglu, Actel Jonathan Rose, U. Toronto Richard Rudell, Synopsys Rob Rutenbar, CMU Takayasu Sakurai, Toshiba Martine Schlag, UCSC Tim Southgate, Altera Steve Trimberger, Xilinx Nam-Sung Woo, ATT Program Sunday February 11, 1996 6:00pm Registration 7:00pm Welcoming Reception, Monterey Beach Hotel, Monterey Monday February 12, 1996 7:30am Continental Breakfast/Registration 8:20am Opening Remarks Session 1: Novel FPGA Architectures Chair: Jonathan Rose, University of Toronto 8:30am Hybrid FPGA Architecture, A. Kaviani and S. Brown, University of Toronto 8:50am Plasma: An FPGA for Million Gate Systems, V.R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider, L. Albertson, HP Labs 9:10am Flexible FPGA Architecture Realized of General Purpose Sea of Gates, K. Azegami, S. Kashi- wakura, K. Yamashita, Fujitsu Laboratories Posters: Novel FPGA Architectures 9:30-10:30am Coffee & Posters Session 2: Logic Module Design Chair: Richard Rudell, Synopsys 10:30am Using BDDs to Design ULMs for FPGAs, Z. Zilic and Z.G. Vranesic, University of Toronto 10:50am Series-Parallel Functions and FPGA Logic Module Design, S. Thakur, D.F. Wong, University of Texas, Austin 11:10am Combined Spectral Techniques for Boolean Matching, E. Schubert, W. Rosenstiel, University of Tuebingen Posters: Logic Module Design 11:30-12:00 LUNCH 12:00 - 1:30 Session 3: Performance Issues Chair: Steve Trimberger, Xilinx 1:30pm The Wave Pipeline Effect on LUT-Based FPGA Architectures, E.I. Boemo, S. Lopez-Buedo, J.M. Meneses, Universidad Politecnica de Madrid 1:50pm Timing Optimization for Hierarchical Field- Programmable Gate Arrays, V.C. Chan, D.M. Lewis, University of Toronto 2:10pm Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance, P. Pan, C.L. Liu, Clarkson University Posters: Performance Issues 2:30-3:30pm Coffee & Posters Session 4: Theoretical Issues in Routing Architectures Chair: Jason Cong, UCLA 3:30pm A Method for Generating Random Circuits and Its Application to Routability Measurement, J. Darnauer and W.W-M. Dai, University of California, Santa Cruz 3:50pm Entropy, Counting, and Programmable Interconnect, A. DeHon, MIT 4:10pm Universal Switch Modules for FPGA Design, Y-W. Chang, D.F. Wong, C.K. Wong, University of Texas, Austin Posters: Theoretical Issues in Routing Architectures 4:30-6:00pm Free time/Posters Dinner 6:00-7:30pm 7:30-9:00pm PANEL FPGAs vs. Gate Arrays and Processors: Who Will Win? The FPGA industry has enjoyed rapid growth in the past ten years in terms of chip density and speed as well as ASIC market share. In the same period, however, we have also observed significant advances in all sectors of the semi- conductor industry -- state-of-the-art gate arrays have a capacity of over 10 million transistors and enable the `system-on-a-chip'. Design automation tools have made semi-custom designs much faster and easier to achieve while yielding both high density and high performance. High-end microprocessors have reached over 250 Mhz and can satisfy the needs of many real-time control and DSP/multi-media applications. New rapid prototyping technologies, such as laser-programmed gate arrays, have emerged for high-speed high-density prototyping. Given such a dynamic industry undergoing exponential growth, it is interesting to ask where FPGAs will stand five or ten years from now in the wide spectrum of design technologies. Will its share of the ASIC market continue to increase, or will it become more of a niche technology? It is likely that the relative importance of these technologies will change drastically over the next five to ten years. This panel comprises technology experts in the competing areas of FPGAs, gate arrays, processors and other technologies. They will focus on the technological and economic issues that give one implementation medium an advantage over others and discuss how new technologies and architectural developments may change the competitive balance. They will discuss the past, present and future of the technological forces driving the industry and debate where those forces are likely to take us in the future. Tuesday February 13, 1996 Session 5a: Field-Programmable Analog Arrays Chair: Paul Chow, University of Toronto 8:30am Design and Implementation of a Field- Programmable Analogue Array, A. Bratt and I. Macbeth, Pilkington Microelectronics 8:50am The EPAC Architecture: An Expert Cell Approach to Field-Programmable Analog Arrays, H.W. Klein, IMP Posters: Field-Programmable Analog Arrays 9:10-9:40am Coffee & Posters Session 5b: Testing Chair: Martine Schlag, UC Santa Cruz 9:40am Diagnosing Programmable Interconnect Systems for FPGAs, D. Ashen and F. Lombardi, Texas A&M University 10:10am Evaluation of FPGA Resources for Built-In Self- Test of Programmable Logic Blocks, C. Stroud, P. Chen, S. Konala, M. Abramovici, University of Kentucky Posters: Testing 10:30-11:00am Coffee & Posters Session 6: The Future of Fuse and SRAM FPGA Technologies Chair: Tim Southgate, Altera 11:00am Two invited speakers will present the state of the art in (anti-)fuse and SRAM technologies and discuss the impact of recent developments in these technologies on future architectures. Posters: FPGA Vendors 11:40-12:00 LUNCH 12:00 - 1:30 Session 7: Applications Chair: Dwight Hill, Synopsys 1:30pm DPGA Utilization and Application, A. DeHon, MIT 1:50pm Integrating Software with Run-Time Re- configured Hardware, M.J. Wirthlin and B.L. Hutchings, Brigham Young University 2:10pm Computing the Discrete Fourier Transform on Virtual Systolic Arrays, C. Dick, La Trobe University Posters: Applications 2:30-3:30pm Coffee & Posters Session 8: Design Systems Chair: Pak Chan, UC Santa Cruz 3:30pm RASP: A General Logic Synthesis System for SRAM-based FPGAs, J. Cong and J. Peck, UCLA 3:50pm Emerald - An Architecture-Driven Tool Compiler for FPGAs, D. Cronquist and L. McMurchie, University of Washington 4:10pm Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs, A. Koch, Technical University, Braunschweig Posters: Design Systems 4:30-5:00 5:00pm Symposium Ends. Hotel Information ----------------- The Symposium will be held at the Monterey Beach Hotel, 2600 Sand Dunes Dr., Monterey, CA 93940, USA. The phone number for room reservations is 1-800-242-8627 or +1-408-394-3321 (Fax +1-408-393-1912). Reservations must be made before January 6, 1996. Identify yourself with the group Association for Computing Machinery FPGA `96 Symposium to receive the special Symposium rates, which are $75 for single or double Gardenview and $105 for single/double Oceanview. Parking is free. Check- in time 4pm. Directions to Hotel: From San Jose (a 1.5 hour trip) or San Francisco Airport (2.5 hrs) take HWY 101 South to HWY 156 West to HWY 1 South. On HWY 1 South, take Seaside/Del Rey Oaks exit. The hotel is at this exit, on the ocean side. You can also fly directly to the Monterey Airport, which is served by United, American and other airlines with at least 8 flights per day. FPGA `96 REGISTRATION --------------------- The Symposium registration fee includes a copy of the symposium proceedings, a reception on Sunday evening, February 11, coffee breaks, lunch on both days, and dinner Monday evening, February 12. First Name:___________________________________________ Last Name:____________________________________________ Company/Institution___________________________________ Address:______________________________________________ City:___________________State:________________________ Postal Code:_______________Country:____________________ Email:__________________________________________________ Phone:_______________________Fax:_______________________ ACM Member #____________ Circle Fee: Before January 25, 1996 After January 25, 1996 ACM/SIGDA Member US $320 US $390 *Non-Member US $420 US $490 Student US $90 US $90 (does not include reception or banquet, available for $20 and $35 respectively) *If you are not an ACM/SIGDA member we are giving you the opportunity to join by paying your first year's dues out of your conference non-member registration fee -- a US$100 value. Forms will be available at on-site registration. Guest Reception Tickets #Tickets______x US $20 ______ Guest Banquet Tickets #Tickets______x US $35 ______ Total Fees:____________________(Make checks payable to ACM/FPGA'96) Payment Form (Circle One): AMEX MASTERCARD VISA CHECK Credit Card#:____________________________________ Exp. Date:_______________________________________ Signature:_______________________________________ Send Registration with payment to: FPGA `96 - Colleen Matteis, 553 Monroe St., Santa Clara, CA. 95050, USA. Phone: +1(408)296-6883 Fax: +1(408)985-8274. For registration information contact Colleen Matteis, e-mail: sigda@nextwave.com, or cmatteis@aol.com. Cancellation must be in writing, and received by Colleen Matteis before January 24,1996.Article: 2354
"Steven K. Knapp, Xilinx, Inc." <stevek> wrote: >Tim Eccles <Tim@tile.demon.co.uk> wrote: >>But would it not be relatively straightforward for Xilinx to add a few bytes >>of non-volatile public key memory (read/write) plus private key memory (write >>only) and implement a small decryption engine. > It is possible, but >how much more would you be willing to pay for this capability. > Steve - You could always use KEPROM technology. -TBBArticle: 2355
sheynin@fp.co.nz (Oleg Sheynin) wrote:
>Can someone shed some light on the following question:
>
>What temperature/supply voltage conditions does the simulator
>simulate a design for? And,generally, what degree of confidence about
>the FPGA's functionality at various temperatures/supply voltages can
>a designer get by using the simulator (running the timing simulation
>on a "tied" .lca file)?
>
The Xilinx timing and simulation models are for:
Voltage: 5 volts +5% for commercial grade
5 volts +10% for industrial and military grade
Temperature: +85C junction temperature for commercial grade
+100C junction temperature for industrial grade
+125C case temperature for military grade
Output Loading: 50 pF
The models are worst-case. The only known discrepancies are in the
setup time to input flip-flops and clock-to-output timing from
output flip-flops. The simulator is overly pessimistic in some
cases. Xilinx specifies guaranteed pin-to-pin values for I/O setup,
hold, and clock-to-output times in our data sheets. These should
be used instead of the pessimistic simulation values. We are correcting
this problem in a future release of the software.
-- Steve Knapp
Xilinx, Inc.
Article: 2356In article <48qhl9$9tr$1@mhafm.production.compuserve.com>, 73317.771@CompuServe.COM says... (stuff deleted...) >2. Tribal Microsystems: FLEX-700B ($600) + PAC-DIP40 ($395) + CNV-PLCC-MPU51 >($145) = $1140. > >* PRO: looks flexable, 40 independant pin drivers in base unit, PAC units can >add more pin drivers. BBS updates for new parts. Vector testing. Supports new >low voltage parts I think. Technical people answer the phone and seem to >understand system very well. > >* CON: A little pricy. Maybe more than I need. > We have the FLEX-700 here (it's pretty much the same as the 700B, except that it has a special I/O card instead of a parallel port interface). I've been using it for almost 2 years now for PLDs, CPLDs, and micros and it's worked fine. I've talked to their tech support a couple of times and have downloaded a half dozen new device files from their BBS. I notice that you left out the Logical Devices series of programmers... Any reason in particular? I have a ChipMaster 3000 at home, and I feel like I've been "dead-ended" by Logical on this. I wanted support for the Atmel 89C2051. The response I got from the salesperson was that the ChipMaster 3000 was no longer supported (so much for lifetime -- I guess the product's lifetime -- S/W support by BBS). He then tried to give me a great "deal" on their "new" programmer if I traded in my ChipMaster 3000. No thanks... I was burned once, I'm not going to get burned again... If I had to do it over again, I'd buy the FLEX-700. --Jay ** MY OPINIONS ARE MINE ** not my employer's... -- Jay Francis -- jay@iai.mv.com "I bike therefore I am."Article: 2357
David Mot (logdev@henge.com) wrote: : Low Cost Tool: : Programmers/Universal Chipmaster 2000 $995.00 : PLD Designe Language CUPL PALexpert $495.00 : Call 800 315 7766 Unless yours has some additional modules or extras, CUPL PALexpert is $399.95 *new* from JDR...Article: 2358
In article <48tp3q$idi@newsbf02.news.aol.com>, KeilSoftW (keilsoftw@aol.com) writes: >Hiya > >We have the Needham programmer here. It seems to work OK here. It's what >we use for programming our 251SB parts. > >The only complaints I have are: 1) The software is a little clunky (it's >DOS based) but I'm not sure that is unlike the other products available on >the market. 2) The software doesn't work under Windows 95 (at least it >doesn't work HERE under Windows 95). 3) The wall transformer buzzes quite >loudly. Hmmm, Interesting, I run windows 95 and have the Needhams EMP20 that runs perfectly fine under Windows. Are you using the internal unit or an EMP20? If external, do you have a printer configured to use the same port? I have used the programmer for 8751, 8752, all type of Eproms, MACH parts and some gals so far. It works well. Same gripe though about not being a windows app. Ed SchramArticle: 2359
In article <48gqb9$26g@ixnews3.ix.netcom.com>, Frank Soehnge <fsoehnge@ix.netcom.com> wrote: >For the most part, our relationship with the device manufacturers is >pretty good. Most of them have various models of our programmers in >house and will verify that new devices that we support work like they >expect them to. Thats not to say that things don't go wrong from time >to time. I have had reports from customers that something wasn't >working correctly only to find that there was some subtle item in the >specs that I overlooked. Right; one of the tricky things with device programmers is figuring out how to code all the options a chip might have. I've seen many programmers, for example, which do not support the 8x51's useless "code encryption" array [no big loss since the security on that is nearly worthless, but it would be nice to have it supported]. > I don't think income from programmer sales is >really an issue for device manufacturers. It makes more sense for them >to make sure their products are supported on as many device programmers >as possible. Thanks for your response. I think the biggest concern manufaturers have is the possibility that some- one will program a part with a lousy programmer and then blaim the part manufacturer if the part is unreliable. Personally I like Microchip's "take" on this issue: they make it really easy to produce development programmers but explicitly state that for reliable operation certain extra steps [verify at Vmax and Vmin] are needed. My only complaint with their policy in this case is that they don't state what level of verification is needed if a part will only be used at, e.g., 5.00-5.05 volts. BTW, one problem I have with a lot of programmers is that manufacturers tend to bundle EVERYTHING of the programmer software into one file. This means that if I want to download the upgrate so I can program one new chip I have to download a HUGE file. It would be nicer in many ways if the devices could be divided up by category so as to allow a user to download only those files he needed. BTW, I use a BP programmer at work and I was wondering: [1] Is there any convenient way to wire a harness and use it for in-circuit programming PICs? [2] What testing does the programmer perform on PICs? Since programming uses only a subset of the pins on the device, does the BP do any testing on the other pins? It might be useful if BP supplied test code for different micros and test vectors so that the programmer could verify that the chips were fully operational [I've blown port bins on occasion] :-( -- ------------------------------------------------------------------------------- supercat@mcs.com | "Je crois que je ne vais jamais voir... | J\_/L John Payson | Un animal aussi beau qu'un chat." | ( o o )Article: 2360
Can someone shed some light on the following question: What temperature/supply voltage conditions does the simulator simulate a design for? And,generally, what degree of confidence about the FPGA's functionality at various temperatures/supply voltages can a designer get by using the simulator (running the timing simulation on a "tied" .lca file)?Article: 2361
I see that someone else has my problem. Due to the lack of finance I am only able to teach 20 on-campus students how to design using FPGAs. I need a sub-set of the Xilinx 2064 or 3020 so as to post them to hundreds of off-campus students who are using a 386 or better. Rowland Hill introduced the postage stamp so that the average person could afford to send letters. Look at the postal industry today. How about some cheap, student introductory versions able to be purchased with a text book similar to MicroLogic etc. -- Jack SANDELL TEL (61)(079) 309547 CENTRAL QUEENSLAND UNIVERSITY FAX (61)(079) 309382 ROCKHAMPTON QUEENSLAND, AUSTRALIA 4702Article: 2362
I am one of the founders of NeoCAD, and I am now at Xilinx. I would like to thank those who have had kind words for NeoCAD on this forum, and I want to clear up some misconceptions about AT&T and the Xilinx acquisition of NeoCAD. AT&T recruited the NeoCAD technical staff heavily, and wound up hiring only four engineers from NeoCAD. They are excellent engineers, wonderful people, and we miss them and wish them well. However, they do not comprise a "good chunk of the core development team." In fact, the entire technical management staff and all of the lead engineers are at Xilinx (about 30 NeoCAD engineers and engineering managers). We have also hired replacements for the people who left, and it so happens that they, too, are excellent engineers and wonderful people. The Xilinx and NeoCAD software groups have merged into one team, and we are hard at work combining the best technologies from both companies into a single product, including support for a variety of new FPGA families. ==eric Eric Dellinger Director, Strategic Software Technology Xilinx, Inc.Article: 2363
Somebody asked for XBLOX experiences last week. Here are mine: I'm a consultant / free lance designer and just completing a chip that barely fits into a 4010. It's a spread spectrum controller and its main ingredients are counters of all fla- vours. The Chip runs from a 40/20 MHz clock. This obviously calls for the use of XBLOX. There are about 40 XBLOX devices, including a few bus slices etc. that don't generate hardware. I made the following observations: I needed a clock divider by 20 million ( 20 MHz to 1 Hz ) with 1:1 duty cycle. Not much to it: Input pad -- clk_div -- output pad. XBLOX crashed the PC. Scared by my exaggerated expectations i then tried a divider by 2000. XBLOX survived the synthesis but the generated clk_div divided by something like 2800. Dividers by 200 and smaller seemed to work, as well as a divider by 10000. I cascaded several of them and played games with the count enable inputs, so i could still have everything synchronous with the global 20 MHz clock. This changed the timing, of course. I had to add pipeline stages in the surrounding circuit to make up for the extra delays. The complexity of the whole thing has increased from a single symbol to a sheet. Building it from msi-like macros would have probably been less mess, even without fast carry logic. The story is not at its end, however. Recently we decided that it would be a good idea to synchronize this divider with some other stuff. Looks simple. Isn't. The manual says: When the SYNC_CTRL input is high, the clock divider is reset to the beginning of the duty cycle. If i drive both EN and SYNC_CTRL high for one clock cycle, the divider happily keeps counting - and it shouldn't. I spent most of this day with XACT and a HP16500 to investigate what's going on and what hardware has been generated. I don't think it's my job to reverse engineer my own chips. I think it's a negative effect of systems like XBLOX that you are effectively locked into one single vendor. In addition you loose knowledge about the implementation of your design. You have to trust your tool vendor and cannot prove parts of your design. Throw lots of test vectors at the problem and your design will probably simulate ok; but can you choose the right vectors if you know nothing about the innards of the black box? I told our local XILINX representative ( Metronik) about the crash and the wrong divide ratios already half a year ago, when 5.1 came out. The FAE found it funny and remarkable. Maybe he relayed it to XILINX, but i never got any response at all. I didn't find them helpful with other problems, too. 4XMPL: The (now probably outdated) diskette installation software crashed when the video mode number was != 3 (on PC under MessDos). Was i really the first one to discover that a 20" monitor can display more than 25*80 chars? (I had Vmode=100, 40*100 with a nice font on most ET4000* cards) The current CD-rom installation program cannot find one of it's files if you have Microsoft share loaded. Given the time that i finally got my 5.1 CD-Rom (after complaining), a few hundred people with local networks must have already stumbled over this. Should everybody reinvent the wheel? I think that this newsgroup could be most valuable to publish such findings. Another thing: I once had a simulator named SILOS from Simucad ( with a quite offensive user interface). XILINX don't support it any more. The current version, SILOS III, seems to be pretty and accepts Verilog input, too. Does anybody know of a supplier of an XNF -> Verilog converter that runs on PC? Metronik proposed buying Cadence; (or VHDL would be even better). No thank you; it's my own money and i have esthetic problems with VHDL. And I watched others using it. A product for the opposite direction (Verilog -> XNF) would be interesting, too. Now, that the Pentium Pro is approaching it's probably a bad time to change to a workstation. Gerhard Hoffmann (who is surprisingly verbose today. A 118 lines post. Happens every other year.) -- # Gerhard Hoffmann # phone: +49 30 782 02 33 # # Gleditschstr. 79 # fax: +49 30 782 02 63 # # D10823 Berlin # on the air: dk4xp # # Germany # in the air: d-1441, d-kick #Article: 2364
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F P L '96
S I X T H I N T E R N A T I O N A L W O R K S H O P
FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
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_| September 23 - 25, 1996 (Monday - Wednesday) _|
_| _|
_| Darmstadt, Germany _|
_| _|
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C A L L F O R P A P E R S A N D P A R T I C I P A T I O N
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_| Paper Deadline March 6, 1996 _|
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PLEASE DISTRIBUTE THIS CALL TO ALL INTERESTED COLLEAGUES AND PEOPLE
ACCORDING TO YOUR MAILING LIST, THANKS IN ADVANCE!
AIM
The aim of this workshop is to bring together workers from throughout
the world for a wide ranging discussion of all forms of field
programmable logic (but particularly field programmable gate arrays)
and their applications. It is intended to discuss the increasing range
of device types, industrial applications, advanced CAD developments,
research applications, novel systems architectures and educational
experiences. The workshop will include regular presentations, posters
and discussion sessions and it is expected that most of the delegates
will wish to make some contribution to one or more of these. The
workshop is to be considered as continuation of four already heldSE
international workshops in Oxford (1991 and 1993), Vienna (1992) and
Prague (1994).
CALL FOR CONTRIBUTIONS
Contributions are invited for regular presentation, poster and
discussion sessions. Prospective authors are invited to submit an
abstract of at least 500 words or a full paper by 6 March 1996 to the
Program Chairman. Please preface this by your full correspondence
address, including e-mail, and fax, a list of (at most) 5 one-line
statements that best encapsulate the essence of your proposed
contribution, and a note of your preferred presentation format. Please
mail 10 copies if possible, but submissions by e-mail
(abakus@informatik.uni-kl.de) or fax (+49 631 205-2640) will also be
accepted.
NOTIFICATION OF ACCEPTANCE will be posted by 8 May 1996 and final
papers must be received by 3 July 1996 to guarantee distribution at
the workshop. Accepted papers will be published in book form by
Springer before the workshop. Potential exhibitors and tutorial
presenters are also invited to contact the Program Chairman. The
official conference language as well as the language of submissions
and accepted papers will be English.
SCOPE
Field Programmable Logic has been available for a number of years, but
the increasing power and variety of devices now available is extending
its role from that of simply being a convenient way of implementing
the system glue logic to an increasing ability to implement mainstream
system functions. The speed with which devices can be programmed makes
them ideal for prototyping and education, the reprogrammable devices
are opening up sophisticated new applications and hardware/software
trade-offs. CAD is developed for automatic compilation of advanced
designs and routes to custom circuits are now available.
WORKSHOP TOPICS:
The topics should cover, but are not restricted to:
- New and future commercial devices
- Novel chip architectures
- New software and hardware development tools
- Bridges to other CAD and to custom circuits
- High-level design and compilation research
- Industrial applications and experiences
- Trade-offs betweendevices, architectures and technologies;
Benchmark comparisons
- Smartapplications
- Custom computers
- Hardware/Software Co-Designusing FPL
- Novel machine paradigms and system architectures
- ASIC emulators, hardware modellers and compiled accelerators
- Fault models, testability methods, reliability
- Educationalexperiences and opportunities
GENERAL CHAIRMAN:
Prof. Manfred Glesner
Darmstadt University of Technology
Karlstrasse 15
D-64283 Darmstadt
Germany
Phone: +49 6151 16-5136
Fax: +49 6151 16-4936
email: glesner@microelectronic.e-technik.th-darmstadt.de
PROGRAM CHAIRMAN:
Prof. Reiner W. Hartenstein
University of Kaiserslautern
P. O. Box 3049
D-67653 Kaiserslautern
Germany
Phone: +49 631 205-2606
Fax: +49 631 205-2640
email: hartenst@rhrk.uni-kl.de
PROGRAM COMMITTEE: Jeffrey Arnold, IDA CCS, USA
Peter Athanas, Virginia Tech, USA
Gaetano Borriello, U. of Washington, USA
Stephen Brown, U. of Toronto, CA
Klaus Buchenrieder, Siemens AG, FRG
Bernard Courtois, INPG, Grenoble, France
Keith Dimond, U. of Kent, UK
Patrick Foulk, Heriot-Watt U., UK
Norbert Fristacky, Slovak Technical U., SK
Manfred Glesner, TH Darmstadt, FRG
Daniel Gajski, UC Irvine, USA
John Gray, Xilinx, UK
Herbert Gruenbacher, Vienna U., Austria
Reiner Hartenstein, U. of Kaiserslautern, FRG
Udo Kebschull, U. of Tuebingen, FRG
Andres Keevallik, Tallinn Technical U., Estonia
Chong-Min Kyung, KAIST-Inst. of Techn., South Korea
Wayne Luk, Imperial College, UK
Patrick Lysaght, U. of Strathclyde, Scotland
Will Moore, Oxford U., UK
Klaus Mueller-Glaser, U. Karlsruhe, FRG
Wolfgang Nebel, U. of Oldenburg, FRG
Peter Noakes, U. of Essex, UK
Franco Pirri, U. of Firenze, Italy
Jonathan Rose, U. of Toronto, Canada
Zoran Salcic, U. of Auckland, New Zealand
Mariagiovanna Sami, Politechnico di Milano, Italy
Alberto Sangiovanni-Vincentelli, UC Berkeley, USA
Michal Servit, Czech T. U., Czech Republic
Mike Smith, U. of Hawaii, USA
Steve Trimberger, Xilinx, USA
LOCAL DETAILS
The workshop will be held at the Orangerie in Darmstadt, on 23rd -
25th September 1996. The Orangerie is an attractive old palace, which
contains rooms for congresses. A bus ticket for reaching the Orangerie
during the workshop is included in the registration fee. Darmstadt,
which is situated in the Rhein-Main-Area nearby Frankfurt, Wiesbaden,
Mainz and Heidelberg, has numerous cultural and tourist attractions as
well as plenty to interest accompanying partners. There are fast
connections to Frankfurt International Airport. All the latest
information about FPL'96 can be accessed via a WWW-page. The URL for
this document is:
http://www.microelectronic.e-technik.th-darmstadt.de/fpl96/fpl96.html
REPLY FORM FOR REGISTRATION FORM
We encourage you to reply via e-mail, giving us the information listed
below. If you do not have the possibility to use e-mail, please copy
the form below and send or fax it in advance to the General Chairman.
-------------------- FPL `96 - REGISTRATION FORM --------------------
Name: .........................................................
(Family Name) (First and Middle)
Affiliation:.........................................................
Address: .........................................................
.........................................................
Country: .........................................................
Phone: .........................................................
Fax: .........................................................
E-mail: .........................................................
Registration fees *)
_
| | Normal fee DM 490
- Includes attendance to all sessions, social program,
banquet, workshop proceedings and bus ticket.
_
| | Student fee DM 250
- Includes attendance to all sessions and bus ticket.
_
| | Spouse / Partner fee DM 200
- Includes social program, banquet and bus ticket.
TOTAL AMOUNT: DM ....
Payment should be made in advance, in DM. Please select method of
payment:
_
| | Transfer to our bank account
- Darmstaedter Volksbank e. G. (BLZ: 50890000)
Account No.: 1218611 (recipient: Prof. Manfred Glesner)
Please specify: "FPL'96 & delegate name"
_
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Please specify: "FPL'96 & delegate name"
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| | Credit Card: (check one)
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| | VISA | | EUROCARD / MASTERCARD
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CREDIT CARD ONLY:
Credit card number:..................................................
Name of holder: ..................................................
Expiration date: ..................................................
Signature of holder:.................................................
*) IMPORTANT: Any bank charges must be paid by the sender.The amount
arriving at our bank must not be less than the registration fee.
Please take care that any banking fees are settled.
Date and Signature:..................................................
---------------------------- End of form ----------------------------
----------------- FPL `96 - Hotel Reservation Form ------------------
*** DEADLINE: August 23rd, 1996 ***
Name: .........................................................
(Family Name) (First and Middle)
Affiliation:.........................................................
Address: .........................................................
.........................................................
Country: .........................................................
Phone: .........................................................
Fax: .........................................................
TYPE OF ROOM:
_
| | single room
-
_
| | single room
-
_
| | single room
-
PREFERED CATEGORY:
_
| | category I about DM 210
-
_
| | category II about DM 130
-
_
| | category III about DM 90
-
Prices are per person and night.
(You will be informed about single / double room conditions)
Check in date: ......................................................
Check out date:......................................................
Arrival time: ......................................................
_ _
Arrival by: | | train | | car
- -
..................... .........................................
(Date) (Stamp and Signature)
---------------------------- End of form ----------------------------
Please send or fax Hotel Reservation Form in advance
(until August 23rd 1996) to:
Magistrat der Stadt Darmstadt
Verkehrsamt
z.Hd. Frau Neubauer
Luisenplatz 5
D-64283 Darmstadt
Germany
Hotel accomodation is merely found for you. Therefore, we do not take
any responsibility.
Verkehrsamt der Stadt Darmstadt
Tourist-Information
am Hauptbahnhof
Tel.: (+49) 6151 - 13 27 82
Fax: (+49) 6151 - 13 27 83
Article: 2365
In article <DICyDw.6vB@tr.unisys.com>, peb@trsvr.tr.unisys.com (Pete Becker) wrote:
>
>What software is available on the PC platform for FPGA synthesis from VHDL?
>What would you say about performance-cost curve?
>
>
>===================================================
>Disclaimer: My comments and questions are composed
>of opinions that may or may not be my employer's,
>mine, or anyone else's.
>---------------------------------------------------
> Peter Becker o o \ /
> peb@trsvr.tr.unisys.com -|- -/\ _o | ?
> pbecker@netaxs.com (home) / \ |\ /\\ /o\ o_/_/
>===================================================
Take a look at Exemplar. They have platforms that run on PC (as well as UNIX).
Depending on the particular FPGA technology your targeting, they support various vendors
with specific optimization algorithm's (and they support most of the popular FPGA/CPLD
vendors ie: Xilinx, AT&T, Altera ... etc.).
Regards,
Wayne Hammerschlag
schlag@servtech.com
schlag@io.org
Article: 2366
>>>>> "Steven" == Steven K Knapp, Xilinx, Inc <stevek> writes:
Steven> The bigger problem happens during manufacturing. Any
Steven> non-volatile bits require a deviation from standard CMOS
Steven> technology. Even a few bits of non- volatile storage can
Steven> add signficantly to the device cost. It is possible, but
Steven> how much more would you be willing to pay for this
Steven> capability.
No it does not. That is if you don't care about how big these cells
are and how long they take to program. If you really need just a few
bits (the suggested public key memory would need a few hundred), it is
possible to come up with an EPROM or even EEPROM cell in standard
CMOS.
--
Achim Gratz
-+==##{([***Murphy is always right***])}##==+-
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 4575 - 325
Article: 2367In article <48refa$799@sifon.cc.mcgill.ca> Comp Arch Lab Group #6 <comarch6> writes: >Hi, > >We're trying to implement 52 bytes of byte-addressable RAM >on a Xilinx 4000. We pulled the VHDL source for a register file from >Mentor graphic's Design Architect. Unfortunately, it was mostly >behaviourally described. Synthesis using Autologic took 3 hrs... >Place and route using Xact's Xmake resulted in 300% using of the CLB's function >generators and NONE of the flip-flops. > >Obviously a low-level structural description is in order, but we're not sure >what an efficient implementation would be. What you really want to do is check out the on-chip Xilinx RAM. We have a technical report on this and other synthesis issues at http://www.vlsivie.tuwien.ac.at/mike/vhdl4fpga ftp://ftp.vlsivie.tuwien.ac.at/pub/vhdl4fpga/tr.ps Hope this helps, m. -- Michael Gschwind, Institut f. Technische Informatik, TU Wien snail: Treitlstraße 3-182-2 || A-1040 Wien || Austria email: mike@vlsivie.tuwien.ac.at PGP key available via www (or email) www : URL:http://www.vlsivie.tuwien.ac.at/mike/mike.html phone: +(43)(1)58801 8156 fax: +(43)(1)586 9697 Multiculturalism is the concept that European cultures should be flexible enough to accommodate the inflexibility of all others.Article: 2368
None of these so called simulators come close to what is reality unless the circuit under test is put into a cold chamber where you can control the temperature to few tenth of a degree!!Article: 2369
shouldn't that be 5V MINUS 5 or 10 percent? -- Andrew M. Dyer | "All that's left of me is slight insanity, adyer@mcs.com | what's on the right I don't know" adyer@zarniwoop.chi.il.us (home) | -- Bob Mould "Hoover Dam"Article: 2370
Here is a Xilinx XNF netlister which we use to extract netlists from NTK files as generated by diglog (Chipmunk). ftp://ftp.cs.indiana.edu/pub/goo/Chipmunk/netgen.tar.Z I also included some sample designs that run on the Xilinx 3K/4K demo board. ftp://ftp.cs.indiana.edu/pub/goo/Chipmunk/Demo.tar.Z You will still need to have access to the Xilinx core FPGA tools. The entry level pacakage of just the core tools which can target the smaller Xilinx chips (up to 3042 and 4003) is available for $1000 from several chip suppliers. Chipmunk and this pacakage is probably the cheapest way to thet into Xilinx FPGAs. See ya, -ingo -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */Article: 2371
In article <48rufk$m55@henge2.henge.com>, David Mot <logdev@henge.com> wrote:
> Logical Device Inc. Offers Low Cost Universal Programmer Chipmaster 3000.
> The cost is $995.00, however you may get a refurbished one for $495.00.
> This will also include the CUPL PALexpert regularly going for $495.00
> The combination offers an excellent development environment for PLDs
> Call Logical Devices at 1 800 315 7766 and ask for Jeff Williams
David,
Why was I told by Logical Device's sales department that the Chipmaster 3000
is no longer being supported??? (That was the reason I was given for Logical
Device's lack of ATMEL 89C2051 support).
--Jay
Article: 2372
In article <jfrancis-2411951143140001@jfrancis.tiac.net>,
jfrancis@tiac.net (Jay Francis) wrote:
> Why was I told by Logical Device's sales department that the Chipmaster 3000
> is no longer being supported??? (That was the reason I was given for Logical
> Device's lack of ATMEL 89C2051 support).
Ok, I'll respond to my own post here... It seems that the CM3000 is still
supported (why was I told 6 months ago that is wasn't??? and that I should
trade in my CM3000 towards a new programmer??? -- actually -- I was FAXED
this information, so at least I know I'm wasn't hearing things...), and
that they now
have 89C2051 support.
--Jay
Article: 2373
In article <48vk86$lcj@mailman.xilinx> "Steven K. Knapp, Xilinx, Inc." <stevek> writes:
>The Xilinx timing and simulation models are for:
>Voltage: 5 volts +5% for commercial grade
> 5 volts +10% for industrial and military grade
>Temperature: +85C junction temperature for commercial grade
> +100C junction temperature for industrial grade
> +125C case temperature for military grade
>Output Loading: 50 pF
>The models are worst-case.
I always assumed that the longest net delays ("worst-case") are exhibited at
highest temperature and _lowest_ supply voltage (not the highest one). Was I
wrong in that?
Article: 2374I placed the instructions and a basic program to program the Atmel 17Cxxx FPGA Configuration EEPROMs on a PC parallel port in our ftp archive: ftp://ftp.cs.indiana.edu://pub/goo/eeprg.zip It's pretty straight forward and we have used it to program config. proms for Xilinx chips on one of our robots... Enjoy, -ingo -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */
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