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Another vendor of PC based verilog is Frontline (408-456-0222). There verilog implimentation is the best I've seen (as of a year ago). Understand they now have a compiled verilog version. Bob Hoffman || Any opinions expressed above are purely accidental || bobh@galaxy.nsc.com || and certainly don't have my employers consent! ||Article: 2326
Erik Jessen <ejessen@ix.netcom.com> wrote:
>As a practical matter, if you want to keep someone from copying your design,
>simply design it so that you can't debug it yourself - put in lots of async.
>logic, race conditions, etc. And then lay it out so that the timing is right
>on the edge. If you're really careful, build up some RC circuits using normal
>routing - if someone else' process has different parameters, the circuit will
>fail erratically (or, even better, just corrupt the data, like toggling the
>parity bit and one other bit).
Erik, on this one I must STRONGLY DISAGREE!!! The way I make my $$$ is by doing
Verilog/VHDL/synthesis/Design-For-Test training and doing crisis intervention
on projects in trouble. This philosophy you outline, although it may make the
design hard to reverse-engineer, also has the very nasty side effect of very
possibly making the design unbuildable by the original design team! And, if it
is buildable, you'll probably get erratic or low yields. The other side effect
is that it locks you into that one foundry who *can* build your "funky" IC.
(What happens if the foundry loses its process [as does happen from time to
time] or that they decide to serve another customer with a bigger order leaving
you to shop for another foundry?)
Overall, I think this is a DANGEROUS design philosophy being advocated here.
(Wait a minute! If more design groups do this, it means I'll get more
customers for my Crisis Intervention practice...)
On the other hand, I think it's a GREAT idea to design with lots of race
conditions, asynchronous logic, bizarre RC circuits, and funny, illogical
layout! More designers SHOULD think this way!!!! Have a nice day. :^)
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 2327
Hi All:
I am looking for a "good" device programmer. I want one that connects to a PC
parallel port, not serial or custom card. I would like to spend less than $1K.
I would like software updates to support new parts via BBS (or ftp etc). I
would like a company with good long term support. I need to program EProms
27512's some pal/gals, 8742's, 8752's and now INTEL's 87C251SB processor.
Though my currents needs are modest, I do not want to get "dead ended" again.
Naturally the reason I am looking now is that my current programmer doesn't
support the '251 and is no longer supported by the mfg. What programmers do
you use / like, why? Can you recommend a good source of comparison data? I
have found information on the following company products and would like any
feedback or suggestions you can offer, etc.
1. ADVIN: Pilot-U40 $1995 + adaptors = too much $
pro: individual software programmable pin drivers for each pin
con: too expensive
2. Tribal Microsystems: FLEX-700B ($600) + PAC-DIP40 ($395) + CNV-PLCC-MPU51
($145) = $1140.
* PRO: looks flexable, 40 independant pin drivers in base unit, PAC units can
add more pin drivers. BBS updates for new parts. Vector testing. Supports new
low voltage parts I think. Technical people answer the phone and seem to
understand system very well.
* CON: A little pricy. Maybe more than I need.
3. Needhams Electronics: EMP-20 ($449.95) + F44[44 pin PLCC w/ family module
07] ($105) = $554.95.
* PRO: seem to fill current needs. BBS updates. Technical people on phone.
Good price.
* CON: Less flexible than FLEX-700?
4. EETools: PRO MAX ($445) + family module 07 ($25) + F44 ($125) = $595.
* PRO: See above Needhams EMP-20, seems to be same unit.
<
* CON: See above, also not orig mfg, less understanding, further from source.
5. BP: 1200 series about $2500 too expensive.
Thanks, Cla.
Article: 2328What software is available on the PC platform for FPGA synthesis from VHDL? What would you say about performance-cost curve? =================================================== Disclaimer: My comments and questions are composed of opinions that may or may not be my employer's, mine, or anyone else's. --------------------------------------------------- Peter Becker o o \ / peb@trsvr.tr.unisys.com -|- -/\ _o | ? pbecker@netaxs.com (home) / \ |\ /\\ /o\ o_/_/ ===================================================Article: 2329
In article <DICsBy.CGE@world.std.com>, jcooley@world.std.com (John Cooley) wrote: > >Erik, on this one I must STRONGLY DISAGREE!!! The way I make my $$$ is by doing >Verilog/VHDL/synthesis/Design-For-Test training and doing crisis intervention >on projects in trouble. This philosophy you outline, although it may make the >design hard to reverse-engineer, also has the very nasty side effect of very >possibly making the design unbuildable by the original design team! And, if it >is buildable, you'll probably get erratic or low yields. The other side effect >is that it locks you into that one foundry who *can* build your "funky" IC. >(What happens if the foundry loses its process [as does happen from time to >time] or that they decide to serve another customer with a bigger order leaving >you to shop for another foundry?) > >Overall, I think this is a DANGEROUS design philosophy being advocated here. > > (Wait a minute! If more design groups do this, it means I'll get more > customers for my Crisis Intervention practice...) > > Sigh! John, I guess most people missed my emoticon; I was trying to be sarcastic about the whole thing. I've worked on a lot of full-custom, async. designs, where the original builder had left the company, and no-one wanted to touch the circuit, because they couldn't tell what the *** it did! I kept trying to push for simple replacement by a std-cell, synchronous design (which would actually have been smaller than the full-custom, because the full-custom was in an old process). Every manager agreed that that was the right idea, but they couldn't back it politically, because they'd sold upper management on the high costs of full-custom design, by saying that you got really cheap chips. Imagine walking in to upper management 2 years later, and saying that std-cell was cheaper than full custom! We also did use dummy gates, because some of our chips had been reverse engineered. I thought those were more pain than they were worth (I couldn't see them stopping anyone, and they sure were a pain to work around). But, it was company policy. As I said in an earlier post, to me time-to-market, and time-to-revision are everything; that means a well-documented design, well-tested methodology, and designing in a really clean, synchronous style. I'm pretty much known for pushing hard on these topics. There are times when async. is the only way to get done what you need, but it's not all that often (at least, in the ASICs I've worked on). I'll try and make my sarcasm more blatant next time... Erik ps: John, here I am, trying to generate business for you, and you put me down! ;) ;) ;) Erik Jessen Com-Solutions, Inc. (619) 942-9790 The views expressed here are purely my own.Article: 2330
In article <199511182115.QAA00630@jaws.cs.indiana.edu>, "Ingo Cyliax" <cyliax@cs.indiana.edu> wrote: Ingo, Please put your stuff somewhere out with other Linux stuff; the more Linux tools available, the better! Erik Erik Jessen Com-Solutions, Inc. (619) 942-9790 The views expressed here are purely my own.Article: 2331
jcooley@world.std.com (John Cooley) wrote: > > Erik Jessen <ejessen@ix.netcom.com> wrote: > >As a practical matter, if you want to keep someone from copying your design, > >simply design it so that you can't debug it yourself - put in lots of async. > >logic, race conditions, etc. And then lay it out so that the timing is right > >on the edge. If you're really careful, build up some RC circuits using normal > >routing - if someone else' process has different parameters, the circuit will > >fail erratically (or, even better, just corrupt the data, like toggling the > >parity bit and one other bit). > <stuff snipped> > On the other hand, I think it's a GREAT idea to design with lots of race > conditions, asynchronous logic, bizarre RC circuits, and funny, illogical > layout! More designers SHOULD think this way!!!! Have a nice day. :^) > John, I'll second that. The more people who do this, the more $ I'll make fixing their designs that suddenly don't work halfway through production! I like those jobs, since they usually pay real well! -Ray Andraka Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 email randraka@ids.net The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure.Article: 2332
0896892083-0003@t-online.de (Jan Kubuschok) writes: >Hi! >I have trouble installing XAct for Windows. The problem is that the dongle >can't be found by the software. Any idea?? >The printerport works fine with an HP-Laserjet. >It's onboard a ASUS PT55XE with 32MB RAM and an 133mhz CPU. >Hope on help. >Jan. I just love dongle protected software. If memory serves, you have to have a special file containing the dongle's code number on your hard disk in one of the XACT subdirectories. This magic file should have come with your XACT software. I went thru this pain about 4 months ago when I had to get XACT running on out systems. Call up the XACT support line and give them a hard time about a $10000 package that doesn't run.Article: 2333
Hi, We're trying to implement 52 bytes of byte-addressable RAM on a Xilinx 4000. We pulled the VHDL source for a register file from Mentor graphic's Design Architect. Unfortunately, it was mostly behaviourally described. Synthesis using Autologic took 3 hrs... Place and route using Xact's Xmake resulted in 300% using of the CLB's function generators and NONE of the flip-flops. Obviously a low-level structural description is in order, but we're not sure what an efficient implementation would be. We looked at the application note XAPP 031.000 in the Xilinx data book which discusses configuring CLB look-up tables as user RAM, but not at the VHDL level. Any help would be greatly appreciated. please e-mail to comarch6@ee.mcgill.ca Barnaby ChanArticle: 2334
In article <DICFy3.CpD@tr.unisys.com>, Pete Becker writes: > WARP2 (VHDL) from Cypress is $99. It is Cypress specific, but it's cheap. I > don't know much about the performance, though. Unfortunately, being Cypress specific is a problem, more than is obvious. The chips are not readily available in small quantities. Relying exclusively on samples for my prototypes makes it rather uneasy. Cypress chips are not well supported by device programmers. The last I checked, the DataIO Chiplab48 was the only option at least among approachable device programmers. ---- If reply fails due to uunet botching DNS again, try eric@wolf359.us.com Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 2335
john,
You are totaly corect for an up-to date HDL code. Whats about 3 years
old code or something like that.
I face the same problems, with managers and engineers, when asking for
design rules for logic chip designer. Although its not so secret, they
will not give it for a million.
regards, yehuda
--
o \ o / __o __| \/ |__ o__ \ o / o
/|\ | /| __\o \o | o/ o/__ |\ | /|\
/ \ / \ |\ /) | ( \ /o\ / ) | (\ / \ / \ / \
======================================================================
Yehuda D. Yizraeli
Tel: 972-4855-0011 Ext. 132 {Callers outside Israel}
Tel: 04- 855-0011 Ext. 132 {Callers within Israel}
Fax: 972-4855-1122
E-mail: yehuda@chipx.co.il
Article: 2336Regarding CUPL comments from Mr. David Decker , Currently there are 25000 CUPL users. Extensive usage of CUPL with Xilinx FPGAs in many companies and universities all over the world. No one product however will satisfy all needs. There are over 350,000 digital design engineers world wide and each will find a clever way to use PLDs and FPGAs. Last customer was attempting to use CUPL to create an oscillator using a 22V10!!! The comments from Mr. Decker can be true however may be specific to his very special design. Some of the comments also relate to the XNF optimizer created by Xilinx, and supplied by CUPL. Regarding persistant outputs Abel does not provide this either. This is not a design feature that is advisable to use as it may leave room for design errors. So far Mr. Decker is the only customer insisting to have this feature. CUPL is available on a trial basis FREE of charge for 30 days. If anyone is considering Xilinx design, they can get this package from Logical Devices directly at 1 800 315 7766/ 303 279 6868 ( Jeff Williams). Currently work is on the way to add new FPGA support feature on CUPL such as timing simulation, graphical state diagram, and more extensive FPGA syntax and state machine capability. CUPL is growing rapidly as one the best supported and well accepted logic design languages in the world.Article: 2337
Regarding CUPL comments from Mr. David Decker , Currently there are 25000 CUPL users. Extensive usage of CUPL with Xilinx FPGAs in many companies and universities all over the world. No one product however will satisfy all needs. There are over 350,000 digital design engineers world wide and each will find a clever way to use PLDs and FPGAs. Last customer was attempting to use CUPL to create an oscillator using a 22V10!!! The comments from Mr. Decker can be true however may be specific to his very special design. Some of the comments also relate to the XNF optimizer created by Xilinx, and supplied by CUPL. Regarding persistant outputs Abel does not provide this either. This is not a design feature that is advisable to use as it may leave room for design errors. So far Mr. Decker is the only customer insisting to have this feature. CUPL is available on a trial basis FREE of charge for 30 days. If anyone is considering Xilinx design, they can get this package from Logical Devices directly at 1 800 315 7766/ 303 279 6868 ( Jeff Williams). Currently work is on the way to add new FPGA support feature on CUPL such as timing simulation, graphical state diagram, and more extensive FPGA syntax and state machine capability. CUPL is growing rapidly as one the best supported and well accepted logic design languages in the world.Article: 2338
Logical Device Inc. Offers Low Cost Universal Programmer Chipmaster 3000. The cost is $995.00, however you may get a refurbished one for $495.00. This will also include the CUPL PALexpert regularly going for $495.00 The combination offers an excellent development environment for PLDs Call Logical Devices at 1 800 315 7766 and ask for Jeff WilliamsArticle: 2339
testArticle: 2340
Jeff Williams: Peb@trsvr.tr.unisys.com is interested in low cost programmerArticle: 2341
Jeff Williams: Peb@trsvr.tr.unisys.com is interested in low cost programmerArticle: 2342
Low Cost Tool: Programmers/Universal Chipmaster 2000 $995.00 PLD Designe Language CUPL PALexpert $495.00 Call 800 315 7766Article: 2343
Is there a simple way to take a XILINX netlist and convert it into a Mentor format? Dick -- Dick Gray gray@diasemi.co.uk _/_/_/ _/_/_/ _/ _/_/ _/_/ Dialog Semiconductor _/ _/ _/ _/ _/ _/ _/ _/ _/ Mixed-Signal Asics for All _/ _/ _/ _/_/_/_/ _/ _/ _/ _/ _/_/ tel: (+44) 1793 875327 _/_/_/ _/ _/ _/ _/_/_/ _/_/ _/_/Article: 2344
jcooley@world.std.com (John Cooley) wrote:
><msgid@msg.ti.com> wrote:
>>Can any one reccomend Verilog for a PC platform? (Pentium)
>interHDL Inc <eli@netcom.com> wrote:
>>Viper from interHDL. Contact info@interhdl.com or call (415) 428-4200
>Other than Eli promoting his own company for Verilog (I can't blame a guy
>for trying!) you may also want to check out: Model Tech at (503) 641-1340;
>Chronologic/ViewLogic at (800) VERILOG; Simucad at (415) 487-9700; and
>Wellspring Solutions at "elliot@wellspring.com". (These are the names
>that quickly come to mind; you may want to call the Open Verilog
>International office at (408) 353-8899 or e-mail "georgia@netcom.com"
>for a complete list of PC and UNIX Verilog vending companies.)
> - John Cooley
> Part Time EDA Consumer Advocate
> Full Time ASIC, FPGA & EDA Design Consultant
Another possibility, if it meets your requirements, is the QuickWorks
tool set from QuickLogic (408-987-2000). This s/w is about US$2995
and includes
- TurboWriter context-sensitive editor based on CodeWright
- SILOS III Verilog simulator
- FGPA synthesis using, Synplify-Lite from Synplicity
- SCS schematic capture (OEMed from Data I/O, I think)
- spDE s/w from QuickLogic for FPGA place and route
Restrictions include
- synthesis is only for QuickLogic devices
- EDIF output can only be generated after synthesis has been
completed.
I've used this package and been reasonably happy with the synthesis
results, not jumping for joy, but reasonably happy. As a way to get
Verilog on a PC platform it is an excellent solution. You can write
code and see what the resulting h/w looks like VERY quickly. If you
are looking to do very large system level simulations, this is not the
tool for the job.
Garnett
----------------------------------------CUSTOMER FIRST, QUALITY ALWAYS
GARNETT HAMILTON DY 4 Systems Inc **** ***
Senior Hardware Designer 21 Fitzgerald Rd *** * *** *** ***
Nepean, ON ** ** ** *** *** *
Tel: (613) 596-9922 ext 471 Canada * *** * *** *** **
Fax: (613) 596-0574 K2H 9J4 **** *** ***
Email: ghamilton@dy4.com ***
Article: 2345This is a multi-part message in MIME format. ---------------------------------5873350425071 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii Someone should contact this guy as he is talking about problems on the internet. If we help him, we should suggest that he reply with a FIXED resolution from tech support. Seamus ---------------------------------5873350425071 Content-Transfer-Encoding: 7bit Content-Type: ---------------------------------5873350425071--Article: 2346
ejessen@ix.netcom.com (Erik Jessen) writes: >In article <DI6H3x.5Lz@world.std.com>, > jcooley@world.std.com (John Cooley) wrote: >>Jyri Hamalainen <jyrih@cat.co.za> wrote: >>>Does anyone here know anything about protecting ASIC's from reverse >>>engineering? OR logic camourflaging? With modern technologies such as >>>electron beam induced current imaging and Charge induced voltage >>>alteration (Scania Labs), I suppose there are no more solutions to >>>protecting ones investment? >Jyri, >I've used some special layout cells we called "fake gates" - they looked like >normal combinatoric-logic cells, but actually had their outputs shorted to >either VDD or GND. If someone reverse-engineered the design, and didn't >notice, it would cause the design to behave erratically, every 3-5 days. >As a practical matter, if you want to keep someone from copying your design, >simply design it so that you can't debug it yourself - put in lots of async. >logic, race conditions, etc. And then lay it out so that the timing is right >on the edge. If you're really careful, build up some RC circuits using normal >routing - if someone else' process has different parameters, the circuit will >fail erratically (or, even better, just corrupt the data, like toggling the >parity bit and one other bit). >:> >Erik Arrggghhh! you must be *really* mad! Mike -- Copyright 1995 M.Hasselberg.Microsoft Network is prohibited from redistributing this work in any form, in whole or in part. Distribution Licenses for this work is available to Microsoft for $999. Posting without permission constitutes an agreement to these terms. Send violation informations to mikelh@zonta.ping.de .Article: 2347
Tim Eccles <Tim@tile.demon.co.uk> wrote: >In article <DHFC7I.9Dy@zoo.toronto.edu> > henry@zoo.toronto.edu "Henry Spencer" writes: > ><snip> > >>> In fairness, there is one tricky problem: customers who want to make >>> their products reverse-engineering-proof. This is hard to do with the >>> Xilinx approach, in which the bit stream to program the FPGA *must* come >>> from an external source and hence is easily tapped. To handle this in the >>> context of an open architecture, the chip needs to have either encryption >>> hardware or on-chip nonvolatile memory, neither of which is trivial. > >But would it not be relatively straightforward for Xilinx to add a few bytes >of non-volatile public key memory (read/write) plus private key memory (write >only) and implement a small decryption engine. The configuration data rates >are so low that a serial arithmetic scheme should be possible. > >Even a simple system would give a huge increase in design security. The bigger problem happens during manufacturing. Any non-volatile bits require a deviation from standard CMOS technology. Even a few bits of non- volatile storage can add signficantly to the device cost. It is possible, but how much more would you be willing to pay for this capability. If design security is your ulimate goal, you should also investigate our new XC8100 MicroVia-based FPGA products. These are pin-compatible with the XC4000 but are based on a highly-secure non-volatile process. The actual memory cells are buried beneath metal and oxide. Conseptually, there are even more secure than gate arrays or full-custom--there is no easy means to optically observe a programmed cell. Check out http://www.xilinx.com/products/fpgaspec.htm#XC8100 for more information. -- Steve Knapp Xilinx, Inc.Article: 2348
Hiya We have the Needham programmer here. It seems to work OK here. It's what we use for programming our 251SB parts. The only complaints I have are: 1) The software is a little clunky (it's DOS based) but I'm not sure that is unlike the other products available on the market. 2) The software doesn't work under Windows 95 (at least it doesn't work HERE under Windows 95). 3) The wall transformer buzzes quite loudly. Other than those gripes, we've found it to be a pretty solid unit. It works well for the 251 and for other 8051 varieties that we program here. Jon Ward Keil SoftwareArticle: 2349
In article <48tmdi$73p@mailman.xilinx>,
Steven K. Knapp, Xilinx, Inc. <stevek> wrote:
>
>The bigger problem happens during manufacturing. Any non-volatile bits
>require a deviation from standard CMOS technology. Even a few bits of non-
>volatile storage can add signficantly to the device cost. It is possible, but
>how much more would you be willing to pay for this capability.
>
Actually, you can do non-volatility in a standard process, if density
isn't a big issue -- and for a few bytes of storage it wouldn't
be. See:
OHSAKI K; ASAMOTO N; TAKAGAKI S.
A SINGLE POLY-EEPROM CELL STRUCTURE FOR USE IN STANDARD CMOS PROCESSES.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994 MAR, V29 N3:311-316.
For an example from IBM Japan.
--
-------------------------------------------------------------------------------
John Lazzaro My Home Page: http://http.cs.berkeley.edu/~lazzaro
lazzaro@cs.berkeley.edu Chipmunk CAD: http://www.pcmp.caltech.edu/chipmunk/
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