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"Steven K. Knapp, Xilinx, Inc." <stevek> wrote: >The Xilinx timing and simulation models are for: > >Voltage: 5 volts +5% for commercial grade > 5 volts +10% for industrial and military grade This should be MINUS 5% or 10%. CMOS is slowest at high temperature and low voltage. My mistake. -- Steve Knapp Xilinx, Inc.Article: 2376
There is an "HDL Design Guide for FPGAs" on the Xilinx Web site. It provides a section with full details on how to implement memory using VHDL and Verilog. It is in Adobe Acrobat format. You can download the document from: http://www.xilinx.com/appnotes/hdl_dg.pdf It is a big document (over 1.2 Mb) so it may take a while to download. -- Steve Knapp Xilinx, Inc.Article: 2377
Hello all, I am looking for some FPGA prototype platform, containing 2-3 fast FPGA (preferred ALTERA FLEX10K and LATTICE CPLD mixture) and some fast RAM Any hints ? Thanks a lot, AndreasArticle: 2378
In article <4910eg$nav@newsun.netmbx.de> gerhard@netmbx.netmbx.de (Gerhard Hoffmann) writes: I needed a clock divider by 20 million ( 20 MHz to 1 Hz ) with 1:1 duty cycle. Not much to it: Input pad -- clk_div -- output pad. XBLOX crashed the PC. Scared by my exaggerated expectations i then tried a divider by 2000. XBLOX survived the synthesis but the generated clk_div divided by something like 2800. Dividers by 200 and smaller seemed to work, as well as a divider by 10000. I cascaded several of them and played games with the count enable inputs, so i could still have everything synchronous with the global 20 MHz clock. This changed the timing, of course. I had to add pipeline stages in the surrounding circuit to make up for the extra delays. The complexity of the whole thing has increased from a single symbol to a sheet. Building it from msi-like macros would have probably been less mess, even without fast carry logic. We have observed the same kind of problems with using clk_div in Xact 5.0. The 5.0 release notes mention that synthesizing large division ratios may take a very long time because clk_div is implemented as an LFSR counter. To find the proper initial shift register state that provides the right division ratio may take a lot of time. I too have observed strange division ratios, and have finally decided to create my own LFSR counter/divider from various XBLOX macros. The only difficulty is to find the proper initial shift register state, for which I wrote a short matlab function. cheers, Eric -- Eric Aardoom CAA Institute of Satellite Navigation Dept. of Electronic and Electrical Engineering University of Leeds, LS2 9JT, UK E-mail: E.Aardoom@CAAISN.leeds.ac.uk Phone: +44 113 233 2090 Fax: +44 113 233 2032Article: 2379
In article <496uta$d8a@gwsun.medinf.mu-luebeck.de>, Andreas Doering <doering@iti.mu-luebeck.de> wrote: >Hello all, >I am looking for some FPGA prototype platform, >containing 2-3 fast FPGA (preferred ALTERA FLEX10K and LATTICE CPLD mixture) >and some fast RAM >Any hints ? Andreas: The FLEX10K hasn't been around long enough to make prototype boards very likely (I think), especially not with a mixture of Lattice CPLDs. The only thing close to what you want seems to be the Altera RIPP10 board with eight sockets that can hold either FLEX81188 FPGAs or IQ160 FPIDs. It also has four 512Kx8 SRAMs. They may still have some of these boards left. You might be able to build a QFP-to-PGA converter daughterboard so you can hook the LATTICE devices into the existing sockets. I doubt there's any easy way to convert from the 81188 to the 10K series, however. -- || Dave Van den Bout -- XESS Corp. || || 2608 Sweetgum Dr., Apex, NC 27502 || || (919) 387-0076 FAX:(919) 387-1302 || || devb@xess.com devb@vnet.net ||Article: 2380
Eric Aardoom wrote: > We have observed the same kind of problems with using clk_div in Xact > 5.0. The 5.0 release notes mention that synthesizing large division > ratios may take a very long time because clk_div is implemented as an > LFSR counter. To find the proper initial shift register state that > provides the right division ratio may take a lot of time. I too have > observed strange division ratios, and have finally decided to create > my own LFSR counter/divider from various XBLOX macros. The only > difficulty is to find the proper initial shift register state, for > which I wrote a short matlab function. Yes. We also construct our own LFSR counters. If the counter is very long, I prefer to factor it into two cascaded counters, the TC of the junior counter feeding the CE of the senior. In some cases, I prefer to spend a flop or two to resynchronize TCs. Having done so, it is easy to arrange for global reset to force an inital jam, should that be needed. With Viewlogic, a shift register is representable as a single symbol having a $ARRAY attribute, making XBLOX unnecessary. (If this symbology seems arcane, draw a box around the array and forget what lies within, as one does with XBLOX.) Best regards, -- Bill Clark Clark Associates., Inc. wclark@clark.com +1 303 444 1890Article: 2381
The Best PLD/FPGA Design Tools Now Are Affordable! CUPL Professional Edition CUPL can now be rented through internet only. This is one of the more popular design languages offered. It now includes VHDL design entry and your choice of schematic interface. CUPL Professional Edition ( Total Designer 4.6) uses " C " like language and outputs JEDEC for programming. It includes a behavioural simulation ( Unit Delay) as part of the package. Rental Fee is $99.00/Month and there is a 4 Months minimum. You can charge this to your credit card today and get delivery within 48 hours. Send you order to logdev@henge.com attention J. Williams, or to MOT3152@aol.com attention D. Mot *Note VHDL compiler is extra ( $150.0/mo)Article: 2382
Chipmaster 3000 is now on sale for inventory close out at special prices. This product is being replaced by Chipmaster 6000 with 30% more device support and direct printer port interface. In addition it has 48 pin drivers and can directly program all 44 Pin PLCC devices using only one PLCC 44 socket adaptor. The one selling feature on this product is that it can read most Motorola 68HCXXX micro!!Article: 2383
Why Spend $2K just on an Altera Programmer. Now there is a new Altera Max 7000 Development system available from Logical Devices for about $1K that unlike the Altera system that needs a PC plug in card, operates through the serial port and can support now most of the Max 7000 family and soon All of them!!! This kit also includes a compiler for the 7032!! Using a universal front end language it means you won't be stuck with Altera Chips only, and visa versa. Using this Free Compiler and a $995.00 fitter you can support the 7064 and 7128 also!! both 100 and 160 pin QFP adaptors are in the works and will ship in December. PLCC adaptors are stock items...... Chips now supported 7032/7064/70128/70160/7096 to be avail next quarter; 7192/7256 ........ Product Name SYSAP1-101 Price $995.00 Includes Choice of PLCC adaptor, Boolean Compiler, 7032 fitter ( 7064/128 fitter $995) send order to logdev@henge.comArticle: 2384
Is there any VHDL/Verilog source available in the public domain for byte-wise CRC-32 computation. The serial computation is fairly straightforward and I know of algorithms to do the calculation with a 256x32 ROM table - but they are not really suitable for implementing inside an FPGA. Help appreciated. Som Sikdar ssikdar@best.comArticle: 2385
Second Call for Papers
IEE Colloquium
Hardware-software cosynthesis for reconfigurable systems
February 22, 1995.
System architectures that incorporate field programmable hardware as
well as ``conventional'' ASIC and microprocessor parts are becoming
increasingly popular. Systems such as these promise improved time to
market, painless field-upgrades, and through dynamically
reprogrammable hardware, applications that optimise their own hardware
at runtime. This colloquium, the third in the IEE Hardware-software
codesign series, is to address the challenge of synthesising such
systems. Papers are invited on all aspects of synthesising reliable
and maintainable reconfigurable systems. Papers that address toolkits
for cosynthesis, and illustrate methodologies through case studies
will be particularly welcome. The colloquium will be held at
Hewlett-Packard Research Laboratories, Bristol, England.
Submissions should consist of three copies of a 700 to 1000 word
summary including a short description of the problem and its
significance with references to previous work, plus the title,
authors' names, affiliations, addresses, topic category, telephone and
facsimile numbers, and e-mail addresses if available.
The deadline for submissions is December 8, 1995. Authors will be
notified of acceptance by December 20, 1995 and full papers will be
due by January 19, 1995.
For further details please contact Richard Taylor, Hewlett-Packard
Laboratories, Filton Road, Bristol BS12 6QZ, UK. Phone (44) 117 922
9545, Email rwt@hpl.hp.com. or Claire Coleshill, IEE, Savoy Place,
London, WC2R 0BL, United Kingdom. Phone (44) 171 344 5419, Fax (44)
171 497 3633, Email : ccoleshill@iee.org.uk
Article: 2386In article <49b8fk$nv8@henge2.henge.com> logdev@henge.com "David Mot" writes: "Chipmaster 3000 is now on sale for inventory close out at special prices. This "product is being replaced by Chipmaster 6000 with 30% more device support and "direct printer port interface. In addition it has 48 pin drivers and can " directly "program all 44 Pin PLCC devices using only one PLCC 44 socket adaptor. The one "selling feature on this product is that it can read most Motorola 68HCXXX micro!"! " " David, Look closely at this group, and you will find that although, like myself, some of the contributors work for companies which sell EDA tools or device programmers, we choose not to use the group to advertise our products and services. This is because of the desire of the group's users, as discussed in the group's early days, to not have such adverts appearing here. It's also an accepted part of netiquette that comp.* groups aren't the place for adverts. If you really want to get your message over, then why not start/join in with a legitimate technical discussion which relates to some aspect of your products? The problem with advertising in these groups is that once it becomes accepted, as soon as you promote the latest deal on your product, then every single vendor of that type of product will feel justified/compelled to post a similar ad, and the group will be swamped. -- David PashleyArticle: 2387
In article <ssikdar.21.00006806@best.com>, Som Sikdar <ssikdar@best.com> wrote: > >Is there any VHDL/Verilog source available in the public domain for byte-wise >CRC-32 computation. > >The serial computation is fairly straightforward and I know of algorithms to >do the calculation with a 256x32 ROM table - but they are not really suitable >for implementing inside an FPGA. > >Help appreciated. > >Som Sikdar >ssikdar@best.com Parallel CRC computation was a favorite topic in Computer Design from the late 60s to early 70s. Check it out in your local library. Good Luck. Hing-FaiArticle: 2388
Bob Hoffman x8931 <bobh@galaxy.nsc.com> wrote:
>The rumor I've heard is that AT&T did an additional savvy thing, which
>was to hire a good chunk of the core development team. It remains to
>be seen how the new AT&T release of Foundry preforms, but this combination
>(source code and developers) looks to have some real potential.
I heard the same thing about AT&T hiring a number of the NeoCAD developers
away from the Xilinx purchase. This gives AT&T a way out of their reliance
on NeoCAD problem... but I wonder what Motorola FPGA is doing to solve this
same problem.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 2389Frontline is offering a 2 for one deal too! John Cooley (jcooley@world.std.com) wrote: : <msgid@msg.ti.com> wrote: : >Can any one reccomend Verilog for a PC platform? (Pentium) : interHDL Inc <eli@netcom.com> wrote: : >Viper from interHDL. Contact info@interhdl.com or call (415) 428-4200 : Other than Eli promoting his own company for Verilog (I can't blame a guy : for trying!) you may also want to check out: Model Tech at (503) 641-1340; : Chronologic/ViewLogic at (800) VERILOG; Simucad at (415) 487-9700; and : Wellspring Solutions at "elliot@wellspring.com". (These are the names : that quickly come to mind; you may want to call the Open Verilog : International office at (408) 353-8899 or e-mail "georgia@netcom.com" : for a complete list of PC and UNIX Verilog vending companies.) : - John Cooley : Part Time EDA Consumer Advocate : Full Time ASIC, FPGA & EDA Design Consultant : =========================================================================== : Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other : users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! : : !!! "It's not a BUG, jcooley@world.std.com : /o o\ / it's a FEATURE!" (508) 429-4357 : ( > ) : \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, : _] [_ Verilog, VHDL and numerous Design Methodologies. : Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 : Legal Disclaimer: "As always, anything said here is only opinion."Article: 2390
Frontline is offering a two for one sale. Here is there phone #: 408-456-0222, ask for Rich Curtin. I would suggest you try them all out. Wellspring has a real good product too, by the way. Garnett Hamilton (ghamilton@dy4.com) wrote: : jcooley@world.std.com (John Cooley) wrote: : ><msgid@msg.ti.com> wrote: : >>Can any one reccomend Verilog for a PC platform? (Pentium) : >interHDL Inc <eli@netcom.com> wrote: : >>Viper from interHDL. Contact info@interhdl.com or call (415) 428-4200 : >Other than Eli promoting his own company for Verilog (I can't blame a guy : >for trying!) you may also want to check out: Model Tech at (503) 641-1340; : >Chronologic/ViewLogic at (800) VERILOG; Simucad at (415) 487-9700; and : >Wellspring Solutions at "elliot@wellspring.com". (These are the names : >that quickly come to mind; you may want to call the Open Verilog : >International office at (408) 353-8899 or e-mail "georgia@netcom.com" : >for a complete list of PC and UNIX Verilog vending companies.) : > - John Cooley : > Part Time EDA Consumer Advocate : > Full Time ASIC, FPGA & EDA Design Consultant : Another possibility, if it meets your requirements, is the QuickWorks : tool set from QuickLogic (408-987-2000). This s/w is about US$2995 : and includes : - TurboWriter context-sensitive editor based on CodeWright : - SILOS III Verilog simulator : - FGPA synthesis using, Synplify-Lite from Synplicity : - SCS schematic capture (OEMed from Data I/O, I think) : - spDE s/w from QuickLogic for FPGA place and route : Restrictions include : - synthesis is only for QuickLogic devices : - EDIF output can only be generated after synthesis has been : completed. : I've used this package and been reasonably happy with the synthesis : results, not jumping for joy, but reasonably happy. As a way to get : Verilog on a PC platform it is an excellent solution. You can write : code and see what the resulting h/w looks like VERY quickly. If you : are looking to do very large system level simulations, this is not the : tool for the job. : Garnett : ----------------------------------------CUSTOMER FIRST, QUALITY ALWAYS : GARNETT HAMILTON DY 4 Systems Inc **** *** : Senior Hardware Designer 21 Fitzgerald Rd *** * *** *** *** : Nepean, ON ** ** ** *** *** * : Tel: (613) 596-9922 ext 471 Canada * *** * *** *** ** : Fax: (613) 596-0574 K2H 9J4 **** *** *** : Email: ghamilton@dy4.com ***Article: 2391
We were told of a LATTICE GAL16VP8, which is rumoured to have HYSTERESIS but the LATTICE rep in Sydney seems to prefer hibernation to selling. We have Phoned / Faxed / Phoned, and still are none the wiser. Does this part exist ? What is it worth ? Is it std pinout ( AMD had/dropped a 16V8HD, that was non-std ) What else is there, with hysteresis ? Thanks for any help - jim granville.Article: 2392
Perhaps this is of interest. I have created an experimental set of C++
classes called "CNets" that let me specify structural (not behavioural)
designs which ultimately emit XNF primitives such as nets, gates, and
flipflops. Using this specification language I can build up higher
level modules, the most sophisticated of which is a pipelined 32-bit
RISC processor plus on-chip peripherals such as boot ROM, UART, and
DRAM controller, in ~65% of a XC4010.
I use this approach in preference to both schematic capture and to
synthesis from HDLs. It is more flexible, more powerful, and more
reusable than schematic capture and yet still allows me to precisely
and explicitly control primitive instantiation and placement, which can
be tricky using synthesis. Not to mention this approach is much more
affordable than HDL synthesis.
(By the way, "CNets" does NOT deliver FPGA device independence, but it
could be adapted to that purpose. I'm not convinced device
independence is such a panacea anyway -- for instance, either you
design to exploit distributed SRAMs and 3-state buses or you don't, and
if your current target device doesn't implement them you probably
should not require them.)
For instance, here is my universal linear feedback shift register
divider, which is known to work nicely for simple divisors like
n==(25000000/9600):
// emit an lfsr counter and decoder to divide by n
//
// See "Efficient Shift Registers, LFSR Counters, and
// Long Pseudo-Random Sequence Generators", Peter Alfke,
// Xilinx App Note, Aug. 1995
//
void lfsr_div(Net out, Net ce, Net reset, unsigned n) {
...
// choose appropriate width counter
static unsigned taps[32][4] = {
{ 0 }, { 0 }, { 0 }, { 3, 2 },
{ 4, 3 }, { 5, 3 }, { 6, 5 }, { 7, 6 },
{ 8, 6, 5, 4 }, { 9, 5 }, { 10, 7 }, { 11, 9 },
{ 12, 6, 4, 1 }, { 13, 4, 3, 1 }, { 14, 5, 3, 1 }, { 15, 14 },
{ 16, 15, 13, 4 }, { 17, 14 }, { 18, 11 }, { 19, 6, 2, 1 },
{ 20, 17 }, { 21, 19 }, { 22, 21 }, { 23, 18 },
{ 24, 23, 22, 17 }, { 25, 22 }, { 26, 6, 2, 1 }, { 27, 5, 2, 1
},
{ 28, 25 }, { 29, 27 }, { 30, 6, 4, 1, }, { 31, 28 }
};
check(n <= (1 << 30));
for (unsigned bits = 1; n >= (1U << bits); bits++)
;
check((1U << (bits-1)) <= n && n < (1U << bits));
// determine bit pattern of terminal state (after n-1 clockings of lfsr)
unsigned w = 0;
for (unsigned i = 1; i < n; i++) {
unsigned in = 0;
for (unsigned j = 0; j < 4 && taps[bits][j]; j++)
in ^= (w >> (taps[bits][j]) - 1) & 1;
w = ((w << 1) & ((1 << bits) - 1)) ^ !in;
check(w != 0);
}
// emit shift register and gates to recognize terminal state
bus(lfsr, bits+1);
out = lfsr(bits,1) == w;
lfsr[0] = gnd;
net(lfsr_in) = nomap(xnor(lfsr[taps[bits][0]], lfsr[taps[bits][1]],
lfsr[taps[bits][2]], lfsr[taps[bits][3]]));
net(lfsr_reset) = out | reset;
ff(lfsr[1], lfsr_in & ~lfsr_reset, ce);
for (i = 2; i <= bits; i++)
ff(lfsr[i], lfsr[i-1] & ~lfsr_reset, ce);
}
In case it's not perfectly obvious, :-), the last two groups of statements do
the following:
bus(lfsr, bits+1); -- declare lfsr to be a bus of bits+1 nets
out = lfsr(bits,1) == w; -- emit AND gate(s) to recognize the
word 'w' in bits (bits..1) of bus lfsr
lfsr[0] = gnd; -- set lfsr[0] to gnd, necessary for the
following XNOR to be correct when
taps[i] is 0
-- emit an XNOR of up to 4 inputs taking various taps from the lfsr
shift register flipflop outputs. 'nomap' suppresses the default FMAP:
net(lfsr_in) = nomap(xnor(lfsr[taps[bits][0]], lfsr[taps[bits][1]],
lfsr[taps[bits][2]], lfsr[taps[bits][3]]));
-- set lfsr_reset to be the OR of out and reset signals:
net(lfsr_reset) = out | reset;
-- emit a flipflop driving lfsr[1] whose D is the AND of lfsr_in and
NOT lfsr_reset and whose clock enable is 'ce':
ff(lfsr[1], lfsr_in & ~lfsr_reset, ce);
-- emit the rest of the flipflops, each of whose D input is the Q output of
the previous 'flop, qualified by not reset, and whose clock enables
are 'ce':
for (i = 2; i <= bits; i++)
ff(lfsr[i], lfsr[i-1] & ~lfsr_reset, ce);
Anyway, the salient ideas are:
* extend a real programming language with circuit specification datatypes
* employ structural specification, close to the FPGA primitive elements
Is anyone else using a similar approach?
Jan Gray
Redmond, WA
// coder of Microsoft dev tools by day, electronics hobbyist "as time permits"
Article: 2393Joe Samson (samson@ptd10c.erim.org) wrote: : >I have trouble installing XAct for Windows. The problem is that the dongle : >can't be found by the software. Any idea?? This problem is due to the new parallel port modes (EPP, ECP, bidirectional, compatible and unidirectional). The key licensing software is very sensitive to that set-up, you should set-up the parallel port in BIOS set-up to either compatible or unidirectional. Another solution is to install an "old" parallel port card, what I mean by that is an XT or AT vintage card, that will also do the trick. I am one of the first external beta testers for XACT 6 (for windows) and encoutered this problem the first time I installed the software on a Gateway P5-120 and a Thinkpad 755cx. On the Gateway, hit F1 at reset, go into peripheral config and change the parallel port mode to compatible. On a Thinkpad, same procedure but select unidirectional. Other PCs have similar set-ups. For more info or help pn XACT 6.0, feel free to email me at arnaud@ecla.com --AlainArticle: 2394
Does anyone have a utility that will read the checksum from an Altera POF file? Altera tells me the only way to get a checksum is to use the maxplus software. I want to be able to run this from a make file. Jim Kapcio Picker InternationalArticle: 2395
In article <490iga$6g3@mailman.xilinx>, <ericd> writes:
|> I am one of the founders of NeoCAD, and I am now at Xilinx.
|>
|> The Xilinx and NeoCAD software groups have merged into one team,
|> and we are hard at work combining the best technologies from both
|> companies into a single product, including support for a variety
*******************************
|> of new FPGA families.
*********************
|>
|> ==eric
|>
|> Eric Dellinger
|> Director, Strategic Software Technology
|> Xilinx, Inc.
|>
Eric,
Which "new FPGA families" will you support?
That is, Xilinx families only, or also non-Xilinx families?
Will you support AT&T Orca?
Bill
Article: 2396In article <1995Nov28.225208.454@decus.org.nz>, <granville@decus.org.nz> wrote: >We were told of a LATTICE GAL16VP8, which is rumoured to have HYSTERESIS >but the LATTICE rep in Sydney seems to prefer hibernation to selling. >We have Phoned / Faxed / Phoned, and still are none the wiser. > > Does this part exist ? The databook says a GAL16VP8 is a 16V8 with 64mA IOL, -32mA IOH, and "typical hysteresis of 200mV" on all inputs. > Is it std pinout ( AMD had/dropped a 16V8HD, that was non-std ) No. VCC and GND pins are moved to support those big output drivers. (Unfortunately, this particular datasheet doesn't seem to be on <http://www.lattice.com>; most datasheets are.) If you're still interested, send a note to "gal@lattice.com". This is a technical support alias, but they'll know who contact in international sales. -- Jay Lessert jayl@lattice.com Lattice Semiconductor Corp. (voice)1.503.681.0118 Hillsboro, OR, USA (fax)1.503.693.0540Article: 2397
I read recently someone from xilinx saying that AT&T hired 4 of the original
Neocad people, perhaps not enough to give them a great advantage though
obviously some help?
In article <DIpyCr.6t1@world.std.com>,
jcooley@world.std.com (John Cooley) wrote:
>Bob Hoffman x8931 <bobh@galaxy.nsc.com> wrote:
>>The rumor I've heard is that AT&T did an additional savvy thing, which
>>was to hire a good chunk of the core development team. It remains to
[snip]
>I heard the same thing about AT&T hiring a number of the NeoCAD developers
{snip]
Article: 2398I'm looking for a VHDL bus model of the motorola 68EC000. I've got a start on one, but its not particularly good, and I don't have much time to spend tweaking it. If anyone knows where I can find either comercial or public domain models, please let me know. tia, scott -- __________________________________________________ | | | homebrew is the elixir of the gods | | | --------------------------------------------------Article: 2399
Jan Gray wrote: > > Perhaps this is of interest. I have created an experimental set of C++ > classes called "CNets" that let me specify structural (not behavioural) > designs which ultimately emit XNF primitives such as nets, gates, and > flipflops. Using this specification language I can build up higher > level modules, the most sophisticated of which is a pipelined 32-bit > RISC processor plus on-chip peripherals such as boot ROM, UART, and > DRAM controller, in ~65% of a XC4010. > > I use this approach in preference to both schematic capture and to > synthesis from HDLs. It is more flexible, more powerful, and more > reusable than schematic capture and yet still allows me to precisely > and explicitly control primitive instantiation and placement, which can > be tricky using synthesis. Not to mention this approach is much more > affordable than HDL synthesis. >... I've not done anything like that but am very interested in what you are doing. (I've used programmatic editor macros to generate and replicate XNF and to replicate LCA interconnect. Most of this has been ad hoc, but a few macros have been generalized.) Are you at all interested in physical-design generalizations to go along with logic classes? Generalizations involving only dimension or dimensionality are not too hard to code (I guess that's obvious). -- Bill Clark Clark Associates., Inc. wclark@clark.com +1 303 444 1890
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