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Hi, Brad Eckert wrote: > > What's the cheapest way for me to teach myself VHDL? What are the free > resources on the net? Check out the FAQ of the newsgroup comp.lang.vhdl : http://www.vhdl.org/vi/comp.lang.vhdl/ The FAQ includes a list of on-line tutorials, books, free and commercial compiler/simulator for PCs, ... Bye,... Edwin -- ----------------------------------------------------------- Edwin Naroska Computer Engineering Institute (Lehrstuhl fuer Datenverarbeitungssysteme) University of Dortmund 44221 Dortmund Germany email: edwin@ds.e-technik.uni-dortmund.de phone: ++49 231 7552406 fax: ++49 231 7553251 -----------------------------------------------------------Article: 7676
Nestor Caouras wrote: > Hi. > > I've been looking around for development/demo boards that support the > larger XILINX and ALTERA devices (such as xc4085 and FLEX10k100). Up > to > now I've only been able to find boards for Xilinx devices up to 10k > devices (i.e. xc4010). If anyone knows of a third party > vendor/manufacturer that develops such boards, can you please contact > me. > > Your help will be greatly appreciated. > > Thanks in advance. > -- > Nestor Caouras > nestor@ece.concordia.ca > http://www.ece.concordia.ca/~nestor/addr.html > |-------------------------------------------| > | Dept. of Electrical and Computer Eng. | > | Concordia University | > | 1455 de Maisonneuve Blvd (West) | > | Montreal, Quebec, Canada H3G 1M8. | > | Tel: (514)848-8784 Fax: (514)848-2802 | > |-------------------------------------------| Nestor, Check at http://www.associatedpro.com/aps under the products and boards. We offer both a 240 pin QFP and a 208 pin QFP solution for XILINX boards, as well as the low cost 84 pin PLCC version. We also have a Lucent 84 pin PLCC board which will be followed by a Lucent 208QFP board soon. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 7677
does anyone know how to but a birectional bus on to an fpga using in ibuf and obuf components as there does not seem to be a bidirectional buf. Thanks DaveyArticle: 7678
Brad Eckert wrote: > What's the cheapest way for me to teach myself VHDL? What are the > free > resources on the net? > > -- Brad Eckert Brad if you check at http://www.associatedpro.com/aps/x84lab we have a free VHDL tutorial. Also, you can download a limited Peak-VHDL simulator and synthesis tool from our website. Another place you might want to try is CYPRESS semiconductors $99.00 VHDL tool (CPLD only). -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 7679
Hi. I've been looking around for development/demo boards that support the larger XILINX and ALTERA devices (such as xc4085 and FLEX10k100). Up to now I've only been able to find boards for Xilinx devices up to 10k devices (i.e. xc4010). If anyone knows of a third party vendor/manufacturer that develops such boards, can you please contact me. Your help will be greatly appreciated. Thanks in advance. -- Nestor Caouras nestor@ece.concordia.ca http://www.ece.concordia.ca/~nestor/addr.html |-------------------------------------------| | Dept. of Electrical and Computer Eng. | | Concordia University | | 1455 de Maisonneuve Blvd (West) | | Montreal, Quebec, Canada H3G 1M8. | | Tel: (514)848-8784 Fax: (514)848-2802 | |-------------------------------------------|Article: 7680
Hi. I've been looking around for development/prototyping boards that support the larger XILINX and ALTERA devices (such as xc4085 and FLEX10k100). Up to now I've only been able to find boards for Xilinx devices up to 10k devices (i.e. xc4010). If anyone knows of a third party vendor/manufacturer that develops such boards, can you please contact me. Your help will be greatly appreciated. Thanks in advance. -- Nestor Caouras nestor@ece.concordia.ca http://www.ece.concordia.ca/~nestor/addr.html |-------------------------------------------| | Dept. of Electrical and Computer Eng. | | Concordia University | | 1455 de Maisonneuve Blvd (West) | | Montreal, Quebec, Canada H3G 1M8. | | Tel: (514)848-8784 Fax: (514)848-2802 | |-------------------------------------------|Article: 7681
Hi. I've been looking around for development/prototyping boards that support the larger XILINX and ALTERA devices (such as xc4085 and FLEX10k100). Up to now I've only been able to find boards for Xilinx devices up to 10k devices (i.e. xc4010). If anyone knows of a third party vendor/manufacturer that develops such boards, can you please contact me. Your help will be greatly appreciated. Thanks in advance. -- Nestor Caouras nestor@ece.concordia.ca http://www.ece.concordia.ca/~nestor/addr.html |-------------------------------------------| | Dept. of Electrical and Computer Eng. | | Concordia University | | 1455 de Maisonneuve Blvd (West) | | Montreal, Quebec, Canada H3G 1M8. | | Tel: (514)848-8784 Fax: (514)848-2802 | |-------------------------------------------|Article: 7682
I am currently working on a research project to build a gigabit network. We are currently using FPGAs to implement much of the network interface. Now one problem we face is that we want to implement a clock recovery scheme for the network that will need to operate at the data rate of 1 GHz. Since we do not have the time or resources to do ASICs or custom VLSI, we are trying to find an alternative. My question is are there any very high speed gate arrays that could operate at this frequency? I have heard of ECL gate arrays but could not find any. Are there any companies that make these? I have also heard rumors of GaAs FPGAs but have not found these either. Do these exist? Does anyone know of a company that sells these? Thanks in advance. -- David C. Hoffmeister dch@eng.umd.edu University of Maryland at College ParkArticle: 7683
For Xilinx you need to use a tbuf with an ibuf to get the input portion, and an obuft for the output portion. Don't know how other vendors do it. david.surphlis@gecm.com wrote in article <6107sd$t4r@gcsin3.geccs.gecm.com>... > > does anyone know how to but a birectional bus on to an fpga > using in ibuf and obuf components as there does not seem to be a > bidirectional buf. > > Thanks > Davey > >Article: 7684
I got old version of xilinx demo board, XC40XX-PC84 REV. 2 ASSEMBLY # 0430454, last weekend at ACP computer show. Please, some one can show me where to get documentation about this Demo board. Thanks a lot for your help.Article: 7685
In article <6107sd$t4r@gcsin3.geccs.gecm.com>, <david.surphlis@gecm.com> wrote: >does anyone know how to but a birectional bus on to an fpga >using in ibuf and obuf components as there does not seem to be a >bidirectional buf. I assume you are refering to the Xilinx parts. On Xilinx 4000 series, you use an IOPAD connected to an IBUF and an OBUFE (tri-stated obuf) to drive an off-chip bidirectional bus. If this is also connected to an on-chip bidirectional bus, the IBUF's output should go through a BUFT (normal Xilinx tri-state buffer). -- Nicholas C. Weaver "Trouble will come in its own time. It always nweaver@cs.berkeley.edu does. But that is tomorrow. Give me http://www.cs.berkeley.edu/~nweaver/ today and I will be happy." It is a tale, told by an idiot, full of sound and fury, .signifying nothing.Article: 7686
You could take a look at Dynachip http://www.dyna.com/ for ECL FPGAs (270 MHz system clock claimed). Since gigabit clock recovery is a semi-analog function typically implemented with PLLs, it might be awkward to do with generic gate arrays, though some vendors will supply on-chip PLL blocks (LSI Logic?) If you haven't already, you might also take a look at Vitesse's stuff to make sure you aren't re-inventing the wheel : http://www.vitesse.com/ Maybe also check out HP and Motorola's gigabit parts. regards, tom David C. Hoffmeister wrote: > > I am currently working on a research project to > build a gigabit network. We are currently using FPGAs to > implement much of the network interface. > Now one problem we face is that we want to implement > a clock recovery scheme for the network that will need to operate > at the data rate of 1 GHz. Since we do not have the time or > resources to do ASICs or custom VLSI, we are trying to find an > alternative. > My question is are there any very high speed gate arrays > that could operate at this frequency? I have heard of ECL gate > arrays but could not find any. Are there any companies that make > these? I have also heard rumors of GaAs FPGAs but have not found > these either. Do these exist? Does anyone know of a company that > sells these? > Thanks in advance. > > -- > > David C. Hoffmeister > dch@eng.umd.edu > University of Maryland at College ParkArticle: 7687
In article <6109sq$18t@cappuccino.eng.umd.edu>, dch@Glue.umd.edu (David C. Hoffmeister) writes: |> |> Since we do not have the time or |> resources to do ASICs or custom VLSI, we are trying to find an |> alternative. |> My question is are there any very high speed gate arrays |> that could operate at this frequency? I have heard of ECL gate |> arrays but could not find any. Are there any companies that make A new company, Dynachip, is currently offering BiCMOS FPGAs w/ ECL signal level I/Os. For more information call: Rolf Krueger (408)481-3100 x158 Applications Manager DynaChip Corp. Sunnyvale, CA |> these? I have also heard rumors of GaAs FPGAs but have not found |> these either. Do these exist? Does anyone know of a company that |> sells these? |> Thanks in advance. |> -- |> |> David C. Hoffmeister |> dch@eng.umd.edu |> University of Maryland at College Park You might also consider low-cost NRE ASIC alternatives such as from Orbit Semiconductor, ChipExpress, or MOSIS. --Bill Zuk --zuk@LL.mit.eduArticle: 7688
In article <6109sq$18t@cappuccino.eng.umd.edu>,
David C. Hoffmeister <dch@Glue.umd.edu> wrote:
> Now one problem we face is that we want to implement
>a clock recovery scheme for the network that will need to operate
>at the data rate of 1 GHz. Since we do not have the time or
>resources to do ASICs or custom VLSI, we are trying to find an
>alternative.
Your best bet is probably going to be descrete ECL from Motorola and Synergy
Semiconductor. Use shift registers to turn your bit stream into
slower/wider words that can be handled by available FPGAs. Synergy has lots
of phase locked loop chips for clock recovery, but you may have trouble
getting shift registers above about 700MHz or so (for a 10E142).
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7689In the past I have experienced many difficulties for fitting ALTERA device (MAX 5K and 7K) when I started my design by setting the pin allocation (to get the PCB at the right time) . Today I have to design with a FLEX 10K30 (208 pins) where I have to fix now about 130 pins (I have 3 bus of 16bits and I expect my design to be less than 15k gates). Is there a chance for me to succeed ? Is there a method for choosing the pin allocation in order to improve routability ? In advance Thank you for any advice. PS : please excuse my poor english !Article: 7690
Hi, We're Hunter International, an Engineering Recruitment firm based out of Chicago, and this message will be of interest to many of you who are experts in dealing with DSP driven development projects. We have a tremendous need for professionals in your area of expertise for a client of ours that is doing absolutely stellar design and development. This firm is located in Northern California, literally the "Valley", and is one of the nation's top employers. They have a great need for the best Hardware and Software professional the industry has to offer. The projects they are working on are simply at the top tier in the field, and salary/benefits are just about, if not the, best going today. There are multiple opportunities for both H/W & S/W, and it's a safe bet that even three years of experience will be enough, so there's room for people of all levels. Please consider this to be a very genuine, as well as unique, chance to do some amazing work for a world class firm. The R & D will be extremely enticing. The location of the facility and it's surroundings are second to none. There is even a fully functional health club on the premises! The salary and benefits are exceptional. Full relo, great investment plans, etc... If you have any desire to see what Northern California has to offer, this firm in particular, please contact us at your convenience. We guarantee that you WILL be impressed beyond your expectations with this company, and the location is simply gorgeous. All serious inquiries will be answered. All responses will be completely confidential. All DSP pro's can consider themselves as likely candidates. You will not be disappointed! Please write to us at: cleaner@starnetinc.com or fax us at: Hunter International (815)356-9225 Attn: David Steiger Thanks in advance, Dave...Article: 7691
hi, you might want to contact SPEC who is making a complementary gaas fpga based on the atmel 6002, if my memory is correct. hope this helps, ------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) ------------------------------------------------------------- David C. Hoffmeister <dch@Glue.umd.edu> wrote in article <6109sq$18t@cappuccino.eng.umd.edu>... > > I am currently working on a research project to > build a gigabit network. We are currently using FPGAs to > implement much of the network interface. > Now one problem we face is that we want to implement > a clock recovery scheme for the network that will need to operate > at the data rate of 1 GHz. Since we do not have the time or > resources to do ASICs or custom VLSI, we are trying to find an > alternative. > My question is are there any very high speed gate arrays > that could operate at this frequency? I have heard of ECL gate > arrays but could not find any. Are there any companies that make > these? I have also heard rumors of GaAs FPGAs but have not found > these either. Do these exist? Does anyone know of a company that > sells these? > Thanks in advance. > > > -- > > David C. Hoffmeister > dch@eng.umd.edu > University of Maryland at College Park >Article: 7692
In article <01bccef6$bd017fc0$7819fecc@tecra>, "Jan Gray" <jsgray@acm.org.nospam> says: > >This just in from our paper designs department: the XC4062XL and XC4085XL >are sooo big... > >The J32 (www3.sympatico.ca/jsgray/homebrew.htm) (a 32-bit RISC in half a >XC4010) processor's datapath, if redesigned for XC4000XL, should fit nicely >in 16 rows by 8-9 columns of CLBs. This got me thinking: > >16x9 datapath >16x5 (guess) control logic >16x6 16-entry by 4-word-line instruction cache >16x2 page mode DRAM controller (also reqs. 40-50 IOBs) >---------------------------------- >16x22 integrated 32-bit RISC processor (32-bit instructions) >8x22 integrated 16-bit RISC processor (16-bit instructions) > >Assuming careful floorplanning, it should be possible to place six 32-bit >processor tiles, or twelve 16-bit processor tiles, in a single 56x56 >XC4085XL with space left over for interprocessor interconnect. Also the >number of processor tiles can be doubled if we eschew the I-cache and >simplify the microarchitecture -- though performance would greatly suffer. I've been thinking along these lines, too. A coworker designed an 8-bit "nanoprocessor" that fits into 36 Xilinx cells. So, theoretically, about 80 (well, say 64) of these critters should fit into a XC4085XL. Call it massive parallel computation. (Of course, we lack enough IO lines to make this work. We should give every one of the nanoprocessors an instruction cache.) Just a comment. Gregor Glawitsch | Tel: ++43 (0)732 655 755 - 33 Utimaco Safe Concept GmbH | Fax: ++43 (0)732 655 755 - 5 Europaplatz 6 | email (office): Gregor.Glawitsch@utimaco.co.at A-4020 Linz, Austria | email (home) : Gregor.Glawitsch@magnet.atArticle: 7693
>As for expecting quality software for free, do you expect quality IC >databooks for free? It costs a lot of money to produce those things, you >know. (Have you priced specialty technical books lately?) Yet somehow, >people who are in business to sell *ICs* have figured out that it's worth >giving the databooks away rather than trying to charge $100 each, because >they sell more *ICs* that way. Even the ones who do charge for databooks >are not recovering much more than shipping and handling costs. Ask any of >them, and they'll tell you that treating their databooks as a profit >center, rather than as a marketing tool, would be shooting themselves in >the foot... if not the head. > >Most companies that want to sell ICs spend a lot of money and go to a lot >of effort to make it as easy as possible for engineers to make use of their >products. Unfortunately, the FPGA companies haven't yet figured out that >their product is FPGAs, not software. In this business, shooting yourself >in the foot is considered standard practice. Could not have put it better myself. In fact, National, Texas, and others *did* virtually stop giving out data books (here in the UK) until Maxim and Linear Technology started doing it, and started doing very well. Now the big names are back to giving them out quite liberally. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 7694
Nestor Caouras wrote: > > Hi. > > I've been looking around for development/prototyping boards that support > the larger XILINX and ALTERA devices (such as xc4085 and FLEX10k100). Up > to now I've only been able to find boards for Xilinx devices up to 10k > devices (i.e. xc4010). If anyone knows of a third party > vendor/manufacturer that develops such boards, can you please contact > me. Nova Engineering makes a nice board for 240-pin 10K devices. It can use any device from 10K20 to 10K70. Check it out at http://www.nova-eng.com Regards, Rune Baeverrud The FreeCore Library http://193.215.128.3/freecoreArticle: 7695
Fliptronics has an ISA board that will take any of the Xilinx 5.0 volt pq/hq 240 pin devices. A board with landing zones for more than 1 device, and a board with 3.3 volt part support are also under development. All of these boards also include DRAM SIMM sockets, SRAM, and a large wirewrap area. Email me for more info. Philip Freidin fliptron@netcom.com In article <3433A8B5.6647@ece.concordia.ca> Nestor Caouras <nestor@ece.concordia.ca> writes: >Hi. > >I've been looking around for development/prototyping boards that support >the larger XILINX and ALTERA devices (such as xc4085 and FLEX10k100). Up >to now I've only been able to find boards for Xilinx devices up to 10k >devices (i.e. xc4010). If anyone knows of a third party >vendor/manufacturer that develops such boards, can you please contact >me. > >Your help will be greatly appreciated. > >Thanks in advance. >-- >Nestor Caouras >nestor@ece.concordia.ca >http://www.ece.concordia.ca/~nestor/addr.html >|-------------------------------------------| >| Dept. of Electrical and Computer Eng. | >| Concordia University | >| 1455 de Maisonneuve Blvd (West) | >| Montreal, Quebec, Canada H3G 1M8. | >| Tel: (514)848-8784 Fax: (514)848-2802 | >|-------------------------------------------|Article: 7696
Hi all, If you are designer who likes working with people and solving problems, you might be interested to know that QuickLogic is looking to hire an experienced design or applications engineer to join our Customer Engineering team. Customer Engineers are responsible for helping designers using our FPGAs and many other applications functions. Those candidates with VHDL or Verilog experience and good communications skills are the most qualified. The position description is at QuickLogic Web site at www.quicklogic.com under the employment link. Send me an email if you're interested. If you're a recruiter, contact our human resources department first at 408-990-4000. - Brian Small QuickLogic Customer Engineering Manager small@quicklogic.comArticle: 7697
In article <01bccef6$bd017fc0$7819fecc@tecra>,
Jan Gray <jsgray@acm.org.nospam> wrote:
>This just in from our paper designs department: the XC4062XL and XC4085XL
>are sooo big...
>
>The J32 (www3.sympatico.ca/jsgray/homebrew.htm) (a 32-bit RISC in half a
>XC4010) processor's datapath, if redesigned for XC4000XL, should fit nicely
>in 16 rows by 8-9 columns of CLBs. This got me thinking:
I took a look at your web site... you should try to make your processor MIPS
R3000 compatible (minus the multiply, divide, variable endianness,
coprocessor, trap handling and MMU). The R3000 is clean and simple, so you
might be able to do it without too much work. I've made hand-held R3000
computers before- it's easy to get GNU C to generate ROMable code and so on.
It would be very nice if there were a low-power fully static version of the
R3000 for handheld applications, and you could probably get a lot of money
for it if you wanted. With the R3041 from IDT for example, you have to turn
the power off to the microprocessor and it's a big mess. You can get 4
rechargable AA cells to last for about 3 weeks on standby, but only for an
hour if the processor is on continually. Generally it would be cool to have
a C compiler for your processor. You could try getting the MIPS linux port
to run...
The MIPS R3000 has 32 registers (register 0 is hardwired to 0), a program
counter and 3 instruction formats. The biggest difference between it and
your J32 is the that it has no condition flags. Instead it has instructions
like branch if register 1 equals register 2. The other big difference is
that you need a shifter of some sort: either multicycle or a barrel-shifter
(although a barrel-shifter might be too big: I'd rather have it slow and
small, but compatible).
The three instruction formats are:
Immediate:|6 op-code|5 src reg|5 target reg|16 immediate |
Jump: |6 op-code|26 direct address |
Register: |6 op-code|5 src reg|5 target reg|5 dst reg|5 shift|6 alufunc|
The shift field is only used for special shift instructions, it is ignored
otherwise (and must be set to zero). The direct address in the jump field
gets shifted left by 2 and the missing top-2 bits come from the PC. There
and jump, branch and conditional branch instructions which store the old PC
value in register 31. Jumps and branches have one delay slot. For some of
the conditional branches, the result of the instruction of the branch delay
slot is ignored if the branch is not taken. When the processor resets, it
starts executing instructions at location 0xbfc00000.
The instructions are:
arithmetic: add, addi, addiu, addu, and, andi, nor, or, ori, sub, subu, xor,
xori.
(u means unsigned. signed add causes a trap if there's an overflow)
branch: beq, beql, bgez, bgezal, bgezall, bgezl, bgtz, bgtzl, blez, blezl,
bltz, bltzal, bltzall, bltzl, bne, bnel, j, jal, jalr, jr.
(al means 'and link'. 'l' means likely (branches ignore delay slot
instruction result if they fail), 'r' means register, as in the jump
destination is in a register)
load/store: lb, lbu, lh, lhu, ll, lui, lw, lwl, lwr, sb, sh, sw, swl, swr.
(b=byte, h=16-bits, w=word, u=unsigned, l=left, r=right. swl and swr are
used to store words which cross 32-bit boundaries by storing each half
separately)
shift: sll, sllv, sra, srav, srl, srlv.
(v means variable (amount to shift in register), a=arithmetic, l=logical)
set: slt, slti, sltiu, sltu.
(sets target register to 1 if less than; clears it otherwise)
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7698Your proble IMHO is either trivial or impossible. If you know the direction of data flow, then you just activate either the IBUF or the OBUF to connect the internal bidirectional bus to the external one. If you don't know whether the source is inside the chip or outside, it is either impossible or it needs somebody smarter than I am. The problem is than you go through an amplifier whenever you enter or exit the chip, and that amplifier is in your way, since it would just latch up. But you never know, somebody may give you an answer... Peter Alfke, Xilinx ApplicationsArticle: 7699
In article <343560FB.E7733771@xilinx.com>,
Peter Alfke <peter.alfke@xilinx.com> wrote:
>Your proble IMHO is either trivial or impossible.
>If you know the direction of data flow, then you just activate either
>the IBUF or the OBUF to connect the internal bidirectional bus to the
>external one.
>If you don't know whether the source is inside the chip or outside, it
>is either impossible or it needs somebody smarter than I am.
>The problem is than you go through an amplifier whenever you enter or
>exit the chip, and that amplifier is in your way, since it would just
>latch up.
>But you never know, somebody may give you an answer...
It's certainly possible: heck mere telephones accomplish this. A telephone
is a two-wire device (there is no seperate ground) and is bidirectional- yet
there are still such things as telephone line repeaters that don't latch up
or oscillate. Why can't your company's FPGAs do it? They must be inferior
products :-) :-) :-)
Thomas Edison (or one of his engineers) was the first person to figure out a
way to do this.
Big hint: if you put a resistor in series with the line, the polarity of the
voltage drop across it will tell you the direction of the signal.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
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